Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Actions Semi Owl Smart Power System (SPS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright 2012 Actions Semi Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Author: Actions Semi, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * Copyright (c) 2017 Andreas Färber
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/pm_domain.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/soc/actions/owl-sps.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <dt-bindings/power/owl-s500-powergate.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <dt-bindings/power/owl-s700-powergate.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <dt-bindings/power/owl-s900-powergate.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) struct owl_sps_domain_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 	const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 	int pwr_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 	int ack_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 	unsigned int genpd_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) struct owl_sps_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	unsigned num_domains;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	const struct owl_sps_domain_info *domains;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) struct owl_sps {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	const struct owl_sps_info *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	struct genpd_onecell_data genpd_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	struct generic_pm_domain *domains[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define to_owl_pd(gpd) container_of(gpd, struct owl_sps_domain, genpd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) struct owl_sps_domain {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	struct generic_pm_domain genpd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	const struct owl_sps_domain_info *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	struct owl_sps *sps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) static int owl_sps_set_power(struct owl_sps_domain *pd, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	u32 pwr_mask, ack_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	ack_mask = BIT(pd->info->ack_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	pwr_mask = BIT(pd->info->pwr_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	return owl_sps_set_pg(pd->sps->base, pwr_mask, ack_mask, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) static int owl_sps_power_on(struct generic_pm_domain *domain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	struct owl_sps_domain *pd = to_owl_pd(domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	dev_dbg(pd->sps->dev, "%s power on", pd->info->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	return owl_sps_set_power(pd, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) static int owl_sps_power_off(struct generic_pm_domain *domain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	struct owl_sps_domain *pd = to_owl_pd(domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	dev_dbg(pd->sps->dev, "%s power off", pd->info->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	return owl_sps_set_power(pd, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) static int owl_sps_init_domain(struct owl_sps *sps, int index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	struct owl_sps_domain *pd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	pd = devm_kzalloc(sps->dev, sizeof(*pd), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	if (!pd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	pd->info = &sps->info->domains[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	pd->sps = sps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	pd->genpd.name = pd->info->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	pd->genpd.power_on = owl_sps_power_on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	pd->genpd.power_off = owl_sps_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	pd->genpd.flags = pd->info->genpd_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	pm_genpd_init(&pd->genpd, NULL, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	sps->genpd_data.domains[index] = &pd->genpd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) static int owl_sps_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	const struct owl_sps_info *sps_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	struct owl_sps *sps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	if (!pdev->dev.of_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 		dev_err(&pdev->dev, "no device node\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	match = of_match_device(pdev->dev.driver->of_match_table, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	if (!match || !match->data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 		dev_err(&pdev->dev, "unknown compatible or missing data\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	sps_info = match->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	sps = devm_kzalloc(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 			   struct_size(sps, domains, sps_info->num_domains),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 			   GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	if (!sps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	sps->base = of_io_request_and_map(pdev->dev.of_node, 0, "owl-sps");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	if (IS_ERR(sps->base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 		dev_err(&pdev->dev, "failed to map sps registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		return PTR_ERR(sps->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	sps->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	sps->info = sps_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	sps->genpd_data.domains = sps->domains;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	sps->genpd_data.num_domains = sps_info->num_domains;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	for (i = 0; i < sps_info->num_domains; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		ret = owl_sps_init_domain(sps, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	ret = of_genpd_add_provider_onecell(pdev->dev.of_node, &sps->genpd_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 		dev_err(&pdev->dev, "failed to add provider (%d)", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static const struct owl_sps_domain_info s500_sps_domains[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	[S500_PD_VDE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 		.name = "VDE",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 		.pwr_bit = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		.ack_bit = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	[S500_PD_VCE_SI] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		.name = "VCE_SI",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 		.pwr_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 		.ack_bit = 17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	[S500_PD_USB2_1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		.name = "USB2_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 		.pwr_bit = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 		.ack_bit = 18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	[S500_PD_CPU2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		.name = "CPU2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 		.pwr_bit = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 		.ack_bit = 21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 		.genpd_flags = GENPD_FLAG_ALWAYS_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	[S500_PD_CPU3] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		.name = "CPU3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 		.pwr_bit = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 		.ack_bit = 22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		.genpd_flags = GENPD_FLAG_ALWAYS_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	[S500_PD_DMA] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 		.name = "DMA",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		.pwr_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		.ack_bit = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	[S500_PD_DS] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 		.name = "DS",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 		.pwr_bit = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 		.ack_bit = 13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	[S500_PD_USB3] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 		.name = "USB3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 		.pwr_bit = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 		.ack_bit = 14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	[S500_PD_USB2_0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 		.name = "USB2_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 		.pwr_bit = 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 		.ack_bit = 15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static const struct owl_sps_info s500_sps_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	.num_domains = ARRAY_SIZE(s500_sps_domains),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	.domains = s500_sps_domains,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) static const struct owl_sps_domain_info s700_sps_domains[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	[S700_PD_VDE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 		.name = "VDE",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 		.pwr_bit = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	[S700_PD_VCE_SI] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 		.name = "VCE_SI",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 		.pwr_bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	[S700_PD_USB2_1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 		.name = "USB2_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 		.pwr_bit = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	[S700_PD_HDE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		.name = "HDE",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 		.pwr_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	[S700_PD_DMA] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 		.name = "DMA",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 		.pwr_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	[S700_PD_DS] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 		.name = "DS",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		.pwr_bit = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	[S700_PD_USB3] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 		.name = "USB3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 		.pwr_bit = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	[S700_PD_USB2_0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 		.name = "USB2_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 		.pwr_bit = 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static const struct owl_sps_info s700_sps_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	.num_domains = ARRAY_SIZE(s700_sps_domains),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	.domains = s700_sps_domains,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) static const struct owl_sps_domain_info s900_sps_domains[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	[S900_PD_GPU_B] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 		.name = "GPU_B",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 		.pwr_bit = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	[S900_PD_VCE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 		.name = "VCE",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 		.pwr_bit = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	[S900_PD_SENSOR] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 		.name = "SENSOR",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 		.pwr_bit = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	[S900_PD_VDE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 		.name = "VDE",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 		.pwr_bit = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	[S900_PD_HDE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 		.name = "HDE",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 		.pwr_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	[S900_PD_USB3] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 		.name = "USB3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 		.pwr_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	[S900_PD_DDR0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 		.name = "DDR0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 		.pwr_bit = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	[S900_PD_DDR1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 		.name = "DDR1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 		.pwr_bit = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	[S900_PD_DE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 		.name = "DE",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 		.pwr_bit = 13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	[S900_PD_NAND] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 		.name = "NAND",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 		.pwr_bit = 14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	[S900_PD_USB2_H0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 		.name = "USB2_H0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 		.pwr_bit = 15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	[S900_PD_USB2_H1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 		.name = "USB2_H1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 		.pwr_bit = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) static const struct owl_sps_info s900_sps_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	.num_domains = ARRAY_SIZE(s900_sps_domains),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	.domains = s900_sps_domains,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) static const struct of_device_id owl_sps_of_matches[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	{ .compatible = "actions,s500-sps", .data = &s500_sps_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	{ .compatible = "actions,s700-sps", .data = &s700_sps_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	{ .compatible = "actions,s900-sps", .data = &s900_sps_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) static struct platform_driver owl_sps_platform_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	.probe = owl_sps_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 		.name = "owl-sps",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 		.of_match_table = owl_sps_of_matches,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 		.suppress_bind_attrs = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) static int __init owl_sps_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	return platform_driver_register(&owl_sps_platform_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) postcore_initcall(owl_sps_init);