^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #include <linux/sh_intc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #include <linux/irqdomain.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/list.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/radix-tree.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define _INTC_MK(fn, mode, addr_e, addr_d, width, shift) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) ((shift) | ((width) << 5) | ((fn) << 9) | ((mode) << 13) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) ((addr_e) << 16) | ((addr_d << 24)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define _INTC_SHIFT(h) (h & 0x1f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define _INTC_WIDTH(h) ((h >> 5) & 0xf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define _INTC_FN(h) ((h >> 9) & 0xf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define _INTC_MODE(h) ((h >> 13) & 0x7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define _INTC_ADDR_E(h) ((h >> 16) & 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define _INTC_ADDR_D(h) ((h >> 24) & 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define IS_SMP(x) (x.smp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define INTC_REG(d, x, c) (d->reg[(x)] + ((d->smp[(x)] & 0xff) * c))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SMP_NR(d, x) ((d->smp[(x)] >> 8) ? (d->smp[(x)] >> 8) : 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define IS_SMP(x) 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define INTC_REG(d, x, c) (d->reg[(x)])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define SMP_NR(d, x) 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) struct intc_handle_int {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) unsigned int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) unsigned long handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) struct intc_window {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) phys_addr_t phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) void __iomem *virt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) unsigned long size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) struct intc_map_entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) intc_enum enum_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) struct intc_desc_int *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) struct intc_subgroup_entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) unsigned int pirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) intc_enum enum_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) unsigned long handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) struct intc_desc_int {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) struct list_head list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) struct device dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) struct radix_tree_root tree;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) raw_spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) unsigned int index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) unsigned long *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) unsigned long *smp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) unsigned int nr_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct intc_handle_int *prio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) unsigned int nr_prio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) struct intc_handle_int *sense;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) unsigned int nr_sense;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) struct intc_window *window;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) unsigned int nr_windows;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) struct irq_domain *domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) struct irq_chip chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) bool skip_suspend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) REG_FN_ERR = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) REG_FN_TEST_BASE = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) REG_FN_WRITE_BASE = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) REG_FN_MODIFY_BASE = 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) enum { MODE_ENABLE_REG = 0, /* Bit(s) set -> interrupt enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) MODE_MASK_REG, /* Bit(s) set -> interrupt disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) MODE_DUAL_REG, /* Two registers, set bit to enable / disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) MODE_PRIO_REG, /* Priority value written to enable interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) MODE_PCLR_REG, /* Above plus all bits set to disable interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static inline struct intc_desc_int *get_intc_desc(unsigned int irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) struct irq_chip *chip = irq_get_chip(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) return container_of(chip, struct intc_desc_int, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * Grumble.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static inline void activate_irq(int irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) irq_modify_status(irq, IRQ_NOREQUEST, IRQ_NOPROBE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static inline int intc_handle_int_cmp(const void *a, const void *b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) const struct intc_handle_int *_a = a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) const struct intc_handle_int *_b = b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) return _a->irq - _b->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* access.c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) extern unsigned long
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) (*intc_reg_fns[])(unsigned long addr, unsigned long h, unsigned long data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) extern unsigned long
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) (*intc_enable_fns[])(unsigned long addr, unsigned long handle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) unsigned long (*fn)(unsigned long,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) unsigned long, unsigned long),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) unsigned int irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) extern unsigned long
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) (*intc_disable_fns[])(unsigned long addr, unsigned long handle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) unsigned long (*fn)(unsigned long,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) unsigned long, unsigned long),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) unsigned int irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) extern unsigned long
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) (*intc_enable_noprio_fns[])(unsigned long addr, unsigned long handle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) unsigned long (*fn)(unsigned long,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) unsigned long, unsigned long),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) unsigned int irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) unsigned long intc_phys_to_virt(struct intc_desc_int *d, unsigned long address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) unsigned int intc_get_reg(struct intc_desc_int *d, unsigned long address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) unsigned int intc_set_field_from_handle(unsigned int value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) unsigned int field_value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) unsigned int handle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) unsigned long intc_get_field_from_handle(unsigned int value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) unsigned int handle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /* balancing.c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #ifdef CONFIG_INTC_BALANCING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) void intc_balancing_enable(unsigned int irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) void intc_balancing_disable(unsigned int irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) void intc_set_dist_handle(unsigned int irq, struct intc_desc *desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) struct intc_desc_int *d, intc_enum id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static inline void intc_balancing_enable(unsigned int irq) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static inline void intc_balancing_disable(unsigned int irq) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) intc_set_dist_handle(unsigned int irq, struct intc_desc *desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct intc_desc_int *d, intc_enum id) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /* chip.c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) extern struct irq_chip intc_irq_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) void _intc_enable(struct irq_data *data, unsigned long handle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /* core.c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) extern struct list_head intc_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) extern raw_spinlock_t intc_big_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) extern struct bus_type intc_subsys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) unsigned int intc_get_dfl_prio_level(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) unsigned int intc_get_prio_level(unsigned int irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) void intc_set_prio_level(unsigned int irq, unsigned int level);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /* handle.c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) unsigned int intc_get_mask_handle(struct intc_desc *desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) struct intc_desc_int *d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) intc_enum enum_id, int do_grps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) unsigned int intc_get_prio_handle(struct intc_desc *desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) struct intc_desc_int *d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) intc_enum enum_id, int do_grps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) unsigned int intc_get_sense_handle(struct intc_desc *desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) struct intc_desc_int *d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) intc_enum enum_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) void intc_set_ack_handle(unsigned int irq, struct intc_desc *desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) struct intc_desc_int *d, intc_enum id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) unsigned long intc_get_ack_handle(unsigned int irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) void intc_enable_disable_enum(struct intc_desc *desc, struct intc_desc_int *d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) intc_enum enum_id, int enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /* irqdomain.c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) void intc_irq_domain_init(struct intc_desc_int *d, struct intc_hw_desc *hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /* virq.c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) void intc_subgroup_init(struct intc_desc *desc, struct intc_desc_int *d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) void intc_irq_xlate_set(unsigned int irq, intc_enum id, struct intc_desc_int *d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) struct intc_map_entry *intc_irq_xlate_get(unsigned int irq);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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