^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Shared interrupt handling code for IPR and INTC2 types of IRQs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2007, 2008 Magnus Damm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2009, 2010 Paul Mundt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * This file is subject to the terms and conditions of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * License. See the file "COPYING" in the main directory of this archive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "internals.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) static unsigned long ack_handle[INTC_NR_IRQS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) static intc_enum __init intc_grp_id(struct intc_desc *desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) intc_enum enum_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) struct intc_group *g = desc->hw.groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) unsigned int i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) for (i = 0; g && enum_id && i < desc->hw.nr_groups; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) g = desc->hw.groups + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) for (j = 0; g->enum_ids[j]; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) if (g->enum_ids[j] != enum_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) return g->enum_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) static unsigned int __init _intc_mask_data(struct intc_desc *desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) struct intc_desc_int *d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) intc_enum enum_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) unsigned int *reg_idx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) unsigned int *fld_idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) struct intc_mask_reg *mr = desc->hw.mask_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) unsigned int fn, mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) unsigned long reg_e, reg_d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) while (mr && enum_id && *reg_idx < desc->hw.nr_mask_regs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) mr = desc->hw.mask_regs + *reg_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) for (; *fld_idx < ARRAY_SIZE(mr->enum_ids); (*fld_idx)++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) if (mr->enum_ids[*fld_idx] != enum_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) if (mr->set_reg && mr->clr_reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) fn = REG_FN_WRITE_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) mode = MODE_DUAL_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) reg_e = mr->clr_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) reg_d = mr->set_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) fn = REG_FN_MODIFY_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) if (mr->set_reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) mode = MODE_ENABLE_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) reg_e = mr->set_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) reg_d = mr->set_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) mode = MODE_MASK_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) reg_e = mr->clr_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) reg_d = mr->clr_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) fn += (mr->reg_width >> 3) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) return _INTC_MK(fn, mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) intc_get_reg(d, reg_e),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) intc_get_reg(d, reg_d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) (mr->reg_width - 1) - *fld_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) *fld_idx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) (*reg_idx)++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) unsigned int __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) intc_get_mask_handle(struct intc_desc *desc, struct intc_desc_int *d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) intc_enum enum_id, int do_grps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) unsigned int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) unsigned int j = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) unsigned int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) ret = _intc_mask_data(desc, d, enum_id, &i, &j);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) if (do_grps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) return intc_get_mask_handle(desc, d, intc_grp_id(desc, enum_id), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static unsigned int __init _intc_prio_data(struct intc_desc *desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) struct intc_desc_int *d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) intc_enum enum_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) unsigned int *reg_idx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) unsigned int *fld_idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct intc_prio_reg *pr = desc->hw.prio_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) unsigned int fn, n, mode, bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) unsigned long reg_e, reg_d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) while (pr && enum_id && *reg_idx < desc->hw.nr_prio_regs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) pr = desc->hw.prio_regs + *reg_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) for (; *fld_idx < ARRAY_SIZE(pr->enum_ids); (*fld_idx)++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) if (pr->enum_ids[*fld_idx] != enum_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) if (pr->set_reg && pr->clr_reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) fn = REG_FN_WRITE_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) mode = MODE_PCLR_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) reg_e = pr->set_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) reg_d = pr->clr_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) fn = REG_FN_MODIFY_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) mode = MODE_PRIO_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) if (!pr->set_reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) reg_e = pr->set_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) reg_d = pr->set_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) fn += (pr->reg_width >> 3) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) n = *fld_idx + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) BUG_ON(n * pr->field_width > pr->reg_width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) bit = pr->reg_width - (n * pr->field_width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) return _INTC_MK(fn, mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) intc_get_reg(d, reg_e),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) intc_get_reg(d, reg_d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) pr->field_width, bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) *fld_idx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) (*reg_idx)++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) unsigned int __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) intc_get_prio_handle(struct intc_desc *desc, struct intc_desc_int *d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) intc_enum enum_id, int do_grps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) unsigned int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) unsigned int j = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) unsigned int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) ret = _intc_prio_data(desc, d, enum_id, &i, &j);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) if (do_grps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) return intc_get_prio_handle(desc, d, intc_grp_id(desc, enum_id), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static unsigned int intc_ack_data(struct intc_desc *desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) struct intc_desc_int *d, intc_enum enum_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) struct intc_mask_reg *mr = desc->hw.ack_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) unsigned int i, j, fn, mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) unsigned long reg_e, reg_d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) for (i = 0; mr && enum_id && i < desc->hw.nr_ack_regs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) mr = desc->hw.ack_regs + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) for (j = 0; j < ARRAY_SIZE(mr->enum_ids); j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) if (mr->enum_ids[j] != enum_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) fn = REG_FN_MODIFY_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) mode = MODE_ENABLE_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) reg_e = mr->set_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) reg_d = mr->set_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) fn += (mr->reg_width >> 3) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) return _INTC_MK(fn, mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) intc_get_reg(d, reg_e),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) intc_get_reg(d, reg_d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) (mr->reg_width - 1) - j);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) static void intc_enable_disable(struct intc_desc_int *d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) unsigned long handle, int do_enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) unsigned long addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) unsigned int cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) unsigned long (*fn)(unsigned long, unsigned long,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) unsigned long (*)(unsigned long, unsigned long,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) unsigned long),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) unsigned int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) if (do_enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) for (cpu = 0; cpu < SMP_NR(d, _INTC_ADDR_E(handle)); cpu++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) addr = INTC_REG(d, _INTC_ADDR_E(handle), cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) fn = intc_enable_noprio_fns[_INTC_MODE(handle)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) fn(addr, handle, intc_reg_fns[_INTC_FN(handle)], 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) for (cpu = 0; cpu < SMP_NR(d, _INTC_ADDR_D(handle)); cpu++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) addr = INTC_REG(d, _INTC_ADDR_D(handle), cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) fn = intc_disable_fns[_INTC_MODE(handle)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) fn(addr, handle, intc_reg_fns[_INTC_FN(handle)], 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) void __init intc_enable_disable_enum(struct intc_desc *desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) struct intc_desc_int *d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) intc_enum enum_id, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) unsigned int i, j, data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /* go through and enable/disable all mask bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) i = j = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) data = _intc_mask_data(desc, d, enum_id, &i, &j);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) if (data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) intc_enable_disable(d, data, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) j++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) } while (data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /* go through and enable/disable all priority fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) i = j = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) data = _intc_prio_data(desc, d, enum_id, &i, &j);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) if (data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) intc_enable_disable(d, data, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) j++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) } while (data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) unsigned int __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) intc_get_sense_handle(struct intc_desc *desc, struct intc_desc_int *d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) intc_enum enum_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) struct intc_sense_reg *sr = desc->hw.sense_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) unsigned int i, j, fn, bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) for (i = 0; sr && enum_id && i < desc->hw.nr_sense_regs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) sr = desc->hw.sense_regs + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) for (j = 0; j < ARRAY_SIZE(sr->enum_ids); j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) if (sr->enum_ids[j] != enum_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) fn = REG_FN_MODIFY_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) fn += (sr->reg_width >> 3) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) BUG_ON((j + 1) * sr->field_width > sr->reg_width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) bit = sr->reg_width - ((j + 1) * sr->field_width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) return _INTC_MK(fn, 0, intc_get_reg(d, sr->reg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 0, sr->field_width, bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) void intc_set_ack_handle(unsigned int irq, struct intc_desc *desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) struct intc_desc_int *d, intc_enum id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) * Nothing to do for this IRQ.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) if (!desc->hw.ack_regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) raw_spin_lock_irqsave(&intc_big_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) ack_handle[irq] = intc_ack_data(desc, d, id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) raw_spin_unlock_irqrestore(&intc_big_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) unsigned long intc_get_ack_handle(unsigned int irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) return ack_handle[irq];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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