^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Helper routines for SuperH Clock Pulse Generator blocks (CPG).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2010 Magnus Damm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2010 - 2012 Paul Mundt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * This file is subject to the terms and conditions of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * License. See the file "COPYING" in the main directory of this archive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/compiler.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/sh_clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define CPG_CKSTP_BIT BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) static unsigned int sh_clk_read(struct clk *clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) if (clk->flags & CLK_ENABLE_REG_8BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) return ioread8(clk->mapped_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) else if (clk->flags & CLK_ENABLE_REG_16BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) return ioread16(clk->mapped_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) return ioread32(clk->mapped_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) static void sh_clk_write(int value, struct clk *clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) if (clk->flags & CLK_ENABLE_REG_8BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) iowrite8(value, clk->mapped_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) else if (clk->flags & CLK_ENABLE_REG_16BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) iowrite16(value, clk->mapped_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) iowrite32(value, clk->mapped_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) static int sh_clk_mstp_enable(struct clk *clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) sh_clk_write(sh_clk_read(clk) & ~(1 << clk->enable_bit), clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) if (clk->status_reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) unsigned int (*read)(const void __iomem *addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) void __iomem *mapped_status = (phys_addr_t)clk->status_reg -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) (phys_addr_t)clk->enable_reg + clk->mapped_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) if (clk->flags & CLK_ENABLE_REG_8BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) read = ioread8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) else if (clk->flags & CLK_ENABLE_REG_16BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) read = ioread16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) read = ioread32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) for (i = 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) (read(mapped_status) & (1 << clk->enable_bit)) && i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) i--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) if (!i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) pr_err("cpg: failed to enable %p[%d]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) clk->enable_reg, clk->enable_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) static void sh_clk_mstp_disable(struct clk *clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) sh_clk_write(sh_clk_read(clk) | (1 << clk->enable_bit), clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static struct sh_clk_ops sh_clk_mstp_clk_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) .enable = sh_clk_mstp_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) .disable = sh_clk_mstp_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) .recalc = followparent_recalc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) int __init sh_clk_mstp_register(struct clk *clks, int nr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct clk *clkp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) int k;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) for (k = 0; !ret && (k < nr); k++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) clkp = clks + k;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) clkp->ops = &sh_clk_mstp_clk_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) ret |= clk_register(clkp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * Div/mult table lookup helpers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) static inline struct clk_div_table *clk_to_div_table(struct clk *clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) return clk->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static inline struct clk_div_mult_table *clk_to_div_mult_table(struct clk *clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) return clk_to_div_table(clk)->div_mult_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * Common div ops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static long sh_clk_div_round_rate(struct clk *clk, unsigned long rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) return clk_rate_table_round(clk, clk->freq_table, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static unsigned long sh_clk_div_recalc(struct clk *clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct clk_div_mult_table *table = clk_to_div_mult_table(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) unsigned int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) clk_rate_table_build(clk, clk->freq_table, table->nr_divisors,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) table, clk->arch_flags ? &clk->arch_flags : NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) idx = (sh_clk_read(clk) >> clk->enable_bit) & clk->div_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) return clk->freq_table[idx].frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static int sh_clk_div_set_rate(struct clk *clk, unsigned long rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) struct clk_div_table *dt = clk_to_div_table(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) unsigned long value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) idx = clk_rate_table_find(clk, clk->freq_table, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) if (idx < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) return idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) value = sh_clk_read(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) value &= ~(clk->div_mask << clk->enable_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) value |= (idx << clk->enable_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) sh_clk_write(value, clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /* XXX: Should use a post-change notifier */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) if (dt->kick)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) dt->kick(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static int sh_clk_div_enable(struct clk *clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) if (clk->div_mask == SH_CLK_DIV6_MSK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) int ret = sh_clk_div_set_rate(clk, clk->rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) sh_clk_write(sh_clk_read(clk) & ~CPG_CKSTP_BIT, clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static void sh_clk_div_disable(struct clk *clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) val = sh_clk_read(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) val |= CPG_CKSTP_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) * div6 clocks require the divisor field to be non-zero or the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * above CKSTP toggle silently fails. Ensure that the divisor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) * array is reset to its initial state on disable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) if (clk->flags & CLK_MASK_DIV_ON_DISABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) val |= clk->div_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) sh_clk_write(val, clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) static struct sh_clk_ops sh_clk_div_clk_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .recalc = sh_clk_div_recalc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .set_rate = sh_clk_div_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .round_rate = sh_clk_div_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static struct sh_clk_ops sh_clk_div_enable_clk_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) .recalc = sh_clk_div_recalc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) .set_rate = sh_clk_div_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) .round_rate = sh_clk_div_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .enable = sh_clk_div_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .disable = sh_clk_div_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static int __init sh_clk_init_parent(struct clk *clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) if (clk->parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) if (!clk->parent_table || !clk->parent_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) if (!clk->src_width) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) pr_err("sh_clk_init_parent: cannot select parent clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) val = (sh_clk_read(clk) >> clk->src_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) val &= (1 << clk->src_width) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) if (val >= clk->parent_num) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) pr_err("sh_clk_init_parent: parent table size failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) clk_reparent(clk, clk->parent_table[val]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) if (!clk->parent) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) pr_err("sh_clk_init_parent: unable to set parent");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) static int __init sh_clk_div_register_ops(struct clk *clks, int nr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) struct clk_div_table *table, struct sh_clk_ops *ops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) struct clk *clkp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) void *freq_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) int nr_divs = table->div_mult_table->nr_divisors;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) int freq_table_size = sizeof(struct cpufreq_frequency_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) int k;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) freq_table_size *= (nr_divs + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) freq_table = kcalloc(nr, freq_table_size, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) if (!freq_table) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) pr_err("%s: unable to alloc memory\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) for (k = 0; !ret && (k < nr); k++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) clkp = clks + k;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) clkp->ops = ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) clkp->priv = table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) clkp->freq_table = freq_table + (k * freq_table_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) clkp->freq_table[nr_divs].frequency = CPUFREQ_TABLE_END;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) ret = clk_register(clkp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) if (ret == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) ret = sh_clk_init_parent(clkp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) * div6 support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static int sh_clk_div6_divisors[64] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) static struct clk_div_mult_table div6_div_mult_table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) .divisors = sh_clk_div6_divisors,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) .nr_divisors = ARRAY_SIZE(sh_clk_div6_divisors),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) static struct clk_div_table sh_clk_div6_table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) .div_mult_table = &div6_div_mult_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) static int sh_clk_div6_set_parent(struct clk *clk, struct clk *parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) struct clk_div_mult_table *table = clk_to_div_mult_table(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) if (!clk->parent_table || !clk->parent_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) /* Search the parent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) for (i = 0; i < clk->parent_num; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) if (clk->parent_table[i] == parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) if (i == clk->parent_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) ret = clk_reparent(clk, parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) value = sh_clk_read(clk) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) ~(((1 << clk->src_width) - 1) << clk->src_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) sh_clk_write(value | (i << clk->src_shift), clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) /* Rebuild the frequency table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) clk_rate_table_build(clk, clk->freq_table, table->nr_divisors,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) table, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) static struct sh_clk_ops sh_clk_div6_reparent_clk_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) .recalc = sh_clk_div_recalc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) .round_rate = sh_clk_div_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) .set_rate = sh_clk_div_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) .enable = sh_clk_div_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) .disable = sh_clk_div_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) .set_parent = sh_clk_div6_set_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) int __init sh_clk_div6_register(struct clk *clks, int nr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) return sh_clk_div_register_ops(clks, nr, &sh_clk_div6_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) &sh_clk_div_enable_clk_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) int __init sh_clk_div6_reparent_register(struct clk *clks, int nr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) return sh_clk_div_register_ops(clks, nr, &sh_clk_div6_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) &sh_clk_div6_reparent_clk_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) * div4 support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) static int sh_clk_div4_set_parent(struct clk *clk, struct clk *parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) struct clk_div_mult_table *table = clk_to_div_mult_table(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) /* we really need a better way to determine parent index, but for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) * now assume internal parent comes with CLK_ENABLE_ON_INIT set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) * no CLK_ENABLE_ON_INIT means external clock...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) if (parent->flags & CLK_ENABLE_ON_INIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) value = sh_clk_read(clk) & ~(1 << 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) value = sh_clk_read(clk) | (1 << 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) ret = clk_reparent(clk, parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) sh_clk_write(value, clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) /* Rebiuld the frequency table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) clk_rate_table_build(clk, clk->freq_table, table->nr_divisors,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) table, &clk->arch_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) static struct sh_clk_ops sh_clk_div4_reparent_clk_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) .recalc = sh_clk_div_recalc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) .set_rate = sh_clk_div_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) .round_rate = sh_clk_div_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) .enable = sh_clk_div_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) .disable = sh_clk_div_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) .set_parent = sh_clk_div4_set_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) int __init sh_clk_div4_register(struct clk *clks, int nr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) struct clk_div4_table *table)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) return sh_clk_div_register_ops(clks, nr, table, &sh_clk_div_clk_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) int __init sh_clk_div4_enable_register(struct clk *clks, int nr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) struct clk_div4_table *table)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) return sh_clk_div_register_ops(clks, nr, table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) &sh_clk_div_enable_clk_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) int __init sh_clk_div4_reparent_register(struct clk *clks, int nr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) struct clk_div4_table *table)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) return sh_clk_div_register_ops(clks, nr, table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) &sh_clk_div4_reparent_clk_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) /* FSI-DIV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) static unsigned long fsidiv_recalc(struct clk *clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) value = __raw_readl(clk->mapping->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) value >>= 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) if (value < 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) return clk->parent->rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) return clk->parent->rate / value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) static long fsidiv_round_rate(struct clk *clk, unsigned long rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) return clk_rate_div_range_round(clk, 1, 0xffff, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) static void fsidiv_disable(struct clk *clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) __raw_writel(0, clk->mapping->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) static int fsidiv_enable(struct clk *clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) value = __raw_readl(clk->mapping->base) >> 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) if (value < 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) __raw_writel((value << 16) | 0x3, clk->mapping->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) static int fsidiv_set_rate(struct clk *clk, unsigned long rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) idx = (clk->parent->rate / rate) & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) if (idx < 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) __raw_writel(0, clk->mapping->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) __raw_writel(idx << 16, clk->mapping->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) static struct sh_clk_ops fsidiv_clk_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) .recalc = fsidiv_recalc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) .round_rate = fsidiv_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) .set_rate = fsidiv_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) .enable = fsidiv_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) .disable = fsidiv_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) int __init sh_clk_fsidiv_register(struct clk *clks, int nr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) struct clk_mapping *map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) for (i = 0; i < nr; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) map = kzalloc(sizeof(struct clk_mapping), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) if (!map) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) pr_err("%s: unable to alloc memory\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) /* clks[i].enable_reg came from SH_CLK_FSIDIV() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) map->phys = (phys_addr_t)clks[i].enable_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) map->len = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) clks[i].enable_reg = 0; /* remove .enable_reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) clks[i].ops = &fsidiv_clk_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) clks[i].mapping = map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) clk_register(&clks[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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