^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Driver for Western Digital WD7193, WD7197 and WD7296 SCSI cards
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright 2013 Ondrej Zary
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Original driver by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Aaron Dewell <dewell@woods.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Gaerti <Juergen.Gaertner@mbox.si.uni-hannover.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * HW documentation available in book:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * SPIDER Command Protocol
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * by Chandru M. Sippy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * SCSI Storage Products (MCP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * Western Digital Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * 09-15-95
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * http://web.archive.org/web/20070717175254/http://sun1.rrzn.uni-hannover.de/gaertner.juergen/wd719x/Linux/Docu/Spider/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * Driver workflow:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * 1. SCSI command is transformed to SCB (Spider Control Block) by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * queuecommand function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * 2. The address of the SCB is stored in a list to be able to access it, if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * something goes wrong.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * 3. The address of the SCB is written to the Controller, which loads the SCB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * via BM-DMA and processes it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * 4. After it has finished, it generates an interrupt, and sets registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * flaws:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * - abort/reset functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * ToDo:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * - tagged queueing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #include <linux/firmware.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #include <linux/eeprom_93cx6.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #include <scsi/scsi_cmnd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #include <scsi/scsi_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #include <scsi/scsi_host.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #include "wd719x.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* low-level register access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) static inline u8 wd719x_readb(struct wd719x *wd, u8 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) return ioread8(wd->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static inline u32 wd719x_readl(struct wd719x *wd, u8 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) return ioread32(wd->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static inline void wd719x_writeb(struct wd719x *wd, u8 reg, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) iowrite8(val, wd->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static inline void wd719x_writew(struct wd719x *wd, u8 reg, u16 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) iowrite16(val, wd->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) static inline void wd719x_writel(struct wd719x *wd, u8 reg, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) iowrite32(val, wd->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* wait until the command register is ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) static inline int wd719x_wait_ready(struct wd719x *wd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) if (wd719x_readb(wd, WD719X_AMR_COMMAND) == WD719X_CMD_READY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) } while (i++ < WD719X_WAIT_FOR_CMD_READY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) dev_err(&wd->pdev->dev, "command register is not ready: 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) wd719x_readb(wd, WD719X_AMR_COMMAND));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /* poll interrupt status register until command finishes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) static inline int wd719x_wait_done(struct wd719x *wd, int timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) u8 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) while (timeout > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) status = wd719x_readb(wd, WD719X_AMR_INT_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) if (status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) timeout--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) if (timeout <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) dev_err(&wd->pdev->dev, "direct command timed out\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) if (status != WD719X_INT_NOERRORS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) u8 sue = wd719x_readb(wd, WD719X_AMR_SCB_ERROR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /* we get this after wd719x_dev_reset, it's not an error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) if (sue == WD719X_SUE_TERM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* we get this after wd719x_bus_reset, it's not an error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) if (sue == WD719X_SUE_RESET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) dev_err(&wd->pdev->dev, "direct command failed, status 0x%02x, SUE 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) status, sue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static int wd719x_direct_cmd(struct wd719x *wd, u8 opcode, u8 dev, u8 lun,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) u8 tag, dma_addr_t data, int timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /* clear interrupt status register (allow command register to clear) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) wd719x_writeb(wd, WD719X_AMR_INT_STATUS, WD719X_INT_NONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /* Wait for the Command register to become free */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) if (wd719x_wait_ready(wd))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /* disable interrupts except for RESET/ABORT (it breaks them) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) if (opcode != WD719X_CMD_BUSRESET && opcode != WD719X_CMD_ABORT &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) opcode != WD719X_CMD_ABORT_TAG && opcode != WD719X_CMD_RESET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) dev |= WD719X_DISABLE_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) wd719x_writeb(wd, WD719X_AMR_CMD_PARAM, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) wd719x_writeb(wd, WD719X_AMR_CMD_PARAM_2, lun);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) wd719x_writeb(wd, WD719X_AMR_CMD_PARAM_3, tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) if (data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) wd719x_writel(wd, WD719X_AMR_SCB_IN, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /* clear interrupt status register again */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) wd719x_writeb(wd, WD719X_AMR_INT_STATUS, WD719X_INT_NONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /* Now, write the command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) wd719x_writeb(wd, WD719X_AMR_COMMAND, opcode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) if (timeout) /* wait for the command to complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) ret = wd719x_wait_done(wd, timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /* clear interrupt status register (clean up) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) if (opcode != WD719X_CMD_READ_FIRMVER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) wd719x_writeb(wd, WD719X_AMR_INT_STATUS, WD719X_INT_NONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static void wd719x_destroy(struct wd719x *wd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) /* stop the RISC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) if (wd719x_direct_cmd(wd, WD719X_CMD_SLEEP, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) WD719X_WAIT_FOR_RISC))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) dev_warn(&wd->pdev->dev, "RISC sleep command failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /* disable RISC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) wd719x_writeb(wd, WD719X_PCI_MODE_SELECT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) WARN_ON_ONCE(!list_empty(&wd->active_scbs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /* free internal buffers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) dma_free_coherent(&wd->pdev->dev, wd->fw_size, wd->fw_virt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) wd->fw_phys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) wd->fw_virt = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) dma_free_coherent(&wd->pdev->dev, WD719X_HASH_TABLE_SIZE, wd->hash_virt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) wd->hash_phys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) wd->hash_virt = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) dma_free_coherent(&wd->pdev->dev, sizeof(struct wd719x_host_param),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) wd->params, wd->params_phys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) wd->params = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) free_irq(wd->pdev->irq, wd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /* finish a SCSI command, unmap buffers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static void wd719x_finish_cmd(struct wd719x_scb *scb, int result)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) struct scsi_cmnd *cmd = scb->cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) struct wd719x *wd = shost_priv(cmd->device->host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) list_del(&scb->list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) dma_unmap_single(&wd->pdev->dev, scb->phys,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) sizeof(struct wd719x_scb), DMA_BIDIRECTIONAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) scsi_dma_unmap(cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) dma_unmap_single(&wd->pdev->dev, cmd->SCp.dma_handle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) SCSI_SENSE_BUFFERSIZE, DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) cmd->result = result << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) cmd->scsi_done(cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) /* Build a SCB and send it to the card */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static int wd719x_queuecommand(struct Scsi_Host *sh, struct scsi_cmnd *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) int i, count_sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) struct wd719x_scb *scb = scsi_cmd_priv(cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) struct wd719x *wd = shost_priv(sh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) scb->cmd = cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) scb->CDB_tag = 0; /* Tagged queueing not supported yet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) scb->devid = cmd->device->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) scb->lun = cmd->device->lun;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) /* copy the command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) memcpy(scb->CDB, cmd->cmnd, cmd->cmd_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) /* map SCB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) scb->phys = dma_map_single(&wd->pdev->dev, scb, sizeof(*scb),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) DMA_BIDIRECTIONAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) if (dma_mapping_error(&wd->pdev->dev, scb->phys))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) goto out_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) /* map sense buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) scb->sense_buf_length = SCSI_SENSE_BUFFERSIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) cmd->SCp.dma_handle = dma_map_single(&wd->pdev->dev, cmd->sense_buffer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) SCSI_SENSE_BUFFERSIZE, DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) if (dma_mapping_error(&wd->pdev->dev, cmd->SCp.dma_handle))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) goto out_unmap_scb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) scb->sense_buf = cpu_to_le32(cmd->SCp.dma_handle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) /* request autosense */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) scb->SCB_options |= WD719X_SCB_FLAGS_AUTO_REQUEST_SENSE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) /* check direction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) if (cmd->sc_data_direction == DMA_TO_DEVICE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) scb->SCB_options |= WD719X_SCB_FLAGS_CHECK_DIRECTION
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) | WD719X_SCB_FLAGS_PCI_TO_SCSI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) else if (cmd->sc_data_direction == DMA_FROM_DEVICE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) scb->SCB_options |= WD719X_SCB_FLAGS_CHECK_DIRECTION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) /* Scather/gather */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) count_sg = scsi_dma_map(cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) if (count_sg < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) goto out_unmap_sense;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) BUG_ON(count_sg > WD719X_SG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) if (count_sg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) struct scatterlist *sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) scb->data_length = cpu_to_le32(count_sg *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) sizeof(struct wd719x_sglist));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) scb->data_p = cpu_to_le32(scb->phys +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) offsetof(struct wd719x_scb, sg_list));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) scsi_for_each_sg(cmd, sg, count_sg, i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) scb->sg_list[i].ptr = cpu_to_le32(sg_dma_address(sg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) scb->sg_list[i].length = cpu_to_le32(sg_dma_len(sg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) scb->SCB_options |= WD719X_SCB_FLAGS_DO_SCATTER_GATHER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) } else { /* zero length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) scb->data_length = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) scb->data_p = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) spin_lock_irqsave(wd->sh->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) /* check if the Command register is free */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) if (wd719x_readb(wd, WD719X_AMR_COMMAND) != WD719X_CMD_READY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) spin_unlock_irqrestore(wd->sh->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) return SCSI_MLQUEUE_HOST_BUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) list_add(&scb->list, &wd->active_scbs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) /* write pointer to the AMR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) wd719x_writel(wd, WD719X_AMR_SCB_IN, scb->phys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) /* send SCB opcode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) wd719x_writeb(wd, WD719X_AMR_COMMAND, WD719X_CMD_PROCESS_SCB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) spin_unlock_irqrestore(wd->sh->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) out_unmap_sense:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) dma_unmap_single(&wd->pdev->dev, cmd->SCp.dma_handle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) SCSI_SENSE_BUFFERSIZE, DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) out_unmap_scb:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) dma_unmap_single(&wd->pdev->dev, scb->phys, sizeof(*scb),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) DMA_BIDIRECTIONAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) out_error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) cmd->result = DID_ERROR << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) cmd->scsi_done(cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static int wd719x_chip_init(struct wd719x *wd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) u32 risc_init[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) const struct firmware *fw_wcs, *fw_risc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) const char fwname_wcs[] = "wd719x-wcs.bin";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) const char fwname_risc[] = "wd719x-risc.bin";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) memset(wd->hash_virt, 0, WD719X_HASH_TABLE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) /* WCS (sequencer) firmware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) ret = request_firmware(&fw_wcs, fwname_wcs, &wd->pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) dev_err(&wd->pdev->dev, "Unable to load firmware %s: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) fwname_wcs, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) /* RISC firmware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) ret = request_firmware(&fw_risc, fwname_risc, &wd->pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) dev_err(&wd->pdev->dev, "Unable to load firmware %s: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) fwname_risc, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) release_firmware(fw_wcs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) wd->fw_size = ALIGN(fw_wcs->size, 4) + fw_risc->size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) if (!wd->fw_virt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) wd->fw_virt = dma_alloc_coherent(&wd->pdev->dev, wd->fw_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) &wd->fw_phys, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) if (!wd->fw_virt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) goto wd719x_init_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) /* make a fresh copy of WCS and RISC code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) memcpy(wd->fw_virt, fw_wcs->data, fw_wcs->size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) memcpy(wd->fw_virt + ALIGN(fw_wcs->size, 4), fw_risc->data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) fw_risc->size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) /* Reset the Spider Chip and adapter itself */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) wd719x_writeb(wd, WD719X_PCI_PORT_RESET, WD719X_PCI_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) udelay(WD719X_WAIT_FOR_RISC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) /* Clear PIO mode bits set by BIOS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) wd719x_writeb(wd, WD719X_AMR_CMD_PARAM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) /* ensure RISC is not running */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) wd719x_writeb(wd, WD719X_PCI_MODE_SELECT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) /* ensure command port is ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) wd719x_writeb(wd, WD719X_AMR_COMMAND, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) if (wd719x_wait_ready(wd)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) ret = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) goto wd719x_init_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) /* Transfer the first 2K words of RISC code to kick start the uP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) risc_init[0] = wd->fw_phys; /* WCS FW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) risc_init[1] = wd->fw_phys + ALIGN(fw_wcs->size, 4); /* RISC FW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) risc_init[2] = wd->hash_phys; /* hash table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) /* clear DMA status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) wd719x_writeb(wd, WD719X_PCI_CHANNEL2_3STATUS, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) /* address to read firmware from */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) wd719x_writel(wd, WD719X_PCI_EXTERNAL_ADDR, risc_init[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) /* base address to write firmware to (on card) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) wd719x_writew(wd, WD719X_PCI_INTERNAL_ADDR, WD719X_PRAM_BASE_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) /* size: first 2K words */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) wd719x_writew(wd, WD719X_PCI_DMA_TRANSFER_SIZE, 2048 * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) /* start DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) wd719x_writeb(wd, WD719X_PCI_CHANNEL2_3CMD, WD719X_START_CHANNEL2_3DMA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) /* wait for DMA to complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) i = WD719X_WAIT_FOR_RISC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) while (i-- > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) u8 status = wd719x_readb(wd, WD719X_PCI_CHANNEL2_3STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) if (status == WD719X_START_CHANNEL2_3DONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) if (status == WD719X_START_CHANNEL2_3ABORT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) dev_warn(&wd->pdev->dev, "RISC bootstrap failed: DMA aborted\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) goto wd719x_init_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) if (i < 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) dev_warn(&wd->pdev->dev, "RISC bootstrap failed: DMA timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) ret = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) goto wd719x_init_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) /* firmware is loaded, now initialize and wake up the RISC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) /* write RISC initialization long words to Spider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) wd719x_writel(wd, WD719X_AMR_SCB_IN, risc_init[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) wd719x_writel(wd, WD719X_AMR_SCB_IN + 4, risc_init[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) wd719x_writel(wd, WD719X_AMR_SCB_IN + 8, risc_init[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) /* disable interrupts during initialization of RISC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) wd719x_writeb(wd, WD719X_AMR_CMD_PARAM, WD719X_DISABLE_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) /* issue INITIALIZE RISC comand */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) wd719x_writeb(wd, WD719X_AMR_COMMAND, WD719X_CMD_INIT_RISC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) /* enable advanced mode (wake up RISC) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) wd719x_writeb(wd, WD719X_PCI_MODE_SELECT, WD719X_ENABLE_ADVANCE_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) udelay(WD719X_WAIT_FOR_RISC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) ret = wd719x_wait_done(wd, WD719X_WAIT_FOR_RISC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) /* clear interrupt status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) wd719x_writeb(wd, WD719X_AMR_INT_STATUS, WD719X_INT_NONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) dev_warn(&wd->pdev->dev, "Unable to initialize RISC\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) goto wd719x_init_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) /* RISC is up and running */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) /* Read FW version from RISC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) ret = wd719x_direct_cmd(wd, WD719X_CMD_READ_FIRMVER, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) WD719X_WAIT_FOR_RISC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) dev_warn(&wd->pdev->dev, "Unable to read firmware version\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) goto wd719x_init_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) dev_info(&wd->pdev->dev, "RISC initialized with firmware version %.2x.%.2x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) wd719x_readb(wd, WD719X_AMR_SCB_OUT + 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) wd719x_readb(wd, WD719X_AMR_SCB_OUT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) /* RESET SCSI bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) ret = wd719x_direct_cmd(wd, WD719X_CMD_BUSRESET, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) WD719X_WAIT_FOR_SCSI_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) dev_warn(&wd->pdev->dev, "SCSI bus reset failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) goto wd719x_init_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) /* use HostParameter structure to set Spider's Host Parameter Block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) ret = wd719x_direct_cmd(wd, WD719X_CMD_SET_PARAM, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) sizeof(struct wd719x_host_param), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) wd->params_phys, WD719X_WAIT_FOR_RISC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) dev_warn(&wd->pdev->dev, "Failed to set HOST PARAMETERS\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) goto wd719x_init_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) /* initiate SCAM (does nothing if disabled in BIOS) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) /* bug?: we should pass a mask of static IDs which we don't have */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) ret = wd719x_direct_cmd(wd, WD719X_CMD_INIT_SCAM, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) WD719X_WAIT_FOR_SCSI_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) dev_warn(&wd->pdev->dev, "SCAM initialization failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) goto wd719x_init_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) /* clear AMR_BIOS_SHARE_INT register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) wd719x_writeb(wd, WD719X_AMR_BIOS_SHARE_INT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) wd719x_init_end:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) release_firmware(fw_wcs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) release_firmware(fw_risc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) static int wd719x_abort(struct scsi_cmnd *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) int action, result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) struct wd719x_scb *scb = scsi_cmd_priv(cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) struct wd719x *wd = shost_priv(cmd->device->host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) dev_info(&wd->pdev->dev, "abort command, tag: %x\n", cmd->tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) action = /*cmd->tag ? WD719X_CMD_ABORT_TAG : */WD719X_CMD_ABORT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) spin_lock_irqsave(wd->sh->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) result = wd719x_direct_cmd(wd, action, cmd->device->id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) cmd->device->lun, cmd->tag, scb->phys, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) wd719x_finish_cmd(scb, DID_ABORT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) spin_unlock_irqrestore(wd->sh->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) if (result)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) return FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) return SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) static int wd719x_reset(struct scsi_cmnd *cmd, u8 opcode, u8 device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) int result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) struct wd719x *wd = shost_priv(cmd->device->host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) struct wd719x_scb *scb, *tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) dev_info(&wd->pdev->dev, "%s reset requested\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) (opcode == WD719X_CMD_BUSRESET) ? "bus" : "device");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) spin_lock_irqsave(wd->sh->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) result = wd719x_direct_cmd(wd, opcode, device, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) WD719X_WAIT_FOR_SCSI_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) /* flush all SCBs (or all for a device if dev_reset) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) list_for_each_entry_safe(scb, tmp, &wd->active_scbs, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) if (opcode == WD719X_CMD_BUSRESET ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) scb->cmd->device->id == device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) wd719x_finish_cmd(scb, DID_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) spin_unlock_irqrestore(wd->sh->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) if (result)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) return FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) return SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) static int wd719x_dev_reset(struct scsi_cmnd *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) return wd719x_reset(cmd, WD719X_CMD_RESET, cmd->device->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) static int wd719x_bus_reset(struct scsi_cmnd *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) return wd719x_reset(cmd, WD719X_CMD_BUSRESET, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) static int wd719x_host_reset(struct scsi_cmnd *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) struct wd719x *wd = shost_priv(cmd->device->host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) struct wd719x_scb *scb, *tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) dev_info(&wd->pdev->dev, "host reset requested\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) spin_lock_irqsave(wd->sh->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) /* stop the RISC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) if (wd719x_direct_cmd(wd, WD719X_CMD_SLEEP, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) WD719X_WAIT_FOR_RISC))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) dev_warn(&wd->pdev->dev, "RISC sleep command failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) /* disable RISC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) wd719x_writeb(wd, WD719X_PCI_MODE_SELECT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) /* flush all SCBs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) list_for_each_entry_safe(scb, tmp, &wd->active_scbs, list)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) wd719x_finish_cmd(scb, DID_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) spin_unlock_irqrestore(wd->sh->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) /* Try to reinit the RISC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) return wd719x_chip_init(wd) == 0 ? SUCCESS : FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) static int wd719x_biosparam(struct scsi_device *sdev, struct block_device *bdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) sector_t capacity, int geom[])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) if (capacity >= 0x200000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) geom[0] = 255; /* heads */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) geom[1] = 63; /* sectors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) geom[0] = 64; /* heads */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) geom[1] = 32; /* sectors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) geom[2] = sector_div(capacity, geom[0] * geom[1]); /* cylinders */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) /* process a SCB-completion interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) static inline void wd719x_interrupt_SCB(struct wd719x *wd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) union wd719x_regs regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) struct wd719x_scb *scb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) int result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) /* now have to find result from card */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) switch (regs.bytes.SUE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) case WD719X_SUE_NOERRORS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) result = DID_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) case WD719X_SUE_REJECTED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) dev_err(&wd->pdev->dev, "command rejected\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) result = DID_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) case WD719X_SUE_SCBQFULL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) dev_err(&wd->pdev->dev, "SCB queue is full\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) result = DID_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) case WD719X_SUE_TERM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) dev_dbg(&wd->pdev->dev, "SCB terminated by direct command\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) result = DID_ABORT; /* or DID_RESET? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) case WD719X_SUE_CHAN1ABORT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) case WD719X_SUE_CHAN23ABORT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) result = DID_ABORT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) dev_err(&wd->pdev->dev, "DMA abort\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) case WD719X_SUE_CHAN1PAR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) case WD719X_SUE_CHAN23PAR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) result = DID_PARITY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) dev_err(&wd->pdev->dev, "DMA parity error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) case WD719X_SUE_TIMEOUT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) result = DID_TIME_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) dev_dbg(&wd->pdev->dev, "selection timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) case WD719X_SUE_RESET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) dev_dbg(&wd->pdev->dev, "bus reset occurred\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) result = DID_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) case WD719X_SUE_BUSERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) dev_dbg(&wd->pdev->dev, "SCSI bus error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) result = DID_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) case WD719X_SUE_WRONGWAY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) dev_err(&wd->pdev->dev, "wrong data transfer direction\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) result = DID_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) case WD719X_SUE_BADPHASE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) dev_err(&wd->pdev->dev, "invalid SCSI phase\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) result = DID_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) case WD719X_SUE_TOOLONG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) dev_err(&wd->pdev->dev, "record too long\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) result = DID_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) case WD719X_SUE_BUSFREE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) dev_err(&wd->pdev->dev, "unexpected bus free\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) result = DID_NO_CONNECT; /* or DID_ERROR ???*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) case WD719X_SUE_ARSDONE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) dev_dbg(&wd->pdev->dev, "auto request sense\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) if (regs.bytes.SCSI == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) result = DID_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) result = DID_PARITY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) case WD719X_SUE_IGNORED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) dev_err(&wd->pdev->dev, "target id %d ignored command\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) scb->cmd->device->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) result = DID_NO_CONNECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) case WD719X_SUE_WRONGTAGS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) dev_err(&wd->pdev->dev, "reversed tags\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) result = DID_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) case WD719X_SUE_BADTAGS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) dev_err(&wd->pdev->dev, "tag type not supported by target\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) result = DID_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) case WD719X_SUE_NOSCAMID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) dev_err(&wd->pdev->dev, "no SCAM soft ID available\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) result = DID_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) dev_warn(&wd->pdev->dev, "unknown SUE error code: 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) regs.bytes.SUE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) result = DID_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) wd719x_finish_cmd(scb, result);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) static irqreturn_t wd719x_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) struct wd719x *wd = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) union wd719x_regs regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) u32 SCB_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) spin_lock_irqsave(wd->sh->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) /* read SCB pointer back from card */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) SCB_out = wd719x_readl(wd, WD719X_AMR_SCB_OUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) /* read all status info at once */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) regs.all = cpu_to_le32(wd719x_readl(wd, WD719X_AMR_OP_CODE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) switch (regs.bytes.INT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) case WD719X_INT_NONE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) spin_unlock_irqrestore(wd->sh->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) case WD719X_INT_LINKNOSTATUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) dev_err(&wd->pdev->dev, "linked command completed with no status\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) case WD719X_INT_BADINT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) dev_err(&wd->pdev->dev, "unsolicited interrupt\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) case WD719X_INT_NOERRORS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) case WD719X_INT_LINKNOERRORS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) case WD719X_INT_ERRORSLOGGED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) case WD719X_INT_SPIDERFAILED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) /* was the cmd completed a direct or SCB command? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) if (regs.bytes.OPC == WD719X_CMD_PROCESS_SCB) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) struct wd719x_scb *scb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) list_for_each_entry(scb, &wd->active_scbs, list)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) if (SCB_out == scb->phys)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) if (SCB_out == scb->phys)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) wd719x_interrupt_SCB(wd, regs, scb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) dev_err(&wd->pdev->dev, "card returned invalid SCB pointer\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) dev_dbg(&wd->pdev->dev, "direct command 0x%x completed\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) regs.bytes.OPC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) case WD719X_INT_PIOREADY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) dev_err(&wd->pdev->dev, "card indicates PIO data ready but we never use PIO\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) /* interrupt will not be cleared until all data is read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) dev_err(&wd->pdev->dev, "unknown interrupt reason: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) regs.bytes.INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) /* clear interrupt so another can happen */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) wd719x_writeb(wd, WD719X_AMR_INT_STATUS, WD719X_INT_NONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) spin_unlock_irqrestore(wd->sh->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) static void wd719x_eeprom_reg_read(struct eeprom_93cx6 *eeprom)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) struct wd719x *wd = eeprom->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) u8 reg = wd719x_readb(wd, WD719X_PCI_GPIO_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) eeprom->reg_data_out = reg & WD719X_EE_DO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) static void wd719x_eeprom_reg_write(struct eeprom_93cx6 *eeprom)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) struct wd719x *wd = eeprom->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) u8 reg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) if (eeprom->reg_data_in)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) reg |= WD719X_EE_DI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) if (eeprom->reg_data_clock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) reg |= WD719X_EE_CLK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) if (eeprom->reg_chip_select)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) reg |= WD719X_EE_CS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) wd719x_writeb(wd, WD719X_PCI_GPIO_DATA, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) /* read config from EEPROM so it can be downloaded by the RISC on (re-)init */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) static void wd719x_read_eeprom(struct wd719x *wd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) struct eeprom_93cx6 eeprom;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) u8 gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) struct wd719x_eeprom_header header;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) eeprom.data = wd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) eeprom.register_read = wd719x_eeprom_reg_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) eeprom.register_write = wd719x_eeprom_reg_write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) eeprom.width = PCI_EEPROM_WIDTH_93C46;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) /* set all outputs to low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) wd719x_writeb(wd, WD719X_PCI_GPIO_DATA, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) /* configure GPIO pins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) gpio = wd719x_readb(wd, WD719X_PCI_GPIO_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) /* GPIO outputs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) gpio &= (~(WD719X_EE_CLK | WD719X_EE_DI | WD719X_EE_CS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) /* GPIO input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) gpio |= WD719X_EE_DO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) wd719x_writeb(wd, WD719X_PCI_GPIO_CONTROL, gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) /* read EEPROM header */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) eeprom_93cx6_multireadb(&eeprom, 0, (u8 *)&header, sizeof(header));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) if (header.sig1 == 'W' && header.sig2 == 'D')
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) eeprom_93cx6_multireadb(&eeprom, header.cfg_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) (u8 *)wd->params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) sizeof(struct wd719x_host_param));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) else { /* default EEPROM values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) dev_warn(&wd->pdev->dev, "EEPROM signature is invalid (0x%02x 0x%02x), using default values\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) header.sig1, header.sig2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) wd->params->ch_1_th = 0x10; /* 16 DWs = 64 B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) wd->params->scsi_conf = 0x4c; /* 48ma, spue, parity check */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) wd->params->own_scsi_id = 0x07; /* ID 7, SCAM disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) wd->params->sel_timeout = 0x4d; /* 250 ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) wd->params->sleep_timer = 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) wd->params->cdb_size = cpu_to_le16(0x5555); /* all 6 B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) wd->params->scsi_pad = 0x1b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) if (wd->type == WD719X_TYPE_7193) /* narrow card - disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) wd->params->wide = cpu_to_le32(0x00000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) else /* initiate & respond to WIDE messages */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) wd->params->wide = cpu_to_le32(0xffffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) wd->params->sync = cpu_to_le32(0xffffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) wd->params->soft_mask = 0x00; /* all disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) wd->params->unsol_mask = 0x00; /* all disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) /* disable TAGGED messages */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) wd->params->tag_en = cpu_to_le16(0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) /* Read card type from GPIO bits 1 and 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) static enum wd719x_card_type wd719x_detect_type(struct wd719x *wd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) u8 card = wd719x_readb(wd, WD719X_PCI_GPIO_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) card |= WD719X_GPIO_ID_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) wd719x_writeb(wd, WD719X_PCI_GPIO_CONTROL, card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) card = wd719x_readb(wd, WD719X_PCI_GPIO_DATA) & WD719X_GPIO_ID_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) switch (card) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) case 0x08:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) return WD719X_TYPE_7193;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) case 0x02:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) return WD719X_TYPE_7197;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) case 0x00:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) return WD719X_TYPE_7296;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) dev_warn(&wd->pdev->dev, "unknown card type 0x%x\n", card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) return WD719X_TYPE_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) static int wd719x_board_found(struct Scsi_Host *sh)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) struct wd719x *wd = shost_priv(sh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) static const char * const card_types[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) "Unknown card", "WD7193", "WD7197", "WD7296"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) INIT_LIST_HEAD(&wd->active_scbs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) sh->base = pci_resource_start(wd->pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) wd->type = wd719x_detect_type(wd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) wd->sh = sh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) sh->irq = wd->pdev->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) wd->fw_virt = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) /* memory area for host (EEPROM) parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) wd->params = dma_alloc_coherent(&wd->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) sizeof(struct wd719x_host_param),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) &wd->params_phys, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) if (!wd->params) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) dev_warn(&wd->pdev->dev, "unable to allocate parameter buffer\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) /* memory area for the RISC for hash table of outstanding requests */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) wd->hash_virt = dma_alloc_coherent(&wd->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) WD719X_HASH_TABLE_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) &wd->hash_phys, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) if (!wd->hash_virt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) dev_warn(&wd->pdev->dev, "unable to allocate hash buffer\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) goto fail_free_params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) ret = request_irq(wd->pdev->irq, wd719x_interrupt, IRQF_SHARED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) "wd719x", wd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) dev_warn(&wd->pdev->dev, "unable to assign IRQ %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) wd->pdev->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) goto fail_free_hash;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) /* read parameters from EEPROM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) wd719x_read_eeprom(wd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) ret = wd719x_chip_init(wd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) goto fail_free_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) sh->this_id = wd->params->own_scsi_id & WD719X_EE_SCSI_ID_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) dev_info(&wd->pdev->dev, "%s at I/O 0x%lx, IRQ %u, SCSI ID %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) card_types[wd->type], sh->base, sh->irq, sh->this_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) fail_free_irq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) free_irq(wd->pdev->irq, wd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) fail_free_hash:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) dma_free_coherent(&wd->pdev->dev, WD719X_HASH_TABLE_SIZE, wd->hash_virt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) wd->hash_phys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) fail_free_params:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) dma_free_coherent(&wd->pdev->dev, sizeof(struct wd719x_host_param),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) wd->params, wd->params_phys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) static struct scsi_host_template wd719x_template = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) .module = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) .name = "Western Digital 719x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) .cmd_size = sizeof(struct wd719x_scb),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) .queuecommand = wd719x_queuecommand,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) .eh_abort_handler = wd719x_abort,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) .eh_device_reset_handler = wd719x_dev_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) .eh_bus_reset_handler = wd719x_bus_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) .eh_host_reset_handler = wd719x_host_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) .bios_param = wd719x_biosparam,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) .proc_name = "wd719x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) .can_queue = 255,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) .this_id = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) .sg_tablesize = WD719X_SG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) static int wd719x_pci_probe(struct pci_dev *pdev, const struct pci_device_id *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) struct Scsi_Host *sh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) struct wd719x *wd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) err = pci_enable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(32))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) dev_warn(&pdev->dev, "Unable to set 32-bit DMA mask\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) goto disable_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) err = pci_request_regions(pdev, "wd719x");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) goto disable_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) pci_set_master(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) err = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) if (pci_resource_len(pdev, 0) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) goto release_region;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) sh = scsi_host_alloc(&wd719x_template, sizeof(struct wd719x));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) if (!sh)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) goto release_region;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) wd = shost_priv(sh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) wd->base = pci_iomap(pdev, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) if (!wd->base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) goto free_host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) wd->pdev = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) err = wd719x_board_found(sh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) goto unmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) err = scsi_add_host(sh, &wd->pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) goto destroy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) scsi_scan_host(sh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) pci_set_drvdata(pdev, sh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) destroy:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) wd719x_destroy(wd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) unmap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) pci_iounmap(pdev, wd->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) free_host:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) scsi_host_put(sh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) release_region:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) pci_release_regions(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) disable_device:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) pci_disable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) static void wd719x_pci_remove(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) struct Scsi_Host *sh = pci_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) struct wd719x *wd = shost_priv(sh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) scsi_remove_host(sh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) wd719x_destroy(wd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) pci_iounmap(pdev, wd->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) pci_release_regions(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) pci_disable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) scsi_host_put(sh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) static const struct pci_device_id wd719x_pci_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) { PCI_DEVICE(PCI_VENDOR_ID_WD, 0x3296) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) MODULE_DEVICE_TABLE(pci, wd719x_pci_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) static struct pci_driver wd719x_pci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) .name = "wd719x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) .id_table = wd719x_pci_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) .probe = wd719x_pci_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) .remove = wd719x_pci_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) module_pci_driver(wd719x_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) MODULE_DESCRIPTION("Western Digital WD7193/7197/7296 SCSI driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) MODULE_AUTHOR("Ondrej Zary, Aaron Dewell, Juergen Gaertner");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) MODULE_FIRMWARE("wd719x-wcs.bin");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) MODULE_FIRMWARE("wd719x-risc.bin");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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