Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *    wd33c93.h -  Linux device driver definitions for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *                 Commodore Amiga A2091/590 SCSI controller card
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *    IMPORTANT: This file is for version 1.25 - 09/Jul/1997
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * Copyright (c) 1996 John Shifflett, GeoLog Consulting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  *    john@geolog.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  *    jshiffle@netcom.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #ifndef WD33C93_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #define WD33C93_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define PROC_INTERFACE     /* add code for /proc/scsi/wd33c93/xxx interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #ifdef  PROC_INTERFACE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define PROC_STATISTICS    /* add code for keeping various real time stats */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define SYNC_DEBUG         /* extra info on sync negotiation printed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define DEBUGGING_ON       /* enable command-line debugging bitmask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define DEBUG_DEFAULTS 0   /* default debugging bitmask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #ifdef DEBUGGING_ON
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define DB(f,a) if (hostdata->args & (f)) a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define DB(f,a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define uchar unsigned char
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) /* wd register names */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define WD_OWN_ID    0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define WD_CONTROL      0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define WD_TIMEOUT_PERIOD  0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define WD_CDB_1     0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define WD_CDB_2     0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define WD_CDB_3     0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define WD_CDB_4     0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define WD_CDB_5     0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define WD_CDB_6     0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define WD_CDB_7     0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define WD_CDB_8     0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define WD_CDB_9     0x0b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define WD_CDB_10    0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define WD_CDB_11    0x0d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define WD_CDB_12    0x0e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define WD_TARGET_LUN      0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define WD_COMMAND_PHASE   0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define WD_SYNCHRONOUS_TRANSFER 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define WD_TRANSFER_COUNT_MSB 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define WD_TRANSFER_COUNT  0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define WD_TRANSFER_COUNT_LSB 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define WD_DESTINATION_ID  0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define WD_SOURCE_ID    0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define WD_SCSI_STATUS     0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define WD_COMMAND      0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define WD_DATA      0x19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define WD_QUEUE_TAG    0x1a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define WD_AUXILIARY_STATUS   0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) /* WD commands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define WD_CMD_RESET    0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define WD_CMD_ABORT    0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define WD_CMD_ASSERT_ATN  0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define WD_CMD_NEGATE_ACK  0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define WD_CMD_DISCONNECT  0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define WD_CMD_RESELECT    0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define WD_CMD_SEL_ATN     0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define WD_CMD_SEL      0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define WD_CMD_SEL_ATN_XFER   0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define WD_CMD_SEL_XFER    0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define WD_CMD_RESEL_RECEIVE  0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define WD_CMD_RESEL_SEND  0x0b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define WD_CMD_WAIT_SEL_RECEIVE 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define WD_CMD_TRANS_ADDR  0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define WD_CMD_TRANS_INFO  0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define WD_CMD_TRANSFER_PAD   0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define WD_CMD_SBT_MODE    0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) /* ASR register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define ASR_INT         (0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define ASR_LCI         (0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define ASR_BSY         (0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define ASR_CIP         (0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define ASR_PE          (0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define ASR_DBR         (0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) /* SCSI Bus Phases */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define PHS_DATA_OUT    0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define PHS_DATA_IN     0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define PHS_COMMAND     0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define PHS_STATUS      0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define PHS_MESS_OUT    0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define PHS_MESS_IN     0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* Command Status Register definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)   /* reset state interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define CSR_RESET    0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define CSR_RESET_AF    0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)   /* successful completion interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define CSR_RESELECT    0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define CSR_SELECT      0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define CSR_SEL_XFER_DONE  0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define CSR_XFER_DONE      0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)   /* paused or aborted interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define CSR_MSGIN    0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define CSR_SDP         0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define CSR_SEL_ABORT      0x22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define CSR_RESEL_ABORT    0x25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define CSR_RESEL_ABORT_AM 0x27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define CSR_ABORT    0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)   /* terminated interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define CSR_INVALID     0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define CSR_UNEXP_DISC     0x41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define CSR_TIMEOUT     0x42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define CSR_PARITY      0x43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define CSR_PARITY_ATN     0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define CSR_BAD_STATUS     0x45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define CSR_UNEXP    0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)   /* service required interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define CSR_RESEL    0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define CSR_RESEL_AM    0x81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define CSR_DISC     0x85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define CSR_SRV_REQ     0x88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)    /* Own ID/CDB Size register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define OWNID_EAF    0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define OWNID_EHP    0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define OWNID_RAF    0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define OWNID_FS_8   0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define OWNID_FS_12  0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define OWNID_FS_16  0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)    /* define these so we don't have to change a2091.c, etc. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define WD33C93_FS_8_10  OWNID_FS_8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define WD33C93_FS_12_15 OWNID_FS_12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define WD33C93_FS_16_20 OWNID_FS_16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)    /* pass input-clock explicitly. accepted mhz values are 8-10,12-20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define WD33C93_FS_MHZ(mhz) (mhz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)    /* Control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define CTRL_HSP     0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define CTRL_HA      0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define CTRL_IDI     0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define CTRL_EDI     0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define CTRL_HHP     0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define CTRL_POLLED  0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define CTRL_BURST   0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define CTRL_BUS     0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define CTRL_DMA     0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)    /* Timeout Period register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define TIMEOUT_PERIOD_VALUE  20    /* 20 = 200 ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)    /* Synchronous Transfer Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define STR_FSS      0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)    /* Destination ID register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define DSTID_DPD    0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define DATA_OUT_DIR 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define DATA_IN_DIR  1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define DSTID_SCC    0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)    /* Source ID register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define SRCID_MASK   0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define SRCID_SIV    0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define SRCID_DSP    0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define SRCID_ES     0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define SRCID_ER     0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)    /* This is what the 3393 chip looks like to us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #ifdef CONFIG_WD33C93_PIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)    unsigned int   SASR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)    unsigned int   SCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)    volatile unsigned char  *SASR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)    volatile unsigned char  *SCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) } wd33c93_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) typedef int (*dma_setup_t) (struct scsi_cmnd *SCpnt, int dir_in);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) typedef void (*dma_stop_t) (struct Scsi_Host *instance,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 		struct scsi_cmnd *SCpnt, int status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define ILLEGAL_STATUS_BYTE   0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define DEFAULT_SX_PER   376     /* (ns) fairly safe */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define DEFAULT_SX_OFF   0       /* aka async */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define OPTIMUM_SX_PER   252     /* (ns) best we can do (mult-of-4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define OPTIMUM_SX_OFF   12      /* size of wd3393 fifo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) struct sx_period {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)    unsigned int   period_ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)    uchar          reg_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)    };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /* FEF: defines for hostdata->dma_buffer_pool */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define BUF_CHIP_ALLOCED 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define BUF_SCSI_ALLOCED 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) struct WD33C93_hostdata {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)     struct Scsi_Host *next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)     wd33c93_regs     regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)     spinlock_t       lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)     uchar            clock_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)     uchar            chip;             /* what kind of wd33c93? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)     uchar            microcode;        /* microcode rev */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)     uchar            dma_buffer_pool;  /* FEF: buffer from chip_ram? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)     int              dma_dir;          /* data transfer dir. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)     dma_setup_t      dma_setup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)     dma_stop_t       dma_stop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)     unsigned int     dma_xfer_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)     uchar            *dma_bounce_buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)     unsigned int     dma_bounce_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)     volatile uchar   busy[8];          /* index = target, bit = lun */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)     volatile struct scsi_cmnd *input_Q;       /* commands waiting to be started */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)     volatile struct scsi_cmnd *selecting;     /* trying to select this command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)     volatile struct scsi_cmnd *connected;     /* currently connected command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)     volatile struct scsi_cmnd *disconnected_Q;/* commands waiting for reconnect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)     uchar            state;            /* what we are currently doing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)     uchar            dma;              /* current state of DMA (on/off) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)     uchar            level2;           /* extent to which Level-2 commands are used */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)     uchar            disconnect;       /* disconnect/reselect policy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)     unsigned int     args;             /* set from command-line argument */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)     uchar            incoming_msg[8];  /* filled during message_in phase */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)     int              incoming_ptr;     /* mainly used with EXTENDED messages */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)     uchar            outgoing_msg[8];  /* send this during next message_out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)     int              outgoing_len;     /* length of outgoing message */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)     unsigned int     default_sx_per;   /* default transfer period for SCSI bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)     uchar            sync_xfer[8];     /* sync_xfer reg settings per target */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)     uchar            sync_stat[8];     /* status of sync negotiation per target */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)     uchar            no_sync;          /* bitmask: don't do sync on these targets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)     uchar            no_dma;           /* set this flag to disable DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)     uchar            dma_mode;         /* DMA Burst Mode or Single Byte DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)     uchar            fast;             /* set this flag to enable Fast SCSI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)     struct sx_period sx_table[9];      /* transfer periods for actual DTC-setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #ifdef PROC_INTERFACE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)     uchar            proc;             /* bitmask: what's in proc output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #ifdef PROC_STATISTICS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)     unsigned long    cmd_cnt[8];       /* # of commands issued per target */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)     unsigned long    int_cnt;          /* # of interrupts serviced */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)     unsigned long    pio_cnt;          /* # of pio data transfers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)     unsigned long    dma_cnt;          /* # of DMA data transfers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)     unsigned long    disc_allowed_cnt[8]; /* # of disconnects allowed per target */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)     unsigned long    disc_done_cnt[8]; /* # of disconnects done per target*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)     };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) /* defines for hostdata->chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define C_WD33C93       0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define C_WD33C93A      1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define C_WD33C93B      2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define C_UNKNOWN_CHIP  100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) /* defines for hostdata->state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define S_UNCONNECTED         0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define S_SELECTING           1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define S_RUNNING_LEVEL2      2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define S_CONNECTED           3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define S_PRE_TMP_DISC        4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define S_PRE_CMP_DISC        5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) /* defines for hostdata->dma */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define D_DMA_OFF          0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define D_DMA_RUNNING      1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) /* defines for hostdata->level2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) /* NOTE: only the first 3 are implemented so far */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define L2_NONE      1  /* no combination commands - we get lots of ints */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define L2_SELECT    2  /* start with SEL_ATN_XFER, but never resume it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define L2_BASIC     3  /* resume after STATUS ints & RDP messages */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define L2_DATA      4  /* resume after DATA_IN/OUT ints */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define L2_MOST      5  /* resume after anything except a RESELECT int */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define L2_RESELECT  6  /* resume after everything, including RESELECT ints */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define L2_ALL       7  /* always resume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) /* defines for hostdata->disconnect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define DIS_NEVER    0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define DIS_ADAPTIVE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define DIS_ALWAYS   2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) /* defines for hostdata->args */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define DB_TEST1              1<<0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define DB_TEST2              1<<1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define DB_QUEUE_COMMAND      1<<2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define DB_EXECUTE            1<<3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define DB_INTR               1<<4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define DB_TRANSFER           1<<5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define DB_MASK               0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) /* defines for hostdata->sync_stat[] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define SS_UNSET     0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define SS_FIRST     1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define SS_WAITING   2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define SS_SET       3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) /* defines for hostdata->proc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define PR_VERSION   1<<0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define PR_INFO      1<<1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define PR_STATISTICS 1<<2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define PR_CONNECTED 1<<3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define PR_INPUTQ    1<<4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define PR_DISCQ     1<<5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define PR_TEST      1<<6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define PR_STOP      1<<7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) void wd33c93_init (struct Scsi_Host *instance, const wd33c93_regs regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)          dma_setup_t setup, dma_stop_t stop, int clock_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) int wd33c93_abort (struct scsi_cmnd *cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) int wd33c93_queuecommand (struct Scsi_Host *h, struct scsi_cmnd *cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) void wd33c93_intr (struct Scsi_Host *instance);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) int wd33c93_show_info(struct seq_file *, struct Scsi_Host *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) int wd33c93_write_info(struct Scsi_Host *, char *, int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) int wd33c93_host_reset (struct scsi_cmnd *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #endif /* WD33C93_H */