Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * drivers/scsi/ufs/unipro.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2013 Samsung Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #ifndef _UNIPRO_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #define _UNIPRO_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  * M-TX Configuration Attributes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #define TX_HIBERN8TIME_CAPABILITY		0x000F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define TX_MODE					0x0021
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define TX_HSRATE_SERIES			0x0022
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define TX_HSGEAR				0x0023
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define TX_PWMGEAR				0x0024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define TX_AMPLITUDE				0x0025
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define TX_HS_SLEWRATE				0x0026
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define TX_SYNC_SOURCE				0x0027
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define TX_HS_SYNC_LENGTH			0x0028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define TX_HS_PREPARE_LENGTH			0x0029
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define TX_LS_PREPARE_LENGTH			0x002A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define TX_HIBERN8_CONTROL			0x002B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define TX_LCC_ENABLE				0x002C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define TX_PWM_BURST_CLOSURE_EXTENSION		0x002D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define TX_BYPASS_8B10B_ENABLE			0x002E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define TX_DRIVER_POLARITY			0x002F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define TX_HS_UNTERMINATED_LINE_DRIVE_ENABLE	0x0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define TX_LS_TERMINATED_LINE_DRIVE_ENABLE	0x0031
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define TX_LCC_SEQUENCER			0x0032
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define TX_MIN_ACTIVATETIME			0x0033
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define TX_PWM_G6_G7_SYNC_LENGTH		0x0034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define TX_REFCLKFREQ				0x00EB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define TX_CFGCLKFREQVAL			0x00EC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define	CFGEXTRATTR				0x00F0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define DITHERCTRL2				0x00F1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41)  * M-RX Configuration Attributes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define RX_MODE					0x00A1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define RX_HSRATE_SERIES			0x00A2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define RX_HSGEAR				0x00A3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define RX_PWMGEAR				0x00A4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define RX_LS_TERMINATED_ENABLE			0x00A5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define RX_HS_UNTERMINATED_ENABLE		0x00A6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define RX_ENTER_HIBERN8			0x00A7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define RX_BYPASS_8B10B_ENABLE			0x00A8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define RX_TERMINATION_FORCE_ENABLE		0x00A9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define RX_MIN_ACTIVATETIME_CAPABILITY		0x008F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define RX_HIBERN8TIME_CAPABILITY		0x0092
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define RX_REFCLKFREQ				0x00EB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define	RX_CFGCLKFREQVAL			0x00EC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define CFGWIDEINLN				0x00F0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define CFGRXCDR8				0x00BA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define ENARXDIRECTCFG4				0x00F2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define CFGRXOVR8				0x00BD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define RXDIRECTCTRL2				0x00C7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define ENARXDIRECTCFG3				0x00F3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define RXCALCTRL				0x00B4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define ENARXDIRECTCFG2				0x00F4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define CFGRXOVR4				0x00E9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define RXSQCTRL				0x00B5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define CFGRXOVR6				0x00BF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define RX_HS_G1_SYNC_LENGTH_CAP		0x008B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define RX_HS_G1_PREP_LENGTH_CAP		0x008C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define RX_HS_G2_SYNC_LENGTH_CAP		0x0094
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define RX_HS_G3_SYNC_LENGTH_CAP		0x0095
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define RX_HS_G2_PREP_LENGTH_CAP		0x0096
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define RX_HS_G3_PREP_LENGTH_CAP		0x0097
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define RX_ADV_GRANULARITY_CAP			0x0098
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define RX_MIN_ACTIVATETIME_CAP			0x008F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define RX_HIBERN8TIME_CAP			0x0092
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define RX_ADV_HIBERN8TIME_CAP			0x0099
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define RX_ADV_MIN_ACTIVATETIME_CAP		0x009A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define is_mphy_tx_attr(attr)			(attr < RX_MODE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define RX_ADV_FINE_GRAN_STEP(x)		((((x) & 0x3) << 1) | 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define SYNC_LEN_FINE(x)			((x) & 0x3F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define SYNC_LEN_COARSE(x)			((1 << 6) | ((x) & 0x3F))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define PREP_LEN(x)				((x) & 0xF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define RX_MIN_ACTIVATETIME_UNIT_US		100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define HIBERN8TIME_UNIT_US			100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90)  * Common Block Attributes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define TX_GLOBALHIBERNATE			UNIPRO_CB_OFFSET(0x002B)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define REFCLKMODE				UNIPRO_CB_OFFSET(0x00BF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define DIRECTCTRL19				UNIPRO_CB_OFFSET(0x00CD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define DIRECTCTRL10				UNIPRO_CB_OFFSET(0x00E6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define CDIRECTCTRL6				UNIPRO_CB_OFFSET(0x00EA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define RTOBSERVESELECT				UNIPRO_CB_OFFSET(0x00F0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define CBDIVFACTOR				UNIPRO_CB_OFFSET(0x00F1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define CBDCOCTRL5				UNIPRO_CB_OFFSET(0x00F3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define CBPRGPLL2				UNIPRO_CB_OFFSET(0x00F8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define CBPRGTUNING				UNIPRO_CB_OFFSET(0x00FB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define UNIPRO_CB_OFFSET(x)			(0x8000 | x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)  * PHY Adpater attributes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define PA_ACTIVETXDATALANES	0x1560
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define PA_ACTIVERXDATALANES	0x1580
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define PA_TXTRAILINGCLOCKS	0x1564
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define PA_PHY_TYPE		0x1500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define PA_AVAILTXDATALANES	0x1520
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define PA_AVAILRXDATALANES	0x1540
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define PA_MINRXTRAILINGCLOCKS	0x1543
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define PA_TXPWRSTATUS		0x1567
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define PA_RXPWRSTATUS		0x1582
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define PA_TXFORCECLOCK		0x1562
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define PA_TXPWRMODE		0x1563
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define PA_LEGACYDPHYESCDL	0x1570
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define PA_MAXTXSPEEDFAST	0x1521
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define PA_MAXTXSPEEDSLOW	0x1522
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define PA_MAXRXSPEEDFAST	0x1541
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define PA_MAXRXSPEEDSLOW	0x1542
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define PA_TXLINKSTARTUPHS	0x1544
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define PA_LOCAL_TX_LCC_ENABLE	0x155E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define PA_TXSPEEDFAST		0x1565
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define PA_TXSPEEDSLOW		0x1566
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define PA_REMOTEVERINFO	0x15A0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define PA_TXGEAR		0x1568
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define PA_TXTERMINATION	0x1569
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define PA_HSSERIES		0x156A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define PA_PWRMODE		0x1571
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define PA_RXGEAR		0x1583
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define PA_RXTERMINATION	0x1584
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define PA_MAXRXPWMGEAR		0x1586
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define PA_MAXRXHSGEAR		0x1587
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define PA_RXHSUNTERMCAP	0x15A5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define PA_RXLSTERMCAP		0x15A6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define PA_GRANULARITY		0x15AA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define PA_PACPREQTIMEOUT	0x1590
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define PA_PACPREQEOBTIMEOUT	0x1591
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define PA_HIBERN8TIME		0x15A7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define PA_LOCALVERINFO		0x15A9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define PA_GRANULARITY		0x15AA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define PA_TACTIVATE		0x15A8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define PA_PACPFRAMECOUNT	0x15C0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define PA_PACPERRORCOUNT	0x15C1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define PA_PHYTESTCONTROL	0x15C2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define PA_PWRMODEUSERDATA0	0x15B0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define PA_PWRMODEUSERDATA1	0x15B1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define PA_PWRMODEUSERDATA2	0x15B2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define PA_PWRMODEUSERDATA3	0x15B3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define PA_PWRMODEUSERDATA4	0x15B4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define PA_PWRMODEUSERDATA5	0x15B5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define PA_PWRMODEUSERDATA6	0x15B6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define PA_PWRMODEUSERDATA7	0x15B7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define PA_PWRMODEUSERDATA8	0x15B8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define PA_PWRMODEUSERDATA9	0x15B9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define PA_PWRMODEUSERDATA10	0x15BA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define PA_PWRMODEUSERDATA11	0x15BB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define PA_CONNECTEDTXDATALANES	0x1561
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define PA_CONNECTEDRXDATALANES	0x1581
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define PA_LOGICALLANEMAP	0x15A1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define PA_SLEEPNOCONFIGTIME	0x15A2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define PA_STALLNOCONFIGTIME	0x15A3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define PA_SAVECONFIGTIME	0x15A4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define PA_TXHSADAPTTYPE       0x15D4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /* Adpat type for PA_TXHSADAPTTYPE attribute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define PA_REFRESH_ADAPT       0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define PA_INITIAL_ADAPT       0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define PA_NO_ADAPT            0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define PA_TACTIVATE_TIME_UNIT_US	10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define PA_HIBERN8_TIME_UNIT_US		100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /*Other attributes*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define VS_MPHYCFGUPDT		0xD085
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define VS_DEBUGOMC		0xD09E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define VS_POWERSTATE		0xD083
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define PA_GRANULARITY_MIN_VAL	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define PA_GRANULARITY_MAX_VAL	6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /* PHY Adapter Protocol Constants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define PA_MAXDATALANES	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define DL_FC0ProtectionTimeOutVal_Default	8191
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define DL_TC0ReplayTimeOutVal_Default		65535
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define DL_AFC0ReqTimeOutVal_Default		32767
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define DL_FC1ProtectionTimeOutVal_Default	8191
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define DL_TC1ReplayTimeOutVal_Default		65535
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define DL_AFC1ReqTimeOutVal_Default		32767
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define DME_LocalFC0ProtectionTimeOutVal	0xD041
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define DME_LocalTC0ReplayTimeOutVal		0xD042
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define DME_LocalAFC0ReqTimeOutVal		0xD043
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /* PA power modes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	FAST_MODE	= 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	SLOW_MODE	= 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	FASTAUTO_MODE	= 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	SLOWAUTO_MODE	= 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	UNCHANGED	= 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define PWRMODE_MASK		0xF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define PWRMODE_RX_OFFSET	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /* PA TX/RX Frequency Series */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	PA_HS_MODE_A	= 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	PA_HS_MODE_B	= 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) enum ufs_pwm_gear_tag {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	UFS_PWM_DONT_CHANGE,	/* Don't change Gear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	UFS_PWM_G1,		/* PWM Gear 1 (default for reset) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	UFS_PWM_G2,		/* PWM Gear 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	UFS_PWM_G3,		/* PWM Gear 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	UFS_PWM_G4,		/* PWM Gear 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	UFS_PWM_G5,		/* PWM Gear 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	UFS_PWM_G6,		/* PWM Gear 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	UFS_PWM_G7,		/* PWM Gear 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) enum ufs_hs_gear_tag {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	UFS_HS_DONT_CHANGE,	/* Don't change Gear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	UFS_HS_G1,		/* HS Gear 1 (default for reset) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	UFS_HS_G2,		/* HS Gear 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	UFS_HS_G3,		/* HS Gear 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	UFS_HS_G4,		/* HS Gear 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) enum ufs_unipro_ver {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	UFS_UNIPRO_VER_RESERVED = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	UFS_UNIPRO_VER_1_40 = 1, /* UniPro version 1.40 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	UFS_UNIPRO_VER_1_41 = 2, /* UniPro version 1.41 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	UFS_UNIPRO_VER_1_6  = 3, /* UniPro version 1.6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	UFS_UNIPRO_VER_1_61 = 4, /* UniPro version 1.61 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	UFS_UNIPRO_VER_1_8  = 5, /* UniPro version 1.8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	UFS_UNIPRO_VER_MAX  = 6, /* UniPro unsupported version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	/* UniPro version field mask in PA_LOCALVERINFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	UFS_UNIPRO_VER_MASK = 0xF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)  * Data Link Layer Attributes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define DL_TC0TXFCTHRESHOLD	0x2040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define DL_FC0PROTTIMEOUTVAL	0x2041
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define DL_TC0REPLAYTIMEOUTVAL	0x2042
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define DL_AFC0REQTIMEOUTVAL	0x2043
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define DL_AFC0CREDITTHRESHOLD	0x2044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define DL_TC0OUTACKTHRESHOLD	0x2045
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define DL_TC1TXFCTHRESHOLD	0x2060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define DL_FC1PROTTIMEOUTVAL	0x2061
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define DL_TC1REPLAYTIMEOUTVAL	0x2062
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define DL_AFC1REQTIMEOUTVAL	0x2063
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define DL_AFC1CREDITTHRESHOLD	0x2064
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define DL_TC1OUTACKTHRESHOLD	0x2065
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define DL_TXPREEMPTIONCAP	0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define DL_TC0TXMAXSDUSIZE	0x2001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define DL_TC0RXINITCREDITVAL	0x2002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define DL_TC0TXBUFFERSIZE	0x2005
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define DL_PEERTC0PRESENT	0x2046
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define DL_PEERTC0RXINITCREVAL	0x2047
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define DL_TC1TXMAXSDUSIZE	0x2003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define DL_TC1RXINITCREDITVAL	0x2004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define DL_TC1TXBUFFERSIZE	0x2006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define DL_PEERTC1PRESENT	0x2066
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define DL_PEERTC1RXINITCREVAL	0x2067
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)  * Network Layer Attributes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define N_DEVICEID		0x3000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define N_DEVICEID_VALID	0x3001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define N_TC0TXMAXSDUSIZE	0x3020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define N_TC1TXMAXSDUSIZE	0x3021
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)  * Transport Layer Attributes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define T_NUMCPORTS		0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define T_NUMTESTFEATURES	0x4001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define T_CONNECTIONSTATE	0x4020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define T_PEERDEVICEID		0x4021
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define T_PEERCPORTID		0x4022
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define T_TRAFFICCLASS		0x4023
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define T_PROTOCOLID		0x4024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define T_CPORTFLAGS		0x4025
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define T_TXTOKENVALUE		0x4026
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define T_RXTOKENVALUE		0x4027
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define T_LOCALBUFFERSPACE	0x4028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define T_PEERBUFFERSPACE	0x4029
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define T_CREDITSTOSEND		0x402A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define T_CPORTMODE		0x402B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define T_TC0TXMAXSDUSIZE	0x4060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define T_TC1TXMAXSDUSIZE	0x4061
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #ifdef FALSE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #undef FALSE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #ifdef TRUE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #undef TRUE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) /* Boolean attribute values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	FALSE = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	TRUE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) /* CPort setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define E2EFC_ON	(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define E2EFC_OFF	(0 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define CSD_N_ON	(0 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define CSD_N_OFF	(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define CSV_N_ON	(0 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define CSV_N_OFF	(1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define CPORT_DEF_FLAGS	(CSV_N_OFF | CSD_N_OFF | E2EFC_OFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) /* CPort connection state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	CPORT_IDLE = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	CPORT_CONNECTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #endif /* _UNIPRO_H_ */