^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Universal Flash Storage Host controller driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2011-2013 Samsung India Software Operations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Authors:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Santosh Yaraganavi <santosh.sy@samsung.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Vinayak Holikatti <h.vinayak@samsung.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #ifndef _UFSHCI_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define _UFSHCI_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) TASK_REQ_UPIU_SIZE_DWORDS = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) TASK_RSP_UPIU_SIZE_DWORDS = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) ALIGNED_UPIU_SIZE = 512,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /* UFSHCI Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) REG_CONTROLLER_CAPABILITIES = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) REG_UFS_VERSION = 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) REG_CONTROLLER_DEV_ID = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) REG_CONTROLLER_PROD_ID = 0x14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) REG_AUTO_HIBERNATE_IDLE_TIMER = 0x18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) REG_INTERRUPT_STATUS = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) REG_INTERRUPT_ENABLE = 0x24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) REG_CONTROLLER_STATUS = 0x30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) REG_CONTROLLER_ENABLE = 0x34,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER = 0x38,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) REG_UIC_ERROR_CODE_DATA_LINK_LAYER = 0x3C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) REG_UIC_ERROR_CODE_NETWORK_LAYER = 0x40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) REG_UIC_ERROR_CODE_TRANSPORT_LAYER = 0x44,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) REG_UIC_ERROR_CODE_DME = 0x48,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL = 0x4C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) REG_UTP_TRANSFER_REQ_LIST_BASE_L = 0x50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) REG_UTP_TRANSFER_REQ_LIST_BASE_H = 0x54,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) REG_UTP_TRANSFER_REQ_DOOR_BELL = 0x58,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) REG_UTP_TRANSFER_REQ_LIST_CLEAR = 0x5C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) REG_UTP_TRANSFER_REQ_LIST_RUN_STOP = 0x60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) REG_UTP_TRANSFER_REQ_LIST_COMPL = 0x64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) REG_UTP_TASK_REQ_LIST_BASE_L = 0x70,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) REG_UTP_TASK_REQ_LIST_BASE_H = 0x74,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) REG_UTP_TASK_REQ_DOOR_BELL = 0x78,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) REG_UTP_TASK_REQ_LIST_CLEAR = 0x7C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) REG_UTP_TASK_REQ_LIST_RUN_STOP = 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) REG_UIC_COMMAND = 0x90,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) REG_UIC_COMMAND_ARG_1 = 0x94,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) REG_UIC_COMMAND_ARG_2 = 0x98,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) REG_UIC_COMMAND_ARG_3 = 0x9C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) UFSHCI_REG_SPACE_SIZE = 0xA0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) REG_UFS_CCAP = 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) REG_UFS_CRYPTOCAP = 0x104,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) UFSHCI_CRYPTO_REG_SPACE_SIZE = 0x400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /* Controller capability masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) MASK_TRANSFER_REQUESTS_SLOTS = 0x0000001F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) MASK_TASK_MANAGEMENT_REQUEST_SLOTS = 0x00070000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) MASK_AUTO_HIBERN8_SUPPORT = 0x00800000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) MASK_64_ADDRESSING_SUPPORT = 0x01000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) MASK_OUT_OF_ORDER_DATA_DELIVERY_SUPPORT = 0x02000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) MASK_UIC_DME_TEST_MODE_SUPPORT = 0x04000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) MASK_CRYPTO_SUPPORT = 0x10000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define UFS_MASK(mask, offset) ((mask) << (offset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* UFS Version 08h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define MINOR_VERSION_NUM_MASK UFS_MASK(0xFFFF, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define MAJOR_VERSION_NUM_MASK UFS_MASK(0xFFFF, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * Controller UFSHCI version
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * - 2.x and newer use the following scheme:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * major << 8 + minor << 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * - 1.x has been converted to match this in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * ufshcd_get_ufs_version()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) static inline u32 ufshci_version(u32 major, u32 minor)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) return (major << 8) + (minor << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * HCDDID - Host Controller Identification Descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * - Device ID and Device Class 10h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define DEVICE_CLASS UFS_MASK(0xFFFF, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define DEVICE_ID UFS_MASK(0xFF, 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * HCPMID - Host Controller Identification Descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * - Product/Manufacturer ID 14h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define MANUFACTURE_ID_MASK UFS_MASK(0xFFFF, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define PRODUCT_ID_MASK UFS_MASK(0xFFFF, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* AHIT - Auto-Hibernate Idle Timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define UFSHCI_AHIBERN8_TIMER_MASK GENMASK(9, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define UFSHCI_AHIBERN8_SCALE_MASK GENMASK(12, 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define UFSHCI_AHIBERN8_SCALE_FACTOR 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define UFSHCI_AHIBERN8_MAX (1023 * 100000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * IS - Interrupt Status - 20h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define UTP_TRANSFER_REQ_COMPL 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define UIC_DME_END_PT_RESET 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define UIC_ERROR 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define UIC_TEST_MODE 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define UIC_POWER_MODE 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define UIC_HIBERNATE_EXIT 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define UIC_HIBERNATE_ENTER 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define UIC_LINK_LOST 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define UIC_LINK_STARTUP 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define UTP_TASK_REQ_COMPL 0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define UIC_COMMAND_COMPL 0x400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define DEVICE_FATAL_ERROR 0x800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define CONTROLLER_FATAL_ERROR 0x10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define SYSTEM_BUS_FATAL_ERROR 0x20000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define CRYPTO_ENGINE_FATAL_ERROR 0x40000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define UFSHCD_UIC_HIBERN8_MASK (UIC_HIBERNATE_ENTER |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) UIC_HIBERNATE_EXIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define UFSHCD_UIC_PWR_MASK (UFSHCD_UIC_HIBERN8_MASK |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) UIC_POWER_MODE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define UFSHCD_UIC_MASK (UIC_COMMAND_COMPL | UFSHCD_UIC_PWR_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define UFSHCD_ERROR_MASK (UIC_ERROR |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) DEVICE_FATAL_ERROR |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) CONTROLLER_FATAL_ERROR |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) SYSTEM_BUS_FATAL_ERROR |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) CRYPTO_ENGINE_FATAL_ERROR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define INT_FATAL_ERRORS (DEVICE_FATAL_ERROR |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) CONTROLLER_FATAL_ERROR |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) SYSTEM_BUS_FATAL_ERROR |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) CRYPTO_ENGINE_FATAL_ERROR |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) UIC_LINK_LOST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /* HCS - Host Controller Status 30h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define DEVICE_PRESENT 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define UTP_TRANSFER_REQ_LIST_READY 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define UTP_TASK_REQ_LIST_READY 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define UIC_COMMAND_READY 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define HOST_ERROR_INDICATOR 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define DEVICE_ERROR_INDICATOR 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define UIC_POWER_MODE_CHANGE_REQ_STATUS_MASK UFS_MASK(0x7, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define UFSHCD_STATUS_READY (UTP_TRANSFER_REQ_LIST_READY |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) UTP_TASK_REQ_LIST_READY |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) UIC_COMMAND_READY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) PWR_OK = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) PWR_LOCAL = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) PWR_REMOTE = 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) PWR_BUSY = 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) PWR_ERROR_CAP = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) PWR_FATAL_ERROR = 0x05,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /* HCE - Host Controller Enable 34h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define CONTROLLER_ENABLE 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define CONTROLLER_DISABLE 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define CRYPTO_GENERAL_ENABLE 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /* UECPA - Host UIC Error Code PHY Adapter Layer 38h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define UIC_PHY_ADAPTER_LAYER_ERROR 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define UIC_PHY_ADAPTER_LAYER_ERROR_CODE_MASK 0x1F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define UIC_PHY_ADAPTER_LAYER_LANE_ERR_MASK 0xF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define UIC_PHY_ADAPTER_LAYER_GENERIC_ERROR 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /* UECDL - Host UIC Error Code Data Link Layer 3Ch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define UIC_DATA_LINK_LAYER_ERROR 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define UIC_DATA_LINK_LAYER_ERROR_CODE_MASK 0xFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define UIC_DATA_LINK_LAYER_ERROR_TCX_REP_TIMER_EXP 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define UIC_DATA_LINK_LAYER_ERROR_AFCX_REQ_TIMER_EXP 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define UIC_DATA_LINK_LAYER_ERROR_FCX_PRO_TIMER_EXP 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define UIC_DATA_LINK_LAYER_ERROR_RX_BUF_OF 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define UIC_DATA_LINK_LAYER_ERROR_PA_INIT 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define UIC_DATA_LINK_LAYER_ERROR_NAC_RECEIVED 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define UIC_DATA_LINK_LAYER_ERROR_TCx_REPLAY_TIMEOUT 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) /* UECN - Host UIC Error Code Network Layer 40h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define UIC_NETWORK_LAYER_ERROR 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define UIC_NETWORK_LAYER_ERROR_CODE_MASK 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define UIC_NETWORK_UNSUPPORTED_HEADER_TYPE 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define UIC_NETWORK_BAD_DEVICEID_ENC 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define UIC_NETWORK_LHDR_TRAP_PACKET_DROPPING 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) /* UECT - Host UIC Error Code Transport Layer 44h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define UIC_TRANSPORT_LAYER_ERROR 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define UIC_TRANSPORT_LAYER_ERROR_CODE_MASK 0x7F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define UIC_TRANSPORT_UNSUPPORTED_HEADER_TYPE 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define UIC_TRANSPORT_UNKNOWN_CPORTID 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define UIC_TRANSPORT_NO_CONNECTION_RX 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define UIC_TRANSPORT_CONTROLLED_SEGMENT_DROPPING 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define UIC_TRANSPORT_BAD_TC 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define UIC_TRANSPORT_E2E_CREDIT_OVERFOW 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define UIC_TRANSPORT_SAFETY_VALUE_DROPPING 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /* UECDME - Host UIC Error Code DME 48h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define UIC_DME_ERROR 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define UIC_DME_ERROR_CODE_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) /* UTRIACR - Interrupt Aggregation control register - 0x4Ch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define INT_AGGR_TIMEOUT_VAL_MASK 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define INT_AGGR_COUNTER_THRESHOLD_MASK UFS_MASK(0x1F, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define INT_AGGR_COUNTER_AND_TIMER_RESET 0x10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define INT_AGGR_STATUS_BIT 0x100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define INT_AGGR_PARAM_WRITE 0x1000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define INT_AGGR_ENABLE 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) /* UTRLRSR - UTP Transfer Request Run-Stop Register 60h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) /* UTMRLRSR - UTP Task Management Request Run-Stop Register 80h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define UTP_TASK_REQ_LIST_RUN_STOP_BIT 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) /* UICCMD - UIC Command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define COMMAND_OPCODE_MASK 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define GEN_SELECTOR_INDEX_MASK 0xFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define MIB_ATTRIBUTE_MASK UFS_MASK(0xFFFF, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define RESET_LEVEL 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define ATTR_SET_TYPE_MASK UFS_MASK(0xFF, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define CONFIG_RESULT_CODE_MASK 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define GENERIC_ERROR_CODE_MASK 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) /* GenSelectorIndex calculation macros for M-PHY attributes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define UIC_ARG_MPHY_TX_GEN_SEL_INDEX(lane) (lane)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define UIC_ARG_MPHY_RX_GEN_SEL_INDEX(lane) (PA_MAXDATALANES + (lane))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define UIC_ARG_MIB_SEL(attr, sel) ((((attr) & 0xFFFF) << 16) |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) ((sel) & 0xFFFF))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define UIC_ARG_MIB(attr) UIC_ARG_MIB_SEL(attr, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define UIC_ARG_ATTR_TYPE(t) (((t) & 0xFF) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define UIC_GET_ATTR_ID(v) (((v) >> 16) & 0xFFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) /* Link Status*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) enum link_status {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) UFSHCD_LINK_IS_DOWN = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) UFSHCD_LINK_IS_UP = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) /* UIC Commands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) enum uic_cmd_dme {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) UIC_CMD_DME_GET = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) UIC_CMD_DME_SET = 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) UIC_CMD_DME_PEER_GET = 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) UIC_CMD_DME_PEER_SET = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) UIC_CMD_DME_POWERON = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) UIC_CMD_DME_POWEROFF = 0x11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) UIC_CMD_DME_ENABLE = 0x12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) UIC_CMD_DME_RESET = 0x14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) UIC_CMD_DME_END_PT_RST = 0x15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) UIC_CMD_DME_LINK_STARTUP = 0x16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) UIC_CMD_DME_HIBER_ENTER = 0x17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) UIC_CMD_DME_HIBER_EXIT = 0x18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) UIC_CMD_DME_TEST_MODE = 0x1A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) /* UIC Config result code / Generic error code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) UIC_CMD_RESULT_SUCCESS = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) UIC_CMD_RESULT_INVALID_ATTR = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) UIC_CMD_RESULT_FAILURE = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) UIC_CMD_RESULT_INVALID_ATTR_VALUE = 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) UIC_CMD_RESULT_READ_ONLY_ATTR = 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) UIC_CMD_RESULT_WRITE_ONLY_ATTR = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) UIC_CMD_RESULT_BAD_INDEX = 0x05,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) UIC_CMD_RESULT_LOCKED_ATTR = 0x06,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) UIC_CMD_RESULT_BAD_TEST_FEATURE_INDEX = 0x07,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) UIC_CMD_RESULT_PEER_COMM_FAILURE = 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) UIC_CMD_RESULT_BUSY = 0x09,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) UIC_CMD_RESULT_DME_FAILURE = 0x0A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define MASK_UIC_COMMAND_RESULT 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define INT_AGGR_COUNTER_THLD_VAL(c) (((c) & 0x1F) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define INT_AGGR_TIMEOUT_VAL(t) (((t) & 0xFF) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) /* Interrupt disable masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) /* Interrupt disable mask for UFSHCI v1.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) INTERRUPT_MASK_ALL_VER_10 = 0x30FFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) INTERRUPT_MASK_RW_VER_10 = 0x30000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) /* Interrupt disable mask for UFSHCI v1.1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) INTERRUPT_MASK_ALL_VER_11 = 0x31FFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) /* Interrupt disable mask for UFSHCI v2.1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) INTERRUPT_MASK_ALL_VER_21 = 0x71FFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) /* CCAP - Crypto Capability 100h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) union ufs_crypto_capabilities {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) __le32 reg_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) u8 num_crypto_cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) u8 config_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) u8 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) u8 config_array_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) enum ufs_crypto_key_size {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) UFS_CRYPTO_KEY_SIZE_INVALID = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) UFS_CRYPTO_KEY_SIZE_128 = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) UFS_CRYPTO_KEY_SIZE_192 = 0x2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) UFS_CRYPTO_KEY_SIZE_256 = 0x3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) UFS_CRYPTO_KEY_SIZE_512 = 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) enum ufs_crypto_alg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) UFS_CRYPTO_ALG_AES_XTS = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) UFS_CRYPTO_ALG_BITLOCKER_AES_CBC = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) UFS_CRYPTO_ALG_AES_ECB = 0x2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) UFS_CRYPTO_ALG_ESSIV_AES_CBC = 0x3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) /* x-CRYPTOCAP - Crypto Capability X */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) union ufs_crypto_cap_entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) __le32 reg_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) u8 algorithm_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) u8 sdus_mask; /* Supported data unit size mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) u8 key_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) u8 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define UFS_CRYPTO_CONFIGURATION_ENABLE (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define UFS_CRYPTO_KEY_MAX_SIZE 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) /* x-CRYPTOCFG - Crypto Configuration X */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) union ufs_crypto_cfg_entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) __le32 reg_val[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) u8 crypto_key[UFS_CRYPTO_KEY_MAX_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) u8 data_unit_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) u8 crypto_cap_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) u8 reserved_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) u8 config_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) u8 reserved_multi_host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) u8 reserved_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) u8 vsb[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) u8 reserved_3[56];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) * Request Descriptor Definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) /* Transfer request command type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) UTP_CMD_TYPE_SCSI = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) UTP_CMD_TYPE_UFS = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) UTP_CMD_TYPE_DEV_MANAGE = 0x2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) /* To accommodate UFS2.0 required Command type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) UTP_CMD_TYPE_UFS_STORAGE = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) UTP_SCSI_COMMAND = 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) UTP_NATIVE_UFS_COMMAND = 0x10000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) UTP_DEVICE_MANAGEMENT_FUNCTION = 0x20000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) UTP_REQ_DESC_INT_CMD = 0x01000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) UTP_REQ_DESC_CRYPTO_ENABLE_CMD = 0x00800000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) /* UTP Transfer Request Data Direction (DD) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) UTP_NO_DATA_TRANSFER = 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) UTP_HOST_TO_DEVICE = 0x02000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) UTP_DEVICE_TO_HOST = 0x04000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) /* Overall command status values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) OCS_SUCCESS = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) OCS_INVALID_CMD_TABLE_ATTR = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) OCS_INVALID_PRDT_ATTR = 0x2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) OCS_MISMATCH_DATA_BUF_SIZE = 0x3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) OCS_MISMATCH_RESP_UPIU_SIZE = 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) OCS_PEER_COMM_FAILURE = 0x5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) OCS_ABORTED = 0x6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) OCS_FATAL_ERROR = 0x7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) OCS_DEVICE_FATAL_ERROR = 0x8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) OCS_INVALID_CRYPTO_CONFIG = 0x9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) OCS_GENERAL_CRYPTO_ERROR = 0xA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) OCS_INVALID_COMMAND_STATUS = 0x0F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) MASK_OCS = 0x0F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) /* The maximum length of the data byte count field in the PRDT is 256KB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #define PRDT_DATA_BYTE_COUNT_MAX (256 * 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) /* The granularity of the data byte count field in the PRDT is 32-bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define PRDT_DATA_BYTE_COUNT_PAD 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) * struct ufshcd_sg_entry - UFSHCI PRD Entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) * @base_addr: Lower 32bit physical address DW-0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) * @upper_addr: Upper 32bit physical address DW-1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) * @reserved: Reserved for future use DW-2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) * @size: size of physical segment DW-3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) struct ufshcd_sg_entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) __le32 base_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) __le32 upper_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) __le32 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) __le32 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) * followed by variant-specific fields if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) * hba->sg_entry_size != sizeof(struct ufshcd_sg_entry)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) * struct utp_transfer_cmd_desc - UFS Command Descriptor structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) * @command_upiu: Command UPIU Frame address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) * @response_upiu: Response UPIU Frame address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) * @prd_table: Physical Region Descriptor: an array of SG_ALL struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) * ufshcd_sg_entry's. Variant-specific fields may be present after each.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) struct utp_transfer_cmd_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) u8 command_upiu[ALIGNED_UPIU_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) u8 response_upiu[ALIGNED_UPIU_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) u8 prd_table[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) #define sizeof_utp_transfer_cmd_desc(hba) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) (sizeof(struct utp_transfer_cmd_desc) + SG_ALL * (hba)->sg_entry_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) * struct request_desc_header - Descriptor Header common to both UTRD and UTMRD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) * @dword0: Descriptor Header DW0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) * @dword1: Descriptor Header DW1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) * @dword2: Descriptor Header DW2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) * @dword3: Descriptor Header DW3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) struct request_desc_header {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) __le32 dword_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) __le32 dword_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) __le32 dword_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) __le32 dword_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) * struct utp_transfer_req_desc - UTRD structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) * @header: UTRD header DW-0 to DW-3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) * @command_desc_base_addr_lo: UCD base address low DW-4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) * @command_desc_base_addr_hi: UCD base address high DW-5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) * @response_upiu_length: response UPIU length DW-6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) * @response_upiu_offset: response UPIU offset DW-6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) * @prd_table_length: Physical region descriptor length DW-7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) * @prd_table_offset: Physical region descriptor offset DW-7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) struct utp_transfer_req_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) /* DW 0-3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) struct request_desc_header header;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) /* DW 4-5*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) __le32 command_desc_base_addr_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) __le32 command_desc_base_addr_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) /* DW 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) __le16 response_upiu_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) __le16 response_upiu_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) /* DW 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) __le16 prd_table_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) __le16 prd_table_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) * UTMRD structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) struct utp_task_req_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) /* DW 0-3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) struct request_desc_header header;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) /* DW 4-11 - Task request UPIU structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) struct utp_upiu_header req_header;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) __be32 input_param1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) __be32 input_param2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) __be32 input_param3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) __be32 __reserved1[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) /* DW 12-19 - Task Management Response UPIU structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) struct utp_upiu_header rsp_header;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) __be32 output_param1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) __be32 output_param2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) __be32 __reserved2[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) #endif /* End of Header */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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