Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * UFS Host driver for Synopsys Designware Core
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Copyright (C) 2015-2016 Synopsys, Inc. (www.synopsys.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  * Authors: Joao Pinto <jpinto@synopsys.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #ifndef _UFSHCI_DWC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define _UFSHCI_DWC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) /* DWC HC UFSHCI specific Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) enum dwc_specific_registers {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 	DWC_UFS_REG_HCLKDIV	= 0xFC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) /* Clock Divider Values: Hex equivalent of frequency in MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) enum clk_div_values {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 	DWC_UFS_REG_HCLKDIV_DIV_62_5	= 0x3e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 	DWC_UFS_REG_HCLKDIV_DIV_125	= 0x7d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	DWC_UFS_REG_HCLKDIV_DIV_200	= 0xc8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /* Selector Index */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) enum selector_index {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	SELIND_LN0_TX		= 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 	SELIND_LN1_TX		= 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	SELIND_LN0_RX		= 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	SELIND_LN1_RX		= 0x05,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #endif /* End of Header */