^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Universal Flash Storage Host controller driver Core
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2011-2013 Samsung India Software Operations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Authors:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Santosh Yaraganavi <santosh.sy@samsung.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Vinayak Holikatti <h.vinayak@samsung.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/async.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/devfreq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/nls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/bitfield.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/blk-pm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/blkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "ufshcd.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "ufshcd-add-info.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "ufs_quirks.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "unipro.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include "ufs-sysfs.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include "ufs-debugfs.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include "ufs_bsg.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include "ufshcd-crypto.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include "ufshpb.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <asm/unaligned.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/blkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define CREATE_TRACE_POINTS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <trace/events/ufs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #undef CREATE_TRACE_POINTS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <trace/hooks/ufshcd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define UFSHCD_ENABLE_INTRS (UTP_TRANSFER_REQ_COMPL |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) UTP_TASK_REQ_COMPL |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) UFSHCD_ERROR_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* UIC command timeout, unit: ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define UIC_CMD_TIMEOUT 5000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* NOP OUT retries waiting for NOP IN response */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define NOP_OUT_RETRIES 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /* Timeout after 50 msecs if NOP OUT hangs without response */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define NOP_OUT_TIMEOUT 50 /* msecs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /* Query request retries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define QUERY_REQ_RETRIES 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* Query request timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define QUERY_REQ_TIMEOUT 1500 /* 1.5 seconds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /* Task management command timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define TM_CMD_TIMEOUT 100 /* msecs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* maximum number of retries for a general UIC command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define UFS_UIC_COMMAND_RETRIES 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /* maximum number of link-startup retries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define DME_LINKSTARTUP_RETRIES 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /* Maximum retries for Hibern8 enter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define UIC_HIBERN8_ENTER_RETRIES 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* maximum number of reset retries before giving up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define MAX_HOST_RESET_RETRIES 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /* Expose the flag value from utp_upiu_query.value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define MASK_QUERY_UPIU_FLAG_LOC 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /* Interrupt aggregation default timeout, unit: 40us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define INT_AGGR_DEF_TO 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* default delay of autosuspend: 2000 ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define RPM_AUTOSUSPEND_DELAY_MS 2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* Default delay of RPM device flush delayed work */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define RPM_DEV_FLUSH_RECHECK_WORK_DELAY_MS 5000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* Default value of wait time before gating device ref clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define UFSHCD_REF_CLK_GATING_WAIT_US 0xFF /* microsecs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /* Polling time to wait for fDeviceInit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define FDEVICEINIT_COMPL_TIMEOUT 1500 /* millisecs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define ufshcd_toggle_vreg(_dev, _vreg, _on) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) ({ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) int _ret; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) if (_on) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) _ret = ufshcd_enable_vreg(_dev, _vreg); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) else \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) _ret = ufshcd_disable_vreg(_dev, _vreg); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) _ret; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define ufshcd_hex_dump(prefix_str, buf, len) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) size_t __len = (len); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) print_hex_dump(KERN_ERR, prefix_str, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) __len > 4 ? DUMP_PREFIX_OFFSET : DUMP_PREFIX_NONE,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 16, 4, buf, __len, false); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) int ufshcd_dump_regs(struct ufs_hba *hba, size_t offset, size_t len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) const char *prefix)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) u32 *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) size_t pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) if (offset % 4 != 0 || len % 4 != 0) /* keep readl happy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) regs = kzalloc(len, GFP_ATOMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) if (!regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) for (pos = 0; pos < len; pos += 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) regs[pos / 4] = ufshcd_readl(hba, offset + pos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) ufshcd_hex_dump(prefix, regs, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) kfree(regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) EXPORT_SYMBOL_GPL(ufshcd_dump_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) UFSHCD_MAX_CHANNEL = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) UFSHCD_MAX_ID = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) UFSHCD_NUM_RESERVED = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) UFSHCD_CMD_PER_LUN = 32 - UFSHCD_NUM_RESERVED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) UFSHCD_CAN_QUEUE = 32 - UFSHCD_NUM_RESERVED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /* UFSHCD states */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) UFSHCD_STATE_RESET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) UFSHCD_STATE_ERROR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) UFSHCD_STATE_OPERATIONAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) UFSHCD_STATE_EH_SCHEDULED_FATAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) UFSHCD_STATE_EH_SCHEDULED_NON_FATAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /* UFSHCD error handling flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) UFSHCD_EH_IN_PROGRESS = (1 << 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /* UFSHCD UIC layer error flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) UFSHCD_UIC_DL_PA_INIT_ERROR = (1 << 0), /* Data link layer error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) UFSHCD_UIC_DL_NAC_RECEIVED_ERROR = (1 << 1), /* Data link layer error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) UFSHCD_UIC_DL_TCx_REPLAY_ERROR = (1 << 2), /* Data link layer error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) UFSHCD_UIC_NL_ERROR = (1 << 3), /* Network layer error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) UFSHCD_UIC_TL_ERROR = (1 << 4), /* Transport Layer error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) UFSHCD_UIC_DME_ERROR = (1 << 5), /* DME error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) UFSHCD_UIC_PA_GENERIC_ERROR = (1 << 6), /* Generic PA error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define ufshcd_set_eh_in_progress(h) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) ((h)->eh_flags |= UFSHCD_EH_IN_PROGRESS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define ufshcd_eh_in_progress(h) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) ((h)->eh_flags & UFSHCD_EH_IN_PROGRESS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define ufshcd_clear_eh_in_progress(h) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) ((h)->eh_flags &= ~UFSHCD_EH_IN_PROGRESS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) struct ufs_pm_lvl_states ufs_pm_lvl_states[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) {UFS_ACTIVE_PWR_MODE, UIC_LINK_ACTIVE_STATE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {UFS_ACTIVE_PWR_MODE, UIC_LINK_HIBERN8_STATE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {UFS_SLEEP_PWR_MODE, UIC_LINK_ACTIVE_STATE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {UFS_SLEEP_PWR_MODE, UIC_LINK_HIBERN8_STATE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {UFS_POWERDOWN_PWR_MODE, UIC_LINK_HIBERN8_STATE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {UFS_POWERDOWN_PWR_MODE, UIC_LINK_OFF_STATE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static inline enum ufs_dev_pwr_mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) ufs_get_pm_lvl_to_dev_pwr_mode(enum ufs_pm_level lvl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) return ufs_pm_lvl_states[lvl].dev_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static inline enum uic_link_state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) ufs_get_pm_lvl_to_link_pwr_state(enum ufs_pm_level lvl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) return ufs_pm_lvl_states[lvl].link_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static inline enum ufs_pm_level
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) ufs_get_desired_pm_lvl_for_dev_link_state(enum ufs_dev_pwr_mode dev_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) enum uic_link_state link_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) enum ufs_pm_level lvl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) for (lvl = UFS_PM_LVL_0; lvl < UFS_PM_LVL_MAX; lvl++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) if ((ufs_pm_lvl_states[lvl].dev_state == dev_state) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) (ufs_pm_lvl_states[lvl].link_state == link_state))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) return lvl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /* if no match found, return the level 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) return UFS_PM_LVL_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static struct ufs_dev_fix ufs_fixups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) /* UFS cards deviations table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) UFS_FIX(UFS_VENDOR_MICRON, UFS_ANY_MODEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) UFS_DEVICE_QUIRK_SWAP_L2P_ENTRY_FOR_HPB_READ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) UFS_FIX(UFS_VENDOR_SAMSUNG, UFS_ANY_MODEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) UFS_FIX(UFS_VENDOR_SKHYNIX, UFS_ANY_MODEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) UFS_DEVICE_QUIRK_HOST_PA_SAVECONFIGTIME),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) UFS_FIX(UFS_VENDOR_SKHYNIX, "hB8aL1" /*H28U62301AMR*/,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) UFS_DEVICE_QUIRK_HOST_VS_DEBUGSAVECONFIGTIME),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) UFS_FIX(UFS_VENDOR_TOSHIBA, UFS_ANY_MODEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) UFS_FIX(UFS_VENDOR_TOSHIBA, "THGLF2G9C8KBADG",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) UFS_DEVICE_QUIRK_PA_TACTIVATE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) UFS_FIX(UFS_VENDOR_TOSHIBA, "THGLF2G9D8KBADG",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) UFS_DEVICE_QUIRK_PA_TACTIVATE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) END_FIX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) static irqreturn_t ufshcd_tmc_handler(struct ufs_hba *hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) static void ufshcd_async_scan(void *data, async_cookie_t cookie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) static int ufshcd_reset_and_restore(struct ufs_hba *hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static int ufshcd_eh_host_reset_handler(struct scsi_cmnd *cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) static void ufshcd_hba_exit(struct ufs_hba *hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) static int ufshcd_probe_hba(struct ufs_hba *hba, bool async);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) static int ufshcd_host_reset_and_restore(struct ufs_hba *hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static void ufshcd_resume_clkscaling(struct ufs_hba *hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) static void ufshcd_suspend_clkscaling(struct ufs_hba *hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) static void __ufshcd_suspend_clkscaling(struct ufs_hba *hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) static int ufshcd_scale_clks(struct ufs_hba *hba, bool scale_up);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static irqreturn_t ufshcd_intr(int irq, void *__hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) static int ufshcd_change_power_mode(struct ufs_hba *hba,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) struct ufs_pa_layer_attr *pwr_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) static void ufshcd_schedule_eh_work(struct ufs_hba *hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) static int ufshcd_setup_hba_vreg(struct ufs_hba *hba, bool on);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) static int ufshcd_setup_vreg(struct ufs_hba *hba, bool on);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) static inline int ufshcd_config_vreg_hpm(struct ufs_hba *hba,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) struct ufs_vreg *vreg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) static int ufshcd_try_to_abort_task(struct ufs_hba *hba, int tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) static int ufshcd_wb_buf_flush_enable(struct ufs_hba *hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) static int ufshcd_wb_buf_flush_disable(struct ufs_hba *hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) static int ufshcd_wb_ctrl(struct ufs_hba *hba, bool enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) static int ufshcd_wb_toggle_flush_during_h8(struct ufs_hba *hba, bool set);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) static inline void ufshcd_wb_toggle_flush(struct ufs_hba *hba, bool enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) static void ufshcd_hba_vreg_set_lpm(struct ufs_hba *hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) static void ufshcd_hba_vreg_set_hpm(struct ufs_hba *hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) static inline bool ufshcd_valid_tag(struct ufs_hba *hba, int tag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) return tag >= 0 && tag < hba->nutrs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) static inline void ufshcd_enable_irq(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) if (!hba->is_irq_enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) enable_irq(hba->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) hba->is_irq_enabled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) static inline void ufshcd_disable_irq(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) if (hba->is_irq_enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) disable_irq(hba->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) hba->is_irq_enabled = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) static inline void ufshcd_wb_config(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) if (!ufshcd_is_wb_allowed(hba))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) ret = ufshcd_wb_ctrl(hba, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) dev_err(hba->dev, "%s: Enable WB failed: %d\n", __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) dev_info(hba->dev, "%s: Write Booster Configured\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) ret = ufshcd_wb_toggle_flush_during_h8(hba, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) dev_err(hba->dev, "%s: En WB flush during H8: failed: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) if (!(hba->quirks & UFSHCI_QUIRK_SKIP_MANUAL_WB_FLUSH_CTRL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) ufshcd_wb_toggle_flush(hba, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) static void ufshcd_scsi_unblock_requests(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) if (atomic_dec_and_test(&hba->scsi_block_reqs_cnt))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) scsi_unblock_requests(hba->host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) static void ufshcd_scsi_block_requests(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) if (atomic_inc_return(&hba->scsi_block_reqs_cnt) == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) scsi_block_requests(hba->host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) static void ufshcd_add_cmd_upiu_trace(struct ufs_hba *hba, unsigned int tag,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) const char *str)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) struct utp_upiu_req *rq = hba->lrb[tag].ucd_req_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) trace_ufshcd_upiu(dev_name(hba->dev), str, &rq->header, &rq->sc.cdb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) static void ufshcd_add_query_upiu_trace(struct ufs_hba *hba, unsigned int tag,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) const char *str)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) struct utp_upiu_req *rq = hba->lrb[tag].ucd_req_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) trace_ufshcd_upiu(dev_name(hba->dev), str, &rq->header, &rq->qr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) static void ufshcd_add_tm_upiu_trace(struct ufs_hba *hba, unsigned int tag,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) const char *str)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) struct utp_task_req_desc *descp = &hba->utmrdl_base_addr[tag];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) trace_android_vh_ufs_send_tm_command(hba, tag, str);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) trace_ufshcd_upiu(dev_name(hba->dev), str, &descp->req_header,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) &descp->input_param1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) static void ufshcd_add_uic_command_trace(struct ufs_hba *hba,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) struct uic_command *ucmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) const char *str)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) u32 cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) trace_android_vh_ufs_send_uic_command(hba, ucmd, str);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) if (!trace_ufshcd_uic_command_enabled())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) if (!strcmp(str, "send"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) cmd = ucmd->command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) cmd = ufshcd_readl(hba, REG_UIC_COMMAND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) trace_ufshcd_uic_command(dev_name(hba->dev), str, cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) ufshcd_readl(hba, REG_UIC_COMMAND_ARG_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) ufshcd_readl(hba, REG_UIC_COMMAND_ARG_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) ufshcd_readl(hba, REG_UIC_COMMAND_ARG_3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) static void ufshcd_add_command_trace(struct ufs_hba *hba,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) unsigned int tag, const char *str)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) sector_t lba = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) u8 opcode = 0, group_id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) u32 intr, doorbell;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) struct ufshcd_lrb *lrbp = &hba->lrb[tag];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) struct scsi_cmnd *cmd = lrbp->cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) int transfer_len = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) if (!trace_ufshcd_command_enabled()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) /* trace UPIU W/O tracing command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) if (cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) ufshcd_add_cmd_upiu_trace(hba, tag, str);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) if (cmd) { /* data phase exists */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) /* trace UPIU also */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) ufshcd_add_cmd_upiu_trace(hba, tag, str);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) opcode = cmd->cmnd[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) if ((opcode == READ_10) || (opcode == WRITE_10)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) * Currently we only fully trace read(10) and write(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) * commands
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) if (cmd->request && cmd->request->bio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) lba = cmd->request->bio->bi_iter.bi_sector;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) transfer_len = be32_to_cpu(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) lrbp->ucd_req_ptr->sc.exp_data_transfer_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) if (opcode == WRITE_10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) group_id = lrbp->cmd->cmnd[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) } else if (opcode == UNMAP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) if (cmd->request) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) lba = scsi_get_lba(cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) transfer_len = blk_rq_bytes(cmd->request);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) intr = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) trace_ufshcd_command(dev_name(hba->dev), str, tag,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) doorbell, transfer_len, intr, lba, opcode, group_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) static void ufshcd_print_clk_freqs(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) struct ufs_clk_info *clki;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) struct list_head *head = &hba->clk_list_head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) if (list_empty(head))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) list_for_each_entry(clki, head, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) if (!IS_ERR_OR_NULL(clki->clk) && clki->min_freq &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) clki->max_freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) dev_err(hba->dev, "clk: %s, rate: %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) clki->name, clki->curr_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) static void ufshcd_print_evt(struct ufs_hba *hba, u32 id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) char *err_name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) bool found = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) struct ufs_event_hist *e;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) if (id >= UFS_EVT_CNT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) e = &hba->ufs_stats.event[id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) for (i = 0; i < UFS_EVENT_HIST_LENGTH; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) int p = (i + e->pos) % UFS_EVENT_HIST_LENGTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) if (e->tstamp[p] == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) dev_err(hba->dev, "%s[%d] = 0x%x at %lld us\n", err_name, p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) e->val[p], ktime_to_us(e->tstamp[p]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) found = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) if (!found)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) dev_err(hba->dev, "No record of %s\n", err_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) static void ufshcd_print_evt_hist(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) ufshcd_dump_regs(hba, 0, UFSHCI_REG_SPACE_SIZE, "host_regs: ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) ufshcd_print_evt(hba, UFS_EVT_PA_ERR, "pa_err");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) ufshcd_print_evt(hba, UFS_EVT_DL_ERR, "dl_err");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) ufshcd_print_evt(hba, UFS_EVT_NL_ERR, "nl_err");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) ufshcd_print_evt(hba, UFS_EVT_TL_ERR, "tl_err");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) ufshcd_print_evt(hba, UFS_EVT_DME_ERR, "dme_err");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) ufshcd_print_evt(hba, UFS_EVT_AUTO_HIBERN8_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) "auto_hibern8_err");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) ufshcd_print_evt(hba, UFS_EVT_FATAL_ERR, "fatal_err");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) ufshcd_print_evt(hba, UFS_EVT_LINK_STARTUP_FAIL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) "link_startup_fail");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) ufshcd_print_evt(hba, UFS_EVT_RESUME_ERR, "resume_fail");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) ufshcd_print_evt(hba, UFS_EVT_SUSPEND_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) "suspend_fail");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) ufshcd_print_evt(hba, UFS_EVT_DEV_RESET, "dev_reset");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) ufshcd_print_evt(hba, UFS_EVT_HOST_RESET, "host_reset");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) ufshcd_print_evt(hba, UFS_EVT_ABORT, "task_abort");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) ufshcd_vops_dbg_register_dump(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) static
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) void ufshcd_print_trs(struct ufs_hba *hba, unsigned long bitmap, bool pr_prdt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) struct ufshcd_lrb *lrbp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) int prdt_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) int tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) for_each_set_bit(tag, &bitmap, hba->nutrs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) lrbp = &hba->lrb[tag];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) dev_err(hba->dev, "UPIU[%d] - issue time %lld us\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) tag, ktime_to_us(lrbp->issue_time_stamp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) dev_err(hba->dev, "UPIU[%d] - complete time %lld us\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) tag, ktime_to_us(lrbp->compl_time_stamp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) dev_err(hba->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) "UPIU[%d] - Transfer Request Descriptor phys@0x%llx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) tag, (u64)lrbp->utrd_dma_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) ufshcd_hex_dump("UPIU TRD: ", lrbp->utr_descriptor_ptr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) sizeof(struct utp_transfer_req_desc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) dev_err(hba->dev, "UPIU[%d] - Request UPIU phys@0x%llx\n", tag,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) (u64)lrbp->ucd_req_dma_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) ufshcd_hex_dump("UPIU REQ: ", lrbp->ucd_req_ptr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) sizeof(struct utp_upiu_req));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) dev_err(hba->dev, "UPIU[%d] - Response UPIU phys@0x%llx\n", tag,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) (u64)lrbp->ucd_rsp_dma_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) ufshcd_hex_dump("UPIU RSP: ", lrbp->ucd_rsp_ptr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) sizeof(struct utp_upiu_rsp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) prdt_length = le16_to_cpu(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) lrbp->utr_descriptor_ptr->prd_table_length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) prdt_length /= hba->sg_entry_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) dev_err(hba->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) "UPIU[%d] - PRDT - %d entries phys@0x%llx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) tag, prdt_length,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) (u64)lrbp->ucd_prdt_dma_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) if (pr_prdt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) ufshcd_hex_dump("UPIU PRDT: ", lrbp->ucd_prdt_ptr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) hba->sg_entry_size * prdt_length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) static void ufshcd_print_tmrs(struct ufs_hba *hba, unsigned long bitmap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) int tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) for_each_set_bit(tag, &bitmap, hba->nutmrs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) struct utp_task_req_desc *tmrdp = &hba->utmrdl_base_addr[tag];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) dev_err(hba->dev, "TM[%d] - Task Management Header\n", tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) ufshcd_hex_dump("", tmrdp, sizeof(*tmrdp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) static void ufshcd_print_host_state(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) struct scsi_device *sdev_ufs = hba->sdev_ufs_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) dev_err(hba->dev, "UFS Host state=%d\n", hba->ufshcd_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) dev_err(hba->dev, "outstanding reqs=0x%lx tasks=0x%lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) hba->outstanding_reqs, hba->outstanding_tasks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) dev_err(hba->dev, "saved_err=0x%x, saved_uic_err=0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) hba->saved_err, hba->saved_uic_err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) dev_err(hba->dev, "Device power mode=%d, UIC link state=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) hba->curr_dev_pwr_mode, hba->uic_link_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) dev_err(hba->dev, "PM in progress=%d, sys. suspended=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) hba->pm_op_in_progress, hba->is_sys_suspended);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) dev_err(hba->dev, "Auto BKOPS=%d, Host self-block=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) hba->auto_bkops_enabled, hba->host->host_self_blocked);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) dev_err(hba->dev, "Clk gate=%d\n", hba->clk_gating.state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) dev_err(hba->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) "last_hibern8_exit_tstamp at %lld us, hibern8_exit_cnt=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) ktime_to_us(hba->ufs_stats.last_hibern8_exit_tstamp),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) hba->ufs_stats.hibern8_exit_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) dev_err(hba->dev, "last intr at %lld us, last intr status=0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) ktime_to_us(hba->ufs_stats.last_intr_ts),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) hba->ufs_stats.last_intr_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) dev_err(hba->dev, "error handling flags=0x%x, req. abort count=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) hba->eh_flags, hba->req_abort_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) dev_err(hba->dev, "hba->ufs_version=0x%x, Host capabilities=0x%x, caps=0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) hba->ufs_version, hba->capabilities, hba->caps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) dev_err(hba->dev, "quirks=0x%x, dev. quirks=0x%x\n", hba->quirks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) hba->dev_quirks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) if (sdev_ufs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) dev_err(hba->dev, "UFS dev info: %.8s %.16s rev %.4s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) sdev_ufs->vendor, sdev_ufs->model, sdev_ufs->rev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) ufshcd_print_clk_freqs(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) * ufshcd_print_pwr_info - print power params as saved in hba
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) * power info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) * @hba: per-adapter instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) static void ufshcd_print_pwr_info(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) static const char * const names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) "INVALID MODE",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) "FAST MODE",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) "SLOW_MODE",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) "INVALID MODE",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) "FASTAUTO_MODE",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) "SLOWAUTO_MODE",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) "INVALID MODE",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) dev_err(hba->dev, "%s:[RX, TX]: gear=[%d, %d], lane[%d, %d], pwr[%s, %s], rate = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) hba->pwr_info.gear_rx, hba->pwr_info.gear_tx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) hba->pwr_info.lane_rx, hba->pwr_info.lane_tx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) names[hba->pwr_info.pwr_rx],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) names[hba->pwr_info.pwr_tx],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) hba->pwr_info.hs_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) void ufshcd_delay_us(unsigned long us, unsigned long tolerance)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) if (!us)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) if (us < 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) udelay(us);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) usleep_range(us, us + tolerance);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) EXPORT_SYMBOL_GPL(ufshcd_delay_us);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) * ufshcd_wait_for_register - wait for register value to change
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) * @hba: per-adapter interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) * @reg: mmio register offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) * @mask: mask to apply to the read register value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) * @val: value to wait for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) * @interval_us: polling interval in microseconds
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) * @timeout_ms: timeout in milliseconds
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) * Return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) * -ETIMEDOUT on error, zero on success.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) int ufshcd_wait_for_register(struct ufs_hba *hba, u32 reg, u32 mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) u32 val, unsigned long interval_us,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) unsigned long timeout_ms)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) /* ignore bits that we don't intend to wait on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) val = val & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) while ((ufshcd_readl(hba, reg) & mask) != val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) usleep_range(interval_us, interval_us + 50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) if (time_after(jiffies, timeout)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) if ((ufshcd_readl(hba, reg) & mask) != val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) err = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) * ufshcd_get_intr_mask - Get the interrupt bit mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) * @hba: Pointer to adapter instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) * Returns interrupt bit mask per version
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) static inline u32 ufshcd_get_intr_mask(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) if (hba->ufs_version == ufshci_version(1, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) return INTERRUPT_MASK_ALL_VER_10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) if (hba->ufs_version <= ufshci_version(2, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) return INTERRUPT_MASK_ALL_VER_11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) return INTERRUPT_MASK_ALL_VER_21;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) * ufshcd_get_ufs_version - Get the UFS version supported by the HBA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) * @hba: Pointer to adapter instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) * Returns UFSHCI version supported by the controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) static inline u32 ufshcd_get_ufs_version(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) u32 ufshci_ver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) if (hba->quirks & UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) ufshci_ver = ufshcd_vops_get_ufs_hci_version(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) ufshci_ver = ufshcd_readl(hba, REG_UFS_VERSION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) * UFSHCI v1.x uses a different version scheme, in order
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) * to allow the use of comparisons with the ufshci_version
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) * function, we convert it to the same scheme as ufs 2.0+.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) if (ufshci_ver & 0x00010000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) return ufshci_version(1, ufshci_ver & 0x00000100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) return ufshci_ver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) * ufshcd_is_device_present - Check if any device connected to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) * the host controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) * @hba: pointer to adapter instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) * Returns true if device present, false if no device detected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) static inline bool ufshcd_is_device_present(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) DEVICE_PRESENT) ? true : false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) * ufshcd_get_tr_ocs - Get the UTRD Overall Command Status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) * @lrbp: pointer to local command reference block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) * This function is used to get the OCS field from UTRD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) * Returns the OCS field in the UTRD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) static inline int ufshcd_get_tr_ocs(struct ufshcd_lrb *lrbp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) return le32_to_cpu(lrbp->utr_descriptor_ptr->header.dword_2) & MASK_OCS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) * ufshcd_utrl_clear - Clear a bit in UTRLCLR register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) * @hba: per adapter instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) * @pos: position of the bit to be cleared
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) static inline void ufshcd_utrl_clear(struct ufs_hba *hba, u32 pos)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) if (hba->quirks & UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) ufshcd_writel(hba, (1 << pos), REG_UTP_TRANSFER_REQ_LIST_CLEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) ufshcd_writel(hba, ~(1 << pos),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) REG_UTP_TRANSFER_REQ_LIST_CLEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) * ufshcd_utmrl_clear - Clear a bit in UTRMLCLR register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) * @hba: per adapter instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) * @pos: position of the bit to be cleared
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) static inline void ufshcd_utmrl_clear(struct ufs_hba *hba, u32 pos)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) if (hba->quirks & UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) ufshcd_writel(hba, (1 << pos), REG_UTP_TASK_REQ_LIST_CLEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) ufshcd_writel(hba, ~(1 << pos), REG_UTP_TASK_REQ_LIST_CLEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) * ufshcd_outstanding_req_clear - Clear a bit in outstanding request field
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) * @hba: per adapter instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) * @tag: position of the bit to be cleared
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) static inline void ufshcd_outstanding_req_clear(struct ufs_hba *hba, int tag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) clear_bit(tag, &hba->outstanding_reqs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) * ufshcd_get_lists_status - Check UCRDY, UTRLRDY and UTMRLRDY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) * @reg: Register value of host controller status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) * Returns integer, 0 on Success and positive value if failed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) static inline int ufshcd_get_lists_status(u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) return !((reg & UFSHCD_STATUS_READY) == UFSHCD_STATUS_READY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) * ufshcd_get_uic_cmd_result - Get the UIC command result
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) * @hba: Pointer to adapter instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) * This function gets the result of UIC command completion
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) * Returns 0 on success, non zero value on error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) static inline int ufshcd_get_uic_cmd_result(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_2) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) MASK_UIC_COMMAND_RESULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) * ufshcd_get_dme_attr_val - Get the value of attribute returned by UIC command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) * @hba: Pointer to adapter instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) * This function gets UIC command argument3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) * Returns 0 on success, non zero value on error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) static inline u32 ufshcd_get_dme_attr_val(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) * ufshcd_get_req_rsp - returns the TR response transaction type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) * @ucd_rsp_ptr: pointer to response UPIU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) static inline int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) ufshcd_get_req_rsp(struct utp_upiu_rsp *ucd_rsp_ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) return be32_to_cpu(ucd_rsp_ptr->header.dword_0) >> 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) * ufshcd_get_rsp_upiu_result - Get the result from response UPIU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) * @ucd_rsp_ptr: pointer to response UPIU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) * This function gets the response status and scsi_status from response UPIU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) * Returns the response result code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) static inline int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) ufshcd_get_rsp_upiu_result(struct utp_upiu_rsp *ucd_rsp_ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) return be32_to_cpu(ucd_rsp_ptr->header.dword_1) & MASK_RSP_UPIU_RESULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) * ufshcd_get_rsp_upiu_data_seg_len - Get the data segment length
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) * from response UPIU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) * @ucd_rsp_ptr: pointer to response UPIU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) * Return the data segment length.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) static inline unsigned int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) ufshcd_get_rsp_upiu_data_seg_len(struct utp_upiu_rsp *ucd_rsp_ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) return be32_to_cpu(ucd_rsp_ptr->header.dword_2) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) MASK_RSP_UPIU_DATA_SEG_LEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) * ufshcd_is_exception_event - Check if the device raised an exception event
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) * @ucd_rsp_ptr: pointer to response UPIU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) * The function checks if the device raised an exception event indicated in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) * the Device Information field of response UPIU.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) * Returns true if exception is raised, false otherwise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) static inline bool ufshcd_is_exception_event(struct utp_upiu_rsp *ucd_rsp_ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) return be32_to_cpu(ucd_rsp_ptr->header.dword_2) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) MASK_RSP_EXCEPTION_EVENT ? true : false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) * ufshcd_reset_intr_aggr - Reset interrupt aggregation values.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) * @hba: per adapter instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) ufshcd_reset_intr_aggr(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) ufshcd_writel(hba, INT_AGGR_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) INT_AGGR_COUNTER_AND_TIMER_RESET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) * ufshcd_config_intr_aggr - Configure interrupt aggregation values.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) * @hba: per adapter instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) * @cnt: Interrupt aggregation counter threshold
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) * @tmout: Interrupt aggregation timeout value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) ufshcd_config_intr_aggr(struct ufs_hba *hba, u8 cnt, u8 tmout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) ufshcd_writel(hba, INT_AGGR_ENABLE | INT_AGGR_PARAM_WRITE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) INT_AGGR_COUNTER_THLD_VAL(cnt) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) INT_AGGR_TIMEOUT_VAL(tmout),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) * ufshcd_disable_intr_aggr - Disables interrupt aggregation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) * @hba: per adapter instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) static inline void ufshcd_disable_intr_aggr(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) ufshcd_writel(hba, 0, REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) * ufshcd_enable_run_stop_reg - Enable run-stop registers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) * When run-stop registers are set to 1, it indicates the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) * host controller that it can process the requests
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) * @hba: per adapter instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) static void ufshcd_enable_run_stop_reg(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) ufshcd_writel(hba, UTP_TASK_REQ_LIST_RUN_STOP_BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) REG_UTP_TASK_REQ_LIST_RUN_STOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) ufshcd_writel(hba, UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) REG_UTP_TRANSFER_REQ_LIST_RUN_STOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) * ufshcd_hba_start - Start controller initialization sequence
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) * @hba: per adapter instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) static inline void ufshcd_hba_start(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) u32 val = CONTROLLER_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) if (ufshcd_crypto_enable(hba))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) val |= CRYPTO_GENERAL_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) ufshcd_writel(hba, val, REG_CONTROLLER_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) * ufshcd_is_hba_active - Get controller state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) * @hba: per adapter instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) * Returns false if controller is active, true otherwise
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) static inline bool ufshcd_is_hba_active(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) return (ufshcd_readl(hba, REG_CONTROLLER_ENABLE) & CONTROLLER_ENABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) ? false : true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) u32 ufshcd_get_local_unipro_ver(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) /* HCI version 1.0 and 1.1 supports UniPro 1.41 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) if (hba->ufs_version <= ufshci_version(1, 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) return UFS_UNIPRO_VER_1_41;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) return UFS_UNIPRO_VER_1_6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) EXPORT_SYMBOL(ufshcd_get_local_unipro_ver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) static bool ufshcd_is_unipro_pa_params_tuning_req(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) * If both host and device support UniPro ver1.6 or later, PA layer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) * parameters tuning happens during link startup itself.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) * We can manually tune PA layer parameters if either host or device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) * doesn't support UniPro ver 1.6 or later. But to keep manual tuning
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) * logic simple, we will only do manual tuning if local unipro version
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) * doesn't support ver1.6 or later.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) if (ufshcd_get_local_unipro_ver(hba) < UFS_UNIPRO_VER_1_6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) * ufshcd_set_clk_freq - set UFS controller clock frequencies
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) * @hba: per adapter instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) * @scale_up: If True, set max possible frequency othewise set low frequency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) * Returns 0 if successful
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) * Returns < 0 for any other errors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) static int ufshcd_set_clk_freq(struct ufs_hba *hba, bool scale_up)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) struct ufs_clk_info *clki;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) struct list_head *head = &hba->clk_list_head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) if (list_empty(head))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) list_for_each_entry(clki, head, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) if (!IS_ERR_OR_NULL(clki->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) if (scale_up && clki->max_freq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) if (clki->curr_freq == clki->max_freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) ret = clk_set_rate(clki->clk, clki->max_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) __func__, clki->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) clki->max_freq, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) trace_ufshcd_clk_scaling(dev_name(hba->dev),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) "scaled up", clki->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) clki->curr_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) clki->max_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) clki->curr_freq = clki->max_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) } else if (!scale_up && clki->min_freq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) if (clki->curr_freq == clki->min_freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) ret = clk_set_rate(clki->clk, clki->min_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) __func__, clki->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) clki->min_freq, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) trace_ufshcd_clk_scaling(dev_name(hba->dev),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) "scaled down", clki->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) clki->curr_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) clki->min_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) clki->curr_freq = clki->min_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) dev_dbg(hba->dev, "%s: clk: %s, rate: %lu\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) clki->name, clk_get_rate(clki->clk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) * ufshcd_scale_clks - scale up or scale down UFS controller clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) * @hba: per adapter instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) * @scale_up: True if scaling up and false if scaling down
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) * Returns 0 if successful
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) * Returns < 0 for any other errors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) static int ufshcd_scale_clks(struct ufs_hba *hba, bool scale_up)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) ktime_t start = ktime_get();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) ret = ufshcd_vops_clk_scale_notify(hba, scale_up, PRE_CHANGE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) ret = ufshcd_set_clk_freq(hba, scale_up);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) ret = ufshcd_vops_clk_scale_notify(hba, scale_up, POST_CHANGE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) ufshcd_set_clk_freq(hba, !scale_up);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) trace_ufshcd_profile_clk_scaling(dev_name(hba->dev),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) (scale_up ? "up" : "down"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) ktime_to_us(ktime_sub(ktime_get(), start)), ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) * ufshcd_is_devfreq_scaling_required - check if scaling is required or not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) * @hba: per adapter instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) * @scale_up: True if scaling up and false if scaling down
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) * Returns true if scaling is required, false otherwise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) static bool ufshcd_is_devfreq_scaling_required(struct ufs_hba *hba,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) bool scale_up)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) struct ufs_clk_info *clki;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) struct list_head *head = &hba->clk_list_head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) if (list_empty(head))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) list_for_each_entry(clki, head, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) if (!IS_ERR_OR_NULL(clki->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) if (scale_up && clki->max_freq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) if (clki->curr_freq == clki->max_freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) } else if (!scale_up && clki->min_freq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) if (clki->curr_freq == clki->min_freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) static int ufshcd_wait_for_doorbell_clr(struct ufs_hba *hba,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) u64 wait_timeout_us)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) u32 tm_doorbell;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) u32 tr_doorbell;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) bool timeout = false, do_last_check = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) ktime_t start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) ufshcd_hold(hba, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) spin_lock_irqsave(hba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) * Wait for all the outstanding tasks/transfer requests.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) * Verify by checking the doorbell registers are clear.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) start = ktime_get();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) if (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) ret = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) tm_doorbell = ufshcd_readl(hba, REG_UTP_TASK_REQ_DOOR_BELL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) tr_doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) if (!tm_doorbell && !tr_doorbell) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) timeout = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) } else if (do_last_check) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) spin_unlock_irqrestore(hba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) schedule();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) if (ktime_to_us(ktime_sub(ktime_get(), start)) >
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) wait_timeout_us) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) timeout = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) * We might have scheduled out for long time so make
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) * sure to check if doorbells are cleared by this time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) * or not.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) do_last_check = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) spin_lock_irqsave(hba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) } while (tm_doorbell || tr_doorbell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) if (timeout) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) dev_err(hba->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) "%s: timedout waiting for doorbell to clear (tm=0x%x, tr=0x%x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) __func__, tm_doorbell, tr_doorbell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) ret = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) spin_unlock_irqrestore(hba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) ufshcd_release(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) * ufshcd_scale_gear - scale up/down UFS gear
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) * @hba: per adapter instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) * @scale_up: True for scaling up gear and false for scaling down
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) * Returns 0 for success,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) * Returns -EBUSY if scaling can't happen at this time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) * Returns non-zero for any other errors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) static int ufshcd_scale_gear(struct ufs_hba *hba, bool scale_up)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) struct ufs_pa_layer_attr new_pwr_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) if (scale_up) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) memcpy(&new_pwr_info, &hba->clk_scaling.saved_pwr_info.info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) sizeof(struct ufs_pa_layer_attr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) memcpy(&new_pwr_info, &hba->pwr_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) sizeof(struct ufs_pa_layer_attr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) if (hba->pwr_info.gear_tx > hba->clk_scaling.min_gear ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) hba->pwr_info.gear_rx > hba->clk_scaling.min_gear) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) /* save the current power mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) memcpy(&hba->clk_scaling.saved_pwr_info.info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) &hba->pwr_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) sizeof(struct ufs_pa_layer_attr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) /* scale down gear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) new_pwr_info.gear_tx = hba->clk_scaling.min_gear;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) new_pwr_info.gear_rx = hba->clk_scaling.min_gear;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) /* check if the power mode needs to be changed or not? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) ret = ufshcd_config_pwr_mode(hba, &new_pwr_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) dev_err(hba->dev, "%s: failed err %d, old gear: (tx %d rx %d), new gear: (tx %d rx %d)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) __func__, ret,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) hba->pwr_info.gear_tx, hba->pwr_info.gear_rx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) new_pwr_info.gear_tx, new_pwr_info.gear_rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) static int ufshcd_clock_scaling_prepare(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) #define DOORBELL_CLR_TOUT_US (1000 * 1000) /* 1 sec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) * make sure that there are no outstanding requests when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) * clock scaling is in progress
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) ufshcd_scsi_block_requests(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) down_write(&hba->clk_scaling_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) if (!hba->clk_scaling.is_allowed ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) ufshcd_wait_for_doorbell_clr(hba, DOORBELL_CLR_TOUT_US)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) ret = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) up_write(&hba->clk_scaling_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) ufshcd_scsi_unblock_requests(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) /* let's not get into low power until clock scaling is completed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) ufshcd_hold(hba, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) static void ufshcd_clock_scaling_unprepare(struct ufs_hba *hba, bool writelock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) if (writelock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) up_write(&hba->clk_scaling_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) up_read(&hba->clk_scaling_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) ufshcd_scsi_unblock_requests(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) ufshcd_release(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) * ufshcd_devfreq_scale - scale up/down UFS clocks and gear
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) * @hba: per adapter instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) * @scale_up: True for scaling up and false for scalin down
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) * Returns 0 for success,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) * Returns -EBUSY if scaling can't happen at this time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) * Returns non-zero for any other errors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) static int ufshcd_devfreq_scale(struct ufs_hba *hba, bool scale_up)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) bool is_writelock = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) ret = ufshcd_clock_scaling_prepare(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) /* scale down the gear before scaling down clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) if (!scale_up) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) ret = ufshcd_scale_gear(hba, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) goto out_unprepare;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) ret = ufshcd_scale_clks(hba, scale_up);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) if (!scale_up)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) ufshcd_scale_gear(hba, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) goto out_unprepare;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) /* scale up the gear after scaling up clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) if (scale_up) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) ret = ufshcd_scale_gear(hba, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) ufshcd_scale_clks(hba, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) goto out_unprepare;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) /* Enable Write Booster if we have scaled up else disable it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) downgrade_write(&hba->clk_scaling_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) is_writelock = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) ufshcd_wb_ctrl(hba, scale_up);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) out_unprepare:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) ufshcd_clock_scaling_unprepare(hba, is_writelock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) static void ufshcd_clk_scaling_suspend_work(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) struct ufs_hba *hba = container_of(work, struct ufs_hba,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) clk_scaling.suspend_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) unsigned long irq_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) spin_lock_irqsave(hba->host->host_lock, irq_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) if (hba->clk_scaling.active_reqs || hba->clk_scaling.is_suspended) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) hba->clk_scaling.is_suspended = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) __ufshcd_suspend_clkscaling(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) static void ufshcd_clk_scaling_resume_work(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) struct ufs_hba *hba = container_of(work, struct ufs_hba,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) clk_scaling.resume_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) unsigned long irq_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) spin_lock_irqsave(hba->host->host_lock, irq_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) if (!hba->clk_scaling.is_suspended) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) hba->clk_scaling.is_suspended = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) devfreq_resume_device(hba->devfreq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) static int ufshcd_devfreq_target(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) unsigned long *freq, u32 flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) struct ufs_hba *hba = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) ktime_t start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) bool scale_up, sched_clk_scaling_suspend_work = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) struct list_head *clk_list = &hba->clk_list_head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) struct ufs_clk_info *clki;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) unsigned long irq_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) bool force_out = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) bool force_scaling = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) if (!ufshcd_is_clkscaling_supported(hba))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) clki = list_first_entry(&hba->clk_list_head, struct ufs_clk_info, list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) /* Override with the closest supported frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) *freq = (unsigned long) clk_round_rate(clki->clk, *freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) spin_lock_irqsave(hba->host->host_lock, irq_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) if (ufshcd_eh_in_progress(hba)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) if (!hba->clk_scaling.active_reqs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) sched_clk_scaling_suspend_work = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) if (list_empty(clk_list)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) /* Decide based on the rounded-off frequency and update */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) scale_up = (*freq == clki->max_freq) ? true : false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) if (!scale_up)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) *freq = clki->min_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) trace_android_vh_ufs_clock_scaling(hba, &force_out, &force_scaling, &scale_up);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) /* Update the frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) if (force_out || (!force_scaling && !ufshcd_is_devfreq_scaling_required(hba, scale_up))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) goto out; /* no state change required */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) start = ktime_get();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) ret = ufshcd_devfreq_scale(hba, scale_up);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) trace_ufshcd_profile_clk_scaling(dev_name(hba->dev),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) (scale_up ? "up" : "down"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) ktime_to_us(ktime_sub(ktime_get(), start)), ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) if (sched_clk_scaling_suspend_work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) queue_work(hba->clk_scaling.workq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) &hba->clk_scaling.suspend_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) static bool ufshcd_is_busy(struct request *req, void *priv, bool reserved)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) int *busy = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) WARN_ON_ONCE(reserved);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) (*busy)++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) /* Whether or not any tag is in use by a request that is in progress. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) static bool ufshcd_any_tag_in_use(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) struct request_queue *q = hba->cmd_queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) int busy = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) blk_mq_tagset_busy_iter(q->tag_set, ufshcd_is_busy, &busy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) return busy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) static int ufshcd_devfreq_get_dev_status(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) struct devfreq_dev_status *stat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) struct ufs_hba *hba = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) struct ufs_clk_scaling *scaling = &hba->clk_scaling;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) struct list_head *clk_list = &hba->clk_list_head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) struct ufs_clk_info *clki;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) ktime_t curr_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) if (!ufshcd_is_clkscaling_supported(hba))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) memset(stat, 0, sizeof(*stat));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) spin_lock_irqsave(hba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) curr_t = ktime_get();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) if (!scaling->window_start_t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) goto start_window;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) clki = list_first_entry(clk_list, struct ufs_clk_info, list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) * If current frequency is 0, then the ondemand governor considers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) * there's no initial frequency set. And it always requests to set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) * to max. frequency.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) stat->current_frequency = clki->curr_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) if (scaling->is_busy_started)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) scaling->tot_busy_t += ktime_us_delta(curr_t,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) scaling->busy_start_t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) stat->total_time = ktime_us_delta(curr_t, scaling->window_start_t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) stat->busy_time = scaling->tot_busy_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) start_window:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) scaling->window_start_t = curr_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) scaling->tot_busy_t = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) if (hba->outstanding_reqs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) scaling->busy_start_t = curr_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) scaling->is_busy_started = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) scaling->busy_start_t = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) scaling->is_busy_started = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) spin_unlock_irqrestore(hba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) static int ufshcd_devfreq_init(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) struct list_head *clk_list = &hba->clk_list_head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) struct ufs_clk_info *clki;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) struct devfreq *devfreq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) /* Skip devfreq if we don't have any clocks in the list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) if (list_empty(clk_list))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) clki = list_first_entry(clk_list, struct ufs_clk_info, list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) dev_pm_opp_add(hba->dev, clki->min_freq, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) dev_pm_opp_add(hba->dev, clki->max_freq, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) ufshcd_vops_config_scaling_param(hba, &hba->vps->devfreq_profile,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) &hba->vps->ondemand_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) devfreq = devfreq_add_device(hba->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) &hba->vps->devfreq_profile,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) DEVFREQ_GOV_SIMPLE_ONDEMAND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) &hba->vps->ondemand_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) if (IS_ERR(devfreq)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) ret = PTR_ERR(devfreq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) dev_err(hba->dev, "Unable to register with devfreq %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) dev_pm_opp_remove(hba->dev, clki->min_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) dev_pm_opp_remove(hba->dev, clki->max_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) hba->devfreq = devfreq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) static void ufshcd_devfreq_remove(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) struct list_head *clk_list = &hba->clk_list_head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) struct ufs_clk_info *clki;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) if (!hba->devfreq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) devfreq_remove_device(hba->devfreq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) hba->devfreq = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) clki = list_first_entry(clk_list, struct ufs_clk_info, list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) dev_pm_opp_remove(hba->dev, clki->min_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) dev_pm_opp_remove(hba->dev, clki->max_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) static void __ufshcd_suspend_clkscaling(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) devfreq_suspend_device(hba->devfreq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) spin_lock_irqsave(hba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) hba->clk_scaling.window_start_t = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) spin_unlock_irqrestore(hba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) static void ufshcd_suspend_clkscaling(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) bool suspend = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) cancel_work_sync(&hba->clk_scaling.suspend_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) cancel_work_sync(&hba->clk_scaling.resume_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) spin_lock_irqsave(hba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) if (!hba->clk_scaling.is_suspended) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) suspend = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) hba->clk_scaling.is_suspended = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) spin_unlock_irqrestore(hba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) if (suspend)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) __ufshcd_suspend_clkscaling(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) static void ufshcd_resume_clkscaling(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) bool resume = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) spin_lock_irqsave(hba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) if (hba->clk_scaling.is_suspended) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) resume = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) hba->clk_scaling.is_suspended = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) spin_unlock_irqrestore(hba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) if (resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) devfreq_resume_device(hba->devfreq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) static ssize_t ufshcd_clkscale_enable_show(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) struct ufs_hba *hba = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) return snprintf(buf, PAGE_SIZE, "%d\n", hba->clk_scaling.is_enabled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) static ssize_t ufshcd_clkscale_enable_store(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) struct device_attribute *attr, const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) struct ufs_hba *hba = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) if (kstrtou32(buf, 0, &value))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) down(&hba->host_sem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) if (!ufshcd_is_user_access_allowed(hba)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) err = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) value = !!value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) if (value == hba->clk_scaling.is_enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) pm_runtime_get_sync(hba->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) ufshcd_hold(hba, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) hba->clk_scaling.is_enabled = value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) if (value) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) ufshcd_resume_clkscaling(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) ufshcd_suspend_clkscaling(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) err = ufshcd_devfreq_scale(hba, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) dev_err(hba->dev, "%s: failed to scale clocks up %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) __func__, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) ufshcd_release(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) pm_runtime_put_sync(hba->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) up(&hba->host_sem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) return err ? err : count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) static void ufshcd_init_clk_scaling_sysfs(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) hba->clk_scaling.enable_attr.show = ufshcd_clkscale_enable_show;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) hba->clk_scaling.enable_attr.store = ufshcd_clkscale_enable_store;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) sysfs_attr_init(&hba->clk_scaling.enable_attr.attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) hba->clk_scaling.enable_attr.attr.name = "clkscale_enable";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) hba->clk_scaling.enable_attr.attr.mode = 0644;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) if (device_create_file(hba->dev, &hba->clk_scaling.enable_attr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) dev_err(hba->dev, "Failed to create sysfs for clkscale_enable\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) static void ufshcd_remove_clk_scaling_sysfs(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) if (hba->clk_scaling.enable_attr.attr.name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) device_remove_file(hba->dev, &hba->clk_scaling.enable_attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) static void ufshcd_init_clk_scaling(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) char wq_name[sizeof("ufs_clkscaling_00")];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) if (!ufshcd_is_clkscaling_supported(hba))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) if (!hba->clk_scaling.min_gear)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) hba->clk_scaling.min_gear = UFS_HS_G1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) INIT_WORK(&hba->clk_scaling.suspend_work,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) ufshcd_clk_scaling_suspend_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) INIT_WORK(&hba->clk_scaling.resume_work,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) ufshcd_clk_scaling_resume_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) snprintf(wq_name, sizeof(wq_name), "ufs_clkscaling_%d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) hba->host->host_no);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) hba->clk_scaling.workq = create_singlethread_workqueue(wq_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) hba->clk_scaling.is_initialized = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) static void ufshcd_exit_clk_scaling(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) if (!hba->clk_scaling.is_initialized)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) ufshcd_remove_clk_scaling_sysfs(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) destroy_workqueue(hba->clk_scaling.workq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) ufshcd_devfreq_remove(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) hba->clk_scaling.is_initialized = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) static void ufshcd_ungate_work(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) struct ufs_hba *hba = container_of(work, struct ufs_hba,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) clk_gating.ungate_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) cancel_delayed_work_sync(&hba->clk_gating.gate_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) spin_lock_irqsave(hba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) if (hba->clk_gating.state == CLKS_ON) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) spin_unlock_irqrestore(hba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) goto unblock_reqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) spin_unlock_irqrestore(hba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) ufshcd_hba_vreg_set_hpm(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) ufshcd_setup_clocks(hba, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) ufshcd_enable_irq(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) /* Exit from hibern8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) if (ufshcd_can_hibern8_during_gating(hba)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) /* Prevent gating in this path */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) hba->clk_gating.is_suspended = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) if (ufshcd_is_link_hibern8(hba)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) ret = ufshcd_uic_hibern8_exit(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) dev_err(hba->dev, "%s: hibern8 exit failed %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) ufshcd_set_link_active(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) hba->clk_gating.is_suspended = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) unblock_reqs:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) ufshcd_scsi_unblock_requests(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) * ufshcd_hold - Enable clocks that were gated earlier due to ufshcd_release.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) * Also, exit from hibern8 mode and set the link as active.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) * @hba: per adapter instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) * @async: This indicates whether caller should ungate clocks asynchronously.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) int ufshcd_hold(struct ufs_hba *hba, bool async)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) int rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) bool flush_result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) if (!ufshcd_is_clkgating_allowed(hba))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) spin_lock_irqsave(hba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) hba->clk_gating.active_reqs++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) start:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) switch (hba->clk_gating.state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) case CLKS_ON:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) * Wait for the ungate work to complete if in progress.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) * Though the clocks may be in ON state, the link could
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) * still be in hibner8 state if hibern8 is allowed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) * during clock gating.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) * Make sure we exit hibern8 state also in addition to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) * clocks being ON.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) if (ufshcd_can_hibern8_during_gating(hba) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) ufshcd_is_link_hibern8(hba)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) if (async) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) rc = -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) hba->clk_gating.active_reqs--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) spin_unlock_irqrestore(hba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) flush_result = flush_work(&hba->clk_gating.ungate_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) if (hba->clk_gating.is_suspended && !flush_result)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) spin_lock_irqsave(hba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) goto start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) case REQ_CLKS_OFF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) if (cancel_delayed_work(&hba->clk_gating.gate_work)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) hba->clk_gating.state = CLKS_ON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) trace_ufshcd_clk_gating(dev_name(hba->dev),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) hba->clk_gating.state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) * If we are here, it means gating work is either done or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) * currently running. Hence, fall through to cancel gating
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) * work and to enable clocks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) case CLKS_OFF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) hba->clk_gating.state = REQ_CLKS_ON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) trace_ufshcd_clk_gating(dev_name(hba->dev),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) hba->clk_gating.state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) if (queue_work(hba->clk_gating.clk_gating_workq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) &hba->clk_gating.ungate_work))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) ufshcd_scsi_block_requests(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) * fall through to check if we should wait for this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) * work to be done or not.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) case REQ_CLKS_ON:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) if (async) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) rc = -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) hba->clk_gating.active_reqs--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) spin_unlock_irqrestore(hba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) flush_work(&hba->clk_gating.ungate_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) /* Make sure state is CLKS_ON before returning */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) spin_lock_irqsave(hba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) goto start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) dev_err(hba->dev, "%s: clk gating is in invalid state %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) __func__, hba->clk_gating.state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) spin_unlock_irqrestore(hba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) EXPORT_SYMBOL_GPL(ufshcd_hold);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) static void ufshcd_gate_work(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) struct ufs_hba *hba = container_of(work, struct ufs_hba,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) clk_gating.gate_work.work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) spin_lock_irqsave(hba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) * In case you are here to cancel this work the gating state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) * would be marked as REQ_CLKS_ON. In this case save time by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) * skipping the gating work and exit after changing the clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) * state to CLKS_ON.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) if (hba->clk_gating.is_suspended ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) (hba->clk_gating.state != REQ_CLKS_OFF)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) hba->clk_gating.state = CLKS_ON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) trace_ufshcd_clk_gating(dev_name(hba->dev),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) hba->clk_gating.state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) goto rel_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) if (hba->clk_gating.active_reqs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) || hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) || ufshcd_any_tag_in_use(hba) || hba->outstanding_tasks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) || hba->active_uic_cmd || hba->uic_async_done)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) goto rel_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) spin_unlock_irqrestore(hba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) /* put the link into hibern8 mode before turning off clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) if (ufshcd_can_hibern8_during_gating(hba)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) ret = ufshcd_uic_hibern8_enter(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) hba->clk_gating.state = CLKS_ON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) dev_err(hba->dev, "%s: hibern8 enter failed %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) trace_ufshcd_clk_gating(dev_name(hba->dev),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) hba->clk_gating.state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) ufshcd_set_link_hibern8(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) ufshcd_disable_irq(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) ufshcd_setup_clocks(hba, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) /* Put the host controller in low power mode if possible */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) ufshcd_hba_vreg_set_lpm(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) * In case you are here to cancel this work the gating state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) * would be marked as REQ_CLKS_ON. In this case keep the state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) * as REQ_CLKS_ON which would anyway imply that clocks are off
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) * and a request to turn them on is pending. By doing this way,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) * we keep the state machine in tact and this would ultimately
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) * prevent from doing cancel work multiple times when there are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) * new requests arriving before the current cancel work is done.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) spin_lock_irqsave(hba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) if (hba->clk_gating.state == REQ_CLKS_OFF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) hba->clk_gating.state = CLKS_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) trace_ufshcd_clk_gating(dev_name(hba->dev),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) hba->clk_gating.state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) rel_lock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) spin_unlock_irqrestore(hba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) /* host lock must be held before calling this variant */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) static void __ufshcd_release(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) if (!ufshcd_is_clkgating_allowed(hba))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) hba->clk_gating.active_reqs--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) if (hba->clk_gating.active_reqs || hba->clk_gating.is_suspended ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) hba->outstanding_tasks ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) hba->active_uic_cmd || hba->uic_async_done ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) hba->clk_gating.state == CLKS_OFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) hba->clk_gating.state = REQ_CLKS_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) trace_ufshcd_clk_gating(dev_name(hba->dev), hba->clk_gating.state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) queue_delayed_work(hba->clk_gating.clk_gating_workq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) &hba->clk_gating.gate_work,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) msecs_to_jiffies(hba->clk_gating.delay_ms));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) void ufshcd_release(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) spin_lock_irqsave(hba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) __ufshcd_release(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) spin_unlock_irqrestore(hba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) EXPORT_SYMBOL_GPL(ufshcd_release);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) static ssize_t ufshcd_clkgate_delay_show(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) struct ufs_hba *hba = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) return snprintf(buf, PAGE_SIZE, "%lu\n", hba->clk_gating.delay_ms);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) static ssize_t ufshcd_clkgate_delay_store(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) struct device_attribute *attr, const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) struct ufs_hba *hba = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) unsigned long flags, value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) if (kstrtoul(buf, 0, &value))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) spin_lock_irqsave(hba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) hba->clk_gating.delay_ms = value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) spin_unlock_irqrestore(hba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) static ssize_t ufshcd_clkgate_enable_show(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) struct ufs_hba *hba = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) return snprintf(buf, PAGE_SIZE, "%d\n", hba->clk_gating.is_enabled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) static ssize_t ufshcd_clkgate_enable_store(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) struct device_attribute *attr, const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) struct ufs_hba *hba = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) if (kstrtou32(buf, 0, &value))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) value = !!value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) spin_lock_irqsave(hba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) if (value == hba->clk_gating.is_enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) if (value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) __ufshcd_release(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) hba->clk_gating.active_reqs++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) hba->clk_gating.is_enabled = value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) spin_unlock_irqrestore(hba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) static void ufshcd_init_clk_gating_sysfs(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) hba->clk_gating.delay_attr.show = ufshcd_clkgate_delay_show;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) hba->clk_gating.delay_attr.store = ufshcd_clkgate_delay_store;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) sysfs_attr_init(&hba->clk_gating.delay_attr.attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) hba->clk_gating.delay_attr.attr.name = "clkgate_delay_ms";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) hba->clk_gating.delay_attr.attr.mode = 0644;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) if (device_create_file(hba->dev, &hba->clk_gating.delay_attr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) dev_err(hba->dev, "Failed to create sysfs for clkgate_delay\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) hba->clk_gating.enable_attr.show = ufshcd_clkgate_enable_show;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) hba->clk_gating.enable_attr.store = ufshcd_clkgate_enable_store;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) sysfs_attr_init(&hba->clk_gating.enable_attr.attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) hba->clk_gating.enable_attr.attr.name = "clkgate_enable";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) hba->clk_gating.enable_attr.attr.mode = 0644;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) if (device_create_file(hba->dev, &hba->clk_gating.enable_attr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) dev_err(hba->dev, "Failed to create sysfs for clkgate_enable\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) static void ufshcd_remove_clk_gating_sysfs(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) if (hba->clk_gating.delay_attr.attr.name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) device_remove_file(hba->dev, &hba->clk_gating.delay_attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) if (hba->clk_gating.enable_attr.attr.name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) device_remove_file(hba->dev, &hba->clk_gating.enable_attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) static void ufshcd_init_clk_gating(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) char wq_name[sizeof("ufs_clk_gating_00")];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) if (!ufshcd_is_clkgating_allowed(hba))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) hba->clk_gating.state = CLKS_ON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) hba->clk_gating.delay_ms = 150;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) INIT_DELAYED_WORK(&hba->clk_gating.gate_work, ufshcd_gate_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) INIT_WORK(&hba->clk_gating.ungate_work, ufshcd_ungate_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) snprintf(wq_name, ARRAY_SIZE(wq_name), "ufs_clk_gating_%d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) hba->host->host_no);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) hba->clk_gating.clk_gating_workq = alloc_ordered_workqueue(wq_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) WQ_MEM_RECLAIM | WQ_HIGHPRI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) ufshcd_init_clk_gating_sysfs(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) hba->clk_gating.is_enabled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) hba->clk_gating.is_initialized = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) static void ufshcd_exit_clk_gating(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) if (!hba->clk_gating.is_initialized)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) ufshcd_remove_clk_gating_sysfs(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) cancel_work_sync(&hba->clk_gating.ungate_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) cancel_delayed_work_sync(&hba->clk_gating.gate_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) destroy_workqueue(hba->clk_gating.clk_gating_workq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) hba->clk_gating.is_initialized = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) /* Must be called with host lock acquired */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) static void ufshcd_clk_scaling_start_busy(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) bool queue_resume_work = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) ktime_t curr_t = ktime_get();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) if (!ufshcd_is_clkscaling_supported(hba))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) spin_lock_irqsave(hba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) if (!hba->clk_scaling.active_reqs++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) queue_resume_work = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) if (!hba->clk_scaling.is_enabled || hba->pm_op_in_progress) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) spin_unlock_irqrestore(hba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) if (queue_resume_work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) queue_work(hba->clk_scaling.workq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) &hba->clk_scaling.resume_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) if (!hba->clk_scaling.window_start_t) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) hba->clk_scaling.window_start_t = curr_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) hba->clk_scaling.tot_busy_t = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) hba->clk_scaling.is_busy_started = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) if (!hba->clk_scaling.is_busy_started) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) hba->clk_scaling.busy_start_t = curr_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) hba->clk_scaling.is_busy_started = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) spin_unlock_irqrestore(hba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) static void ufshcd_clk_scaling_update_busy(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) struct ufs_clk_scaling *scaling = &hba->clk_scaling;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) if (!ufshcd_is_clkscaling_supported(hba))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) spin_lock_irqsave(hba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) hba->clk_scaling.active_reqs--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) if (!hba->outstanding_reqs && scaling->is_busy_started) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) scaling->tot_busy_t += ktime_to_us(ktime_sub(ktime_get(),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) scaling->busy_start_t));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) scaling->busy_start_t = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) scaling->is_busy_started = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) spin_unlock_irqrestore(hba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) static inline int ufshcd_monitor_opcode2dir(u8 opcode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) if (opcode == READ_6 || opcode == READ_10 || opcode == READ_16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) return READ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) else if (opcode == WRITE_6 || opcode == WRITE_10 || opcode == WRITE_16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) return WRITE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) static inline bool ufshcd_should_inform_monitor(struct ufs_hba *hba,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) struct ufshcd_lrb *lrbp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) struct ufs_hba_monitor *m = &hba->monitor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) return (m->enabled && lrbp && lrbp->cmd &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) (!m->chunk_size || m->chunk_size == lrbp->cmd->sdb.length) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) ktime_before(hba->monitor.enabled_ts, lrbp->issue_time_stamp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) static void ufshcd_start_monitor(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) int dir = ufshcd_monitor_opcode2dir(*lrbp->cmd->cmnd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) spin_lock_irqsave(hba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) if (dir >= 0 && hba->monitor.nr_queued[dir]++ == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) hba->monitor.busy_start_ts[dir] = ktime_get();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) spin_unlock_irqrestore(hba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) static void ufshcd_update_monitor(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) int dir = ufshcd_monitor_opcode2dir(*lrbp->cmd->cmnd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) spin_lock_irqsave(hba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) if (dir >= 0 && hba->monitor.nr_queued[dir] > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) struct request *req = lrbp->cmd->request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) struct ufs_hba_monitor *m = &hba->monitor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) ktime_t now, inc, lat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) now = lrbp->compl_time_stamp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) inc = ktime_sub(now, m->busy_start_ts[dir]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) m->total_busy[dir] = ktime_add(m->total_busy[dir], inc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) m->nr_sec_rw[dir] += blk_rq_sectors(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) /* Update latencies */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) m->nr_req[dir]++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) lat = ktime_sub(now, lrbp->issue_time_stamp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) m->lat_sum[dir] += lat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) if (m->lat_max[dir] < lat || !m->lat_max[dir])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) m->lat_max[dir] = lat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) if (m->lat_min[dir] > lat || !m->lat_min[dir])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) m->lat_min[dir] = lat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) m->nr_queued[dir]--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) /* Push forward the busy start of monitor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) m->busy_start_ts[dir] = now;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) spin_unlock_irqrestore(hba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) * ufshcd_send_command - Send SCSI or device management commands
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) * @hba: per adapter instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) * @task_tag: Task tag of the command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) static inline
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) void ufshcd_send_command(struct ufs_hba *hba, unsigned int task_tag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) struct ufshcd_lrb *lrbp = &hba->lrb[task_tag];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) lrbp->issue_time_stamp = ktime_get();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) lrbp->compl_time_stamp = ktime_set(0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) ufshcd_vops_setup_xfer_req(hba, task_tag, (lrbp->cmd ? true : false));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) trace_android_vh_ufs_send_command(hba, lrbp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) ufshcd_add_command_trace(hba, task_tag, "send");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) ufshcd_clk_scaling_start_busy(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) if (unlikely(ufshcd_should_inform_monitor(hba, lrbp)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) ufshcd_start_monitor(hba, lrbp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) if (ufshcd_has_utrlcnr(hba)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) set_bit(task_tag, &hba->outstanding_reqs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) ufshcd_writel(hba, 1 << task_tag,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) REG_UTP_TRANSFER_REQ_DOOR_BELL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) spin_lock_irqsave(hba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) set_bit(task_tag, &hba->outstanding_reqs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) ufshcd_writel(hba, 1 << task_tag,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) REG_UTP_TRANSFER_REQ_DOOR_BELL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) spin_unlock_irqrestore(hba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) /* Make sure that doorbell is committed immediately */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) * ufshcd_copy_sense_data - Copy sense data in case of check condition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) * @lrbp: pointer to local reference block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) static inline void ufshcd_copy_sense_data(struct ufshcd_lrb *lrbp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) int len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) if (lrbp->sense_buffer &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) ufshcd_get_rsp_upiu_data_seg_len(lrbp->ucd_rsp_ptr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) int len_to_copy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) len = be16_to_cpu(lrbp->ucd_rsp_ptr->sr.sense_data_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) len_to_copy = min_t(int, UFS_SENSE_SIZE, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) memcpy(lrbp->sense_buffer, lrbp->ucd_rsp_ptr->sr.sense_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) len_to_copy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) * ufshcd_copy_query_response() - Copy the Query Response and the data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) * descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) * @hba: per adapter instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) * @lrbp: pointer to local reference block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) static
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) int ufshcd_copy_query_response(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) struct ufs_query_res *query_res = &hba->dev_cmd.query.response;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) memcpy(&query_res->upiu_res, &lrbp->ucd_rsp_ptr->qr, QUERY_OSF_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) /* Get the descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) if (hba->dev_cmd.query.descriptor &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) lrbp->ucd_rsp_ptr->qr.opcode == UPIU_QUERY_OPCODE_READ_DESC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) u8 *descp = (u8 *)lrbp->ucd_rsp_ptr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) GENERAL_UPIU_REQUEST_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) u16 resp_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) u16 buf_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) /* data segment length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) resp_len = be32_to_cpu(lrbp->ucd_rsp_ptr->header.dword_2) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) MASK_QUERY_DATA_SEG_LEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) buf_len = be16_to_cpu(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) hba->dev_cmd.query.request.upiu_req.length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) if (likely(buf_len >= resp_len)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) memcpy(hba->dev_cmd.query.descriptor, descp, resp_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) dev_warn(hba->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) "%s: rsp size %d is bigger than buffer size %d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) __func__, resp_len, buf_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) * ufshcd_hba_capabilities - Read controller capabilities
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) * @hba: per adapter instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) * Return: 0 on success, negative on error.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) static inline int ufshcd_hba_capabilities(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) hba->capabilities = ufshcd_readl(hba, REG_CONTROLLER_CAPABILITIES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) /* nutrs and nutmrs are 0 based values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) hba->nutrs = (hba->capabilities & MASK_TRANSFER_REQUESTS_SLOTS) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) hba->nutmrs =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) ((hba->capabilities & MASK_TASK_MANAGEMENT_REQUEST_SLOTS) >> 16) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) ufs_hba_add_info(hba)->reserved_slot = hba->nutrs - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) /* Read crypto capabilities */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) err = ufshcd_hba_init_crypto_capabilities(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) dev_err(hba->dev, "crypto setup failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) * ufshcd_ready_for_uic_cmd - Check if controller is ready
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) * to accept UIC commands
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) * @hba: per adapter instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) * Return true on success, else false
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) static inline bool ufshcd_ready_for_uic_cmd(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) if (ufshcd_readl(hba, REG_CONTROLLER_STATUS) & UIC_COMMAND_READY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) * ufshcd_get_upmcrs - Get the power mode change request status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) * @hba: Pointer to adapter instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) * This function gets the UPMCRS field of HCS register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) * Returns value of UPMCRS field
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) static inline u8 ufshcd_get_upmcrs(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) >> 8) & 0x7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) * ufshcd_dispatch_uic_cmd - Dispatch UIC commands to unipro layers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) * @hba: per adapter instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) * @uic_cmd: UIC command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) * Mutex must be held.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) ufshcd_dispatch_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) WARN_ON(hba->active_uic_cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) hba->active_uic_cmd = uic_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) /* Write Args */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) ufshcd_writel(hba, uic_cmd->argument1, REG_UIC_COMMAND_ARG_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) ufshcd_writel(hba, uic_cmd->argument2, REG_UIC_COMMAND_ARG_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) ufshcd_writel(hba, uic_cmd->argument3, REG_UIC_COMMAND_ARG_3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) ufshcd_add_uic_command_trace(hba, uic_cmd, "send");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) /* Write UIC Cmd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) ufshcd_writel(hba, uic_cmd->command & COMMAND_OPCODE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) REG_UIC_COMMAND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) * ufshcd_wait_for_uic_cmd - Wait complectioin of UIC command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) * @hba: per adapter instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) * @uic_cmd: UIC command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) * Must be called with mutex held.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) * Returns 0 only if success.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) ufshcd_wait_for_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) if (wait_for_completion_timeout(&uic_cmd->done,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) msecs_to_jiffies(UIC_CMD_TIMEOUT))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) ret = uic_cmd->argument2 & MASK_UIC_COMMAND_RESULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) ret = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) dev_err(hba->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) "uic cmd 0x%x with arg3 0x%x completion timeout\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) uic_cmd->command, uic_cmd->argument3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) if (!uic_cmd->cmd_active) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) dev_err(hba->dev, "%s: UIC cmd has been completed, return the result\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) ret = uic_cmd->argument2 & MASK_UIC_COMMAND_RESULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) spin_lock_irqsave(hba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) hba->active_uic_cmd = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) spin_unlock_irqrestore(hba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) * __ufshcd_send_uic_cmd - Send UIC commands and retrieve the result
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) * @hba: per adapter instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) * @uic_cmd: UIC command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) * @completion: initialize the completion only if this is set to true
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) * Identical to ufshcd_send_uic_cmd() expect mutex. Must be called
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) * with mutex held and host_lock locked.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) * Returns 0 only if success.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) __ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) bool completion)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) if (!ufshcd_ready_for_uic_cmd(hba)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) dev_err(hba->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) "Controller not ready to accept UIC commands\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) if (completion)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) init_completion(&uic_cmd->done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) uic_cmd->cmd_active = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) ufshcd_dispatch_uic_cmd(hba, uic_cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) * ufshcd_send_uic_cmd - Send UIC commands and retrieve the result
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) * @hba: per adapter instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) * @uic_cmd: UIC command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) * Returns 0 only if success.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) int ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) if (hba->quirks & UFSHCD_QUIRK_BROKEN_UIC_CMD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) ufshcd_hold(hba, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) mutex_lock(&hba->uic_cmd_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) ufshcd_add_delay_before_dme_cmd(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) spin_lock_irqsave(hba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) ret = __ufshcd_send_uic_cmd(hba, uic_cmd, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) spin_unlock_irqrestore(hba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) ret = ufshcd_wait_for_uic_cmd(hba, uic_cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) mutex_unlock(&hba->uic_cmd_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) ufshcd_release(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) * ufshcd_map_sg - Map scatter-gather list to prdt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) * @hba: per adapter instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) * @lrbp: pointer to local reference block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) * Returns 0 in case of success, non-zero value in case of failure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) static int ufshcd_map_sg(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) struct ufshcd_sg_entry *prd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) struct scatterlist *sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) struct scsi_cmnd *cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) int sg_segments;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) cmd = lrbp->cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) sg_segments = scsi_dma_map(cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) if (sg_segments < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) return sg_segments;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) if (sg_segments) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) lrbp->utr_descriptor_ptr->prd_table_length =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) cpu_to_le16(sg_segments * hba->sg_entry_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) lrbp->utr_descriptor_ptr->prd_table_length =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) cpu_to_le16((u16) (sg_segments));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) prd = (struct ufshcd_sg_entry *)lrbp->ucd_prdt_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) scsi_for_each_sg(cmd, sg, sg_segments, i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) prd->size =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) cpu_to_le32(((u32) sg_dma_len(sg))-1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) prd->base_addr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) cpu_to_le32(lower_32_bits(sg->dma_address));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) prd->upper_addr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) cpu_to_le32(upper_32_bits(sg->dma_address));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) prd->reserved = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) prd = (void *)prd + hba->sg_entry_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) lrbp->utr_descriptor_ptr->prd_table_length = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) trace_android_vh_ufs_fill_prdt(hba, lrbp, sg_segments, &err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) * ufshcd_enable_intr - enable interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) * @hba: per adapter instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) * @intrs: interrupt bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) static void ufshcd_enable_intr(struct ufs_hba *hba, u32 intrs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) if (hba->ufs_version == ufshci_version(1, 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) u32 rw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) rw = set & INTERRUPT_MASK_RW_VER_10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) set = rw | ((set ^ intrs) & intrs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) set |= intrs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) * ufshcd_disable_intr - disable interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) * @hba: per adapter instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) * @intrs: interrupt bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) static void ufshcd_disable_intr(struct ufs_hba *hba, u32 intrs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) if (hba->ufs_version == ufshci_version(1, 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) u32 rw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) rw = (set & INTERRUPT_MASK_RW_VER_10) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) ~(intrs & INTERRUPT_MASK_RW_VER_10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) set = rw | ((set & intrs) & ~INTERRUPT_MASK_RW_VER_10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) set &= ~intrs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) * ufshcd_prepare_req_desc_hdr() - Fills the requests header
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) * descriptor according to request
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) * @lrbp: pointer to local reference block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) * @upiu_flags: flags required in the header
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) * @cmd_dir: requests data direction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) static void ufshcd_prepare_req_desc_hdr(struct ufshcd_lrb *lrbp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) u8 *upiu_flags, enum dma_data_direction cmd_dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) struct utp_transfer_req_desc *req_desc = lrbp->utr_descriptor_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) u32 data_direction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) u32 dword_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) u32 dword_1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) u32 dword_3 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) if (cmd_dir == DMA_FROM_DEVICE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) data_direction = UTP_DEVICE_TO_HOST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) *upiu_flags = UPIU_CMD_FLAGS_READ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) } else if (cmd_dir == DMA_TO_DEVICE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) data_direction = UTP_HOST_TO_DEVICE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) *upiu_flags = UPIU_CMD_FLAGS_WRITE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) data_direction = UTP_NO_DATA_TRANSFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) *upiu_flags = UPIU_CMD_FLAGS_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) dword_0 = data_direction | (lrbp->command_type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) << UPIU_COMMAND_TYPE_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) if (lrbp->intr_cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) dword_0 |= UTP_REQ_DESC_INT_CMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) /* Prepare crypto related dwords */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) ufshcd_prepare_req_desc_hdr_crypto(lrbp, &dword_0, &dword_1, &dword_3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) /* Transfer request descriptor header fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) req_desc->header.dword_0 = cpu_to_le32(dword_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) req_desc->header.dword_1 = cpu_to_le32(dword_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) * assigning invalid value for command status. Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) * updates OCS on command completion, with the command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) * status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) req_desc->header.dword_2 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) cpu_to_le32(OCS_INVALID_COMMAND_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) req_desc->header.dword_3 = cpu_to_le32(dword_3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) req_desc->prd_table_length = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) * ufshcd_prepare_utp_scsi_cmd_upiu() - fills the utp_transfer_req_desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) * for scsi commands
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) * @lrbp: local reference block pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) * @upiu_flags: flags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) static
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) void ufshcd_prepare_utp_scsi_cmd_upiu(struct ufshcd_lrb *lrbp, u8 upiu_flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) struct scsi_cmnd *cmd = lrbp->cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) unsigned short cdb_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) /* command descriptor fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) ucd_req_ptr->header.dword_0 = UPIU_HEADER_DWORD(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) UPIU_TRANSACTION_COMMAND, upiu_flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) lrbp->lun, lrbp->task_tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) ucd_req_ptr->header.dword_1 = UPIU_HEADER_DWORD(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) UPIU_COMMAND_SET_TYPE_SCSI, 0, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) /* Total EHS length and Data segment length will be zero */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) ucd_req_ptr->header.dword_2 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) ucd_req_ptr->sc.exp_data_transfer_len = cpu_to_be32(cmd->sdb.length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) cdb_len = min_t(unsigned short, cmd->cmd_len, UFS_CDB_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) memset(ucd_req_ptr->sc.cdb, 0, UFS_CDB_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) memcpy(ucd_req_ptr->sc.cdb, cmd->cmnd, cdb_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) * ufshcd_prepare_utp_query_req_upiu() - fills the utp_transfer_req_desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) * for query requsts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) * @hba: UFS hba
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) * @lrbp: local reference block pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) * @upiu_flags: flags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) static void ufshcd_prepare_utp_query_req_upiu(struct ufs_hba *hba,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530) struct ufshcd_lrb *lrbp, u8 upiu_flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) struct ufs_query *query = &hba->dev_cmd.query;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) u16 len = be16_to_cpu(query->request.upiu_req.length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) /* Query request header */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) ucd_req_ptr->header.dword_0 = UPIU_HEADER_DWORD(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) UPIU_TRANSACTION_QUERY_REQ, upiu_flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) lrbp->lun, lrbp->task_tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) ucd_req_ptr->header.dword_1 = UPIU_HEADER_DWORD(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) 0, query->request.query_func, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) /* Data segment length only need for WRITE_DESC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_WRITE_DESC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) ucd_req_ptr->header.dword_2 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) UPIU_HEADER_DWORD(0, 0, (len >> 8), (u8)len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) ucd_req_ptr->header.dword_2 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) /* Copy the Query Request buffer as is */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) memcpy(&ucd_req_ptr->qr, &query->request.upiu_req,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) QUERY_OSF_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) /* Copy the Descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_WRITE_DESC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) memcpy(ucd_req_ptr + 1, query->descriptor, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) static inline void ufshcd_prepare_utp_nop_upiu(struct ufshcd_lrb *lrbp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) memset(ucd_req_ptr, 0, sizeof(struct utp_upiu_req));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567) /* command descriptor fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) ucd_req_ptr->header.dword_0 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) UPIU_HEADER_DWORD(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) UPIU_TRANSACTION_NOP_OUT, 0, 0, lrbp->task_tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571) /* clear rest of the fields of basic header */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) ucd_req_ptr->header.dword_1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) ucd_req_ptr->header.dword_2 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579) * ufshcd_compose_devman_upiu - UFS Protocol Information Unit(UPIU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580) * for Device Management Purposes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) * @hba: per adapter instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) * @lrbp: pointer to local reference block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584) static int ufshcd_compose_devman_upiu(struct ufs_hba *hba,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) struct ufshcd_lrb *lrbp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) u8 upiu_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) if (hba->ufs_version <= ufshci_version(1, 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) lrbp->command_type = UTP_CMD_TYPE_DEV_MANAGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595) ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags, DMA_NONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596) if (hba->dev_cmd.type == DEV_CMD_TYPE_QUERY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) ufshcd_prepare_utp_query_req_upiu(hba, lrbp, upiu_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598) else if (hba->dev_cmd.type == DEV_CMD_TYPE_NOP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) ufshcd_prepare_utp_nop_upiu(lrbp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607) * ufshcd_comp_scsi_upiu - UFS Protocol Information Unit(UPIU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608) * for SCSI Purposes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609) * @hba: per adapter instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) * @lrbp: pointer to local reference block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612) static int ufshcd_comp_scsi_upiu(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614) u8 upiu_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617) if (hba->ufs_version <= ufshci_version(1, 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618) lrbp->command_type = UTP_CMD_TYPE_SCSI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620) lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622) if (likely(lrbp->cmd)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623) ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624) lrbp->cmd->sc_data_direction);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625) ufshcd_prepare_utp_scsi_cmd_upiu(lrbp, upiu_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634) * ufshcd_upiu_wlun_to_scsi_wlun - maps UPIU W-LUN id to SCSI W-LUN ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635) * @upiu_wlun_id: UPIU W-LUN id
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637) * Returns SCSI W-LUN id
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639) static inline u16 ufshcd_upiu_wlun_to_scsi_wlun(u8 upiu_wlun_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641) return (upiu_wlun_id & ~UFS_UPIU_WLUN_ID) | SCSI_W_LUN_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644) static void ufshcd_init_lrb(struct ufs_hba *hba, struct ufshcd_lrb *lrb, int i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646) struct utp_transfer_cmd_desc *cmd_descp = (void *)hba->ucdl_base_addr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647) i * sizeof_utp_transfer_cmd_desc(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648) struct utp_transfer_req_desc *utrdlp = hba->utrdl_base_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649) dma_addr_t cmd_desc_element_addr = hba->ucdl_dma_addr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650) i * sizeof_utp_transfer_cmd_desc(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651) u16 response_offset = offsetof(struct utp_transfer_cmd_desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652) response_upiu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653) u16 prdt_offset = offsetof(struct utp_transfer_cmd_desc, prd_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655) lrb->utr_descriptor_ptr = utrdlp + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656) lrb->utrd_dma_addr = hba->utrdl_dma_addr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657) i * sizeof(struct utp_transfer_req_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658) lrb->ucd_req_ptr = (struct utp_upiu_req *)cmd_descp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659) lrb->ucd_req_dma_addr = cmd_desc_element_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660) lrb->ucd_rsp_ptr = (struct utp_upiu_rsp *)cmd_descp->response_upiu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661) lrb->ucd_rsp_dma_addr = cmd_desc_element_addr + response_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662) lrb->ucd_prdt_ptr = (struct ufshcd_sg_entry *)cmd_descp->prd_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663) lrb->ucd_prdt_dma_addr = cmd_desc_element_addr + prdt_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667) * ufshcd_queuecommand - main entry point for SCSI requests
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668) * @host: SCSI host pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669) * @cmd: command from SCSI Midlayer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671) * Returns 0 for success, non-zero in case of failure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673) static int ufshcd_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675) struct ufshcd_lrb *lrbp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676) struct ufs_hba *hba;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677) int tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680) hba = shost_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682) tag = cmd->request->tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683) if (!ufshcd_valid_tag(hba, tag)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684) dev_err(hba->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685) "%s: invalid command tag %d: cmd=0x%p, cmd->request=0x%p",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686) __func__, tag, cmd, cmd->request);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690) if (!down_read_trylock(&hba->clk_scaling_lock))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691) return SCSI_MLQUEUE_HOST_BUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693) switch (hba->ufshcd_state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694) case UFSHCD_STATE_OPERATIONAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695) case UFSHCD_STATE_EH_SCHEDULED_NON_FATAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697) case UFSHCD_STATE_EH_SCHEDULED_FATAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699) * pm_runtime_get_sync() is used at error handling preparation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700) * stage. If a scsi cmd, e.g. the SSU cmd, is sent from hba's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701) * PM ops, it can never be finished if we let SCSI layer keep
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702) * retrying it, which gets err handler stuck forever. Neither
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703) * can we let the scsi cmd pass through, because UFS is in bad
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704) * state, the scsi cmd may eventually time out, which will get
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705) * err handler blocked for too long. So, just fail the scsi cmd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706) * sent from PM ops, err handler can recover PM error anyways.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708) if (hba->pm_op_in_progress) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709) hba->force_reset = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710) set_host_byte(cmd, DID_BAD_TARGET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711) cmd->scsi_done(cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715) case UFSHCD_STATE_RESET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716) err = SCSI_MLQUEUE_HOST_BUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718) case UFSHCD_STATE_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2719) set_host_byte(cmd, DID_ERROR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2720) cmd->scsi_done(cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2721) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2722) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2723) dev_WARN_ONCE(hba->dev, 1, "%s: invalid state %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2724) __func__, hba->ufshcd_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2725) set_host_byte(cmd, DID_BAD_TARGET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2726) cmd->scsi_done(cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2727) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2728) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2730) hba->req_abort_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2732) err = ufshcd_hold(hba, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2733) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2734) err = SCSI_MLQUEUE_HOST_BUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2735) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2736) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2737) WARN_ON(ufshcd_is_clkgating_allowed(hba) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2738) (hba->clk_gating.state != CLKS_ON));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2740) lrbp = &hba->lrb[tag];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2741) WARN_ON(lrbp->cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2742) lrbp->cmd = cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2743) lrbp->sense_bufflen = UFS_SENSE_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2744) lrbp->sense_buffer = cmd->sense_buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2745) lrbp->task_tag = tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2746) lrbp->lun = ufshcd_scsi_to_upiu_lun(cmd->device->lun);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2747) lrbp->intr_cmd = !ufshcd_is_intr_aggr_allowed(hba) ? true : false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2749) ufshcd_prepare_lrbp_crypto(cmd->request, lrbp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2751) trace_android_vh_ufs_prepare_command(hba, cmd->request, lrbp, &err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2752) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2753) lrbp->cmd = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2754) ufshcd_release(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2755) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2756) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2758) lrbp->req_abort_skip = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2760) err = ufshpb_prep(hba, lrbp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2761) if (err == -EAGAIN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2762) lrbp->cmd = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2763) ufshcd_release(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2764) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2765) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2767) ufshcd_comp_scsi_upiu(hba, lrbp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2769) err = ufshcd_map_sg(hba, lrbp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2770) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2771) lrbp->cmd = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2772) ufshcd_release(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2773) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2774) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2775) /* Make sure descriptors are ready before ringing the doorbell */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2776) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2778) ufshcd_send_command(hba, tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2779) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2780) up_read(&hba->clk_scaling_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2781) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2782) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2784) static int ufshcd_compose_dev_cmd(struct ufs_hba *hba,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2785) struct ufshcd_lrb *lrbp, enum dev_cmd_type cmd_type, int tag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2786) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2787) lrbp->cmd = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2788) lrbp->sense_bufflen = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2789) lrbp->sense_buffer = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2790) lrbp->task_tag = tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2791) lrbp->lun = 0; /* device management cmd is not specific to any LUN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2792) lrbp->intr_cmd = true; /* No interrupt aggregation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2793) ufshcd_prepare_lrbp_crypto(NULL, lrbp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2794) hba->dev_cmd.type = cmd_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2796) return ufshcd_compose_devman_upiu(hba, lrbp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2797) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2799) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2800) ufshcd_clear_cmd(struct ufs_hba *hba, int tag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2801) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2802) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2803) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2804) u32 mask = 1 << tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2806) /* clear outstanding transaction before retry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2807) spin_lock_irqsave(hba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2808) ufshcd_utrl_clear(hba, tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2809) spin_unlock_irqrestore(hba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2811) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2812) * wait for for h/w to clear corresponding bit in door-bell.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2813) * max. wait is 1 sec.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2814) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2815) err = ufshcd_wait_for_register(hba,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2816) REG_UTP_TRANSFER_REQ_DOOR_BELL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2817) mask, ~mask, 1000, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2819) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2820) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2822) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2823) ufshcd_check_query_response(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2824) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2825) struct ufs_query_res *query_res = &hba->dev_cmd.query.response;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2827) /* Get the UPIU response */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2828) query_res->response = ufshcd_get_rsp_upiu_result(lrbp->ucd_rsp_ptr) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2829) UPIU_RSP_CODE_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2830) return query_res->response;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2831) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2833) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2834) * ufshcd_dev_cmd_completion() - handles device management command responses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2835) * @hba: per adapter instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2836) * @lrbp: pointer to local reference block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2837) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2838) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2839) ufshcd_dev_cmd_completion(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2840) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2841) int resp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2842) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2844) hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2845) resp = ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2847) switch (resp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2848) case UPIU_TRANSACTION_NOP_IN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2849) if (hba->dev_cmd.type != DEV_CMD_TYPE_NOP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2850) err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2851) dev_err(hba->dev, "%s: unexpected response %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2852) __func__, resp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2853) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2854) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2855) case UPIU_TRANSACTION_QUERY_RSP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2856) err = ufshcd_check_query_response(hba, lrbp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2857) if (!err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2858) err = ufshcd_copy_query_response(hba, lrbp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2859) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2860) case UPIU_TRANSACTION_REJECT_UPIU:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2861) /* TODO: handle Reject UPIU Response */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2862) err = -EPERM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2863) dev_err(hba->dev, "%s: Reject UPIU not fully implemented\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2864) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2865) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2866) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2867) err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2868) dev_err(hba->dev, "%s: Invalid device management cmd response: %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2869) __func__, resp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2870) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2871) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2873) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2874) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2876) static int ufshcd_wait_for_dev_cmd(struct ufs_hba *hba,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2877) struct ufshcd_lrb *lrbp, int max_timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2878) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2879) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2880) unsigned long time_left;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2881) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2883) time_left = wait_for_completion_timeout(hba->dev_cmd.complete,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2884) msecs_to_jiffies(max_timeout));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2886) /* Make sure descriptors are ready before ringing the doorbell */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2887) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2888) spin_lock_irqsave(hba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2889) hba->dev_cmd.complete = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2890) if (likely(time_left)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2891) err = ufshcd_get_tr_ocs(lrbp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2892) if (!err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2893) err = ufshcd_dev_cmd_completion(hba, lrbp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2894) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2895) spin_unlock_irqrestore(hba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2897) if (!time_left) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2898) err = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2899) dev_dbg(hba->dev, "%s: dev_cmd request timedout, tag %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2900) __func__, lrbp->task_tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2901) if (!ufshcd_clear_cmd(hba, lrbp->task_tag))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2902) /* successfully cleared the command, retry if needed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2903) err = -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2904) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2905) * in case of an error, after clearing the doorbell,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2906) * we also need to clear the outstanding_request
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2907) * field in hba
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2908) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2909) ufshcd_outstanding_req_clear(hba, lrbp->task_tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2910) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2912) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2913) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2915) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2916) * ufshcd_exec_dev_cmd - API for sending device management requests
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2917) * @hba: UFS hba
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2918) * @cmd_type: specifies the type (NOP, Query...)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2919) * @timeout: timeout in milliseconds
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2920) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2921) * NOTE: Since there is only one available tag for device management commands,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2922) * it is expected you hold the hba->dev_cmd.lock mutex.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2923) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2924) static int ufshcd_exec_dev_cmd(struct ufs_hba *hba,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2925) enum dev_cmd_type cmd_type, int timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2926) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2927) DECLARE_COMPLETION_ONSTACK(wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2928) const u32 tag = ufs_hba_add_info(hba)->reserved_slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2929) struct ufshcd_lrb *lrbp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2930) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2932) /* Protects use of ufs_hba_add_info(hba)->reserved_slot. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2933) lockdep_assert_held(&hba->dev_cmd.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2935) down_read(&hba->clk_scaling_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2937) lrbp = &hba->lrb[tag];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2938) WARN_ON(lrbp->cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2939) err = ufshcd_compose_dev_cmd(hba, lrbp, cmd_type, tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2940) if (unlikely(err))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2941) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2943) hba->dev_cmd.complete = &wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2945) ufshcd_add_query_upiu_trace(hba, tag, "query_send");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2946) /* Make sure descriptors are ready before ringing the doorbell */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2947) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2949) ufshcd_send_command(hba, tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2950) err = ufshcd_wait_for_dev_cmd(hba, lrbp, timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2951) ufshcd_add_query_upiu_trace(hba, tag,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2952) err ? "query_complete_err" : "query_complete");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2954) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2955) up_read(&hba->clk_scaling_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2956) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2957) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2959) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2960) * ufshcd_init_query() - init the query response and request parameters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2961) * @hba: per-adapter instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2962) * @request: address of the request pointer to be initialized
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2963) * @response: address of the response pointer to be initialized
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2964) * @opcode: operation to perform
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2965) * @idn: flag idn to access
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2966) * @index: LU number to access
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2967) * @selector: query/flag/descriptor further identification
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2968) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2969) static inline void ufshcd_init_query(struct ufs_hba *hba,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2970) struct ufs_query_req **request, struct ufs_query_res **response,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2971) enum query_opcode opcode, u8 idn, u8 index, u8 selector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2972) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2973) *request = &hba->dev_cmd.query.request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2974) *response = &hba->dev_cmd.query.response;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2975) memset(*request, 0, sizeof(struct ufs_query_req));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2976) memset(*response, 0, sizeof(struct ufs_query_res));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2977) (*request)->upiu_req.opcode = opcode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2978) (*request)->upiu_req.idn = idn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2979) (*request)->upiu_req.index = index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2980) (*request)->upiu_req.selector = selector;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2981) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2983) int ufshcd_query_flag_retry(struct ufs_hba *hba,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2984) enum query_opcode opcode, enum flag_idn idn, u8 index, bool *flag_res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2985) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2986) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2987) int retries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2989) for (retries = 0; retries < QUERY_REQ_RETRIES; retries++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2990) ret = ufshcd_query_flag(hba, opcode, idn, index, flag_res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2991) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2992) dev_dbg(hba->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2993) "%s: failed with error %d, retries %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2994) __func__, ret, retries);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2995) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2996) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2997) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2999) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3000) dev_err(hba->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3001) "%s: query attribute, opcode %d, idn %d, failed with error %d after %d retires\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3002) __func__, opcode, idn, ret, retries);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3003) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3004) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3005) EXPORT_SYMBOL_GPL(ufshcd_query_flag_retry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3007) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3008) * ufshcd_query_flag() - API function for sending flag query requests
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3009) * @hba: per-adapter instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3010) * @opcode: flag query to perform
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3011) * @idn: flag idn to access
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3012) * @index: flag index to access
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3013) * @flag_res: the flag value after the query request completes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3014) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3015) * Returns 0 for success, non-zero in case of failure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3016) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3017) int ufshcd_query_flag(struct ufs_hba *hba, enum query_opcode opcode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3018) enum flag_idn idn, u8 index, bool *flag_res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3019) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3020) struct ufs_query_req *request = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3021) struct ufs_query_res *response = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3022) int err, selector = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3023) int timeout = QUERY_REQ_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3025) BUG_ON(!hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3027) ufshcd_hold(hba, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3028) mutex_lock(&hba->dev_cmd.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3029) ufshcd_init_query(hba, &request, &response, opcode, idn, index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3030) selector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3032) switch (opcode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3033) case UPIU_QUERY_OPCODE_SET_FLAG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3034) case UPIU_QUERY_OPCODE_CLEAR_FLAG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3035) case UPIU_QUERY_OPCODE_TOGGLE_FLAG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3036) request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3037) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3038) case UPIU_QUERY_OPCODE_READ_FLAG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3039) request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3040) if (!flag_res) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3041) /* No dummy reads */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3042) dev_err(hba->dev, "%s: Invalid argument for read request\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3043) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3044) err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3045) goto out_unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3046) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3047) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3048) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3049) dev_err(hba->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3050) "%s: Expected query flag opcode but got = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3051) __func__, opcode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3052) err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3053) goto out_unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3054) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3056) err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3058) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3059) dev_err(hba->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3060) "%s: Sending flag query for idn %d failed, err = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3061) __func__, idn, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3062) goto out_unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3063) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3065) if (flag_res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3066) *flag_res = (be32_to_cpu(response->upiu_res.value) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3067) MASK_QUERY_UPIU_FLAG_LOC) & 0x1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3069) out_unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3070) mutex_unlock(&hba->dev_cmd.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3071) ufshcd_release(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3072) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3073) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3074) EXPORT_SYMBOL_GPL(ufshcd_query_flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3076) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3077) * ufshcd_query_attr - API function for sending attribute requests
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3078) * @hba: per-adapter instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3079) * @opcode: attribute opcode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3080) * @idn: attribute idn to access
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3081) * @index: index field
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3082) * @selector: selector field
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3083) * @attr_val: the attribute value after the query request completes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3084) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3085) * Returns 0 for success, non-zero in case of failure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3086) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3087) int ufshcd_query_attr(struct ufs_hba *hba, enum query_opcode opcode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3088) enum attr_idn idn, u8 index, u8 selector, u32 *attr_val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3089) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3090) struct ufs_query_req *request = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3091) struct ufs_query_res *response = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3092) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3094) BUG_ON(!hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3096) if (!attr_val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3097) dev_err(hba->dev, "%s: attribute value required for opcode 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3098) __func__, opcode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3099) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3102) ufshcd_hold(hba, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3104) mutex_lock(&hba->dev_cmd.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3105) ufshcd_init_query(hba, &request, &response, opcode, idn, index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3106) selector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3108) switch (opcode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3109) case UPIU_QUERY_OPCODE_WRITE_ATTR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3110) request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3111) request->upiu_req.value = cpu_to_be32(*attr_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3112) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3113) case UPIU_QUERY_OPCODE_READ_ATTR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3114) request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3115) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3116) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3117) dev_err(hba->dev, "%s: Expected query attr opcode but got = 0x%.2x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3118) __func__, opcode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3119) err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3120) goto out_unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3123) err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3125) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3126) dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, index %d, err = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3127) __func__, opcode, idn, index, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3128) goto out_unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3131) *attr_val = be32_to_cpu(response->upiu_res.value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3133) out_unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3134) mutex_unlock(&hba->dev_cmd.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3135) ufshcd_release(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3136) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3138) EXPORT_SYMBOL_GPL(ufshcd_query_attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3140) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3141) * ufshcd_query_attr_retry() - API function for sending query
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3142) * attribute with retries
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3143) * @hba: per-adapter instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3144) * @opcode: attribute opcode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3145) * @idn: attribute idn to access
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3146) * @index: index field
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3147) * @selector: selector field
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3148) * @attr_val: the attribute value after the query request
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3149) * completes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3150) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3151) * Returns 0 for success, non-zero in case of failure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3152) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3153) int ufshcd_query_attr_retry(struct ufs_hba *hba,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3154) enum query_opcode opcode, enum attr_idn idn, u8 index, u8 selector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3155) u32 *attr_val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3156) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3157) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3158) u32 retries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3160) for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3161) ret = ufshcd_query_attr(hba, opcode, idn, index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3162) selector, attr_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3163) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3164) dev_dbg(hba->dev, "%s: failed with error %d, retries %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3165) __func__, ret, retries);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3166) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3167) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3170) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3171) dev_err(hba->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3172) "%s: query attribute, idn %d, failed with error %d after %d retires\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3173) __func__, idn, ret, QUERY_REQ_RETRIES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3174) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3176) EXPORT_SYMBOL_GPL(ufshcd_query_attr_retry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3178) static int __ufshcd_query_descriptor(struct ufs_hba *hba,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3179) enum query_opcode opcode, enum desc_idn idn, u8 index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3180) u8 selector, u8 *desc_buf, int *buf_len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3181) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3182) struct ufs_query_req *request = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3183) struct ufs_query_res *response = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3184) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3186) BUG_ON(!hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3188) if (!desc_buf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3189) dev_err(hba->dev, "%s: descriptor buffer required for opcode 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3190) __func__, opcode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3191) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3194) if (*buf_len < QUERY_DESC_MIN_SIZE || *buf_len > QUERY_DESC_MAX_SIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3195) dev_err(hba->dev, "%s: descriptor buffer size (%d) is out of range\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3196) __func__, *buf_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3197) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3200) ufshcd_hold(hba, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3202) mutex_lock(&hba->dev_cmd.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3203) ufshcd_init_query(hba, &request, &response, opcode, idn, index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3204) selector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3205) hba->dev_cmd.query.descriptor = desc_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3206) request->upiu_req.length = cpu_to_be16(*buf_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3208) switch (opcode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3209) case UPIU_QUERY_OPCODE_WRITE_DESC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3210) request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3211) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3212) case UPIU_QUERY_OPCODE_READ_DESC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3213) request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3214) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3215) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3216) dev_err(hba->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3217) "%s: Expected query descriptor opcode but got = 0x%.2x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3218) __func__, opcode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3219) err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3220) goto out_unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3223) err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3225) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3226) dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, index %d, err = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3227) __func__, opcode, idn, index, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3228) goto out_unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3231) *buf_len = be16_to_cpu(response->upiu_res.length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3233) out_unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3234) hba->dev_cmd.query.descriptor = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3235) mutex_unlock(&hba->dev_cmd.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3236) ufshcd_release(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3237) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3240) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3241) * ufshcd_query_descriptor_retry - API function for sending descriptor requests
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3242) * @hba: per-adapter instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3243) * @opcode: attribute opcode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3244) * @idn: attribute idn to access
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3245) * @index: index field
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3246) * @selector: selector field
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3247) * @desc_buf: the buffer that contains the descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3248) * @buf_len: length parameter passed to the device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3249) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3250) * Returns 0 for success, non-zero in case of failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3251) * The buf_len parameter will contain, on return, the length parameter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3252) * received on the response.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3253) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3254) int ufshcd_query_descriptor_retry(struct ufs_hba *hba,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3255) enum query_opcode opcode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3256) enum desc_idn idn, u8 index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3257) u8 selector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3258) u8 *desc_buf, int *buf_len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3259) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3260) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3261) int retries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3263) for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3264) err = __ufshcd_query_descriptor(hba, opcode, idn, index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3265) selector, desc_buf, buf_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3266) if (!err || err == -EINVAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3267) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3270) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3272) EXPORT_SYMBOL_GPL(ufshcd_query_descriptor_retry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3274) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3275) * ufshcd_map_desc_id_to_length - map descriptor IDN to its length
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3276) * @hba: Pointer to adapter instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3277) * @desc_id: descriptor idn value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3278) * @desc_len: mapped desc length (out)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3279) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3280) void ufshcd_map_desc_id_to_length(struct ufs_hba *hba, enum desc_idn desc_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3281) int *desc_len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3282) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3283) if (desc_id >= QUERY_DESC_IDN_MAX || desc_id == QUERY_DESC_IDN_RFU_0 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3284) desc_id == QUERY_DESC_IDN_RFU_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3285) *desc_len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3286) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3287) *desc_len = hba->desc_size[desc_id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3289) EXPORT_SYMBOL(ufshcd_map_desc_id_to_length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3291) static void ufshcd_update_desc_length(struct ufs_hba *hba,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3292) enum desc_idn desc_id, int desc_index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3293) unsigned char desc_len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3294) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3295) if (hba->desc_size[desc_id] == QUERY_DESC_MAX_SIZE &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3296) desc_id != QUERY_DESC_IDN_STRING && desc_index != UFS_RPMB_UNIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3297) /* For UFS 3.1, the normal unit descriptor is 10 bytes larger
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3298) * than the RPMB unit, however, both descriptors share the same
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3299) * desc_idn, to cover both unit descriptors with one length, we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3300) * choose the normal unit descriptor length by desc_index.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3301) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3302) hba->desc_size[desc_id] = desc_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3305) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3306) * ufshcd_read_desc_param - read the specified descriptor parameter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3307) * @hba: Pointer to adapter instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3308) * @desc_id: descriptor idn value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3309) * @desc_index: descriptor index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3310) * @param_offset: offset of the parameter to read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3311) * @param_read_buf: pointer to buffer where parameter would be read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3312) * @param_size: sizeof(param_read_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3313) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3314) * Return 0 in case of success, non-zero otherwise
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3315) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3316) int ufshcd_read_desc_param(struct ufs_hba *hba,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3317) enum desc_idn desc_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3318) int desc_index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3319) u8 param_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3320) u8 *param_read_buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3321) u8 param_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3322) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3323) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3324) u8 *desc_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3325) int buff_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3326) bool is_kmalloc = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3328) /* Safety check */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3329) if (desc_id >= QUERY_DESC_IDN_MAX || !param_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3330) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3332) /* Get the length of descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3333) ufshcd_map_desc_id_to_length(hba, desc_id, &buff_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3334) if (!buff_len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3335) dev_err(hba->dev, "%s: Failed to get desc length\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3336) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3339) if (param_offset >= buff_len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3340) dev_err(hba->dev, "%s: Invalid offset 0x%x in descriptor IDN 0x%x, length 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3341) __func__, param_offset, desc_id, buff_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3342) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3345) /* Check whether we need temp memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3346) if (param_offset != 0 || param_size < buff_len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3347) desc_buf = kzalloc(buff_len, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3348) if (!desc_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3349) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3350) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3351) desc_buf = param_read_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3352) is_kmalloc = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3355) /* Request for full descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3356) ret = ufshcd_query_descriptor_retry(hba, UPIU_QUERY_OPCODE_READ_DESC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3357) desc_id, desc_index, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3358) desc_buf, &buff_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3360) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3361) dev_err(hba->dev, "%s: Failed reading descriptor. desc_id %d, desc_index %d, param_offset %d, ret %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3362) __func__, desc_id, desc_index, param_offset, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3363) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3366) /* Sanity check */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3367) if (desc_buf[QUERY_DESC_DESC_TYPE_OFFSET] != desc_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3368) dev_err(hba->dev, "%s: invalid desc_id %d in descriptor header\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3369) __func__, desc_buf[QUERY_DESC_DESC_TYPE_OFFSET]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3370) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3371) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3374) /* Update descriptor length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3375) buff_len = desc_buf[QUERY_DESC_LENGTH_OFFSET];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3376) ufshcd_update_desc_length(hba, desc_id, desc_index, buff_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3378) if (is_kmalloc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3379) /* Make sure we don't copy more data than available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3380) if (param_offset >= buff_len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3381) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3382) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3383) memcpy(param_read_buf, &desc_buf[param_offset],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3384) min_t(u32, param_size, buff_len - param_offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3386) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3387) if (is_kmalloc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3388) kfree(desc_buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3389) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3390) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3391) EXPORT_SYMBOL_GPL(ufshcd_read_desc_param);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3393) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3394) * struct uc_string_id - unicode string
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3395) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3396) * @len: size of this descriptor inclusive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3397) * @type: descriptor type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3398) * @uc: unicode string character
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3399) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3400) struct uc_string_id {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3401) u8 len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3402) u8 type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3403) wchar_t uc[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3404) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3406) /* replace non-printable or non-ASCII characters with spaces */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3407) static inline char ufshcd_remove_non_printable(u8 ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3408) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3409) return (ch >= 0x20 && ch <= 0x7e) ? ch : ' ';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3412) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3413) * ufshcd_read_string_desc - read string descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3414) * @hba: pointer to adapter instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3415) * @desc_index: descriptor index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3416) * @buf: pointer to buffer where descriptor would be read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3417) * the caller should free the memory.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3418) * @ascii: if true convert from unicode to ascii characters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3419) * null terminated string.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3420) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3421) * Return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3422) * * string size on success.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3423) * * -ENOMEM: on allocation failure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3424) * * -EINVAL: on a wrong parameter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3425) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3426) int ufshcd_read_string_desc(struct ufs_hba *hba, u8 desc_index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3427) u8 **buf, bool ascii)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3428) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3429) struct uc_string_id *uc_str;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3430) u8 *str;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3431) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3433) if (!buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3434) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3436) uc_str = kzalloc(QUERY_DESC_MAX_SIZE, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3437) if (!uc_str)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3438) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3440) ret = ufshcd_read_desc_param(hba, QUERY_DESC_IDN_STRING, desc_index, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3441) (u8 *)uc_str, QUERY_DESC_MAX_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3442) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3443) dev_err(hba->dev, "Reading String Desc failed after %d retries. err = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3444) QUERY_REQ_RETRIES, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3445) str = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3446) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3447) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3449) if (uc_str->len <= QUERY_DESC_HDR_SIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3450) dev_dbg(hba->dev, "String Desc is of zero length\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3451) str = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3452) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3453) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3456) if (ascii) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3457) ssize_t ascii_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3458) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3459) /* remove header and divide by 2 to move from UTF16 to UTF8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3460) ascii_len = (uc_str->len - QUERY_DESC_HDR_SIZE) / 2 + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3461) str = kzalloc(ascii_len, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3462) if (!str) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3463) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3464) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3465) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3467) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3468) * the descriptor contains string in UTF16 format
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3469) * we need to convert to utf-8 so it can be displayed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3470) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3471) ret = utf16s_to_utf8s(uc_str->uc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3472) uc_str->len - QUERY_DESC_HDR_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3473) UTF16_BIG_ENDIAN, str, ascii_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3475) /* replace non-printable or non-ASCII characters with spaces */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3476) for (i = 0; i < ret; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3477) str[i] = ufshcd_remove_non_printable(str[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3479) str[ret++] = '\0';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3481) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3482) str = kmemdup(uc_str, uc_str->len, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3483) if (!str) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3484) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3485) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3487) ret = uc_str->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3488) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3489) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3490) *buf = str;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3491) kfree(uc_str);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3492) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3493) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3495) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3496) * ufshcd_read_unit_desc_param - read the specified unit descriptor parameter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3497) * @hba: Pointer to adapter instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3498) * @lun: lun id
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3499) * @param_offset: offset of the parameter to read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3500) * @param_read_buf: pointer to buffer where parameter would be read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3501) * @param_size: sizeof(param_read_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3502) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3503) * Return 0 in case of success, non-zero otherwise
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3504) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3505) static inline int ufshcd_read_unit_desc_param(struct ufs_hba *hba,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3506) int lun,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3507) enum unit_desc_param param_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3508) u8 *param_read_buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3509) u32 param_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3510) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3511) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3512) * Unit descriptors are only available for general purpose LUs (LUN id
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3513) * from 0 to 7) and RPMB Well known LU.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3514) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3515) if (!ufs_is_valid_unit_desc_lun(&hba->dev_info, lun, param_offset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3516) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3518) return ufshcd_read_desc_param(hba, QUERY_DESC_IDN_UNIT, lun,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3519) param_offset, param_read_buf, param_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3520) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3522) static int ufshcd_get_ref_clk_gating_wait(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3523) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3524) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3525) u32 gating_wait = UFSHCD_REF_CLK_GATING_WAIT_US;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3527) if (hba->dev_info.wspecversion >= 0x300) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3528) err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3529) QUERY_ATTR_IDN_REF_CLK_GATING_WAIT_TIME, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3530) &gating_wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3531) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3532) dev_err(hba->dev, "Failed reading bRefClkGatingWait. err = %d, use default %uus\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3533) err, gating_wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3535) if (gating_wait == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3536) gating_wait = UFSHCD_REF_CLK_GATING_WAIT_US;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3537) dev_err(hba->dev, "Undefined ref clk gating wait time, use default %uus\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3538) gating_wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3539) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3541) hba->dev_info.clk_gating_wait_us = gating_wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3542) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3544) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3545) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3547) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3548) * ufshcd_memory_alloc - allocate memory for host memory space data structures
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3549) * @hba: per adapter instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3550) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3551) * 1. Allocate DMA memory for Command Descriptor array
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3552) * Each command descriptor consist of Command UPIU, Response UPIU and PRDT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3553) * 2. Allocate DMA memory for UTP Transfer Request Descriptor List (UTRDL).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3554) * 3. Allocate DMA memory for UTP Task Management Request Descriptor List
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3555) * (UTMRDL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3556) * 4. Allocate memory for local reference block(lrb).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3557) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3558) * Returns 0 for success, non-zero in case of failure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3559) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3560) static int ufshcd_memory_alloc(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3561) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3562) size_t utmrdl_size, utrdl_size, ucdl_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3564) /* Allocate memory for UTP command descriptors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3565) ucdl_size = (sizeof_utp_transfer_cmd_desc(hba) * hba->nutrs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3566) hba->ucdl_base_addr = dmam_alloc_coherent(hba->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3567) ucdl_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3568) &hba->ucdl_dma_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3569) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3571) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3572) * UFSHCI requires UTP command descriptor to be 128 byte aligned.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3573) * make sure hba->ucdl_dma_addr is aligned to PAGE_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3574) * if hba->ucdl_dma_addr is aligned to PAGE_SIZE, then it will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3575) * be aligned to 128 bytes as well
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3576) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3577) if (!hba->ucdl_base_addr ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3578) WARN_ON(hba->ucdl_dma_addr & (PAGE_SIZE - 1))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3579) dev_err(hba->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3580) "Command Descriptor Memory allocation failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3581) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3582) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3584) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3585) * Allocate memory for UTP Transfer descriptors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3586) * UFSHCI requires 1024 byte alignment of UTRD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3587) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3588) utrdl_size = (sizeof(struct utp_transfer_req_desc) * hba->nutrs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3589) hba->utrdl_base_addr = dmam_alloc_coherent(hba->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3590) utrdl_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3591) &hba->utrdl_dma_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3592) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3593) if (!hba->utrdl_base_addr ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3594) WARN_ON(hba->utrdl_dma_addr & (PAGE_SIZE - 1))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3595) dev_err(hba->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3596) "Transfer Descriptor Memory allocation failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3597) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3598) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3600) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3601) * Allocate memory for UTP Task Management descriptors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3602) * UFSHCI requires 1024 byte alignment of UTMRD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3603) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3604) utmrdl_size = sizeof(struct utp_task_req_desc) * hba->nutmrs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3605) hba->utmrdl_base_addr = dmam_alloc_coherent(hba->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3606) utmrdl_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3607) &hba->utmrdl_dma_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3608) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3609) if (!hba->utmrdl_base_addr ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3610) WARN_ON(hba->utmrdl_dma_addr & (PAGE_SIZE - 1))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3611) dev_err(hba->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3612) "Task Management Descriptor Memory allocation failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3613) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3614) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3616) /* Allocate memory for local reference block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3617) hba->lrb = devm_kcalloc(hba->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3618) hba->nutrs, sizeof(struct ufshcd_lrb),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3619) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3620) if (!hba->lrb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3621) dev_err(hba->dev, "LRB Memory allocation failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3622) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3623) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3624) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3625) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3626) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3627) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3629) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3630) * ufshcd_host_memory_configure - configure local reference block with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3631) * memory offsets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3632) * @hba: per adapter instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3633) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3634) * Configure Host memory space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3635) * 1. Update Corresponding UTRD.UCDBA and UTRD.UCDBAU with UCD DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3636) * address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3637) * 2. Update each UTRD with Response UPIU offset, Response UPIU length
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3638) * and PRDT offset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3639) * 3. Save the corresponding addresses of UTRD, UCD.CMD, UCD.RSP and UCD.PRDT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3640) * into local reference block.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3641) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3642) static void ufshcd_host_memory_configure(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3643) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3644) struct utp_transfer_req_desc *utrdlp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3645) dma_addr_t cmd_desc_dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3646) dma_addr_t cmd_desc_element_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3647) u16 response_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3648) u16 prdt_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3649) int cmd_desc_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3650) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3652) utrdlp = hba->utrdl_base_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3654) response_offset =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3655) offsetof(struct utp_transfer_cmd_desc, response_upiu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3656) prdt_offset =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3657) offsetof(struct utp_transfer_cmd_desc, prd_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3659) cmd_desc_size = sizeof_utp_transfer_cmd_desc(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3660) cmd_desc_dma_addr = hba->ucdl_dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3662) for (i = 0; i < hba->nutrs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3663) /* Configure UTRD with command descriptor base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3664) cmd_desc_element_addr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3665) (cmd_desc_dma_addr + (cmd_desc_size * i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3666) utrdlp[i].command_desc_base_addr_lo =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3667) cpu_to_le32(lower_32_bits(cmd_desc_element_addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3668) utrdlp[i].command_desc_base_addr_hi =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3669) cpu_to_le32(upper_32_bits(cmd_desc_element_addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3671) /* Response upiu and prdt offset should be in double words */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3672) if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3673) utrdlp[i].response_upiu_offset =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3674) cpu_to_le16(response_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3675) utrdlp[i].prd_table_offset =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3676) cpu_to_le16(prdt_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3677) utrdlp[i].response_upiu_length =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3678) cpu_to_le16(ALIGNED_UPIU_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3679) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3680) utrdlp[i].response_upiu_offset =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3681) cpu_to_le16(response_offset >> 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3682) utrdlp[i].prd_table_offset =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3683) cpu_to_le16(prdt_offset >> 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3684) utrdlp[i].response_upiu_length =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3685) cpu_to_le16(ALIGNED_UPIU_SIZE >> 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3686) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3688) ufshcd_init_lrb(hba, &hba->lrb[i], i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3689) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3690) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3692) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3693) * ufshcd_dme_link_startup - Notify Unipro to perform link startup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3694) * @hba: per adapter instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3695) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3696) * UIC_CMD_DME_LINK_STARTUP command must be issued to Unipro layer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3697) * in order to initialize the Unipro link startup procedure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3698) * Once the Unipro links are up, the device connected to the controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3699) * is detected.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3700) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3701) * Returns 0 on success, non-zero value on failure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3702) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3703) static int ufshcd_dme_link_startup(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3704) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3705) struct uic_command uic_cmd = {0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3706) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3708) uic_cmd.command = UIC_CMD_DME_LINK_STARTUP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3710) ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3711) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3712) dev_dbg(hba->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3713) "dme-link-startup: error code %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3714) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3715) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3716) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3717) * ufshcd_dme_reset - UIC command for DME_RESET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3718) * @hba: per adapter instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3719) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3720) * DME_RESET command is issued in order to reset UniPro stack.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3721) * This function now deals with cold reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3722) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3723) * Returns 0 on success, non-zero value on failure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3724) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3725) static int ufshcd_dme_reset(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3726) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3727) struct uic_command uic_cmd = {0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3728) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3730) uic_cmd.command = UIC_CMD_DME_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3732) ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3733) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3734) dev_err(hba->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3735) "dme-reset: error code %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3737) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3738) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3740) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3741) * ufshcd_dme_enable - UIC command for DME_ENABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3742) * @hba: per adapter instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3743) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3744) * DME_ENABLE command is issued in order to enable UniPro stack.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3745) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3746) * Returns 0 on success, non-zero value on failure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3747) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3748) static int ufshcd_dme_enable(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3749) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3750) struct uic_command uic_cmd = {0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3751) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3753) uic_cmd.command = UIC_CMD_DME_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3755) ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3756) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3757) dev_err(hba->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3758) "dme-enable: error code %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3760) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3761) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3763) static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3764) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3765) #define MIN_DELAY_BEFORE_DME_CMDS_US 1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3766) unsigned long min_sleep_time_us;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3768) if (!(hba->quirks & UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3769) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3771) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3772) * last_dme_cmd_tstamp will be 0 only for 1st call to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3773) * this function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3774) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3775) if (unlikely(!ktime_to_us(hba->last_dme_cmd_tstamp))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3776) min_sleep_time_us = MIN_DELAY_BEFORE_DME_CMDS_US;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3777) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3778) unsigned long delta =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3779) (unsigned long) ktime_to_us(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3780) ktime_sub(ktime_get(),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3781) hba->last_dme_cmd_tstamp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3783) if (delta < MIN_DELAY_BEFORE_DME_CMDS_US)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3784) min_sleep_time_us =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3785) MIN_DELAY_BEFORE_DME_CMDS_US - delta;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3786) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3787) return; /* no more delay required */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3788) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3790) /* allow sleep for extra 50us if needed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3791) usleep_range(min_sleep_time_us, min_sleep_time_us + 50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3792) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3794) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3795) * ufshcd_dme_set_attr - UIC command for DME_SET, DME_PEER_SET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3796) * @hba: per adapter instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3797) * @attr_sel: uic command argument1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3798) * @attr_set: attribute set type as uic command argument2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3799) * @mib_val: setting value as uic command argument3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3800) * @peer: indicate whether peer or local
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3801) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3802) * Returns 0 on success, non-zero value on failure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3803) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3804) int ufshcd_dme_set_attr(struct ufs_hba *hba, u32 attr_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3805) u8 attr_set, u32 mib_val, u8 peer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3806) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3807) struct uic_command uic_cmd = {0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3808) static const char *const action[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3809) "dme-set",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3810) "dme-peer-set"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3811) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3812) const char *set = action[!!peer];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3813) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3814) int retries = UFS_UIC_COMMAND_RETRIES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3816) uic_cmd.command = peer ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3817) UIC_CMD_DME_PEER_SET : UIC_CMD_DME_SET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3818) uic_cmd.argument1 = attr_sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3819) uic_cmd.argument2 = UIC_ARG_ATTR_TYPE(attr_set);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3820) uic_cmd.argument3 = mib_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3822) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3823) /* for peer attributes we retry upon failure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3824) ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3825) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3826) dev_dbg(hba->dev, "%s: attr-id 0x%x val 0x%x error code %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3827) set, UIC_GET_ATTR_ID(attr_sel), mib_val, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3828) } while (ret && peer && --retries);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3830) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3831) dev_err(hba->dev, "%s: attr-id 0x%x val 0x%x failed %d retries\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3832) set, UIC_GET_ATTR_ID(attr_sel), mib_val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3833) UFS_UIC_COMMAND_RETRIES - retries);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3835) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3836) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3837) EXPORT_SYMBOL_GPL(ufshcd_dme_set_attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3839) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3840) * ufshcd_dme_get_attr - UIC command for DME_GET, DME_PEER_GET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3841) * @hba: per adapter instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3842) * @attr_sel: uic command argument1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3843) * @mib_val: the value of the attribute as returned by the UIC command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3844) * @peer: indicate whether peer or local
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3845) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3846) * Returns 0 on success, non-zero value on failure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3847) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3848) int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3849) u32 *mib_val, u8 peer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3850) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3851) struct uic_command uic_cmd = {0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3852) static const char *const action[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3853) "dme-get",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3854) "dme-peer-get"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3855) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3856) const char *get = action[!!peer];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3857) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3858) int retries = UFS_UIC_COMMAND_RETRIES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3859) struct ufs_pa_layer_attr orig_pwr_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3860) struct ufs_pa_layer_attr temp_pwr_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3861) bool pwr_mode_change = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3863) if (peer && (hba->quirks & UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3864) orig_pwr_info = hba->pwr_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3865) temp_pwr_info = orig_pwr_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3867) if (orig_pwr_info.pwr_tx == FAST_MODE ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3868) orig_pwr_info.pwr_rx == FAST_MODE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3869) temp_pwr_info.pwr_tx = FASTAUTO_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3870) temp_pwr_info.pwr_rx = FASTAUTO_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3871) pwr_mode_change = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3872) } else if (orig_pwr_info.pwr_tx == SLOW_MODE ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3873) orig_pwr_info.pwr_rx == SLOW_MODE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3874) temp_pwr_info.pwr_tx = SLOWAUTO_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3875) temp_pwr_info.pwr_rx = SLOWAUTO_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3876) pwr_mode_change = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3877) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3878) if (pwr_mode_change) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3879) ret = ufshcd_change_power_mode(hba, &temp_pwr_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3880) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3881) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3882) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3883) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3885) uic_cmd.command = peer ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3886) UIC_CMD_DME_PEER_GET : UIC_CMD_DME_GET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3887) uic_cmd.argument1 = attr_sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3889) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3890) /* for peer attributes we retry upon failure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3891) ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3892) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3893) dev_dbg(hba->dev, "%s: attr-id 0x%x error code %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3894) get, UIC_GET_ATTR_ID(attr_sel), ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3895) } while (ret && peer && --retries);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3897) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3898) dev_err(hba->dev, "%s: attr-id 0x%x failed %d retries\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3899) get, UIC_GET_ATTR_ID(attr_sel),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3900) UFS_UIC_COMMAND_RETRIES - retries);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3902) if (mib_val && !ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3903) *mib_val = uic_cmd.argument3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3905) if (peer && (hba->quirks & UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3906) && pwr_mode_change)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3907) ufshcd_change_power_mode(hba, &orig_pwr_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3908) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3909) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3910) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3911) EXPORT_SYMBOL_GPL(ufshcd_dme_get_attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3913) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3914) * ufshcd_uic_pwr_ctrl - executes UIC commands (which affects the link power
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3915) * state) and waits for it to take effect.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3916) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3917) * @hba: per adapter instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3918) * @cmd: UIC command to execute
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3919) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3920) * DME operations like DME_SET(PA_PWRMODE), DME_HIBERNATE_ENTER &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3921) * DME_HIBERNATE_EXIT commands take some time to take its effect on both host
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3922) * and device UniPro link and hence it's final completion would be indicated by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3923) * dedicated status bits in Interrupt Status register (UPMS, UHES, UHXS) in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3924) * addition to normal UIC command completion Status (UCCS). This function only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3925) * returns after the relevant status bits indicate the completion.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3926) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3927) * Returns 0 on success, non-zero value on failure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3928) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3929) static int ufshcd_uic_pwr_ctrl(struct ufs_hba *hba, struct uic_command *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3930) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3931) DECLARE_COMPLETION_ONSTACK(uic_async_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3932) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3933) u8 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3934) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3935) bool reenable_intr = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3937) mutex_lock(&hba->uic_cmd_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3938) ufshcd_add_delay_before_dme_cmd(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3940) spin_lock_irqsave(hba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3941) if (ufshcd_is_link_broken(hba)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3942) ret = -ENOLINK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3943) goto out_unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3944) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3945) hba->uic_async_done = &uic_async_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3946) if (ufshcd_readl(hba, REG_INTERRUPT_ENABLE) & UIC_COMMAND_COMPL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3947) ufshcd_disable_intr(hba, UIC_COMMAND_COMPL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3948) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3949) * Make sure UIC command completion interrupt is disabled before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3950) * issuing UIC command.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3951) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3952) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3953) reenable_intr = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3954) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3955) ret = __ufshcd_send_uic_cmd(hba, cmd, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3956) spin_unlock_irqrestore(hba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3957) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3958) dev_err(hba->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3959) "pwr ctrl cmd 0x%x with mode 0x%x uic error %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3960) cmd->command, cmd->argument3, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3961) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3962) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3964) if (!wait_for_completion_timeout(hba->uic_async_done,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3965) msecs_to_jiffies(UIC_CMD_TIMEOUT))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3966) dev_err(hba->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3967) "pwr ctrl cmd 0x%x with mode 0x%x completion timeout\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3968) cmd->command, cmd->argument3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3970) if (!cmd->cmd_active) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3971) dev_err(hba->dev, "%s: Power Mode Change operation has been completed, go check UPMCRS\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3972) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3973) goto check_upmcrs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3974) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3976) ret = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3977) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3978) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3980) check_upmcrs:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3981) status = ufshcd_get_upmcrs(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3982) if (status != PWR_LOCAL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3983) dev_err(hba->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3984) "pwr ctrl cmd 0x%x failed, host upmcrs:0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3985) cmd->command, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3986) ret = (status != PWR_OK) ? status : -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3987) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3988) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3989) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3990) ufshcd_print_host_state(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3991) ufshcd_print_pwr_info(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3992) ufshcd_print_evt_hist(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3993) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3995) spin_lock_irqsave(hba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3996) hba->active_uic_cmd = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3997) hba->uic_async_done = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3998) if (reenable_intr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3999) ufshcd_enable_intr(hba, UIC_COMMAND_COMPL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4000) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4001) dev_err(hba->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4002) "%s: Changing link power status failed (%d). Scheduling error handler\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4003) __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4004) ufshcd_set_link_broken(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4005) ufshcd_schedule_eh_work(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4006) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4007) out_unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4008) spin_unlock_irqrestore(hba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4009) mutex_unlock(&hba->uic_cmd_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4011) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4012) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4014) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4015) * ufshcd_uic_change_pwr_mode - Perform the UIC power mode chage
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4016) * using DME_SET primitives.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4017) * @hba: per adapter instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4018) * @mode: powr mode value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4019) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4020) * Returns 0 on success, non-zero value on failure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4021) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4022) static int ufshcd_uic_change_pwr_mode(struct ufs_hba *hba, u8 mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4023) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4024) struct uic_command uic_cmd = {0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4025) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4027) if (hba->quirks & UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4028) ret = ufshcd_dme_set(hba,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4029) UIC_ARG_MIB_SEL(PA_RXHSUNTERMCAP, 0), 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4030) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4031) dev_err(hba->dev, "%s: failed to enable PA_RXHSUNTERMCAP ret %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4032) __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4033) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4034) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4035) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4037) uic_cmd.command = UIC_CMD_DME_SET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4038) uic_cmd.argument1 = UIC_ARG_MIB(PA_PWRMODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4039) uic_cmd.argument3 = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4040) ufshcd_hold(hba, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4041) ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4042) ufshcd_release(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4044) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4045) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4046) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4048) int ufshcd_link_recovery(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4049) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4050) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4051) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4053) spin_lock_irqsave(hba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4054) hba->ufshcd_state = UFSHCD_STATE_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4055) ufshcd_set_eh_in_progress(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4056) spin_unlock_irqrestore(hba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4058) /* Reset the attached device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4059) ufshcd_vops_device_reset(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4061) ret = ufshcd_host_reset_and_restore(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4063) spin_lock_irqsave(hba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4064) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4065) hba->ufshcd_state = UFSHCD_STATE_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4066) ufshcd_clear_eh_in_progress(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4067) spin_unlock_irqrestore(hba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4069) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4070) dev_err(hba->dev, "%s: link recovery failed, err %d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4071) __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4073) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4074) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4075) EXPORT_SYMBOL_GPL(ufshcd_link_recovery);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4077) int ufshcd_uic_hibern8_enter(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4078) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4079) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4080) struct uic_command uic_cmd = {0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4081) ktime_t start = ktime_get();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4083) ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_ENTER, PRE_CHANGE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4085) uic_cmd.command = UIC_CMD_DME_HIBER_ENTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4086) ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4087) trace_ufshcd_profile_hibern8(dev_name(hba->dev), "enter",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4088) ktime_to_us(ktime_sub(ktime_get(), start)), ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4090) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4091) dev_err(hba->dev, "%s: hibern8 enter failed. ret = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4092) __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4093) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4094) ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_ENTER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4095) POST_CHANGE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4097) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4098) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4099) EXPORT_SYMBOL_GPL(ufshcd_uic_hibern8_enter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4101) int ufshcd_uic_hibern8_exit(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4102) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4103) struct uic_command uic_cmd = {0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4104) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4105) ktime_t start = ktime_get();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4107) ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_EXIT, PRE_CHANGE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4109) uic_cmd.command = UIC_CMD_DME_HIBER_EXIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4110) ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4111) trace_ufshcd_profile_hibern8(dev_name(hba->dev), "exit",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4112) ktime_to_us(ktime_sub(ktime_get(), start)), ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4114) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4115) dev_err(hba->dev, "%s: hibern8 exit failed. ret = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4116) __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4117) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4118) ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_EXIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4119) POST_CHANGE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4120) hba->ufs_stats.last_hibern8_exit_tstamp = ktime_get();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4121) hba->ufs_stats.hibern8_exit_cnt++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4124) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4126) EXPORT_SYMBOL_GPL(ufshcd_uic_hibern8_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4128) void ufshcd_auto_hibern8_update(struct ufs_hba *hba, u32 ahit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4130) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4131) bool update = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4133) if (!ufshcd_is_auto_hibern8_supported(hba))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4134) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4136) spin_lock_irqsave(hba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4137) if (hba->ahit != ahit) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4138) hba->ahit = ahit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4139) update = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4141) spin_unlock_irqrestore(hba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4143) if (update && !pm_runtime_suspended(hba->dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4144) pm_runtime_get_sync(hba->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4145) ufshcd_hold(hba, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4146) ufshcd_auto_hibern8_enable(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4147) ufshcd_release(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4148) pm_runtime_put(hba->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4151) EXPORT_SYMBOL_GPL(ufshcd_auto_hibern8_update);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4153) void ufshcd_auto_hibern8_enable(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4154) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4155) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4157) if (!ufshcd_is_auto_hibern8_supported(hba))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4158) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4160) spin_lock_irqsave(hba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4161) ufshcd_writel(hba, hba->ahit, REG_AUTO_HIBERNATE_IDLE_TIMER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4162) spin_unlock_irqrestore(hba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4165) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4166) * ufshcd_init_pwr_info - setting the POR (power on reset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4167) * values in hba power info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4168) * @hba: per-adapter instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4169) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4170) static void ufshcd_init_pwr_info(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4172) hba->pwr_info.gear_rx = UFS_PWM_G1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4173) hba->pwr_info.gear_tx = UFS_PWM_G1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4174) hba->pwr_info.lane_rx = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4175) hba->pwr_info.lane_tx = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4176) hba->pwr_info.pwr_rx = SLOWAUTO_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4177) hba->pwr_info.pwr_tx = SLOWAUTO_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4178) hba->pwr_info.hs_rate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4181) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4182) * ufshcd_get_max_pwr_mode - reads the max power mode negotiated with device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4183) * @hba: per-adapter instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4184) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4185) static int ufshcd_get_max_pwr_mode(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4186) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4187) struct ufs_pa_layer_attr *pwr_info = &hba->max_pwr_info.info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4189) if (hba->max_pwr_info.is_valid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4190) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4192) pwr_info->pwr_tx = FAST_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4193) pwr_info->pwr_rx = FAST_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4194) pwr_info->hs_rate = PA_HS_MODE_B;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4196) /* Get the connected lane count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4197) ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDRXDATALANES),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4198) &pwr_info->lane_rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4199) ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4200) &pwr_info->lane_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4202) if (!pwr_info->lane_rx || !pwr_info->lane_tx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4203) dev_err(hba->dev, "%s: invalid connected lanes value. rx=%d, tx=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4204) __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4205) pwr_info->lane_rx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4206) pwr_info->lane_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4207) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4210) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4211) * First, get the maximum gears of HS speed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4212) * If a zero value, it means there is no HSGEAR capability.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4213) * Then, get the maximum gears of PWM speed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4214) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4215) ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR), &pwr_info->gear_rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4216) if (!pwr_info->gear_rx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4217) ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4218) &pwr_info->gear_rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4219) if (!pwr_info->gear_rx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4220) dev_err(hba->dev, "%s: invalid max pwm rx gear read = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4221) __func__, pwr_info->gear_rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4222) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4224) pwr_info->pwr_rx = SLOW_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4227) ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4228) &pwr_info->gear_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4229) if (!pwr_info->gear_tx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4230) ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4231) &pwr_info->gear_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4232) if (!pwr_info->gear_tx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4233) dev_err(hba->dev, "%s: invalid max pwm tx gear read = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4234) __func__, pwr_info->gear_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4235) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4237) pwr_info->pwr_tx = SLOW_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4240) hba->max_pwr_info.is_valid = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4241) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4244) static int ufshcd_change_power_mode(struct ufs_hba *hba,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4245) struct ufs_pa_layer_attr *pwr_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4246) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4247) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4249) /* if already configured to the requested pwr_mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4250) if (!hba->force_pmc &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4251) pwr_mode->gear_rx == hba->pwr_info.gear_rx &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4252) pwr_mode->gear_tx == hba->pwr_info.gear_tx &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4253) pwr_mode->lane_rx == hba->pwr_info.lane_rx &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4254) pwr_mode->lane_tx == hba->pwr_info.lane_tx &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4255) pwr_mode->pwr_rx == hba->pwr_info.pwr_rx &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4256) pwr_mode->pwr_tx == hba->pwr_info.pwr_tx &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4257) pwr_mode->hs_rate == hba->pwr_info.hs_rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4258) dev_dbg(hba->dev, "%s: power already configured\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4259) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4262) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4263) * Configure attributes for power mode change with below.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4264) * - PA_RXGEAR, PA_ACTIVERXDATALANES, PA_RXTERMINATION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4265) * - PA_TXGEAR, PA_ACTIVETXDATALANES, PA_TXTERMINATION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4266) * - PA_HSSERIES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4267) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4268) ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXGEAR), pwr_mode->gear_rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4269) ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVERXDATALANES),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4270) pwr_mode->lane_rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4271) if (pwr_mode->pwr_rx == FASTAUTO_MODE ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4272) pwr_mode->pwr_rx == FAST_MODE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4273) ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), TRUE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4274) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4275) ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), FALSE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4277) ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXGEAR), pwr_mode->gear_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4278) ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVETXDATALANES),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4279) pwr_mode->lane_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4280) if (pwr_mode->pwr_tx == FASTAUTO_MODE ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4281) pwr_mode->pwr_tx == FAST_MODE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4282) ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), TRUE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4283) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4284) ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), FALSE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4286) if (pwr_mode->pwr_rx == FASTAUTO_MODE ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4287) pwr_mode->pwr_tx == FASTAUTO_MODE ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4288) pwr_mode->pwr_rx == FAST_MODE ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4289) pwr_mode->pwr_tx == FAST_MODE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4290) ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HSSERIES),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4291) pwr_mode->hs_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4293) if (!(hba->quirks & UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4294) ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4295) DL_FC0ProtectionTimeOutVal_Default);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4296) ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4297) DL_TC0ReplayTimeOutVal_Default);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4298) ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4299) DL_AFC0ReqTimeOutVal_Default);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4300) ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4301) DL_FC1ProtectionTimeOutVal_Default);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4302) ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4303) DL_TC1ReplayTimeOutVal_Default);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4304) ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4305) DL_AFC1ReqTimeOutVal_Default);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4307) ufshcd_dme_set(hba, UIC_ARG_MIB(DME_LocalFC0ProtectionTimeOutVal),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4308) DL_FC0ProtectionTimeOutVal_Default);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4309) ufshcd_dme_set(hba, UIC_ARG_MIB(DME_LocalTC0ReplayTimeOutVal),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4310) DL_TC0ReplayTimeOutVal_Default);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4311) ufshcd_dme_set(hba, UIC_ARG_MIB(DME_LocalAFC0ReqTimeOutVal),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4312) DL_AFC0ReqTimeOutVal_Default);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4315) ret = ufshcd_uic_change_pwr_mode(hba, pwr_mode->pwr_rx << 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4316) | pwr_mode->pwr_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4318) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4319) dev_err(hba->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4320) "%s: power mode change failed %d\n", __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4321) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4322) ufshcd_vops_pwr_change_notify(hba, POST_CHANGE, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4323) pwr_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4325) memcpy(&hba->pwr_info, pwr_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4326) sizeof(struct ufs_pa_layer_attr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4329) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4332) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4333) * ufshcd_config_pwr_mode - configure a new power mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4334) * @hba: per-adapter instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4335) * @desired_pwr_mode: desired power configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4336) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4337) int ufshcd_config_pwr_mode(struct ufs_hba *hba,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4338) struct ufs_pa_layer_attr *desired_pwr_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4339) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4340) struct ufs_pa_layer_attr final_params = { 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4341) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4343) ret = ufshcd_vops_pwr_change_notify(hba, PRE_CHANGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4344) desired_pwr_mode, &final_params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4346) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4347) memcpy(&final_params, desired_pwr_mode, sizeof(final_params));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4349) ret = ufshcd_change_power_mode(hba, &final_params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4351) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4353) EXPORT_SYMBOL_GPL(ufshcd_config_pwr_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4355) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4356) * ufshcd_complete_dev_init() - checks device readiness
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4357) * @hba: per-adapter instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4358) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4359) * Set fDeviceInit flag and poll until device toggles it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4360) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4361) static int ufshcd_complete_dev_init(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4362) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4363) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4364) bool flag_res = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4365) ktime_t timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4367) err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_SET_FLAG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4368) QUERY_FLAG_IDN_FDEVICEINIT, 0, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4369) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4370) dev_err(hba->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4371) "%s setting fDeviceInit flag failed with error %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4372) __func__, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4373) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4376) /* Poll fDeviceInit flag to be cleared */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4377) timeout = ktime_add_ms(ktime_get(), FDEVICEINIT_COMPL_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4378) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4379) err = ufshcd_query_flag(hba, UPIU_QUERY_OPCODE_READ_FLAG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4380) QUERY_FLAG_IDN_FDEVICEINIT, 0, &flag_res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4381) if (!flag_res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4382) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4383) usleep_range(5000, 10000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4384) } while (ktime_before(ktime_get(), timeout));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4386) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4387) dev_err(hba->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4388) "%s reading fDeviceInit flag failed with error %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4389) __func__, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4390) } else if (flag_res) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4391) dev_err(hba->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4392) "%s fDeviceInit was not cleared by the device\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4393) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4394) err = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4396) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4397) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4400) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4401) * ufshcd_make_hba_operational - Make UFS controller operational
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4402) * @hba: per adapter instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4403) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4404) * To bring UFS host controller to operational state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4405) * 1. Enable required interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4406) * 2. Configure interrupt aggregation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4407) * 3. Program UTRL and UTMRL base address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4408) * 4. Configure run-stop-registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4409) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4410) * Returns 0 on success, non-zero value on failure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4411) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4412) int ufshcd_make_hba_operational(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4413) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4414) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4415) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4417) /* Enable required interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4418) ufshcd_enable_intr(hba, UFSHCD_ENABLE_INTRS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4420) /* Configure interrupt aggregation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4421) if (ufshcd_is_intr_aggr_allowed(hba))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4422) ufshcd_config_intr_aggr(hba, hba->nutrs - 1, INT_AGGR_DEF_TO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4423) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4424) ufshcd_disable_intr_aggr(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4426) /* Configure UTRL and UTMRL base address registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4427) ufshcd_writel(hba, lower_32_bits(hba->utrdl_dma_addr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4428) REG_UTP_TRANSFER_REQ_LIST_BASE_L);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4429) ufshcd_writel(hba, upper_32_bits(hba->utrdl_dma_addr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4430) REG_UTP_TRANSFER_REQ_LIST_BASE_H);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4431) ufshcd_writel(hba, lower_32_bits(hba->utmrdl_dma_addr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4432) REG_UTP_TASK_REQ_LIST_BASE_L);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4433) ufshcd_writel(hba, upper_32_bits(hba->utmrdl_dma_addr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4434) REG_UTP_TASK_REQ_LIST_BASE_H);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4436) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4437) * Make sure base address and interrupt setup are updated before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4438) * enabling the run/stop registers below.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4439) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4440) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4442) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4443) * UCRDY, UTMRLDY and UTRLRDY bits must be 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4444) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4445) reg = ufshcd_readl(hba, REG_CONTROLLER_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4446) if (!(ufshcd_get_lists_status(reg))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4447) ufshcd_enable_run_stop_reg(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4448) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4449) dev_err(hba->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4450) "Host controller not ready to process requests");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4451) err = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4452) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4454) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4455) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4456) EXPORT_SYMBOL_GPL(ufshcd_make_hba_operational);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4458) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4459) * ufshcd_hba_stop - Send controller to reset state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4460) * @hba: per adapter instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4461) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4462) void ufshcd_hba_stop(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4463) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4464) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4465) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4467) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4468) * Obtain the host lock to prevent that the controller is disabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4469) * while the UFS interrupt handler is active on another CPU.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4470) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4471) spin_lock_irqsave(hba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4472) ufshcd_writel(hba, CONTROLLER_DISABLE, REG_CONTROLLER_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4473) spin_unlock_irqrestore(hba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4475) err = ufshcd_wait_for_register(hba, REG_CONTROLLER_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4476) CONTROLLER_ENABLE, CONTROLLER_DISABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4477) 10, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4478) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4479) dev_err(hba->dev, "%s: Controller disable failed\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4480) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4481) EXPORT_SYMBOL_GPL(ufshcd_hba_stop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4483) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4484) * ufshcd_hba_execute_hce - initialize the controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4485) * @hba: per adapter instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4486) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4487) * The controller resets itself and controller firmware initialization
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4488) * sequence kicks off. When controller is ready it will set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4489) * the Host Controller Enable bit to 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4490) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4491) * Returns 0 on success, non-zero value on failure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4492) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4493) static int ufshcd_hba_execute_hce(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4494) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4495) int retry_outer = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4496) int retry_inner;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4498) start:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4499) if (!ufshcd_is_hba_active(hba))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4500) /* change controller state to "reset state" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4501) ufshcd_hba_stop(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4503) /* UniPro link is disabled at this point */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4504) ufshcd_set_link_off(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4506) ufshcd_vops_hce_enable_notify(hba, PRE_CHANGE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4508) /* start controller initialization sequence */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4509) ufshcd_hba_start(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4511) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4512) * To initialize a UFS host controller HCE bit must be set to 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4513) * During initialization the HCE bit value changes from 1->0->1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4514) * When the host controller completes initialization sequence
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4515) * it sets the value of HCE bit to 1. The same HCE bit is read back
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4516) * to check if the controller has completed initialization sequence.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4517) * So without this delay the value HCE = 1, set in the previous
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4518) * instruction might be read back.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4519) * This delay can be changed based on the controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4520) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4521) ufshcd_delay_us(hba->vps->hba_enable_delay_us, 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4523) /* wait for the host controller to complete initialization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4524) retry_inner = 50;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4525) while (ufshcd_is_hba_active(hba)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4526) if (retry_inner) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4527) retry_inner--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4528) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4529) dev_err(hba->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4530) "Controller enable failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4531) if (retry_outer) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4532) retry_outer--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4533) goto start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4534) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4535) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4536) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4537) usleep_range(1000, 1100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4538) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4540) /* enable UIC related interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4541) ufshcd_enable_intr(hba, UFSHCD_UIC_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4543) ufshcd_vops_hce_enable_notify(hba, POST_CHANGE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4545) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4546) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4548) int ufshcd_hba_enable(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4549) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4550) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4552) if (hba->quirks & UFSHCI_QUIRK_BROKEN_HCE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4553) ufshcd_set_link_off(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4554) ufshcd_vops_hce_enable_notify(hba, PRE_CHANGE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4556) /* enable UIC related interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4557) ufshcd_enable_intr(hba, UFSHCD_UIC_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4558) ret = ufshcd_dme_reset(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4559) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4560) ret = ufshcd_dme_enable(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4561) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4562) ufshcd_vops_hce_enable_notify(hba, POST_CHANGE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4563) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4564) dev_err(hba->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4565) "Host controller enable failed with non-hce\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4566) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4567) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4568) ret = ufshcd_hba_execute_hce(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4569) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4571) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4572) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4573) EXPORT_SYMBOL_GPL(ufshcd_hba_enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4575) static int ufshcd_disable_tx_lcc(struct ufs_hba *hba, bool peer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4576) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4577) int tx_lanes = 0, i, err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4579) if (!peer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4580) ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4581) &tx_lanes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4582) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4583) ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4584) &tx_lanes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4585) for (i = 0; i < tx_lanes; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4586) if (!peer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4587) err = ufshcd_dme_set(hba,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4588) UIC_ARG_MIB_SEL(TX_LCC_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4589) UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4590) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4591) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4592) err = ufshcd_dme_peer_set(hba,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4593) UIC_ARG_MIB_SEL(TX_LCC_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4594) UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4595) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4596) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4597) dev_err(hba->dev, "%s: TX LCC Disable failed, peer = %d, lane = %d, err = %d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4598) __func__, peer, i, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4599) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4600) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4601) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4603) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4604) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4606) static inline int ufshcd_disable_device_tx_lcc(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4607) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4608) return ufshcd_disable_tx_lcc(hba, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4609) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4611) void ufshcd_update_evt_hist(struct ufs_hba *hba, u32 id, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4612) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4613) struct ufs_event_hist *e;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4615) if (id >= UFS_EVT_CNT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4616) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4618) e = &hba->ufs_stats.event[id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4619) e->val[e->pos] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4620) e->tstamp[e->pos] = ktime_get();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4621) e->cnt += 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4622) e->pos = (e->pos + 1) % UFS_EVENT_HIST_LENGTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4624) ufshcd_vops_event_notify(hba, id, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4625) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4626) EXPORT_SYMBOL_GPL(ufshcd_update_evt_hist);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4628) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4629) * ufshcd_link_startup - Initialize unipro link startup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4630) * @hba: per adapter instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4631) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4632) * Returns 0 for success, non-zero in case of failure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4633) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4634) static int ufshcd_link_startup(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4635) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4636) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4637) int retries = DME_LINKSTARTUP_RETRIES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4638) bool link_startup_again = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4640) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4641) * If UFS device isn't active then we will have to issue link startup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4642) * 2 times to make sure the device state move to active.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4643) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4644) if (!ufshcd_is_ufs_dev_active(hba))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4645) link_startup_again = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4647) link_startup:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4648) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4649) ufshcd_vops_link_startup_notify(hba, PRE_CHANGE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4651) ret = ufshcd_dme_link_startup(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4653) /* check if device is detected by inter-connect layer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4654) if (!ret && !ufshcd_is_device_present(hba)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4655) ufshcd_update_evt_hist(hba,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4656) UFS_EVT_LINK_STARTUP_FAIL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4657) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4658) dev_err(hba->dev, "%s: Device not present\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4659) ret = -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4660) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4661) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4663) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4664) * DME link lost indication is only received when link is up,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4665) * but we can't be sure if the link is up until link startup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4666) * succeeds. So reset the local Uni-Pro and try again.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4667) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4668) if (ret && ufshcd_hba_enable(hba)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4669) ufshcd_update_evt_hist(hba,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4670) UFS_EVT_LINK_STARTUP_FAIL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4671) (u32)ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4672) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4673) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4674) } while (ret && retries--);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4676) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4677) /* failed to get the link up... retire */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4678) ufshcd_update_evt_hist(hba,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4679) UFS_EVT_LINK_STARTUP_FAIL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4680) (u32)ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4681) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4682) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4684) if (link_startup_again) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4685) link_startup_again = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4686) retries = DME_LINKSTARTUP_RETRIES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4687) goto link_startup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4688) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4690) /* Mark that link is up in PWM-G1, 1-lane, SLOW-AUTO mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4691) ufshcd_init_pwr_info(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4692) ufshcd_print_pwr_info(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4694) if (hba->quirks & UFSHCD_QUIRK_BROKEN_LCC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4695) ret = ufshcd_disable_device_tx_lcc(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4696) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4697) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4698) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4700) /* Include any host controller configuration via UIC commands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4701) ret = ufshcd_vops_link_startup_notify(hba, POST_CHANGE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4702) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4703) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4705) /* Clear UECPA once due to LINERESET has happened during LINK_STARTUP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4706) ufshcd_readl(hba, REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4707) ret = ufshcd_make_hba_operational(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4708) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4709) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4710) dev_err(hba->dev, "link startup failed %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4711) ufshcd_print_host_state(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4712) ufshcd_print_pwr_info(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4713) ufshcd_print_evt_hist(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4714) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4715) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4716) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4718) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4719) * ufshcd_verify_dev_init() - Verify device initialization
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4720) * @hba: per-adapter instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4721) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4722) * Send NOP OUT UPIU and wait for NOP IN response to check whether the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4723) * device Transport Protocol (UTP) layer is ready after a reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4724) * If the UTP layer at the device side is not initialized, it may
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4725) * not respond with NOP IN UPIU within timeout of %NOP_OUT_TIMEOUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4726) * and we retry sending NOP OUT for %NOP_OUT_RETRIES iterations.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4727) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4728) static int ufshcd_verify_dev_init(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4729) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4730) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4731) int retries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4733) ufshcd_hold(hba, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4734) mutex_lock(&hba->dev_cmd.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4735) for (retries = NOP_OUT_RETRIES; retries > 0; retries--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4736) err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_NOP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4737) NOP_OUT_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4739) if (!err || err == -ETIMEDOUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4740) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4742) dev_dbg(hba->dev, "%s: error %d retrying\n", __func__, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4743) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4744) mutex_unlock(&hba->dev_cmd.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4745) ufshcd_release(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4747) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4748) dev_err(hba->dev, "%s: NOP OUT failed %d\n", __func__, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4749) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4750) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4752) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4753) * ufshcd_set_queue_depth - set lun queue depth
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4754) * @sdev: pointer to SCSI device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4755) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4756) * Read bLUQueueDepth value and activate scsi tagged command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4757) * queueing. For WLUN, queue depth is set to 1. For best-effort
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4758) * cases (bLUQueueDepth = 0) the queue depth is set to a maximum
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4759) * value that host can queue.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4760) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4761) static void ufshcd_set_queue_depth(struct scsi_device *sdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4762) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4763) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4764) u8 lun_qdepth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4765) struct ufs_hba *hba;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4767) hba = shost_priv(sdev->host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4769) lun_qdepth = hba->nutrs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4770) ret = ufshcd_read_unit_desc_param(hba,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4771) ufshcd_scsi_to_upiu_lun(sdev->lun),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4772) UNIT_DESC_PARAM_LU_Q_DEPTH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4773) &lun_qdepth,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4774) sizeof(lun_qdepth));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4776) /* Some WLUN doesn't support unit descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4777) if (ret == -EOPNOTSUPP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4778) lun_qdepth = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4779) else if (!lun_qdepth)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4780) /* eventually, we can figure out the real queue depth */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4781) lun_qdepth = hba->nutrs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4782) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4783) lun_qdepth = min_t(int, lun_qdepth, hba->nutrs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4785) dev_dbg(hba->dev, "%s: activate tcq with queue depth %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4786) __func__, lun_qdepth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4787) scsi_change_queue_depth(sdev, lun_qdepth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4788) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4790) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4791) * ufshcd_get_lu_wp - returns the "b_lu_write_protect" from UNIT DESCRIPTOR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4792) * @hba: per-adapter instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4793) * @lun: UFS device lun id
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4794) * @b_lu_write_protect: pointer to buffer to hold the LU's write protect info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4795) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4796) * Returns 0 in case of success and b_lu_write_protect status would be returned
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4797) * @b_lu_write_protect parameter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4798) * Returns -ENOTSUPP if reading b_lu_write_protect is not supported.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4799) * Returns -EINVAL in case of invalid parameters passed to this function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4800) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4801) static int ufshcd_get_lu_wp(struct ufs_hba *hba,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4802) u8 lun,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4803) u8 *b_lu_write_protect)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4804) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4805) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4807) if (!b_lu_write_protect)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4808) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4809) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4810) * According to UFS device spec, RPMB LU can't be write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4811) * protected so skip reading bLUWriteProtect parameter for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4812) * it. For other W-LUs, UNIT DESCRIPTOR is not available.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4813) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4814) else if (lun >= hba->dev_info.max_lu_supported)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4815) ret = -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4816) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4817) ret = ufshcd_read_unit_desc_param(hba,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4818) lun,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4819) UNIT_DESC_PARAM_LU_WR_PROTECT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4820) b_lu_write_protect,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4821) sizeof(*b_lu_write_protect));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4822) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4823) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4825) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4826) * ufshcd_get_lu_power_on_wp_status - get LU's power on write protect
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4827) * status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4828) * @hba: per-adapter instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4829) * @sdev: pointer to SCSI device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4830) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4831) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4832) static inline void ufshcd_get_lu_power_on_wp_status(struct ufs_hba *hba,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4833) struct scsi_device *sdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4834) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4835) if (hba->dev_info.f_power_on_wp_en &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4836) !hba->dev_info.is_lu_power_on_wp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4837) u8 b_lu_write_protect;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4839) if (!ufshcd_get_lu_wp(hba, ufshcd_scsi_to_upiu_lun(sdev->lun),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4840) &b_lu_write_protect) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4841) (b_lu_write_protect == UFS_LU_POWER_ON_WP))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4842) hba->dev_info.is_lu_power_on_wp = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4843) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4844) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4846) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4847) * ufshcd_slave_alloc - handle initial SCSI device configurations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4848) * @sdev: pointer to SCSI device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4849) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4850) * Returns success
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4851) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4852) static int ufshcd_slave_alloc(struct scsi_device *sdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4853) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4854) struct ufs_hba *hba;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4856) hba = shost_priv(sdev->host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4858) /* Mode sense(6) is not supported by UFS, so use Mode sense(10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4859) sdev->use_10_for_ms = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4861) /* DBD field should be set to 1 in mode sense(10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4862) sdev->set_dbd_for_ms = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4864) /* allow SCSI layer to restart the device in case of errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4865) sdev->allow_restart = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4867) /* REPORT SUPPORTED OPERATION CODES is not supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4868) sdev->no_report_opcodes = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4870) /* WRITE_SAME command is not supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4871) sdev->no_write_same = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4873) ufshcd_set_queue_depth(sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4875) ufshcd_get_lu_power_on_wp_status(hba, sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4877) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4878) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4880) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4881) * ufshcd_change_queue_depth - change queue depth
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4882) * @sdev: pointer to SCSI device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4883) * @depth: required depth to set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4884) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4885) * Change queue depth and make sure the max. limits are not crossed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4886) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4887) static int ufshcd_change_queue_depth(struct scsi_device *sdev, int depth)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4888) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4889) return scsi_change_queue_depth(sdev, min(depth, sdev->host->can_queue));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4890) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4892) static void ufshcd_hpb_destroy(struct ufs_hba *hba, struct scsi_device *sdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4893) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4894) /* skip well-known LU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4895) if ((sdev->lun >= UFS_UPIU_MAX_UNIT_NUM_ID) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4896) !(hba->dev_info.hpb_enabled) || !ufshpb_is_allowed(hba))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4897) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4899) ufshpb_destroy_lu(hba, sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4900) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4902) static void ufshcd_hpb_configure(struct ufs_hba *hba, struct scsi_device *sdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4903) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4904) /* skip well-known LU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4905) if ((sdev->lun >= UFS_UPIU_MAX_UNIT_NUM_ID) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4906) !(hba->dev_info.hpb_enabled) || !ufshpb_is_allowed(hba))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4907) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4909) ufshpb_init_hpb_lu(hba, sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4910) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4912) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4913) * ufshcd_slave_configure - adjust SCSI device configurations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4914) * @sdev: pointer to SCSI device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4915) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4916) static int ufshcd_slave_configure(struct scsi_device *sdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4917) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4918) struct ufs_hba *hba = shost_priv(sdev->host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4919) struct request_queue *q = sdev->request_queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4921) ufshcd_hpb_configure(hba, sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4923) blk_queue_update_dma_pad(q, PRDT_DATA_BYTE_COUNT_PAD - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4924) if (hba->quirks & UFSHCD_QUIRK_ALIGN_SG_WITH_PAGE_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4925) blk_queue_update_dma_alignment(q, PAGE_SIZE - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4927) if (ufshcd_is_rpm_autosuspend_allowed(hba))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4928) sdev->rpm_autosuspend = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4930) ufshcd_crypto_setup_rq_keyslot_manager(hba, q);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4932) trace_android_vh_ufs_update_sdev(sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4934) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4935) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4937) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4938) * ufshcd_slave_destroy - remove SCSI device configurations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4939) * @sdev: pointer to SCSI device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4940) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4941) static void ufshcd_slave_destroy(struct scsi_device *sdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4942) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4943) struct ufs_hba *hba;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4945) hba = shost_priv(sdev->host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4947) ufshcd_hpb_destroy(hba, sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4949) /* Drop the reference as it won't be needed anymore */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4950) if (ufshcd_scsi_to_upiu_lun(sdev->lun) == UFS_UPIU_UFS_DEVICE_WLUN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4951) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4953) spin_lock_irqsave(hba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4954) hba->sdev_ufs_device = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4955) spin_unlock_irqrestore(hba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4956) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4957) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4959) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4960) * ufshcd_scsi_cmd_status - Update SCSI command result based on SCSI status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4961) * @lrbp: pointer to local reference block of completed command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4962) * @scsi_status: SCSI command status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4963) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4964) * Returns value base on SCSI command status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4965) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4966) static inline int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4967) ufshcd_scsi_cmd_status(struct ufshcd_lrb *lrbp, int scsi_status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4968) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4969) int result = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4971) switch (scsi_status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4972) case SAM_STAT_CHECK_CONDITION:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4973) ufshcd_copy_sense_data(lrbp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4974) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4975) case SAM_STAT_GOOD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4976) result |= DID_OK << 16 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4977) COMMAND_COMPLETE << 8 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4978) scsi_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4979) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4980) case SAM_STAT_TASK_SET_FULL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4981) case SAM_STAT_BUSY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4982) case SAM_STAT_TASK_ABORTED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4983) ufshcd_copy_sense_data(lrbp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4984) result |= scsi_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4985) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4986) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4987) result |= DID_ERROR << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4988) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4989) } /* end of switch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4991) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4992) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4994) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4995) * ufshcd_transfer_rsp_status - Get overall status of the response
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4996) * @hba: per adapter instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4997) * @lrbp: pointer to local reference block of completed command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4998) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4999) * Returns result of the command to notify SCSI midlayer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5000) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5001) static inline int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5002) ufshcd_transfer_rsp_status(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5003) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5004) int result = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5005) int scsi_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5006) int ocs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5008) /* overall command status of utrd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5009) ocs = ufshcd_get_tr_ocs(lrbp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5011) if (hba->quirks & UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5012) if (be32_to_cpu(lrbp->ucd_rsp_ptr->header.dword_1) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5013) MASK_RSP_UPIU_RESULT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5014) ocs = OCS_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5015) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5017) switch (ocs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5018) case OCS_SUCCESS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5019) result = ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5020) hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5021) switch (result) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5022) case UPIU_TRANSACTION_RESPONSE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5023) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5024) * get the response UPIU result to extract
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5025) * the SCSI command status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5026) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5027) result = ufshcd_get_rsp_upiu_result(lrbp->ucd_rsp_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5029) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5030) * get the result based on SCSI status response
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5031) * to notify the SCSI midlayer of the command status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5032) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5033) scsi_status = result & MASK_SCSI_STATUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5034) result = ufshcd_scsi_cmd_status(lrbp, scsi_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5036) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5037) * Currently we are only supporting BKOPs exception
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5038) * events hence we can ignore BKOPs exception event
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5039) * during power management callbacks. BKOPs exception
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5040) * event is not expected to be raised in runtime suspend
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5041) * callback as it allows the urgent bkops.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5042) * During system suspend, we are anyway forcefully
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5043) * disabling the bkops and if urgent bkops is needed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5044) * it will be enabled on system resume. Long term
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5045) * solution could be to abort the system suspend if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5046) * UFS device needs urgent BKOPs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5047) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5048) if (!hba->pm_op_in_progress &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5049) !ufshcd_eh_in_progress(hba) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5050) ufshcd_is_exception_event(lrbp->ucd_rsp_ptr) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5051) schedule_work(&hba->eeh_work)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5052) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5053) * Prevent suspend once eeh_work is scheduled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5054) * to avoid deadlock between ufshcd_suspend
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5055) * and exception event handler.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5056) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5057) pm_runtime_get_noresume(hba->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5058) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5060) if (scsi_status == SAM_STAT_GOOD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5061) ufshpb_rsp_upiu(hba, lrbp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5062) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5063) case UPIU_TRANSACTION_REJECT_UPIU:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5064) /* TODO: handle Reject UPIU Response */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5065) result = DID_ERROR << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5066) dev_err(hba->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5067) "Reject UPIU not fully implemented\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5068) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5069) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5070) dev_err(hba->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5071) "Unexpected request response code = %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5072) result);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5073) result = DID_ERROR << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5074) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5075) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5076) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5077) case OCS_ABORTED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5078) result |= DID_ABORT << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5079) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5080) case OCS_INVALID_COMMAND_STATUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5081) dev_err_ratelimited(hba->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5082) "Retrying request with tag %d / cdb %#02x because of invalid command status\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5083) lrbp->task_tag, lrbp->cmd && lrbp->cmd->cmnd ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5084) lrbp->cmd->cmnd[0] : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5085) result |= DID_REQUEUE << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5086) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5087) case OCS_INVALID_CMD_TABLE_ATTR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5088) case OCS_INVALID_PRDT_ATTR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5089) case OCS_MISMATCH_DATA_BUF_SIZE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5090) case OCS_MISMATCH_RESP_UPIU_SIZE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5091) case OCS_PEER_COMM_FAILURE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5092) case OCS_FATAL_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5093) case OCS_DEVICE_FATAL_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5094) case OCS_INVALID_CRYPTO_CONFIG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5095) case OCS_GENERAL_CRYPTO_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5096) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5097) result |= DID_ERROR << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5098) dev_err(hba->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5099) "OCS error from controller = %x for tag %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5100) ocs, lrbp->task_tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5101) ufshcd_print_evt_hist(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5102) ufshcd_print_host_state(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5103) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5104) } /* end of switch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5106) if ((host_byte(result) != DID_OK) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5107) (host_byte(result) != DID_REQUEUE) && !hba->silence_err_logs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5108) ufshcd_print_trs(hba, 1 << lrbp->task_tag, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5109) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5112) static bool ufshcd_is_auto_hibern8_error(struct ufs_hba *hba,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5113) u32 intr_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5115) if (!ufshcd_is_auto_hibern8_supported(hba) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5116) !ufshcd_is_auto_hibern8_enabled(hba))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5117) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5119) if (!(intr_mask & UFSHCD_UIC_HIBERN8_MASK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5120) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5122) if (hba->active_uic_cmd &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5123) (hba->active_uic_cmd->command == UIC_CMD_DME_HIBER_ENTER ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5124) hba->active_uic_cmd->command == UIC_CMD_DME_HIBER_EXIT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5125) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5127) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5130) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5131) * ufshcd_uic_cmd_compl - handle completion of uic command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5132) * @hba: per adapter instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5133) * @intr_status: interrupt status generated by the controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5134) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5135) * Returns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5136) * IRQ_HANDLED - If interrupt is valid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5137) * IRQ_NONE - If invalid interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5138) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5139) static irqreturn_t ufshcd_uic_cmd_compl(struct ufs_hba *hba, u32 intr_status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5141) irqreturn_t retval = IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5143) spin_lock(hba->host->host_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5144) if (ufshcd_is_auto_hibern8_error(hba, intr_status))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5145) hba->errors |= (UFSHCD_UIC_HIBERN8_MASK & intr_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5147) if ((intr_status & UIC_COMMAND_COMPL) && hba->active_uic_cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5148) hba->active_uic_cmd->argument2 |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5149) ufshcd_get_uic_cmd_result(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5150) hba->active_uic_cmd->argument3 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5151) ufshcd_get_dme_attr_val(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5152) if (!hba->uic_async_done)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5153) hba->active_uic_cmd->cmd_active = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5154) complete(&hba->active_uic_cmd->done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5155) retval = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5158) if ((intr_status & UFSHCD_UIC_PWR_MASK) && hba->uic_async_done) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5159) hba->active_uic_cmd->cmd_active = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5160) complete(hba->uic_async_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5161) retval = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5164) if (retval == IRQ_HANDLED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5165) ufshcd_add_uic_command_trace(hba, hba->active_uic_cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5166) "complete");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5167) spin_unlock(hba->host->host_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5168) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5171) /* Release the resources allocated for processing a SCSI command. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5172) static void ufshcd_release_scsi_cmd(struct ufs_hba *hba,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5173) struct ufshcd_lrb *lrbp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5174) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5175) struct scsi_cmnd *cmd = lrbp->cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5177) scsi_dma_unmap(cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5178) ufshcd_crypto_clear_prdt(hba, lrbp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5179) lrbp->cmd = NULL; /* Mark the command as completed. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5180) ufshcd_release(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5181) ufshcd_clk_scaling_update_busy(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5184) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5185) * __ufshcd_transfer_req_compl - handle SCSI and query command completion
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5186) * @hba: per adapter instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5187) * @completed_reqs: requests to complete
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5188) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5189) static void __ufshcd_transfer_req_compl(struct ufs_hba *hba,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5190) unsigned long completed_reqs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5191) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5192) struct ufshcd_lrb *lrbp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5193) struct scsi_cmnd *cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5194) int index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5196) for_each_set_bit(index, &completed_reqs, hba->nutrs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5197) if (!test_and_clear_bit(index, &hba->outstanding_reqs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5198) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5199) lrbp = &hba->lrb[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5200) lrbp->compl_time_stamp = ktime_get();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5201) cmd = lrbp->cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5202) if (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5203) if (unlikely(ufshcd_should_inform_monitor(hba, lrbp)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5204) ufshcd_update_monitor(hba, lrbp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5205) trace_android_vh_ufs_compl_command(hba, lrbp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5206) ufshcd_add_command_trace(hba, index, "complete");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5207) cmd->result = ufshcd_transfer_rsp_status(hba, lrbp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5208) ufshcd_release_scsi_cmd(hba, lrbp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5209) /* Do not touch lrbp after scsi done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5210) cmd->scsi_done(cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5211) } else if (lrbp->command_type == UTP_CMD_TYPE_DEV_MANAGE ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5212) lrbp->command_type == UTP_CMD_TYPE_UFS_STORAGE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5213) if (hba->dev_cmd.complete) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5214) trace_android_vh_ufs_compl_command(hba, lrbp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5215) ufshcd_add_command_trace(hba, index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5216) "dev_complete");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5217) complete(hba->dev_cmd.complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5218) ufshcd_clk_scaling_update_busy(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5224) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5225) * ufshcd_trc_handler - handle transfer requests completion
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5226) * @hba: per adapter instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5227) * @use_utrlcnr: get completed requests from UTRLCNR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5228) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5229) * Returns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5230) * IRQ_HANDLED - If interrupt is valid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5231) * IRQ_NONE - If invalid interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5232) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5233) static irqreturn_t ufshcd_trc_handler(struct ufs_hba *hba, bool use_utrlcnr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5235) unsigned long completed_reqs = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5237) /* Resetting interrupt aggregation counters first and reading the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5238) * DOOR_BELL afterward allows us to handle all the completed requests.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5239) * In order to prevent other interrupts starvation the DB is read once
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5240) * after reset. The down side of this solution is the possibility of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5241) * false interrupt if device completes another request after resetting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5242) * aggregation and before reading the DB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5243) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5244) if (ufshcd_is_intr_aggr_allowed(hba) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5245) !(hba->quirks & UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5246) ufshcd_reset_intr_aggr(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5248) if (use_utrlcnr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5249) u32 utrlcnr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5251) utrlcnr = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_LIST_COMPL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5252) if (utrlcnr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5253) ufshcd_writel(hba, utrlcnr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5254) REG_UTP_TRANSFER_REQ_LIST_COMPL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5255) completed_reqs = utrlcnr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5257) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5258) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5259) u32 tr_doorbell;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5261) spin_lock_irqsave(hba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5262) tr_doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5263) completed_reqs = tr_doorbell ^ hba->outstanding_reqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5264) spin_unlock_irqrestore(hba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5267) if (completed_reqs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5268) __ufshcd_transfer_req_compl(hba, completed_reqs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5269) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5270) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5271) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5275) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5276) * ufshcd_disable_ee - disable exception event
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5277) * @hba: per-adapter instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5278) * @mask: exception event to disable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5279) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5280) * Disables exception event in the device so that the EVENT_ALERT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5281) * bit is not set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5282) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5283) * Returns zero on success, non-zero error value on failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5284) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5285) static int ufshcd_disable_ee(struct ufs_hba *hba, u16 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5286) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5287) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5288) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5290) if (!(hba->ee_ctrl_mask & mask))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5291) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5293) val = hba->ee_ctrl_mask & ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5294) val &= MASK_EE_STATUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5295) err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5296) QUERY_ATTR_IDN_EE_CONTROL, 0, 0, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5297) if (!err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5298) hba->ee_ctrl_mask &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5299) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5300) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5303) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5304) * ufshcd_enable_ee - enable exception event
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5305) * @hba: per-adapter instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5306) * @mask: exception event to enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5307) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5308) * Enable corresponding exception event in the device to allow
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5309) * device to alert host in critical scenarios.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5310) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5311) * Returns zero on success, non-zero error value on failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5312) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5313) static int ufshcd_enable_ee(struct ufs_hba *hba, u16 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5314) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5315) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5316) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5318) if (hba->ee_ctrl_mask & mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5319) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5321) val = hba->ee_ctrl_mask | mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5322) val &= MASK_EE_STATUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5323) err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5324) QUERY_ATTR_IDN_EE_CONTROL, 0, 0, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5325) if (!err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5326) hba->ee_ctrl_mask |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5327) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5328) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5331) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5332) * ufshcd_enable_auto_bkops - Allow device managed BKOPS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5333) * @hba: per-adapter instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5334) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5335) * Allow device to manage background operations on its own. Enabling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5336) * this might lead to inconsistent latencies during normal data transfers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5337) * as the device is allowed to manage its own way of handling background
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5338) * operations.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5339) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5340) * Returns zero on success, non-zero on failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5341) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5342) static int ufshcd_enable_auto_bkops(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5343) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5344) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5346) if (hba->auto_bkops_enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5347) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5349) err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_SET_FLAG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5350) QUERY_FLAG_IDN_BKOPS_EN, 0, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5351) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5352) dev_err(hba->dev, "%s: failed to enable bkops %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5353) __func__, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5354) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5357) hba->auto_bkops_enabled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5358) trace_ufshcd_auto_bkops_state(dev_name(hba->dev), "Enabled");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5360) /* No need of URGENT_BKOPS exception from the device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5361) err = ufshcd_disable_ee(hba, MASK_EE_URGENT_BKOPS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5362) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5363) dev_err(hba->dev, "%s: failed to disable exception event %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5364) __func__, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5365) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5366) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5369) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5370) * ufshcd_disable_auto_bkops - block device in doing background operations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5371) * @hba: per-adapter instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5372) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5373) * Disabling background operations improves command response latency but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5374) * has drawback of device moving into critical state where the device is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5375) * not-operable. Make sure to call ufshcd_enable_auto_bkops() whenever the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5376) * host is idle so that BKOPS are managed effectively without any negative
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5377) * impacts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5378) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5379) * Returns zero on success, non-zero on failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5380) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5381) static int ufshcd_disable_auto_bkops(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5382) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5383) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5385) if (!hba->auto_bkops_enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5386) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5388) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5389) * If host assisted BKOPs is to be enabled, make sure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5390) * urgent bkops exception is allowed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5391) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5392) err = ufshcd_enable_ee(hba, MASK_EE_URGENT_BKOPS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5393) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5394) dev_err(hba->dev, "%s: failed to enable exception event %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5395) __func__, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5396) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5399) err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_CLEAR_FLAG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5400) QUERY_FLAG_IDN_BKOPS_EN, 0, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5401) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5402) dev_err(hba->dev, "%s: failed to disable bkops %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5403) __func__, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5404) ufshcd_disable_ee(hba, MASK_EE_URGENT_BKOPS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5405) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5408) hba->auto_bkops_enabled = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5409) trace_ufshcd_auto_bkops_state(dev_name(hba->dev), "Disabled");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5410) hba->is_urgent_bkops_lvl_checked = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5411) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5412) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5415) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5416) * ufshcd_force_reset_auto_bkops - force reset auto bkops state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5417) * @hba: per adapter instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5418) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5419) * After a device reset the device may toggle the BKOPS_EN flag
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5420) * to default value. The s/w tracking variables should be updated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5421) * as well. This function would change the auto-bkops state based on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5422) * UFSHCD_CAP_KEEP_AUTO_BKOPS_ENABLED_EXCEPT_SUSPEND.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5423) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5424) static void ufshcd_force_reset_auto_bkops(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5425) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5426) if (ufshcd_keep_autobkops_enabled_except_suspend(hba)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5427) hba->auto_bkops_enabled = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5428) hba->ee_ctrl_mask |= MASK_EE_URGENT_BKOPS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5429) ufshcd_enable_auto_bkops(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5430) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5431) hba->auto_bkops_enabled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5432) hba->ee_ctrl_mask &= ~MASK_EE_URGENT_BKOPS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5433) ufshcd_disable_auto_bkops(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5434) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5435) hba->urgent_bkops_lvl = BKOPS_STATUS_PERF_IMPACT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5436) hba->is_urgent_bkops_lvl_checked = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5437) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5439) static inline int ufshcd_get_bkops_status(struct ufs_hba *hba, u32 *status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5440) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5441) return ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5442) QUERY_ATTR_IDN_BKOPS_STATUS, 0, 0, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5445) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5446) * ufshcd_bkops_ctrl - control the auto bkops based on current bkops status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5447) * @hba: per-adapter instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5448) * @status: bkops_status value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5449) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5450) * Read the bkops_status from the UFS device and Enable fBackgroundOpsEn
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5451) * flag in the device to permit background operations if the device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5452) * bkops_status is greater than or equal to "status" argument passed to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5453) * this function, disable otherwise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5454) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5455) * Returns 0 for success, non-zero in case of failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5456) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5457) * NOTE: Caller of this function can check the "hba->auto_bkops_enabled" flag
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5458) * to know whether auto bkops is enabled or disabled after this function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5459) * returns control to it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5460) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5461) int ufshcd_bkops_ctrl(struct ufs_hba *hba,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5462) enum bkops_status status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5463) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5464) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5465) u32 curr_status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5467) err = ufshcd_get_bkops_status(hba, &curr_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5468) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5469) dev_err(hba->dev, "%s: failed to get BKOPS status %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5470) __func__, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5471) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5472) } else if (curr_status > BKOPS_STATUS_MAX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5473) dev_err(hba->dev, "%s: invalid BKOPS status %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5474) __func__, curr_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5475) err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5476) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5477) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5479) if (curr_status >= status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5480) err = ufshcd_enable_auto_bkops(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5481) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5482) err = ufshcd_disable_auto_bkops(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5483) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5484) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5486) EXPORT_SYMBOL_GPL(ufshcd_bkops_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5488) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5489) * ufshcd_urgent_bkops - handle urgent bkops exception event
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5490) * @hba: per-adapter instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5491) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5492) * Enable fBackgroundOpsEn flag in the device to permit background
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5493) * operations.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5494) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5495) * If BKOPs is enabled, this function returns 0, 1 if the bkops in not enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5496) * and negative error value for any other failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5497) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5498) static int ufshcd_urgent_bkops(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5499) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5500) return ufshcd_bkops_ctrl(hba, hba->urgent_bkops_lvl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5501) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5503) static inline int ufshcd_get_ee_status(struct ufs_hba *hba, u32 *status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5504) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5505) return ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5506) QUERY_ATTR_IDN_EE_STATUS, 0, 0, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5507) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5509) static void ufshcd_bkops_exception_event_handler(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5510) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5511) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5512) u32 curr_status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5514) if (hba->is_urgent_bkops_lvl_checked)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5515) goto enable_auto_bkops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5517) err = ufshcd_get_bkops_status(hba, &curr_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5518) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5519) dev_err(hba->dev, "%s: failed to get BKOPS status %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5520) __func__, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5521) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5522) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5524) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5525) * We are seeing that some devices are raising the urgent bkops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5526) * exception events even when BKOPS status doesn't indicate performace
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5527) * impacted or critical. Handle these device by determining their urgent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5528) * bkops status at runtime.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5529) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5530) if (curr_status < BKOPS_STATUS_PERF_IMPACT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5531) dev_err(hba->dev, "%s: device raised urgent BKOPS exception for bkops status %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5532) __func__, curr_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5533) /* update the current status as the urgent bkops level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5534) hba->urgent_bkops_lvl = curr_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5535) hba->is_urgent_bkops_lvl_checked = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5536) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5538) enable_auto_bkops:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5539) err = ufshcd_enable_auto_bkops(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5540) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5541) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5542) dev_err(hba->dev, "%s: failed to handle urgent bkops %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5543) __func__, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5544) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5546) static int ufshcd_wb_ctrl(struct ufs_hba *hba, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5547) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5548) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5549) u8 index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5550) enum query_opcode opcode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5552) if (!ufshcd_is_wb_allowed(hba))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5553) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5555) if (!(enable ^ hba->wb_enabled))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5556) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5557) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5558) opcode = UPIU_QUERY_OPCODE_SET_FLAG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5559) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5560) opcode = UPIU_QUERY_OPCODE_CLEAR_FLAG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5562) index = ufshcd_wb_get_query_index(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5563) ret = ufshcd_query_flag_retry(hba, opcode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5564) QUERY_FLAG_IDN_WB_EN, index, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5565) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5566) dev_err(hba->dev, "%s write booster %s failed %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5567) __func__, enable ? "enable" : "disable", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5568) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5569) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5571) hba->wb_enabled = enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5572) dev_dbg(hba->dev, "%s write booster %s %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5573) __func__, enable ? "enable" : "disable", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5575) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5576) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5578) static int ufshcd_wb_toggle_flush_during_h8(struct ufs_hba *hba, bool set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5579) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5580) int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5581) u8 index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5583) if (set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5584) val = UPIU_QUERY_OPCODE_SET_FLAG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5585) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5586) val = UPIU_QUERY_OPCODE_CLEAR_FLAG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5588) index = ufshcd_wb_get_query_index(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5589) return ufshcd_query_flag_retry(hba, val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5590) QUERY_FLAG_IDN_WB_BUFF_FLUSH_DURING_HIBERN8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5591) index, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5592) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5594) static inline void ufshcd_wb_toggle_flush(struct ufs_hba *hba, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5595) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5596) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5597) ufshcd_wb_buf_flush_enable(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5598) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5599) ufshcd_wb_buf_flush_disable(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5601) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5603) static int ufshcd_wb_buf_flush_enable(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5604) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5605) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5606) u8 index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5608) if (!ufshcd_is_wb_allowed(hba) || hba->wb_buf_flush_enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5609) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5611) index = ufshcd_wb_get_query_index(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5612) ret = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_SET_FLAG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5613) QUERY_FLAG_IDN_WB_BUFF_FLUSH_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5614) index, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5615) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5616) dev_err(hba->dev, "%s WB - buf flush enable failed %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5617) __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5618) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5619) hba->wb_buf_flush_enabled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5621) dev_dbg(hba->dev, "WB - Flush enabled: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5622) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5623) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5625) static int ufshcd_wb_buf_flush_disable(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5626) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5627) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5628) u8 index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5630) if (!ufshcd_is_wb_allowed(hba) || !hba->wb_buf_flush_enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5631) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5633) index = ufshcd_wb_get_query_index(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5634) ret = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_CLEAR_FLAG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5635) QUERY_FLAG_IDN_WB_BUFF_FLUSH_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5636) index, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5637) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5638) dev_warn(hba->dev, "%s: WB - buf flush disable failed %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5639) __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5640) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5641) hba->wb_buf_flush_enabled = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5642) dev_dbg(hba->dev, "WB - Flush disabled: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5643) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5645) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5646) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5648) static bool ufshcd_wb_presrv_usrspc_keep_vcc_on(struct ufs_hba *hba,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5649) u32 avail_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5650) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5651) u32 cur_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5652) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5653) u8 index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5655) index = ufshcd_wb_get_query_index(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5656) ret = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5657) QUERY_ATTR_IDN_CURR_WB_BUFF_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5658) index, 0, &cur_buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5659) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5660) dev_err(hba->dev, "%s dCurWriteBoosterBufferSize read failed %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5661) __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5662) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5663) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5665) if (!cur_buf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5666) dev_info(hba->dev, "dCurWBBuf: %d WB disabled until free-space is available\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5667) cur_buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5668) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5669) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5670) /* Let it continue to flush when available buffer exceeds threshold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5671) if (avail_buf < hba->vps->wb_flush_threshold)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5672) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5674) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5675) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5677) static bool ufshcd_wb_need_flush(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5678) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5679) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5680) u32 avail_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5681) u8 index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5683) if (!ufshcd_is_wb_allowed(hba))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5684) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5685) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5686) * The ufs device needs the vcc to be ON to flush.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5687) * With user-space reduction enabled, it's enough to enable flush
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5688) * by checking only the available buffer. The threshold
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5689) * defined here is > 90% full.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5690) * With user-space preserved enabled, the current-buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5691) * should be checked too because the wb buffer size can reduce
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5692) * when disk tends to be full. This info is provided by current
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5693) * buffer (dCurrentWriteBoosterBufferSize). There's no point in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5694) * keeping vcc on when current buffer is empty.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5695) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5696) index = ufshcd_wb_get_query_index(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5697) ret = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5698) QUERY_ATTR_IDN_AVAIL_WB_BUFF_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5699) index, 0, &avail_buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5700) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5701) dev_warn(hba->dev, "%s dAvailableWriteBoosterBufferSize read failed %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5702) __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5703) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5704) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5706) if (!hba->dev_info.b_presrv_uspc_en) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5707) if (avail_buf <= UFS_WB_BUF_REMAIN_PERCENT(10))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5708) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5709) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5710) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5712) return ufshcd_wb_presrv_usrspc_keep_vcc_on(hba, avail_buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5713) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5715) static void ufshcd_rpm_dev_flush_recheck_work(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5716) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5717) struct ufs_hba *hba = container_of(to_delayed_work(work),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5718) struct ufs_hba,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5719) rpm_dev_flush_recheck_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5720) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5721) * To prevent unnecessary VCC power drain after device finishes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5722) * WriteBooster buffer flush or Auto BKOPs, force runtime resume
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5723) * after a certain delay to recheck the threshold by next runtime
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5724) * suspend.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5725) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5726) pm_runtime_get_sync(hba->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5727) pm_runtime_put_sync(hba->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5728) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5730) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5731) * ufshcd_exception_event_handler - handle exceptions raised by device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5732) * @work: pointer to work data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5733) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5734) * Read bExceptionEventStatus attribute from the device and handle the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5735) * exception event accordingly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5736) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5737) static void ufshcd_exception_event_handler(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5738) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5739) struct ufs_hba *hba;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5740) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5741) u32 status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5742) hba = container_of(work, struct ufs_hba, eeh_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5744) pm_runtime_get_sync(hba->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5745) ufshcd_scsi_block_requests(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5746) err = ufshcd_get_ee_status(hba, &status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5747) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5748) dev_err(hba->dev, "%s: failed to get exception status %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5749) __func__, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5750) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5751) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5753) status &= hba->ee_ctrl_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5755) if (status & MASK_EE_URGENT_BKOPS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5756) ufshcd_bkops_exception_event_handler(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5758) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5759) ufshcd_scsi_unblock_requests(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5760) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5761) * pm_runtime_get_noresume is called while scheduling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5762) * eeh_work to avoid suspend racing with exception work.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5763) * Hence decrement usage counter using pm_runtime_put_noidle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5764) * to allow suspend on completion of exception event handler.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5765) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5766) pm_runtime_put_noidle(hba->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5767) pm_runtime_put(hba->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5768) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5769) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5771) /* Complete requests that have door-bell cleared */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5772) static void ufshcd_complete_requests(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5773) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5774) ufshcd_trc_handler(hba, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5775) ufshcd_tmc_handler(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5776) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5778) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5779) * ufshcd_quirk_dl_nac_errors - This function checks if error handling is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5780) * to recover from the DL NAC errors or not.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5781) * @hba: per-adapter instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5782) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5783) * Returns true if error handling is required, false otherwise
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5784) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5785) static bool ufshcd_quirk_dl_nac_errors(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5786) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5787) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5788) bool err_handling = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5790) spin_lock_irqsave(hba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5791) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5792) * UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS only workaround the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5793) * device fatal error and/or DL NAC & REPLAY timeout errors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5794) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5795) if (hba->saved_err & (CONTROLLER_FATAL_ERROR | SYSTEM_BUS_FATAL_ERROR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5796) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5798) if ((hba->saved_err & DEVICE_FATAL_ERROR) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5799) ((hba->saved_err & UIC_ERROR) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5800) (hba->saved_uic_err & UFSHCD_UIC_DL_TCx_REPLAY_ERROR)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5801) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5803) if ((hba->saved_err & UIC_ERROR) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5804) (hba->saved_uic_err & UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5805) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5806) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5807) * wait for 50ms to see if we can get any other errors or not.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5808) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5809) spin_unlock_irqrestore(hba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5810) msleep(50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5811) spin_lock_irqsave(hba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5813) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5814) * now check if we have got any other severe errors other than
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5815) * DL NAC error?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5816) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5817) if ((hba->saved_err & INT_FATAL_ERRORS) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5818) ((hba->saved_err & UIC_ERROR) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5819) (hba->saved_uic_err & ~UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5820) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5822) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5823) * As DL NAC is the only error received so far, send out NOP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5824) * command to confirm if link is still active or not.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5825) * - If we don't get any response then do error recovery.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5826) * - If we get response then clear the DL NAC error bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5827) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5829) spin_unlock_irqrestore(hba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5830) err = ufshcd_verify_dev_init(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5831) spin_lock_irqsave(hba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5833) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5834) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5836) /* Link seems to be alive hence ignore the DL NAC errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5837) if (hba->saved_uic_err == UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5838) hba->saved_err &= ~UIC_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5839) /* clear NAC error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5840) hba->saved_uic_err &= ~UFSHCD_UIC_DL_NAC_RECEIVED_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5841) if (!hba->saved_uic_err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5842) err_handling = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5843) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5844) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5845) spin_unlock_irqrestore(hba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5846) return err_handling;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5847) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5849) /* host lock must be held before calling this func */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5850) static inline bool ufshcd_is_saved_err_fatal(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5851) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5852) return (hba->saved_uic_err & UFSHCD_UIC_DL_PA_INIT_ERROR) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5853) (hba->saved_err & (INT_FATAL_ERRORS | UFSHCD_UIC_HIBERN8_MASK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5854) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5856) /* host lock must be held before calling this func */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5857) static inline void ufshcd_schedule_eh_work(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5858) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5859) /* handle fatal errors only when link is not in error state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5860) if (hba->ufshcd_state != UFSHCD_STATE_ERROR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5861) if (hba->force_reset || ufshcd_is_link_broken(hba) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5862) ufshcd_is_saved_err_fatal(hba))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5863) hba->ufshcd_state = UFSHCD_STATE_EH_SCHEDULED_FATAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5864) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5865) hba->ufshcd_state = UFSHCD_STATE_EH_SCHEDULED_NON_FATAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5866) queue_work(hba->eh_wq, &hba->eh_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5867) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5868) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5870) static void ufshcd_clk_scaling_allow(struct ufs_hba *hba, bool allow)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5871) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5872) down_write(&hba->clk_scaling_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5873) hba->clk_scaling.is_allowed = allow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5874) up_write(&hba->clk_scaling_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5875) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5877) static void ufshcd_clk_scaling_suspend(struct ufs_hba *hba, bool suspend)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5878) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5879) if (suspend) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5880) if (hba->clk_scaling.is_enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5881) ufshcd_suspend_clkscaling(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5882) ufshcd_clk_scaling_allow(hba, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5883) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5884) ufshcd_clk_scaling_allow(hba, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5885) if (hba->clk_scaling.is_enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5886) ufshcd_resume_clkscaling(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5887) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5888) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5890) static void ufshcd_err_handling_prepare(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5891) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5892) pm_runtime_get_sync(hba->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5893) if (pm_runtime_status_suspended(hba->dev) || hba->is_sys_suspended) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5894) enum ufs_pm_op pm_op;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5896) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5897) * Don't assume anything of pm_runtime_get_sync(), if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5898) * resume fails, irq and clocks can be OFF, and powers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5899) * can be OFF or in LPM.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5900) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5901) ufshcd_setup_hba_vreg(hba, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5902) ufshcd_enable_irq(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5903) ufshcd_setup_vreg(hba, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5904) ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5905) ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5906) ufshcd_hold(hba, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5907) if (!ufshcd_is_clkgating_allowed(hba))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5908) ufshcd_setup_clocks(hba, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5909) ufshcd_release(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5910) pm_op = hba->is_sys_suspended ? UFS_SYSTEM_PM : UFS_RUNTIME_PM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5911) ufshcd_vops_resume(hba, pm_op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5912) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5913) ufshcd_hold(hba, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5914) if (ufshcd_is_clkscaling_supported(hba) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5915) hba->clk_scaling.is_enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5916) ufshcd_suspend_clkscaling(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5917) ufshcd_clk_scaling_allow(hba, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5918) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5919) ufshcd_scsi_block_requests(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5920) /* Drain ufshcd_queuecommand() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5921) down_write(&hba->clk_scaling_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5922) up_write(&hba->clk_scaling_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5923) cancel_work_sync(&hba->eeh_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5924) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5926) static void ufshcd_err_handling_unprepare(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5927) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5928) ufshcd_scsi_unblock_requests(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5929) ufshcd_release(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5930) if (ufshcd_is_clkscaling_supported(hba))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5931) ufshcd_clk_scaling_suspend(hba, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5932) pm_runtime_put(hba->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5933) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5935) static inline bool ufshcd_err_handling_should_stop(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5936) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5937) return (!hba->is_powered || hba->shutting_down ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5938) hba->ufshcd_state == UFSHCD_STATE_ERROR ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5939) (!(hba->saved_err || hba->saved_uic_err || hba->force_reset ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5940) ufshcd_is_link_broken(hba))));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5941) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5943) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5944) static void ufshcd_recover_pm_error(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5945) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5946) struct Scsi_Host *shost = hba->host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5947) struct scsi_device *sdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5948) struct request_queue *q;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5949) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5951) hba->is_sys_suspended = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5952) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5953) * Set RPM status of hba device to RPM_ACTIVE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5954) * this also clears its runtime error.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5955) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5956) ret = pm_runtime_set_active(hba->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5957) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5958) * If hba device had runtime error, we also need to resume those
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5959) * scsi devices under hba in case any of them has failed to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5960) * resumed due to hba runtime resume failure. This is to unblock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5961) * blk_queue_enter in case there are bios waiting inside it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5962) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5963) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5964) shost_for_each_device(sdev, shost) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5965) q = sdev->request_queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5966) if (q->dev && (q->rpm_status == RPM_SUSPENDED ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5967) q->rpm_status == RPM_SUSPENDING))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5968) pm_request_resume(q->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5969) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5970) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5971) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5972) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5973) static inline void ufshcd_recover_pm_error(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5974) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5975) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5976) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5978) static bool ufshcd_is_pwr_mode_restore_needed(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5979) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5980) struct ufs_pa_layer_attr *pwr_info = &hba->pwr_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5981) u32 mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5983) ufshcd_dme_get(hba, UIC_ARG_MIB(PA_PWRMODE), &mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5985) if (pwr_info->pwr_rx != ((mode >> PWRMODE_RX_OFFSET) & PWRMODE_MASK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5986) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5988) if (pwr_info->pwr_tx != (mode & PWRMODE_MASK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5989) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5991) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5992) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5994) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5995) * ufshcd_err_handler - handle UFS errors that require s/w attention
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5996) * @work: pointer to work structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5997) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5998) static void ufshcd_err_handler(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5999) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6000) struct ufs_hba *hba;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6001) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6002) bool err_xfer = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6003) bool err_tm = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6004) int err = 0, pmc_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6005) int tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6006) bool needs_reset = false, needs_restore = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6008) hba = container_of(work, struct ufs_hba, eh_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6010) down(&hba->host_sem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6011) spin_lock_irqsave(hba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6012) if (ufshcd_err_handling_should_stop(hba)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6013) if (hba->ufshcd_state != UFSHCD_STATE_ERROR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6014) hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6015) spin_unlock_irqrestore(hba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6016) up(&hba->host_sem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6017) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6018) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6019) ufshcd_set_eh_in_progress(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6020) spin_unlock_irqrestore(hba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6021) ufshcd_err_handling_prepare(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6022) /* Complete requests that have door-bell cleared by h/w */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6023) ufshcd_complete_requests(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6024) spin_lock_irqsave(hba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6025) if (hba->ufshcd_state != UFSHCD_STATE_ERROR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6026) hba->ufshcd_state = UFSHCD_STATE_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6027) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6028) * A full reset and restore might have happened after preparation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6029) * is finished, double check whether we should stop.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6030) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6031) if (ufshcd_err_handling_should_stop(hba))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6032) goto skip_err_handling;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6034) if (hba->dev_quirks & UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6035) bool ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6037) spin_unlock_irqrestore(hba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6038) /* release the lock as ufshcd_quirk_dl_nac_errors() may sleep */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6039) ret = ufshcd_quirk_dl_nac_errors(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6040) spin_lock_irqsave(hba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6041) if (!ret && ufshcd_err_handling_should_stop(hba))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6042) goto skip_err_handling;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6043) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6045) if ((hba->saved_err & (INT_FATAL_ERRORS | UFSHCD_UIC_HIBERN8_MASK)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6046) (hba->saved_uic_err &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6047) (hba->saved_uic_err != UFSHCD_UIC_PA_GENERIC_ERROR))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6048) bool pr_prdt = !!(hba->saved_err & SYSTEM_BUS_FATAL_ERROR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6050) spin_unlock_irqrestore(hba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6051) ufshcd_print_host_state(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6052) ufshcd_print_pwr_info(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6053) ufshcd_print_evt_hist(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6054) ufshcd_print_tmrs(hba, hba->outstanding_tasks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6055) ufshcd_print_trs(hba, hba->outstanding_reqs, pr_prdt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6056) spin_lock_irqsave(hba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6057) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6059) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6060) * if host reset is required then skip clearing the pending
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6061) * transfers forcefully because they will get cleared during
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6062) * host reset and restore
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6063) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6064) if (hba->force_reset || ufshcd_is_link_broken(hba) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6065) ufshcd_is_saved_err_fatal(hba) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6066) ((hba->saved_err & UIC_ERROR) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6067) (hba->saved_uic_err & (UFSHCD_UIC_DL_NAC_RECEIVED_ERROR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6068) UFSHCD_UIC_DL_TCx_REPLAY_ERROR)))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6069) needs_reset = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6070) goto do_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6071) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6073) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6074) * If LINERESET was caught, UFS might have been put to PWM mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6075) * check if power mode restore is needed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6076) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6077) if (hba->saved_uic_err & UFSHCD_UIC_PA_GENERIC_ERROR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6078) hba->saved_uic_err &= ~UFSHCD_UIC_PA_GENERIC_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6079) if (!hba->saved_uic_err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6080) hba->saved_err &= ~UIC_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6081) spin_unlock_irqrestore(hba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6082) if (ufshcd_is_pwr_mode_restore_needed(hba))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6083) needs_restore = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6084) spin_lock_irqsave(hba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6085) if (!hba->saved_err && !needs_restore)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6086) goto skip_err_handling;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6087) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6089) hba->silence_err_logs = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6090) /* release lock as clear command might sleep */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6091) spin_unlock_irqrestore(hba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6092) /* Clear pending transfer requests */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6093) for_each_set_bit(tag, &hba->outstanding_reqs, hba->nutrs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6094) if (ufshcd_try_to_abort_task(hba, tag)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6095) err_xfer = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6096) goto lock_skip_pending_xfer_clear;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6097) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6098) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6100) /* Clear pending task management requests */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6101) for_each_set_bit(tag, &hba->outstanding_tasks, hba->nutmrs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6102) if (ufshcd_clear_tm_cmd(hba, tag)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6103) err_tm = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6104) goto lock_skip_pending_xfer_clear;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6108) lock_skip_pending_xfer_clear:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6109) /* Complete the requests that are cleared by s/w */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6110) ufshcd_complete_requests(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6112) spin_lock_irqsave(hba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6113) hba->silence_err_logs = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6114) if (err_xfer || err_tm) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6115) needs_reset = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6116) goto do_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6119) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6120) * After all reqs and tasks are cleared from doorbell,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6121) * now it is safe to retore power mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6122) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6123) if (needs_restore) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6124) spin_unlock_irqrestore(hba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6125) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6126) * Hold the scaling lock just in case dev cmds
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6127) * are sent via bsg and/or sysfs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6128) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6129) down_write(&hba->clk_scaling_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6130) hba->force_pmc = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6131) pmc_err = ufshcd_config_pwr_mode(hba, &(hba->pwr_info));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6132) if (pmc_err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6133) needs_reset = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6134) dev_err(hba->dev, "%s: Failed to restore power mode, err = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6135) __func__, pmc_err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6137) hba->force_pmc = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6138) ufshcd_print_pwr_info(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6139) up_write(&hba->clk_scaling_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6140) spin_lock_irqsave(hba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6143) do_reset:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6144) /* Fatal errors need reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6145) if (needs_reset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6146) hba->force_reset = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6147) spin_unlock_irqrestore(hba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6148) err = ufshcd_reset_and_restore(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6149) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6150) dev_err(hba->dev, "%s: reset and restore failed with err %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6151) __func__, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6152) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6153) ufshcd_recover_pm_error(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6154) spin_lock_irqsave(hba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6157) skip_err_handling:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6158) if (!needs_reset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6159) if (hba->ufshcd_state == UFSHCD_STATE_RESET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6160) hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6161) if (hba->saved_err || hba->saved_uic_err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6162) dev_err_ratelimited(hba->dev, "%s: exit: saved_err 0x%x saved_uic_err 0x%x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6163) __func__, hba->saved_err, hba->saved_uic_err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6165) ufshcd_clear_eh_in_progress(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6166) spin_unlock_irqrestore(hba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6167) ufshcd_err_handling_unprepare(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6168) up(&hba->host_sem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6171) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6172) * ufshcd_update_uic_error - check and set fatal UIC error flags.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6173) * @hba: per-adapter instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6174) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6175) * Returns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6176) * IRQ_HANDLED - If interrupt is valid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6177) * IRQ_NONE - If invalid interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6178) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6179) static irqreturn_t ufshcd_update_uic_error(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6181) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6182) irqreturn_t retval = IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6184) /* PHY layer error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6185) reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6186) if ((reg & UIC_PHY_ADAPTER_LAYER_ERROR) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6187) (reg & UIC_PHY_ADAPTER_LAYER_ERROR_CODE_MASK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6188) ufshcd_update_evt_hist(hba, UFS_EVT_PA_ERR, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6189) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6190) * To know whether this error is fatal or not, DB timeout
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6191) * must be checked but this error is handled separately.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6192) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6193) if (reg & UIC_PHY_ADAPTER_LAYER_LANE_ERR_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6194) dev_dbg(hba->dev, "%s: UIC Lane error reported\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6195) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6197) /* Got a LINERESET indication. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6198) if (reg & UIC_PHY_ADAPTER_LAYER_GENERIC_ERROR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6199) struct uic_command *cmd = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6201) hba->uic_error |= UFSHCD_UIC_PA_GENERIC_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6202) if (hba->uic_async_done && hba->active_uic_cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6203) cmd = hba->active_uic_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6204) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6205) * Ignore the LINERESET during power mode change
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6206) * operation via DME_SET command.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6207) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6208) if (cmd && (cmd->command == UIC_CMD_DME_SET))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6209) hba->uic_error &= ~UFSHCD_UIC_PA_GENERIC_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6211) retval |= IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6214) /* PA_INIT_ERROR is fatal and needs UIC reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6215) reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DATA_LINK_LAYER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6216) if ((reg & UIC_DATA_LINK_LAYER_ERROR) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6217) (reg & UIC_DATA_LINK_LAYER_ERROR_CODE_MASK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6218) ufshcd_update_evt_hist(hba, UFS_EVT_DL_ERR, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6220) if (reg & UIC_DATA_LINK_LAYER_ERROR_PA_INIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6221) hba->uic_error |= UFSHCD_UIC_DL_PA_INIT_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6222) else if (hba->dev_quirks &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6223) UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6224) if (reg & UIC_DATA_LINK_LAYER_ERROR_NAC_RECEIVED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6225) hba->uic_error |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6226) UFSHCD_UIC_DL_NAC_RECEIVED_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6227) else if (reg & UIC_DATA_LINK_LAYER_ERROR_TCx_REPLAY_TIMEOUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6228) hba->uic_error |= UFSHCD_UIC_DL_TCx_REPLAY_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6230) retval |= IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6233) /* UIC NL/TL/DME errors needs software retry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6234) reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_NETWORK_LAYER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6235) if ((reg & UIC_NETWORK_LAYER_ERROR) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6236) (reg & UIC_NETWORK_LAYER_ERROR_CODE_MASK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6237) ufshcd_update_evt_hist(hba, UFS_EVT_NL_ERR, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6238) hba->uic_error |= UFSHCD_UIC_NL_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6239) retval |= IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6242) reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_TRANSPORT_LAYER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6243) if ((reg & UIC_TRANSPORT_LAYER_ERROR) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6244) (reg & UIC_TRANSPORT_LAYER_ERROR_CODE_MASK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6245) ufshcd_update_evt_hist(hba, UFS_EVT_TL_ERR, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6246) hba->uic_error |= UFSHCD_UIC_TL_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6247) retval |= IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6250) reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6251) if ((reg & UIC_DME_ERROR) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6252) (reg & UIC_DME_ERROR_CODE_MASK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6253) ufshcd_update_evt_hist(hba, UFS_EVT_DME_ERR, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6254) hba->uic_error |= UFSHCD_UIC_DME_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6255) retval |= IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6258) dev_dbg(hba->dev, "%s: UIC error flags = 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6259) __func__, hba->uic_error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6260) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6263) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6264) * ufshcd_check_errors - Check for errors that need s/w attention
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6265) * @hba: per-adapter instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6266) * @intr_status: interrupt status generated by the controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6267) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6268) * Returns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6269) * IRQ_HANDLED - If interrupt is valid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6270) * IRQ_NONE - If invalid interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6271) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6272) static irqreturn_t ufshcd_check_errors(struct ufs_hba *hba, u32 intr_status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6273) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6274) bool queue_eh_work = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6275) irqreturn_t retval = IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6277) spin_lock(hba->host->host_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6278) hba->errors |= UFSHCD_ERROR_MASK & intr_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6280) if (hba->errors & INT_FATAL_ERRORS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6281) ufshcd_update_evt_hist(hba, UFS_EVT_FATAL_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6282) hba->errors);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6283) queue_eh_work = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6286) if (hba->errors & UIC_ERROR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6287) hba->uic_error = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6288) retval = ufshcd_update_uic_error(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6289) if (hba->uic_error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6290) dev_err(hba->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6291) "Scheduling error handler because of an UIC error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6292) queue_eh_work = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6296) if (hba->errors & UFSHCD_UIC_HIBERN8_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6297) dev_err(hba->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6298) "%s: Auto Hibern8 %s failed - status: 0x%08x, upmcrs: 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6299) __func__, (hba->errors & UIC_HIBERNATE_ENTER) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6300) "Enter" : "Exit",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6301) hba->errors, ufshcd_get_upmcrs(hba));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6302) ufshcd_update_evt_hist(hba, UFS_EVT_AUTO_HIBERN8_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6303) hba->errors);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6304) ufshcd_set_link_broken(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6305) queue_eh_work = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6308) trace_android_vh_ufs_check_int_errors(hba, queue_eh_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6310) if (queue_eh_work) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6311) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6312) * update the transfer error masks to sticky bits, let's do this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6313) * irrespective of current ufshcd_state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6314) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6315) hba->saved_err |= hba->errors;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6316) hba->saved_uic_err |= hba->uic_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6318) /* dump controller state before resetting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6319) if ((hba->saved_err &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6320) (INT_FATAL_ERRORS | UFSHCD_UIC_HIBERN8_MASK)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6321) (hba->saved_uic_err &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6322) (hba->saved_uic_err != UFSHCD_UIC_PA_GENERIC_ERROR))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6323) dev_err(hba->dev, "%s: saved_err 0x%x saved_uic_err 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6324) __func__, hba->saved_err,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6325) hba->saved_uic_err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6326) ufshcd_dump_regs(hba, 0, UFSHCI_REG_SPACE_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6327) "host_regs: ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6328) ufshcd_print_pwr_info(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6330) ufshcd_schedule_eh_work(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6331) retval |= IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6333) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6334) * if (!queue_eh_work) -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6335) * Other errors are either non-fatal where host recovers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6336) * itself without s/w intervention or errors that will be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6337) * handled by the SCSI core layer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6338) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6339) hba->errors = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6340) hba->uic_error = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6341) spin_unlock(hba->host->host_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6342) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6345) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6346) * ufshcd_tmc_handler - handle task management function completion
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6347) * @hba: per adapter instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6348) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6349) * Returns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6350) * IRQ_HANDLED - If interrupt is valid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6351) * IRQ_NONE - If invalid interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6352) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6353) static irqreturn_t ufshcd_tmc_handler(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6354) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6355) struct request **tmf_rqs = ufs_hba_add_info(hba)->tmf_rqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6356) unsigned long flags, pending, issued;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6357) irqreturn_t ret = IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6358) int tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6360) spin_lock_irqsave(hba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6361) pending = ufshcd_readl(hba, REG_UTP_TASK_REQ_DOOR_BELL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6362) issued = hba->outstanding_tasks & ~pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6363) for_each_set_bit(tag, &issued, hba->nutmrs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6364) struct request *req = tmf_rqs[tag];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6365) struct completion *c = req->end_io_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6367) complete(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6368) ret = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6369) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6370) spin_unlock_irqrestore(hba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6372) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6373) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6375) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6376) * ufshcd_sl_intr - Interrupt service routine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6377) * @hba: per adapter instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6378) * @intr_status: contains interrupts generated by the controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6379) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6380) * Returns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6381) * IRQ_HANDLED - If interrupt is valid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6382) * IRQ_NONE - If invalid interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6383) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6384) static irqreturn_t ufshcd_sl_intr(struct ufs_hba *hba, u32 intr_status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6385) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6386) irqreturn_t retval = IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6388) if (intr_status & UFSHCD_UIC_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6389) retval |= ufshcd_uic_cmd_compl(hba, intr_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6391) if (intr_status & UFSHCD_ERROR_MASK || hba->errors)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6392) retval |= ufshcd_check_errors(hba, intr_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6394) if (intr_status & UTP_TASK_REQ_COMPL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6395) retval |= ufshcd_tmc_handler(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6397) if (intr_status & UTP_TRANSFER_REQ_COMPL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6398) retval |= ufshcd_trc_handler(hba, ufshcd_has_utrlcnr(hba));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6400) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6403) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6404) * ufshcd_intr - Main interrupt service routine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6405) * @irq: irq number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6406) * @__hba: pointer to adapter instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6407) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6408) * Returns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6409) * IRQ_HANDLED - If interrupt is valid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6410) * IRQ_NONE - If invalid interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6411) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6412) static irqreturn_t ufshcd_intr(int irq, void *__hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6413) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6414) u32 intr_status, enabled_intr_status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6415) irqreturn_t retval = IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6416) struct ufs_hba *hba = __hba;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6417) int retries = hba->nutrs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6419) intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6420) hba->ufs_stats.last_intr_status = intr_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6421) hba->ufs_stats.last_intr_ts = ktime_get();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6423) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6424) * There could be max of hba->nutrs reqs in flight and in worst case
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6425) * if the reqs get finished 1 by 1 after the interrupt status is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6426) * read, make sure we handle them by checking the interrupt status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6427) * again in a loop until we process all of the reqs before returning.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6428) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6429) while (intr_status && retries--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6430) enabled_intr_status =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6431) intr_status & ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6432) if (intr_status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6433) ufshcd_writel(hba, intr_status, REG_INTERRUPT_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6434) if (enabled_intr_status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6435) retval |= ufshcd_sl_intr(hba, enabled_intr_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6437) intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6440) if (enabled_intr_status && retval == IRQ_NONE &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6441) !ufshcd_eh_in_progress(hba)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6442) dev_err(hba->dev, "%s: Unhandled interrupt 0x%08x (0x%08x, 0x%08x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6443) __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6444) intr_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6445) hba->ufs_stats.last_intr_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6446) enabled_intr_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6447) ufshcd_dump_regs(hba, 0, UFSHCI_REG_SPACE_SIZE, "host_regs: ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6450) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6453) static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int tag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6454) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6455) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6456) u32 mask = 1 << tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6457) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6459) if (!test_bit(tag, &hba->outstanding_tasks))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6460) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6462) spin_lock_irqsave(hba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6463) ufshcd_utmrl_clear(hba, tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6464) spin_unlock_irqrestore(hba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6466) /* poll for max. 1 sec to clear door bell register by h/w */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6467) err = ufshcd_wait_for_register(hba,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6468) REG_UTP_TASK_REQ_DOOR_BELL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6469) mask, 0, 1000, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6470) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6471) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6474) static int __ufshcd_issue_tm_cmd(struct ufs_hba *hba,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6475) struct utp_task_req_desc *treq, u8 tm_function)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6476) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6477) struct request **tmf_rqs = ufs_hba_add_info(hba)->tmf_rqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6478) struct request_queue *q = hba->tmf_queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6479) struct Scsi_Host *host = hba->host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6480) DECLARE_COMPLETION_ONSTACK(wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6481) struct request *req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6482) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6483) int task_tag, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6485) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6486) * blk_get_request() is used here only to get a free tag.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6487) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6488) req = blk_get_request(q, REQ_OP_DRV_OUT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6489) if (IS_ERR(req))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6490) return PTR_ERR(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6492) req->end_io_data = &wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6493) ufshcd_hold(hba, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6495) spin_lock_irqsave(host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6497) task_tag = req->tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6498) tmf_rqs[req->tag] = req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6499) treq->req_header.dword_0 |= cpu_to_be32(task_tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6501) memcpy(hba->utmrdl_base_addr + task_tag, treq, sizeof(*treq));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6502) ufshcd_vops_setup_task_mgmt(hba, task_tag, tm_function);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6504) /* send command to the controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6505) __set_bit(task_tag, &hba->outstanding_tasks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6507) /* Make sure descriptors are ready before ringing the task doorbell */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6508) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6510) ufshcd_writel(hba, 1 << task_tag, REG_UTP_TASK_REQ_DOOR_BELL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6511) /* Make sure that doorbell is committed immediately */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6512) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6514) spin_unlock_irqrestore(host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6516) ufshcd_add_tm_upiu_trace(hba, task_tag, "tm_send");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6518) /* wait until the task management command is completed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6519) err = wait_for_completion_io_timeout(&wait,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6520) msecs_to_jiffies(TM_CMD_TIMEOUT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6521) if (!err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6522) ufshcd_add_tm_upiu_trace(hba, task_tag, "tm_complete_err");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6523) dev_err(hba->dev, "%s: task management cmd 0x%.2x timed-out\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6524) __func__, tm_function);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6525) if (ufshcd_clear_tm_cmd(hba, task_tag))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6526) dev_WARN(hba->dev, "%s: unable to clear tm cmd (slot %d) after timeout\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6527) __func__, task_tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6528) err = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6529) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6530) err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6531) memcpy(treq, hba->utmrdl_base_addr + task_tag, sizeof(*treq));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6533) ufshcd_add_tm_upiu_trace(hba, task_tag, "tm_complete");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6534) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6536) spin_lock_irqsave(hba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6537) tmf_rqs[req->tag] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6538) __clear_bit(task_tag, &hba->outstanding_tasks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6539) spin_unlock_irqrestore(hba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6541) ufshcd_release(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6542) blk_put_request(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6544) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6545) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6547) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6548) * ufshcd_issue_tm_cmd - issues task management commands to controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6549) * @hba: per adapter instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6550) * @lun_id: LUN ID to which TM command is sent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6551) * @task_id: task ID to which the TM command is applicable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6552) * @tm_function: task management function opcode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6553) * @tm_response: task management service response return value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6554) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6555) * Returns non-zero value on error, zero on success.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6556) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6557) static int ufshcd_issue_tm_cmd(struct ufs_hba *hba, int lun_id, int task_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6558) u8 tm_function, u8 *tm_response)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6559) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6560) struct utp_task_req_desc treq = { { 0 }, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6561) int ocs_value, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6563) /* Configure task request descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6564) treq.header.dword_0 = cpu_to_le32(UTP_REQ_DESC_INT_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6565) treq.header.dword_2 = cpu_to_le32(OCS_INVALID_COMMAND_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6567) /* Configure task request UPIU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6568) treq.req_header.dword_0 = cpu_to_be32(lun_id << 8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6569) cpu_to_be32(UPIU_TRANSACTION_TASK_REQ << 24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6570) treq.req_header.dword_1 = cpu_to_be32(tm_function << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6572) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6573) * The host shall provide the same value for LUN field in the basic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6574) * header and for Input Parameter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6575) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6576) treq.input_param1 = cpu_to_be32(lun_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6577) treq.input_param2 = cpu_to_be32(task_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6579) err = __ufshcd_issue_tm_cmd(hba, &treq, tm_function);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6580) if (err == -ETIMEDOUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6581) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6583) ocs_value = le32_to_cpu(treq.header.dword_2) & MASK_OCS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6584) if (ocs_value != OCS_SUCCESS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6585) dev_err(hba->dev, "%s: failed, ocs = 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6586) __func__, ocs_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6587) else if (tm_response)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6588) *tm_response = be32_to_cpu(treq.output_param1) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6589) MASK_TM_SERVICE_RESP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6590) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6591) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6593) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6594) * ufshcd_issue_devman_upiu_cmd - API for sending "utrd" type requests
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6595) * @hba: per-adapter instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6596) * @req_upiu: upiu request
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6597) * @rsp_upiu: upiu reply
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6598) * @desc_buff: pointer to descriptor buffer, NULL if NA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6599) * @buff_len: descriptor size, 0 if NA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6600) * @cmd_type: specifies the type (NOP, Query...)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6601) * @desc_op: descriptor operation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6602) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6603) * Those type of requests uses UTP Transfer Request Descriptor - utrd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6604) * Therefore, it "rides" the device management infrastructure: uses its tag and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6605) * tasks work queues.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6606) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6607) * Since there is only one available tag for device management commands,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6608) * the caller is expected to hold the hba->dev_cmd.lock mutex.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6609) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6610) static int ufshcd_issue_devman_upiu_cmd(struct ufs_hba *hba,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6611) struct utp_upiu_req *req_upiu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6612) struct utp_upiu_req *rsp_upiu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6613) u8 *desc_buff, int *buff_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6614) enum dev_cmd_type cmd_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6615) enum query_opcode desc_op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6616) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6617) DECLARE_COMPLETION_ONSTACK(wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6618) const u32 tag = ufs_hba_add_info(hba)->reserved_slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6619) struct ufshcd_lrb *lrbp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6620) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6621) u8 upiu_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6623) /* Protects use of ufs_hba_add_info(hba)->reserved_slot. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6624) lockdep_assert_held(&hba->dev_cmd.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6626) down_read(&hba->clk_scaling_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6628) lrbp = &hba->lrb[tag];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6629) WARN_ON(lrbp->cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6630) lrbp->cmd = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6631) lrbp->sense_bufflen = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6632) lrbp->sense_buffer = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6633) lrbp->task_tag = tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6634) lrbp->lun = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6635) lrbp->intr_cmd = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6636) ufshcd_prepare_lrbp_crypto(NULL, lrbp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6637) hba->dev_cmd.type = cmd_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6639) if (hba->ufs_version <= ufshci_version(1, 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6640) lrbp->command_type = UTP_CMD_TYPE_DEV_MANAGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6641) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6642) lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6644) /* update the task tag in the request upiu */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6645) req_upiu->header.dword_0 |= cpu_to_be32(tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6647) ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags, DMA_NONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6649) /* just copy the upiu request as it is */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6650) memcpy(lrbp->ucd_req_ptr, req_upiu, sizeof(*lrbp->ucd_req_ptr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6651) if (desc_buff && desc_op == UPIU_QUERY_OPCODE_WRITE_DESC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6652) /* The Data Segment Area is optional depending upon the query
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6653) * function value. for WRITE DESCRIPTOR, the data segment
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6654) * follows right after the tsf.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6655) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6656) memcpy(lrbp->ucd_req_ptr + 1, desc_buff, *buff_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6657) *buff_len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6658) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6660) memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6662) hba->dev_cmd.complete = &wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6664) /* Make sure descriptors are ready before ringing the doorbell */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6665) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6667) ufshcd_send_command(hba, tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6668) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6669) * ignore the returning value here - ufshcd_check_query_response is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6670) * bound to fail since dev_cmd.query and dev_cmd.type were left empty.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6671) * read the response directly ignoring all errors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6672) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6673) ufshcd_wait_for_dev_cmd(hba, lrbp, QUERY_REQ_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6675) /* just copy the upiu response as it is */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6676) memcpy(rsp_upiu, lrbp->ucd_rsp_ptr, sizeof(*rsp_upiu));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6677) if (desc_buff && desc_op == UPIU_QUERY_OPCODE_READ_DESC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6678) u8 *descp = (u8 *)lrbp->ucd_rsp_ptr + sizeof(*rsp_upiu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6679) u16 resp_len = be32_to_cpu(lrbp->ucd_rsp_ptr->header.dword_2) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6680) MASK_QUERY_DATA_SEG_LEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6682) if (*buff_len >= resp_len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6683) memcpy(desc_buff, descp, resp_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6684) *buff_len = resp_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6685) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6686) dev_warn(hba->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6687) "%s: rsp size %d is bigger than buffer size %d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6688) __func__, resp_len, *buff_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6689) *buff_len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6690) err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6691) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6692) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6694) up_read(&hba->clk_scaling_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6695) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6696) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6698) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6699) * ufshcd_exec_raw_upiu_cmd - API function for sending raw upiu commands
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6700) * @hba: per-adapter instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6701) * @req_upiu: upiu request
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6702) * @rsp_upiu: upiu reply - only 8 DW as we do not support scsi commands
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6703) * @msgcode: message code, one of UPIU Transaction Codes Initiator to Target
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6704) * @desc_buff: pointer to descriptor buffer, NULL if NA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6705) * @buff_len: descriptor size, 0 if NA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6706) * @desc_op: descriptor operation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6707) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6708) * Supports UTP Transfer requests (nop and query), and UTP Task
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6709) * Management requests.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6710) * It is up to the caller to fill the upiu conent properly, as it will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6711) * be copied without any further input validations.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6712) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6713) int ufshcd_exec_raw_upiu_cmd(struct ufs_hba *hba,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6714) struct utp_upiu_req *req_upiu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6715) struct utp_upiu_req *rsp_upiu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6716) int msgcode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6717) u8 *desc_buff, int *buff_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6718) enum query_opcode desc_op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6719) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6720) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6721) enum dev_cmd_type cmd_type = DEV_CMD_TYPE_QUERY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6722) struct utp_task_req_desc treq = { { 0 }, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6723) int ocs_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6724) u8 tm_f = be32_to_cpu(req_upiu->header.dword_1) >> 16 & MASK_TM_FUNC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6726) switch (msgcode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6727) case UPIU_TRANSACTION_NOP_OUT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6728) cmd_type = DEV_CMD_TYPE_NOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6729) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6730) case UPIU_TRANSACTION_QUERY_REQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6731) ufshcd_hold(hba, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6732) mutex_lock(&hba->dev_cmd.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6733) err = ufshcd_issue_devman_upiu_cmd(hba, req_upiu, rsp_upiu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6734) desc_buff, buff_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6735) cmd_type, desc_op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6736) mutex_unlock(&hba->dev_cmd.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6737) ufshcd_release(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6739) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6740) case UPIU_TRANSACTION_TASK_REQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6741) treq.header.dword_0 = cpu_to_le32(UTP_REQ_DESC_INT_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6742) treq.header.dword_2 = cpu_to_le32(OCS_INVALID_COMMAND_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6744) memcpy(&treq.req_header, req_upiu, sizeof(*req_upiu));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6746) err = __ufshcd_issue_tm_cmd(hba, &treq, tm_f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6747) if (err == -ETIMEDOUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6748) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6750) ocs_value = le32_to_cpu(treq.header.dword_2) & MASK_OCS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6751) if (ocs_value != OCS_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6752) dev_err(hba->dev, "%s: failed, ocs = 0x%x\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6753) ocs_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6754) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6755) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6757) memcpy(rsp_upiu, &treq.rsp_header, sizeof(*rsp_upiu));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6759) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6760) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6761) err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6763) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6764) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6766) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6767) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6769) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6770) * ufshcd_eh_device_reset_handler - device reset handler registered to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6771) * scsi layer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6772) * @cmd: SCSI command pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6773) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6774) * Returns SUCCESS/FAILED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6775) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6776) static int ufshcd_eh_device_reset_handler(struct scsi_cmnd *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6777) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6778) struct Scsi_Host *host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6779) struct ufs_hba *hba;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6780) u32 pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6781) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6782) u8 resp = 0xF, lun;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6784) host = cmd->device->host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6785) hba = shost_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6787) lun = ufshcd_scsi_to_upiu_lun(cmd->device->lun);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6788) err = ufshcd_issue_tm_cmd(hba, lun, 0, UFS_LOGICAL_RESET, &resp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6789) if (err || resp != UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6790) if (!err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6791) err = resp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6792) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6793) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6795) /* clear the commands that were pending for corresponding LUN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6796) for_each_set_bit(pos, &hba->outstanding_reqs, hba->nutrs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6797) if (hba->lrb[pos].lun == lun) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6798) err = ufshcd_clear_cmd(hba, pos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6799) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6800) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6801) __ufshcd_transfer_req_compl(hba, 1U << pos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6802) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6803) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6805) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6806) hba->req_abort_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6807) ufshcd_update_evt_hist(hba, UFS_EVT_DEV_RESET, (u32)err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6808) if (!err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6809) err = SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6810) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6811) dev_err(hba->dev, "%s: failed with err %d\n", __func__, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6812) err = FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6813) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6814) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6815) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6817) static void ufshcd_set_req_abort_skip(struct ufs_hba *hba, unsigned long bitmap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6818) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6819) struct ufshcd_lrb *lrbp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6820) int tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6822) for_each_set_bit(tag, &bitmap, hba->nutrs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6823) lrbp = &hba->lrb[tag];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6824) lrbp->req_abort_skip = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6825) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6826) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6828) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6829) * ufshcd_try_to_abort_task - abort a specific task
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6830) * @hba: Pointer to adapter instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6831) * @tag: Task tag/index to be aborted
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6832) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6833) * Abort the pending command in device by sending UFS_ABORT_TASK task management
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6834) * command, and in host controller by clearing the door-bell register. There can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6835) * be race between controller sending the command to the device while abort is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6836) * issued. To avoid that, first issue UFS_QUERY_TASK to check if the command is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6837) * really issued and then try to abort it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6838) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6839) * Returns zero on success, non-zero on failure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6840) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6841) static int ufshcd_try_to_abort_task(struct ufs_hba *hba, int tag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6842) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6843) struct ufshcd_lrb *lrbp = &hba->lrb[tag];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6844) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6845) int poll_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6846) u8 resp = 0xF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6847) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6849) for (poll_cnt = 100; poll_cnt; poll_cnt--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6850) err = ufshcd_issue_tm_cmd(hba, lrbp->lun, lrbp->task_tag,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6851) UFS_QUERY_TASK, &resp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6852) if (!err && resp == UPIU_TASK_MANAGEMENT_FUNC_SUCCEEDED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6853) /* cmd pending in the device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6854) dev_err(hba->dev, "%s: cmd pending in the device. tag = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6855) __func__, tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6856) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6857) } else if (!err && resp == UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6858) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6859) * cmd not pending in the device, check if it is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6860) * in transition.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6861) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6862) dev_err(hba->dev, "%s: cmd at tag %d not pending in the device.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6863) __func__, tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6864) reg = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6865) if (reg & (1 << tag)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6866) /* sleep for max. 200us to stabilize */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6867) usleep_range(100, 200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6868) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6869) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6870) /* command completed already */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6871) dev_err(hba->dev, "%s: cmd at tag %d successfully cleared from DB.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6872) __func__, tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6873) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6874) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6875) dev_err(hba->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6876) "%s: no response from device. tag = %d, err %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6877) __func__, tag, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6878) if (!err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6879) err = resp; /* service response error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6880) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6881) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6882) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6884) if (!poll_cnt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6885) err = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6886) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6887) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6889) err = ufshcd_issue_tm_cmd(hba, lrbp->lun, lrbp->task_tag,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6890) UFS_ABORT_TASK, &resp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6891) if (err || resp != UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6892) if (!err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6893) err = resp; /* service response error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6894) dev_err(hba->dev, "%s: issued. tag = %d, err %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6895) __func__, tag, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6896) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6897) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6898) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6900) err = ufshcd_clear_cmd(hba, tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6901) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6902) dev_err(hba->dev, "%s: Failed clearing cmd at tag %d, err %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6903) __func__, tag, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6905) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6906) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6907) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6909) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6910) * ufshcd_abort - scsi host template eh_abort_handler callback
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6911) * @cmd: SCSI command pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6912) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6913) * Returns SUCCESS/FAILED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6914) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6915) static int ufshcd_abort(struct scsi_cmnd *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6916) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6917) struct Scsi_Host *host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6918) struct ufs_hba *hba;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6919) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6920) unsigned int tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6921) int err = FAILED, res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6922) bool outstanding;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6923) struct ufshcd_lrb *lrbp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6924) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6926) host = cmd->device->host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6927) hba = shost_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6928) tag = cmd->request->tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6929) lrbp = &hba->lrb[tag];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6930) if (!ufshcd_valid_tag(hba, tag)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6931) dev_err(hba->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6932) "%s: invalid command tag %d: cmd=0x%p, cmd->request=0x%p",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6933) __func__, tag, cmd, cmd->request);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6934) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6935) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6937) ufshcd_hold(hba, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6938) reg = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6939) /* If command is already aborted/completed, return FAILED. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6940) if (!(test_bit(tag, &hba->outstanding_reqs))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6941) dev_err(hba->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6942) "%s: cmd at tag %d already completed, outstanding=0x%lx, doorbell=0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6943) __func__, tag, hba->outstanding_reqs, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6944) goto release;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6945) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6947) /* Print Transfer Request of aborted task */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6948) dev_info(hba->dev, "%s: Device abort task at tag %d\n", __func__, tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6950) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6951) * Print detailed info about aborted request.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6952) * As more than one request might get aborted at the same time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6953) * print full information only for the first aborted request in order
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6954) * to reduce repeated printouts. For other aborted requests only print
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6955) * basic details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6956) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6957) scsi_print_command(cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6958) if (!hba->req_abort_count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6959) ufshcd_update_evt_hist(hba, UFS_EVT_ABORT, tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6960) ufshcd_print_evt_hist(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6961) ufshcd_print_host_state(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6962) ufshcd_print_pwr_info(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6963) ufshcd_print_trs(hba, 1 << tag, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6964) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6965) ufshcd_print_trs(hba, 1 << tag, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6966) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6967) hba->req_abort_count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6969) if (!(reg & (1 << tag))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6970) dev_err(hba->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6971) "%s: cmd was completed, but without a notifying intr, tag = %d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6972) __func__, tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6973) __ufshcd_transfer_req_compl(hba, 1UL << tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6974) goto release;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6975) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6977) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6978) * Task abort to the device W-LUN is illegal. When this command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6979) * will fail, due to spec violation, scsi err handling next step
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6980) * will be to send LU reset which, again, is a spec violation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6981) * To avoid these unnecessary/illegal steps, first we clean up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6982) * the lrb taken by this cmd and re-set it in outstanding_reqs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6983) * then queue the eh_work and bail.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6984) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6985) if (lrbp->lun == UFS_UPIU_UFS_DEVICE_WLUN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6986) ufshcd_update_evt_hist(hba, UFS_EVT_ABORT, lrbp->lun);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6988) spin_lock_irqsave(host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6989) hba->force_reset = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6990) ufshcd_schedule_eh_work(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6991) spin_unlock_irqrestore(host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6992) goto release;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6993) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6995) /* Skip task abort in case previous aborts failed and report failure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6996) if (lrbp->req_abort_skip) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6997) dev_err(hba->dev, "%s: skipping abort\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6998) ufshcd_set_req_abort_skip(hba, hba->outstanding_reqs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6999) goto release;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7000) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7002) res = ufshcd_try_to_abort_task(hba, tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7003) if (res) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7004) dev_err(hba->dev, "%s: failed with err %d\n", __func__, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7005) ufshcd_set_req_abort_skip(hba, hba->outstanding_reqs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7006) goto release;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7007) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7009) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7010) * Clear the corresponding bit from outstanding_reqs since the command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7011) * has been aborted successfully.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7012) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7013) spin_lock_irqsave(host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7014) outstanding = __test_and_clear_bit(tag, &hba->outstanding_reqs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7015) spin_unlock_irqrestore(host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7017) if (outstanding)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7018) ufshcd_release_scsi_cmd(hba, lrbp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7020) err = SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7022) release:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7023) /* Matches the ufshcd_hold() call at the start of this function. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7024) ufshcd_release(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7025) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7026) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7028) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7029) * ufshcd_host_reset_and_restore - reset and restore host controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7030) * @hba: per-adapter instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7031) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7032) * Note that host controller reset may issue DME_RESET to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7033) * local and remote (device) Uni-Pro stack and the attributes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7034) * are reset to default state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7035) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7036) * Returns zero on success, non-zero on failure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7037) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7038) static int ufshcd_host_reset_and_restore(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7039) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7040) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7042) ufshpb_reset_host(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7043) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7044) * Stop the host controller and complete the requests
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7045) * cleared by h/w
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7046) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7047) ufshcd_hba_stop(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7048) hba->silence_err_logs = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7049) ufshcd_complete_requests(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7050) hba->silence_err_logs = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7052) /* scale up clocks to max frequency before full reinitialization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7053) ufshcd_set_clk_freq(hba, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7055) err = ufshcd_hba_enable(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7057) /* Establish the link again and restore the device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7058) if (!err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7059) err = ufshcd_probe_hba(hba, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7061) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7062) dev_err(hba->dev, "%s: Host init failed %d\n", __func__, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7063) ufshcd_update_evt_hist(hba, UFS_EVT_HOST_RESET, (u32)err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7064) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7065) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7067) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7068) * ufshcd_reset_and_restore - reset and re-initialize host/device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7069) * @hba: per-adapter instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7070) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7071) * Reset and recover device, host and re-establish link. This
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7072) * is helpful to recover the communication in fatal error conditions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7073) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7074) * Returns zero on success, non-zero on failure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7075) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7076) static int ufshcd_reset_and_restore(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7077) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7078) u32 saved_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7079) u32 saved_uic_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7080) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7081) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7082) int retries = MAX_HOST_RESET_RETRIES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7084) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7085) * This is a fresh start, cache and clear saved error first,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7086) * in case new error generated during reset and restore.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7087) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7088) spin_lock_irqsave(hba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7089) saved_err = hba->saved_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7090) saved_uic_err = hba->saved_uic_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7091) hba->saved_err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7092) hba->saved_uic_err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7093) spin_unlock_irqrestore(hba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7095) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7096) /* Reset the attached device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7097) ufshcd_vops_device_reset(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7099) err = ufshcd_host_reset_and_restore(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7100) } while (err && --retries);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7102) spin_lock_irqsave(hba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7103) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7104) * Inform scsi mid-layer that we did reset and allow to handle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7105) * Unit Attention properly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7106) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7107) scsi_report_bus_reset(hba->host, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7108) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7109) hba->ufshcd_state = UFSHCD_STATE_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7110) hba->saved_err |= saved_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7111) hba->saved_uic_err |= saved_uic_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7113) spin_unlock_irqrestore(hba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7115) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7118) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7119) * ufshcd_eh_host_reset_handler - host reset handler registered to scsi layer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7120) * @cmd: SCSI command pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7121) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7122) * Returns SUCCESS/FAILED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7123) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7124) static int ufshcd_eh_host_reset_handler(struct scsi_cmnd *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7125) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7126) int err = SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7127) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7128) struct ufs_hba *hba;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7130) hba = shost_priv(cmd->device->host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7132) spin_lock_irqsave(hba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7133) hba->force_reset = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7134) ufshcd_schedule_eh_work(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7135) dev_err(hba->dev, "%s: reset in progress - 1\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7136) spin_unlock_irqrestore(hba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7138) flush_work(&hba->eh_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7140) spin_lock_irqsave(hba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7141) if (hba->ufshcd_state == UFSHCD_STATE_ERROR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7142) err = FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7143) spin_unlock_irqrestore(hba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7145) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7148) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7149) * ufshcd_get_max_icc_level - calculate the ICC level
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7150) * @sup_curr_uA: max. current supported by the regulator
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7151) * @start_scan: row at the desc table to start scan from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7152) * @buff: power descriptor buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7153) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7154) * Returns calculated max ICC level for specific regulator
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7155) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7156) static u32 ufshcd_get_max_icc_level(int sup_curr_uA, u32 start_scan, char *buff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7158) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7159) int curr_uA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7160) u16 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7161) u16 unit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7163) for (i = start_scan; i >= 0; i--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7164) data = be16_to_cpup((__be16 *)&buff[2 * i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7165) unit = (data & ATTR_ICC_LVL_UNIT_MASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7166) ATTR_ICC_LVL_UNIT_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7167) curr_uA = data & ATTR_ICC_LVL_VALUE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7168) switch (unit) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7169) case UFSHCD_NANO_AMP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7170) curr_uA = curr_uA / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7171) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7172) case UFSHCD_MILI_AMP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7173) curr_uA = curr_uA * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7174) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7175) case UFSHCD_AMP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7176) curr_uA = curr_uA * 1000 * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7177) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7178) case UFSHCD_MICRO_AMP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7179) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7180) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7182) if (sup_curr_uA >= curr_uA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7183) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7185) if (i < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7186) i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7187) pr_err("%s: Couldn't find valid icc_level = %d", __func__, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7190) return (u32)i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7193) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7194) * ufshcd_calc_icc_level - calculate the max ICC level
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7195) * In case regulators are not initialized we'll return 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7196) * @hba: per-adapter instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7197) * @desc_buf: power descriptor buffer to extract ICC levels from.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7198) * @len: length of desc_buff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7199) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7200) * Returns calculated ICC level
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7201) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7202) static u32 ufshcd_find_max_sup_active_icc_level(struct ufs_hba *hba,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7203) u8 *desc_buf, int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7204) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7205) u32 icc_level = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7207) if (!hba->vreg_info.vcc || !hba->vreg_info.vccq ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7208) !hba->vreg_info.vccq2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7209) dev_err(hba->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7210) "%s: Regulator capability was not set, actvIccLevel=%d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7211) __func__, icc_level);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7212) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7215) if (hba->vreg_info.vcc && hba->vreg_info.vcc->max_uA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7216) icc_level = ufshcd_get_max_icc_level(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7217) hba->vreg_info.vcc->max_uA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7218) POWER_DESC_MAX_ACTV_ICC_LVLS - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7219) &desc_buf[PWR_DESC_ACTIVE_LVLS_VCC_0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7221) if (hba->vreg_info.vccq && hba->vreg_info.vccq->max_uA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7222) icc_level = ufshcd_get_max_icc_level(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7223) hba->vreg_info.vccq->max_uA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7224) icc_level,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7225) &desc_buf[PWR_DESC_ACTIVE_LVLS_VCCQ_0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7227) if (hba->vreg_info.vccq2 && hba->vreg_info.vccq2->max_uA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7228) icc_level = ufshcd_get_max_icc_level(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7229) hba->vreg_info.vccq2->max_uA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7230) icc_level,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7231) &desc_buf[PWR_DESC_ACTIVE_LVLS_VCCQ2_0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7232) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7233) return icc_level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7236) static void ufshcd_set_active_icc_lvl(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7237) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7238) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7239) int buff_len = hba->desc_size[QUERY_DESC_IDN_POWER];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7240) u8 *desc_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7241) u32 icc_level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7243) desc_buf = kmalloc(buff_len, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7244) if (!desc_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7245) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7247) ret = ufshcd_read_desc_param(hba, QUERY_DESC_IDN_POWER, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7248) desc_buf, buff_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7249) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7250) dev_err(hba->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7251) "%s: Failed reading power descriptor.len = %d ret = %d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7252) __func__, buff_len, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7253) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7256) icc_level = ufshcd_find_max_sup_active_icc_level(hba, desc_buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7257) buff_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7258) dev_dbg(hba->dev, "%s: setting icc_level 0x%x", __func__, icc_level);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7260) ret = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7261) QUERY_ATTR_IDN_ACTIVE_ICC_LVL, 0, 0, &icc_level);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7263) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7264) dev_err(hba->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7265) "%s: Failed configuring bActiveICCLevel = %d ret = %d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7266) __func__, icc_level, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7268) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7269) kfree(desc_buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7272) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7273) * ufshcd_scsi_add_wlus - Adds required W-LUs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7274) * @hba: per-adapter instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7275) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7276) * UFS device specification requires the UFS devices to support 4 well known
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7277) * logical units:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7278) * "REPORT_LUNS" (address: 01h)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7279) * "UFS Device" (address: 50h)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7280) * "RPMB" (address: 44h)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7281) * "BOOT" (address: 30h)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7282) * UFS device's power management needs to be controlled by "POWER CONDITION"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7283) * field of SSU (START STOP UNIT) command. But this "power condition" field
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7284) * will take effect only when its sent to "UFS device" well known logical unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7285) * hence we require the scsi_device instance to represent this logical unit in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7286) * order for the UFS host driver to send the SSU command for power management.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7287) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7288) * We also require the scsi_device instance for "RPMB" (Replay Protected Memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7289) * Block) LU so user space process can control this LU. User space may also
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7290) * want to have access to BOOT LU.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7291) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7292) * This function adds scsi device instances for each of all well known LUs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7293) * (except "REPORT LUNS" LU).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7294) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7295) * Returns zero on success (all required W-LUs are added successfully),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7296) * non-zero error value on failure (if failed to add any of the required W-LU).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7297) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7298) static int ufshcd_scsi_add_wlus(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7299) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7300) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7301) struct scsi_device *sdev_boot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7303) hba->sdev_ufs_device = __scsi_add_device(hba->host, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7304) ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_UFS_DEVICE_WLUN), NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7305) if (IS_ERR(hba->sdev_ufs_device)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7306) ret = PTR_ERR(hba->sdev_ufs_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7307) hba->sdev_ufs_device = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7308) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7310) scsi_device_put(hba->sdev_ufs_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7312) hba->sdev_rpmb = __scsi_add_device(hba->host, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7313) ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_RPMB_WLUN), NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7314) if (IS_ERR(hba->sdev_rpmb)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7315) ret = PTR_ERR(hba->sdev_rpmb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7316) goto remove_sdev_ufs_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7318) scsi_device_put(hba->sdev_rpmb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7320) sdev_boot = __scsi_add_device(hba->host, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7321) ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_BOOT_WLUN), NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7322) if (IS_ERR(sdev_boot))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7323) dev_err(hba->dev, "%s: BOOT WLUN not found\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7324) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7325) scsi_device_put(sdev_boot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7326) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7328) remove_sdev_ufs_device:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7329) scsi_remove_device(hba->sdev_ufs_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7330) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7331) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7334) static void ufshcd_wb_probe(struct ufs_hba *hba, u8 *desc_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7335) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7336) struct ufs_dev_info *dev_info = &hba->dev_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7337) u8 lun;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7338) u32 d_lu_wb_buf_alloc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7340) if (!ufshcd_is_wb_allowed(hba))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7341) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7342) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7343) * Probe WB only for UFS-2.2 and UFS-3.1 (and later) devices or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7344) * UFS devices with quirk UFS_DEVICE_QUIRK_SUPPORT_EXTENDED_FEATURES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7345) * enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7346) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7347) if (!(dev_info->wspecversion >= 0x310 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7348) dev_info->wspecversion == 0x220 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7349) (hba->dev_quirks & UFS_DEVICE_QUIRK_SUPPORT_EXTENDED_FEATURES)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7350) goto wb_disabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7352) if (hba->desc_size[QUERY_DESC_IDN_DEVICE] <
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7353) DEVICE_DESC_PARAM_EXT_UFS_FEATURE_SUP + 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7354) goto wb_disabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7356) dev_info->d_ext_ufs_feature_sup =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7357) get_unaligned_be32(desc_buf +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7358) DEVICE_DESC_PARAM_EXT_UFS_FEATURE_SUP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7360) if (!(dev_info->d_ext_ufs_feature_sup & UFS_DEV_WRITE_BOOSTER_SUP))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7361) goto wb_disabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7363) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7364) * WB may be supported but not configured while provisioning.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7365) * The spec says, in dedicated wb buffer mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7366) * a max of 1 lun would have wb buffer configured.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7367) * Now only shared buffer mode is supported.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7368) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7369) dev_info->b_wb_buffer_type =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7370) desc_buf[DEVICE_DESC_PARAM_WB_TYPE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7372) dev_info->b_presrv_uspc_en =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7373) desc_buf[DEVICE_DESC_PARAM_WB_PRESRV_USRSPC_EN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7375) if (dev_info->b_wb_buffer_type == WB_BUF_MODE_SHARED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7376) dev_info->d_wb_alloc_units =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7377) get_unaligned_be32(desc_buf +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7378) DEVICE_DESC_PARAM_WB_SHARED_ALLOC_UNITS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7379) if (!dev_info->d_wb_alloc_units)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7380) goto wb_disabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7381) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7382) for (lun = 0; lun < UFS_UPIU_MAX_WB_LUN_ID; lun++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7383) d_lu_wb_buf_alloc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7384) ufshcd_read_unit_desc_param(hba,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7385) lun,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7386) UNIT_DESC_PARAM_WB_BUF_ALLOC_UNITS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7387) (u8 *)&d_lu_wb_buf_alloc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7388) sizeof(d_lu_wb_buf_alloc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7389) if (d_lu_wb_buf_alloc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7390) dev_info->wb_dedicated_lu = lun;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7391) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7395) if (!d_lu_wb_buf_alloc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7396) goto wb_disabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7398) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7400) wb_disabled:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7401) hba->caps &= ~UFSHCD_CAP_WB_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7404) void ufshcd_fixup_dev_quirks(struct ufs_hba *hba, struct ufs_dev_fix *fixups)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7405) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7406) struct ufs_dev_fix *f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7407) struct ufs_dev_info *dev_info = &hba->dev_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7409) if (!fixups)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7410) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7412) for (f = fixups; f->quirk; f++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7413) if ((f->wmanufacturerid == dev_info->wmanufacturerid ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7414) f->wmanufacturerid == UFS_ANY_VENDOR) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7415) ((dev_info->model &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7416) STR_PRFX_EQUAL(f->model, dev_info->model)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7417) !strcmp(f->model, UFS_ANY_MODEL)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7418) hba->dev_quirks |= f->quirk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7419) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7421) EXPORT_SYMBOL_GPL(ufshcd_fixup_dev_quirks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7423) static void ufs_fixup_device_setup(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7424) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7425) /* fix by general quirk table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7426) ufshcd_fixup_dev_quirks(hba, ufs_fixups);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7428) /* allow vendors to fix quirks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7429) ufshcd_vops_fixup_dev_quirks(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7432) static int ufs_get_device_desc(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7433) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7434) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7435) u8 model_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7436) u8 b_ufs_feature_sup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7437) u8 *desc_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7438) struct ufs_dev_info *dev_info = &hba->dev_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7440) desc_buf = kmalloc(QUERY_DESC_MAX_SIZE, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7441) if (!desc_buf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7442) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7443) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7446) err = ufshcd_read_desc_param(hba, QUERY_DESC_IDN_DEVICE, 0, 0, desc_buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7447) hba->desc_size[QUERY_DESC_IDN_DEVICE]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7448) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7449) dev_err(hba->dev, "%s: Failed reading Device Desc. err = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7450) __func__, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7451) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7452) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7454) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7455) * getting vendor (manufacturerID) and Bank Index in big endian
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7456) * format
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7457) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7458) dev_info->wmanufacturerid = desc_buf[DEVICE_DESC_PARAM_MANF_ID] << 8 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7459) desc_buf[DEVICE_DESC_PARAM_MANF_ID + 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7461) /* getting Specification Version in big endian format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7462) dev_info->wspecversion = desc_buf[DEVICE_DESC_PARAM_SPEC_VER] << 8 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7463) desc_buf[DEVICE_DESC_PARAM_SPEC_VER + 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7464) b_ufs_feature_sup = desc_buf[DEVICE_DESC_PARAM_UFS_FEAT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7466) model_index = desc_buf[DEVICE_DESC_PARAM_PRDCT_NAME];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7468) if (dev_info->wspecversion >= UFS_DEV_HPB_SUPPORT_VERSION &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7469) (b_ufs_feature_sup & UFS_DEV_HPB_SUPPORT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7470) bool hpb_en = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7472) ufshpb_get_dev_info(hba, desc_buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7474) if (!ufshpb_is_legacy(hba))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7475) err = ufshcd_query_flag_retry(hba,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7476) UPIU_QUERY_OPCODE_READ_FLAG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7477) QUERY_FLAG_IDN_HPB_EN, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7478) &hpb_en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7480) if (ufshpb_is_legacy(hba) || (!err && hpb_en))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7481) dev_info->hpb_enabled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7482) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7484) err = ufshcd_read_string_desc(hba, model_index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7485) &dev_info->model, SD_ASCII_STD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7486) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7487) dev_err(hba->dev, "%s: Failed reading Product Name. err = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7488) __func__, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7489) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7490) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7492) ufs_fixup_device_setup(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7494) ufshcd_wb_probe(hba, desc_buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7496) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7497) * ufshcd_read_string_desc returns size of the string
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7498) * reset the error value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7499) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7500) err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7502) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7503) kfree(desc_buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7504) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7505) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7507) static void ufs_put_device_desc(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7508) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7509) struct ufs_dev_info *dev_info = &hba->dev_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7511) kfree(dev_info->model);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7512) dev_info->model = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7513) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7515) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7516) * ufshcd_tune_pa_tactivate - Tunes PA_TActivate of local UniPro
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7517) * @hba: per-adapter instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7518) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7519) * PA_TActivate parameter can be tuned manually if UniPro version is less than
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7520) * 1.61. PA_TActivate needs to be greater than or equal to peerM-PHY's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7521) * RX_MIN_ACTIVATETIME_CAPABILITY attribute. This optimal value can help reduce
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7522) * the hibern8 exit latency.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7523) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7524) * Returns zero on success, non-zero error value on failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7525) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7526) static int ufshcd_tune_pa_tactivate(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7527) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7528) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7529) u32 peer_rx_min_activatetime = 0, tuned_pa_tactivate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7531) ret = ufshcd_dme_peer_get(hba,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7532) UIC_ARG_MIB_SEL(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7533) RX_MIN_ACTIVATETIME_CAPABILITY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7534) UIC_ARG_MPHY_RX_GEN_SEL_INDEX(0)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7535) &peer_rx_min_activatetime);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7536) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7537) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7539) /* make sure proper unit conversion is applied */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7540) tuned_pa_tactivate =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7541) ((peer_rx_min_activatetime * RX_MIN_ACTIVATETIME_UNIT_US)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7542) / PA_TACTIVATE_TIME_UNIT_US);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7543) ret = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7544) tuned_pa_tactivate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7546) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7547) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7548) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7550) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7551) * ufshcd_tune_pa_hibern8time - Tunes PA_Hibern8Time of local UniPro
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7552) * @hba: per-adapter instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7553) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7554) * PA_Hibern8Time parameter can be tuned manually if UniPro version is less than
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7555) * 1.61. PA_Hibern8Time needs to be maximum of local M-PHY's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7556) * TX_HIBERN8TIME_CAPABILITY & peer M-PHY's RX_HIBERN8TIME_CAPABILITY.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7557) * This optimal value can help reduce the hibern8 exit latency.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7558) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7559) * Returns zero on success, non-zero error value on failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7560) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7561) static int ufshcd_tune_pa_hibern8time(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7562) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7563) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7564) u32 local_tx_hibern8_time_cap = 0, peer_rx_hibern8_time_cap = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7565) u32 max_hibern8_time, tuned_pa_hibern8time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7567) ret = ufshcd_dme_get(hba,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7568) UIC_ARG_MIB_SEL(TX_HIBERN8TIME_CAPABILITY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7569) UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7570) &local_tx_hibern8_time_cap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7571) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7572) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7574) ret = ufshcd_dme_peer_get(hba,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7575) UIC_ARG_MIB_SEL(RX_HIBERN8TIME_CAPABILITY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7576) UIC_ARG_MPHY_RX_GEN_SEL_INDEX(0)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7577) &peer_rx_hibern8_time_cap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7578) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7579) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7581) max_hibern8_time = max(local_tx_hibern8_time_cap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7582) peer_rx_hibern8_time_cap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7583) /* make sure proper unit conversion is applied */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7584) tuned_pa_hibern8time = ((max_hibern8_time * HIBERN8TIME_UNIT_US)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7585) / PA_HIBERN8_TIME_UNIT_US);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7586) ret = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HIBERN8TIME),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7587) tuned_pa_hibern8time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7588) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7589) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7590) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7592) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7593) * ufshcd_quirk_tune_host_pa_tactivate - Ensures that host PA_TACTIVATE is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7594) * less than device PA_TACTIVATE time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7595) * @hba: per-adapter instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7596) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7597) * Some UFS devices require host PA_TACTIVATE to be lower than device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7598) * PA_TACTIVATE, we need to enable UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE quirk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7599) * for such devices.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7600) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7601) * Returns zero on success, non-zero error value on failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7602) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7603) static int ufshcd_quirk_tune_host_pa_tactivate(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7604) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7605) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7606) u32 granularity, peer_granularity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7607) u32 pa_tactivate, peer_pa_tactivate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7608) u32 pa_tactivate_us, peer_pa_tactivate_us;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7609) u8 gran_to_us_table[] = {1, 4, 8, 16, 32, 100};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7611) ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_GRANULARITY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7612) &granularity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7613) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7614) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7616) ret = ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_GRANULARITY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7617) &peer_granularity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7618) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7619) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7621) if ((granularity < PA_GRANULARITY_MIN_VAL) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7622) (granularity > PA_GRANULARITY_MAX_VAL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7623) dev_err(hba->dev, "%s: invalid host PA_GRANULARITY %d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7624) __func__, granularity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7625) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7626) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7628) if ((peer_granularity < PA_GRANULARITY_MIN_VAL) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7629) (peer_granularity > PA_GRANULARITY_MAX_VAL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7630) dev_err(hba->dev, "%s: invalid device PA_GRANULARITY %d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7631) __func__, peer_granularity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7632) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7633) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7635) ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_TACTIVATE), &pa_tactivate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7636) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7637) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7639) ret = ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_TACTIVATE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7640) &peer_pa_tactivate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7641) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7642) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7644) pa_tactivate_us = pa_tactivate * gran_to_us_table[granularity - 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7645) peer_pa_tactivate_us = peer_pa_tactivate *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7646) gran_to_us_table[peer_granularity - 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7648) if (pa_tactivate_us > peer_pa_tactivate_us) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7649) u32 new_peer_pa_tactivate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7651) new_peer_pa_tactivate = pa_tactivate_us /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7652) gran_to_us_table[peer_granularity - 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7653) new_peer_pa_tactivate++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7654) ret = ufshcd_dme_peer_set(hba, UIC_ARG_MIB(PA_TACTIVATE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7655) new_peer_pa_tactivate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7656) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7658) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7659) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7660) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7662) static void ufshcd_tune_unipro_params(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7663) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7664) if (ufshcd_is_unipro_pa_params_tuning_req(hba)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7665) ufshcd_tune_pa_tactivate(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7666) ufshcd_tune_pa_hibern8time(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7667) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7669) ufshcd_vops_apply_dev_quirks(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7671) if (hba->dev_quirks & UFS_DEVICE_QUIRK_PA_TACTIVATE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7672) /* set 1ms timeout for PA_TACTIVATE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7673) ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE), 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7675) if (hba->dev_quirks & UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7676) ufshcd_quirk_tune_host_pa_tactivate(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7677) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7679) static void ufshcd_clear_dbg_ufs_stats(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7680) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7681) hba->ufs_stats.hibern8_exit_cnt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7682) hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7683) hba->req_abort_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7684) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7686) static int ufshcd_device_geo_params_init(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7687) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7688) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7689) size_t buff_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7690) u8 *desc_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7692) buff_len = hba->desc_size[QUERY_DESC_IDN_GEOMETRY];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7693) desc_buf = kmalloc(buff_len, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7694) if (!desc_buf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7695) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7696) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7697) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7699) err = ufshcd_read_desc_param(hba, QUERY_DESC_IDN_GEOMETRY, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7700) desc_buf, buff_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7701) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7702) dev_err(hba->dev, "%s: Failed reading Geometry Desc. err = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7703) __func__, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7704) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7705) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7707) if (desc_buf[GEOMETRY_DESC_PARAM_MAX_NUM_LUN] == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7708) hba->dev_info.max_lu_supported = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7709) else if (desc_buf[GEOMETRY_DESC_PARAM_MAX_NUM_LUN] == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7710) hba->dev_info.max_lu_supported = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7712) if (hba->desc_size[QUERY_DESC_IDN_GEOMETRY] >=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7713) GEOMETRY_DESC_PARAM_HPB_MAX_ACTIVE_REGS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7714) ufshpb_get_geo_info(hba, desc_buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7716) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7717) kfree(desc_buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7718) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7719) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7721) static struct ufs_ref_clk ufs_ref_clk_freqs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7722) {19200000, REF_CLK_FREQ_19_2_MHZ},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7723) {26000000, REF_CLK_FREQ_26_MHZ},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7724) {38400000, REF_CLK_FREQ_38_4_MHZ},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7725) {52000000, REF_CLK_FREQ_52_MHZ},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7726) {0, REF_CLK_FREQ_INVAL},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7727) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7729) static enum ufs_ref_clk_freq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7730) ufs_get_bref_clk_from_hz(unsigned long freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7731) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7732) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7734) for (i = 0; ufs_ref_clk_freqs[i].freq_hz; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7735) if (ufs_ref_clk_freqs[i].freq_hz == freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7736) return ufs_ref_clk_freqs[i].val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7738) return REF_CLK_FREQ_INVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7739) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7741) void ufshcd_parse_dev_ref_clk_freq(struct ufs_hba *hba, struct clk *refclk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7742) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7743) unsigned long freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7745) freq = clk_get_rate(refclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7747) hba->dev_ref_clk_freq =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7748) ufs_get_bref_clk_from_hz(freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7750) if (hba->dev_ref_clk_freq == REF_CLK_FREQ_INVAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7751) dev_err(hba->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7752) "invalid ref_clk setting = %ld\n", freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7753) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7755) static int ufshcd_set_dev_ref_clk(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7756) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7757) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7758) u32 ref_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7759) u32 freq = hba->dev_ref_clk_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7761) err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7762) QUERY_ATTR_IDN_REF_CLK_FREQ, 0, 0, &ref_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7764) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7765) dev_err(hba->dev, "failed reading bRefClkFreq. err = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7766) err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7767) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7768) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7770) if (ref_clk == freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7771) goto out; /* nothing to update */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7773) err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7774) QUERY_ATTR_IDN_REF_CLK_FREQ, 0, 0, &freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7776) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7777) dev_err(hba->dev, "bRefClkFreq setting to %lu Hz failed\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7778) ufs_ref_clk_freqs[freq].freq_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7779) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7780) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7782) dev_dbg(hba->dev, "bRefClkFreq setting to %lu Hz succeeded\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7783) ufs_ref_clk_freqs[freq].freq_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7785) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7786) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7787) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7789) static int ufshcd_device_params_init(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7790) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7791) bool flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7792) int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7794) /* Init device descriptor sizes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7795) for (i = 0; i < QUERY_DESC_IDN_MAX; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7796) hba->desc_size[i] = QUERY_DESC_MAX_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7798) /* Init UFS geometry descriptor related parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7799) ret = ufshcd_device_geo_params_init(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7800) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7801) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7803) /* Check and apply UFS device quirks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7804) ret = ufs_get_device_desc(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7805) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7806) dev_err(hba->dev, "%s: Failed getting device info. err = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7807) __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7808) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7809) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7811) ufshcd_get_ref_clk_gating_wait(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7813) if (!ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_READ_FLAG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7814) QUERY_FLAG_IDN_PWR_ON_WPE, 0, &flag))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7815) hba->dev_info.f_power_on_wp_en = flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7817) /* Probe maximum power mode co-supported by both UFS host and device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7818) if (ufshcd_get_max_pwr_mode(hba))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7819) dev_err(hba->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7820) "%s: Failed getting max supported power mode\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7821) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7822) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7823) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7824) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7826) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7827) * ufshcd_add_lus - probe and add UFS logical units
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7828) * @hba: per-adapter instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7829) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7830) static int ufshcd_add_lus(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7831) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7832) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7834) /* Add required well known logical units to scsi mid layer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7835) ret = ufshcd_scsi_add_wlus(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7836) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7837) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7839) /* Initialize devfreq after UFS device is detected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7840) if (ufshcd_is_clkscaling_supported(hba)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7841) memcpy(&hba->clk_scaling.saved_pwr_info.info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7842) &hba->pwr_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7843) sizeof(struct ufs_pa_layer_attr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7844) hba->clk_scaling.saved_pwr_info.is_valid = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7845) hba->clk_scaling.is_allowed = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7847) ret = ufshcd_devfreq_init(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7848) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7849) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7851) hba->clk_scaling.is_enabled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7852) ufshcd_init_clk_scaling_sysfs(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7853) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7855) ufs_bsg_probe(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7856) ufshpb_init(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7857) scsi_scan_host(hba->host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7858) pm_runtime_put_sync(hba->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7860) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7861) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7862) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7864) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7865) * ufshcd_probe_hba - probe hba to detect device and initialize
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7866) * @hba: per-adapter instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7867) * @async: asynchronous execution or not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7868) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7869) * Execute link-startup and verify device initialization
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7870) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7871) static int ufshcd_probe_hba(struct ufs_hba *hba, bool async)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7872) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7873) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7874) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7875) ktime_t start = ktime_get();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7877) hba->ufshcd_state = UFSHCD_STATE_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7879) ret = ufshcd_link_startup(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7880) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7881) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7883) if (hba->quirks & UFSHCD_QUIRK_SKIP_INTERFACE_CONFIGURATION)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7884) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7886) /* Debug counters initialization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7887) ufshcd_clear_dbg_ufs_stats(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7889) /* UniPro link is active now */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7890) ufshcd_set_link_active(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7892) /* Verify device initialization by sending NOP OUT UPIU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7893) ret = ufshcd_verify_dev_init(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7894) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7895) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7897) /* Initiate UFS initialization, and waiting until completion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7898) ret = ufshcd_complete_dev_init(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7899) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7900) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7902) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7903) * Initialize UFS device parameters used by driver, these
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7904) * parameters are associated with UFS descriptors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7905) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7906) if (async) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7907) ret = ufshcd_device_params_init(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7908) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7909) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7910) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7912) ufshcd_tune_unipro_params(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7914) /* UFS device is also active now */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7915) ufshcd_set_ufs_dev_active(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7916) ufshcd_force_reset_auto_bkops(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7918) /* Gear up to HS gear if supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7919) if (hba->max_pwr_info.is_valid) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7920) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7921) * Set the right value to bRefClkFreq before attempting to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7922) * switch to HS gears.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7923) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7924) if (hba->dev_ref_clk_freq != REF_CLK_FREQ_INVAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7925) ufshcd_set_dev_ref_clk(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7926) ret = ufshcd_config_pwr_mode(hba, &hba->max_pwr_info.info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7927) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7928) dev_err(hba->dev, "%s: Failed setting power mode, err = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7929) __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7930) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7931) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7932) ufshcd_print_pwr_info(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7933) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7935) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7936) * bActiveICCLevel is volatile for UFS device (as per latest v2.1 spec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7937) * and for removable UFS card as well, hence always set the parameter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7938) * Note: Error handler may issue the device reset hence resetting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7939) * bActiveICCLevel as well so it is always safe to set this here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7940) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7941) ufshcd_set_active_icc_lvl(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7943) ufshcd_wb_config(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7944) /* Enable Auto-Hibernate if configured */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7945) ufshcd_auto_hibern8_enable(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7947) ufshpb_reset(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7949) trace_android_rvh_ufs_complete_init(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7950) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7951) spin_lock_irqsave(hba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7952) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7953) hba->ufshcd_state = UFSHCD_STATE_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7954) else if (hba->ufshcd_state == UFSHCD_STATE_RESET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7955) hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7956) spin_unlock_irqrestore(hba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7958) trace_ufshcd_init(dev_name(hba->dev), ret,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7959) ktime_to_us(ktime_sub(ktime_get(), start)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7960) hba->curr_dev_pwr_mode, hba->uic_link_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7961) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7962) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7964) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7965) * ufshcd_async_scan - asynchronous execution for probing hba
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7966) * @data: data pointer to pass to this function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7967) * @cookie: cookie data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7968) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7969) static void ufshcd_async_scan(void *data, async_cookie_t cookie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7970) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7971) struct ufs_hba *hba = (struct ufs_hba *)data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7972) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7974) down(&hba->host_sem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7975) /* Initialize hba, detect and initialize UFS device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7976) ret = ufshcd_probe_hba(hba, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7977) up(&hba->host_sem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7978) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7979) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7981) /* Probe and add UFS logical units */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7982) ret = ufshcd_add_lus(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7983) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7984) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7985) * If we failed to initialize the device or the device is not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7986) * present, turn off the power/clocks etc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7987) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7988) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7989) pm_runtime_put_sync(hba->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7990) ufshcd_hba_exit(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7991) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7992) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7994) static const struct attribute_group *ufshcd_driver_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7995) &ufs_sysfs_unit_descriptor_group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7996) &ufs_sysfs_lun_attributes_group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7997) #ifdef CONFIG_SCSI_UFS_HPB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7998) &ufs_sysfs_hpb_stat_group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7999) &ufs_sysfs_hpb_param_group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8000) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8001) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8002) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8004) static struct ufs_hba_variant_params ufs_hba_vps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8005) .hba_enable_delay_us = 1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8006) .wb_flush_threshold = UFS_WB_BUF_REMAIN_PERCENT(40),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8007) .devfreq_profile.polling_ms = 100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8008) .devfreq_profile.target = ufshcd_devfreq_target,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8009) .devfreq_profile.get_dev_status = ufshcd_devfreq_get_dev_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8010) .ondemand_data.upthreshold = 70,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8011) .ondemand_data.downdifferential = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8012) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8014) static struct scsi_host_template ufshcd_driver_template = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8015) .module = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8016) .name = UFSHCD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8017) .proc_name = UFSHCD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8018) .queuecommand = ufshcd_queuecommand,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8019) .slave_alloc = ufshcd_slave_alloc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8020) .slave_configure = ufshcd_slave_configure,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8021) .slave_destroy = ufshcd_slave_destroy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8022) .change_queue_depth = ufshcd_change_queue_depth,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8023) .eh_abort_handler = ufshcd_abort,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8024) .eh_device_reset_handler = ufshcd_eh_device_reset_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8025) .eh_host_reset_handler = ufshcd_eh_host_reset_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8026) .this_id = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8027) .sg_tablesize = SG_ALL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8028) .cmd_per_lun = UFSHCD_CMD_PER_LUN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8029) .can_queue = UFSHCD_CAN_QUEUE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8030) .max_segment_size = PRDT_DATA_BYTE_COUNT_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8031) .max_host_blocked = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8032) .track_queue_depth = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8033) .sdev_groups = ufshcd_driver_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8034) .dma_boundary = PAGE_SIZE - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8035) .rpm_autosuspend_delay = RPM_AUTOSUSPEND_DELAY_MS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8036) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8038) static int ufshcd_config_vreg_load(struct device *dev, struct ufs_vreg *vreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8039) int ua)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8040) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8041) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8043) if (!vreg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8044) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8046) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8047) * "set_load" operation shall be required on those regulators
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8048) * which specifically configured current limitation. Otherwise
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8049) * zero max_uA may cause unexpected behavior when regulator is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8050) * enabled or set as high power mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8051) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8052) if (!vreg->max_uA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8053) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8055) ret = regulator_set_load(vreg->reg, ua);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8056) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8057) dev_err(dev, "%s: %s set load (ua=%d) failed, err=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8058) __func__, vreg->name, ua, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8059) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8061) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8062) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8064) static inline int ufshcd_config_vreg_lpm(struct ufs_hba *hba,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8065) struct ufs_vreg *vreg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8066) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8067) return ufshcd_config_vreg_load(hba->dev, vreg, UFS_VREG_LPM_LOAD_UA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8068) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8070) static inline int ufshcd_config_vreg_hpm(struct ufs_hba *hba,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8071) struct ufs_vreg *vreg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8072) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8073) if (!vreg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8074) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8076) return ufshcd_config_vreg_load(hba->dev, vreg, vreg->max_uA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8077) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8079) static int ufshcd_config_vreg(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8080) struct ufs_vreg *vreg, bool on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8081) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8082) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8083) struct regulator *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8084) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8085) int min_uV, uA_load;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8087) BUG_ON(!vreg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8089) reg = vreg->reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8090) name = vreg->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8092) if (regulator_count_voltages(reg) > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8093) uA_load = on ? vreg->max_uA : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8094) ret = ufshcd_config_vreg_load(dev, vreg, uA_load);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8095) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8096) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8098) if (vreg->min_uV && vreg->max_uV) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8099) min_uV = on ? vreg->min_uV : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8100) ret = regulator_set_voltage(reg, min_uV, vreg->max_uV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8101) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8102) dev_err(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8103) "%s: %s set voltage failed, err=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8104) __func__, name, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8107) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8108) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8111) static int ufshcd_enable_vreg(struct device *dev, struct ufs_vreg *vreg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8113) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8115) if (!vreg || vreg->enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8116) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8118) ret = ufshcd_config_vreg(dev, vreg, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8119) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8120) ret = regulator_enable(vreg->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8122) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8123) vreg->enabled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8124) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8125) dev_err(dev, "%s: %s enable failed, err=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8126) __func__, vreg->name, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8127) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8128) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8131) static int ufshcd_disable_vreg(struct device *dev, struct ufs_vreg *vreg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8133) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8135) if (!vreg || !vreg->enabled || vreg->always_on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8136) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8138) ret = regulator_disable(vreg->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8140) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8141) /* ignore errors on applying disable config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8142) ufshcd_config_vreg(dev, vreg, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8143) vreg->enabled = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8144) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8145) dev_err(dev, "%s: %s disable failed, err=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8146) __func__, vreg->name, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8148) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8149) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8152) static int ufshcd_setup_vreg(struct ufs_hba *hba, bool on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8153) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8154) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8155) struct device *dev = hba->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8156) struct ufs_vreg_info *info = &hba->vreg_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8158) ret = ufshcd_toggle_vreg(dev, info->vcc, on);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8159) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8160) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8162) ret = ufshcd_toggle_vreg(dev, info->vccq, on);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8163) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8164) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8166) ret = ufshcd_toggle_vreg(dev, info->vccq2, on);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8168) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8169) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8170) ufshcd_toggle_vreg(dev, info->vccq2, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8171) ufshcd_toggle_vreg(dev, info->vccq, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8172) ufshcd_toggle_vreg(dev, info->vcc, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8174) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8177) static int ufshcd_setup_hba_vreg(struct ufs_hba *hba, bool on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8178) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8179) struct ufs_vreg_info *info = &hba->vreg_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8181) return ufshcd_toggle_vreg(hba->dev, info->vdd_hba, on);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8184) static int ufshcd_get_vreg(struct device *dev, struct ufs_vreg *vreg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8185) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8186) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8188) if (!vreg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8189) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8191) vreg->reg = devm_regulator_get(dev, vreg->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8192) if (IS_ERR(vreg->reg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8193) ret = PTR_ERR(vreg->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8194) dev_err(dev, "%s: %s get failed, err=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8195) __func__, vreg->name, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8197) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8198) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8201) static int ufshcd_init_vreg(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8202) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8203) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8204) struct device *dev = hba->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8205) struct ufs_vreg_info *info = &hba->vreg_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8207) ret = ufshcd_get_vreg(dev, info->vcc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8208) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8209) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8211) ret = ufshcd_get_vreg(dev, info->vccq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8212) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8213) ret = ufshcd_get_vreg(dev, info->vccq2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8214) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8215) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8218) static int ufshcd_init_hba_vreg(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8219) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8220) struct ufs_vreg_info *info = &hba->vreg_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8222) if (info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8223) return ufshcd_get_vreg(hba->dev, info->vdd_hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8225) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8228) static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8229) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8230) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8231) struct ufs_clk_info *clki;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8232) struct list_head *head = &hba->clk_list_head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8233) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8234) ktime_t start = ktime_get();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8235) bool clk_state_changed = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8237) if (list_empty(head))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8238) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8240) ret = ufshcd_vops_setup_clocks(hba, on, PRE_CHANGE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8241) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8242) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8244) list_for_each_entry(clki, head, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8245) if (!IS_ERR_OR_NULL(clki->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8246) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8247) * Don't disable clocks which are needed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8248) * to keep the link active.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8249) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8250) if (ufshcd_is_link_active(hba) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8251) clki->keep_link_active)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8252) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8254) clk_state_changed = on ^ clki->enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8255) if (on && !clki->enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8256) ret = clk_prepare_enable(clki->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8257) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8258) dev_err(hba->dev, "%s: %s prepare enable failed, %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8259) __func__, clki->name, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8260) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8262) } else if (!on && clki->enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8263) clk_disable_unprepare(clki->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8265) clki->enabled = on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8266) dev_dbg(hba->dev, "%s: clk: %s %sabled\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8267) clki->name, on ? "en" : "dis");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8271) ret = ufshcd_vops_setup_clocks(hba, on, POST_CHANGE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8272) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8273) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8275) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8276) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8277) list_for_each_entry(clki, head, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8278) if (!IS_ERR_OR_NULL(clki->clk) && clki->enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8279) clk_disable_unprepare(clki->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8281) } else if (!ret && on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8282) spin_lock_irqsave(hba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8283) hba->clk_gating.state = CLKS_ON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8284) trace_ufshcd_clk_gating(dev_name(hba->dev),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8285) hba->clk_gating.state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8286) spin_unlock_irqrestore(hba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8289) if (clk_state_changed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8290) trace_ufshcd_profile_clk_gating(dev_name(hba->dev),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8291) (on ? "on" : "off"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8292) ktime_to_us(ktime_sub(ktime_get(), start)), ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8293) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8296) static int ufshcd_init_clocks(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8297) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8298) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8299) struct ufs_clk_info *clki;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8300) struct device *dev = hba->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8301) struct list_head *head = &hba->clk_list_head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8303) if (list_empty(head))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8304) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8306) list_for_each_entry(clki, head, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8307) if (!clki->name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8308) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8310) clki->clk = devm_clk_get(dev, clki->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8311) if (IS_ERR(clki->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8312) ret = PTR_ERR(clki->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8313) dev_err(dev, "%s: %s clk get failed, %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8314) __func__, clki->name, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8315) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8318) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8319) * Parse device ref clk freq as per device tree "ref_clk".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8320) * Default dev_ref_clk_freq is set to REF_CLK_FREQ_INVAL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8321) * in ufshcd_alloc_host().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8322) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8323) if (!strcmp(clki->name, "ref_clk"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8324) ufshcd_parse_dev_ref_clk_freq(hba, clki->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8326) if (clki->max_freq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8327) ret = clk_set_rate(clki->clk, clki->max_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8328) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8329) dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8330) __func__, clki->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8331) clki->max_freq, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8332) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8334) clki->curr_freq = clki->max_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8336) dev_dbg(dev, "%s: clk: %s, rate: %lu\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8337) clki->name, clk_get_rate(clki->clk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8339) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8340) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8343) static int ufshcd_variant_hba_init(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8344) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8345) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8347) if (!hba->vops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8348) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8350) err = ufshcd_vops_init(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8351) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8352) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8354) err = ufshcd_vops_setup_regulators(hba, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8355) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8356) ufshcd_vops_exit(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8357) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8358) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8359) dev_err(hba->dev, "%s: variant %s init failed err %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8360) __func__, ufshcd_get_var_name(hba), err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8361) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8362) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8364) static void ufshcd_variant_hba_exit(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8365) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8366) if (!hba->vops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8367) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8369) ufshcd_vops_setup_regulators(hba, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8371) ufshcd_vops_exit(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8374) static int ufshcd_hba_init(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8375) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8376) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8378) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8379) * Handle host controller power separately from the UFS device power
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8380) * rails as it will help controlling the UFS host controller power
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8381) * collapse easily which is different than UFS device power collapse.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8382) * Also, enable the host controller power before we go ahead with rest
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8383) * of the initialization here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8384) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8385) err = ufshcd_init_hba_vreg(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8386) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8387) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8389) err = ufshcd_setup_hba_vreg(hba, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8390) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8391) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8393) err = ufshcd_init_clocks(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8394) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8395) goto out_disable_hba_vreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8397) err = ufshcd_setup_clocks(hba, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8398) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8399) goto out_disable_hba_vreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8401) err = ufshcd_init_vreg(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8402) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8403) goto out_disable_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8405) err = ufshcd_setup_vreg(hba, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8406) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8407) goto out_disable_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8409) err = ufshcd_variant_hba_init(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8410) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8411) goto out_disable_vreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8413) ufs_debugfs_hba_init(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8415) hba->is_powered = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8416) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8418) out_disable_vreg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8419) ufshcd_setup_vreg(hba, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8420) out_disable_clks:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8421) ufshcd_setup_clocks(hba, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8422) out_disable_hba_vreg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8423) ufshcd_setup_hba_vreg(hba, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8424) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8425) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8428) static void ufshcd_hba_exit(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8429) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8430) if (hba->is_powered) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8431) ufshcd_exit_clk_scaling(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8432) ufshcd_exit_clk_gating(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8433) if (hba->eh_wq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8434) destroy_workqueue(hba->eh_wq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8435) ufs_debugfs_hba_exit(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8436) ufshcd_variant_hba_exit(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8437) ufshcd_setup_vreg(hba, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8438) ufshcd_setup_clocks(hba, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8439) ufshcd_setup_hba_vreg(hba, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8440) hba->is_powered = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8441) ufs_put_device_desc(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8445) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8446) * ufshcd_set_dev_pwr_mode - sends START STOP UNIT command to set device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8447) * power mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8448) * @hba: per adapter instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8449) * @pwr_mode: device power mode to set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8450) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8451) * Returns 0 if requested power mode is set successfully
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8452) * Returns non-zero if failed to set the requested power mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8453) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8454) static int ufshcd_set_dev_pwr_mode(struct ufs_hba *hba,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8455) enum ufs_dev_pwr_mode pwr_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8456) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8457) unsigned char cmd[6] = { START_STOP };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8458) struct scsi_sense_hdr sshdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8459) struct scsi_device *sdp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8460) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8461) int ret, retries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8463) spin_lock_irqsave(hba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8464) sdp = hba->sdev_ufs_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8465) if (sdp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8466) ret = scsi_device_get(sdp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8467) if (!ret && !scsi_device_online(sdp)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8468) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8469) scsi_device_put(sdp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8470) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8471) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8472) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8473) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8474) spin_unlock_irqrestore(hba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8476) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8477) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8479) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8480) * If scsi commands fail, the scsi mid-layer schedules scsi error-
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8481) * handling, which would wait for host to be resumed. Since we know
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8482) * we are functional while we are here, skip host resume in error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8483) * handling context.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8484) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8485) hba->host->eh_noresume = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8487) cmd[4] = pwr_mode << 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8489) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8490) * Current function would be generally called from the power management
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8491) * callbacks hence set the RQF_PM flag so that it doesn't resume the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8492) * already suspended childs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8493) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8494) for (retries = 3; retries > 0; --retries) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8495) ret = scsi_execute(sdp, cmd, DMA_NONE, NULL, 0, NULL, &sshdr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8496) START_STOP_TIMEOUT, 0, 0, RQF_PM, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8497) if (!scsi_status_is_check_condition(ret) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8498) !scsi_sense_valid(&sshdr) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8499) sshdr.sense_key != UNIT_ATTENTION)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8500) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8501) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8502) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8503) sdev_printk(KERN_WARNING, sdp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8504) "START_STOP failed for power mode: %d, result %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8505) pwr_mode, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8506) if (driver_byte(ret) == DRIVER_SENSE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8507) scsi_print_sense_hdr(sdp, NULL, &sshdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8508) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8510) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8511) hba->curr_dev_pwr_mode = pwr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8513) scsi_device_put(sdp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8514) hba->host->eh_noresume = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8515) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8516) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8518) static int ufshcd_link_state_transition(struct ufs_hba *hba,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8519) enum uic_link_state req_link_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8520) int check_for_bkops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8521) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8522) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8524) if (req_link_state == hba->uic_link_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8525) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8527) if (req_link_state == UIC_LINK_HIBERN8_STATE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8528) ret = ufshcd_uic_hibern8_enter(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8529) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8530) ufshcd_set_link_hibern8(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8531) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8532) dev_err(hba->dev, "%s: hibern8 enter failed %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8533) __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8534) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8535) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8536) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8537) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8538) * If autobkops is enabled, link can't be turned off because
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8539) * turning off the link would also turn off the device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8540) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8541) else if ((req_link_state == UIC_LINK_OFF_STATE) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8542) (!check_for_bkops || !hba->auto_bkops_enabled)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8543) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8544) * Let's make sure that link is in low power mode, we are doing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8545) * this currently by putting the link in Hibern8. Otherway to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8546) * put the link in low power mode is to send the DME end point
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8547) * to device and then send the DME reset command to local
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8548) * unipro. But putting the link in hibern8 is much faster.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8549) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8550) ret = ufshcd_uic_hibern8_enter(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8551) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8552) dev_err(hba->dev, "%s: hibern8 enter failed %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8553) __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8554) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8555) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8556) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8557) * Change controller state to "reset state" which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8558) * should also put the link in off/reset state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8559) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8560) ufshcd_hba_stop(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8561) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8562) * TODO: Check if we need any delay to make sure that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8563) * controller is reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8564) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8565) ufshcd_set_link_off(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8566) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8568) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8569) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8570) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8572) static void ufshcd_vreg_set_lpm(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8573) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8574) bool vcc_off = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8576) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8577) * It seems some UFS devices may keep drawing more than sleep current
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8578) * (atleast for 500us) from UFS rails (especially from VCCQ rail).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8579) * To avoid this situation, add 2ms delay before putting these UFS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8580) * rails in LPM mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8581) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8582) if (!ufshcd_is_link_active(hba) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8583) hba->dev_quirks & UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8584) usleep_range(2000, 2100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8586) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8587) * If UFS device is either in UFS_Sleep turn off VCC rail to save some
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8588) * power.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8589) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8590) * If UFS device and link is in OFF state, all power supplies (VCC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8591) * VCCQ, VCCQ2) can be turned off if power on write protect is not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8592) * required. If UFS link is inactive (Hibern8 or OFF state) and device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8593) * is in sleep state, put VCCQ & VCCQ2 rails in LPM mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8594) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8595) * Ignore the error returned by ufshcd_toggle_vreg() as device is anyway
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8596) * in low power state which would save some power.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8597) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8598) * If Write Booster is enabled and the device needs to flush the WB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8599) * buffer OR if bkops status is urgent for WB, keep Vcc on.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8600) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8601) if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8602) !hba->dev_info.is_lu_power_on_wp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8603) ufshcd_setup_vreg(hba, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8604) vcc_off = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8605) } else if (!ufshcd_is_ufs_dev_active(hba)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8606) ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8607) vcc_off = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8608) if (ufshcd_is_link_hibern8(hba) || ufshcd_is_link_off(hba)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8609) ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8610) ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8611) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8612) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8614) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8615) * Some UFS devices require delay after VCC power rail is turned-off.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8616) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8617) if (vcc_off && hba->vreg_info.vcc &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8618) hba->dev_quirks & UFS_DEVICE_QUIRK_DELAY_AFTER_LPM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8619) usleep_range(5000, 5100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8620) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8622) static int ufshcd_vreg_set_hpm(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8623) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8624) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8626) if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8627) !hba->dev_info.is_lu_power_on_wp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8628) ret = ufshcd_setup_vreg(hba, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8629) } else if (!ufshcd_is_ufs_dev_active(hba)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8630) if (!ufshcd_is_link_active(hba)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8631) ret = ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8632) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8633) goto vcc_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8634) ret = ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8635) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8636) goto vccq_lpm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8637) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8638) ret = ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8639) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8640) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8642) vccq_lpm:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8643) ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8644) vcc_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8645) ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8646) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8647) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8648) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8650) static void ufshcd_hba_vreg_set_lpm(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8651) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8652) if (ufshcd_is_link_off(hba) || ufshcd_can_aggressive_pc(hba))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8653) ufshcd_setup_hba_vreg(hba, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8654) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8656) static void ufshcd_hba_vreg_set_hpm(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8657) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8658) if (ufshcd_is_link_off(hba) || ufshcd_can_aggressive_pc(hba))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8659) ufshcd_setup_hba_vreg(hba, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8660) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8662) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8663) * ufshcd_suspend - helper function for suspend operations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8664) * @hba: per adapter instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8665) * @pm_op: desired low power operation type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8666) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8667) * This function will try to put the UFS device and link into low power
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8668) * mode based on the "rpm_lvl" (Runtime PM level) or "spm_lvl"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8669) * (System PM level).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8670) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8671) * If this function is called during shutdown, it will make sure that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8672) * both UFS device and UFS link is powered off.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8673) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8674) * NOTE: UFS device & link must be active before we enter in this function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8675) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8676) * Returns 0 for success and non-zero for failure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8677) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8678) static int ufshcd_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8679) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8680) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8681) enum ufs_pm_level pm_lvl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8682) enum ufs_dev_pwr_mode req_dev_pwr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8683) enum uic_link_state req_link_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8685) hba->pm_op_in_progress = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8686) if (!ufshcd_is_shutdown_pm(pm_op)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8687) pm_lvl = ufshcd_is_runtime_pm(pm_op) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8688) hba->rpm_lvl : hba->spm_lvl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8689) req_dev_pwr_mode = ufs_get_pm_lvl_to_dev_pwr_mode(pm_lvl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8690) req_link_state = ufs_get_pm_lvl_to_link_pwr_state(pm_lvl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8691) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8692) req_dev_pwr_mode = UFS_POWERDOWN_PWR_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8693) req_link_state = UIC_LINK_OFF_STATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8694) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8696) ufshpb_suspend(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8698) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8699) * If we can't transition into any of the low power modes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8700) * just gate the clocks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8701) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8702) ufshcd_hold(hba, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8703) hba->clk_gating.is_suspended = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8705) if (ufshcd_is_clkscaling_supported(hba))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8706) ufshcd_clk_scaling_suspend(hba, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8708) if (req_dev_pwr_mode == UFS_ACTIVE_PWR_MODE &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8709) req_link_state == UIC_LINK_ACTIVE_STATE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8710) goto disable_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8711) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8713) if ((req_dev_pwr_mode == hba->curr_dev_pwr_mode) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8714) (req_link_state == hba->uic_link_state))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8715) goto enable_gating;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8717) /* UFS device & link must be active before we enter in this function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8718) if (!ufshcd_is_ufs_dev_active(hba) || !ufshcd_is_link_active(hba)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8719) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8720) goto enable_gating;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8721) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8723) if (ufshcd_is_runtime_pm(pm_op)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8724) if (ufshcd_can_autobkops_during_suspend(hba)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8725) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8726) * The device is idle with no requests in the queue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8727) * allow background operations if bkops status shows
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8728) * that performance might be impacted.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8729) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8730) ret = ufshcd_urgent_bkops(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8731) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8732) goto enable_gating;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8733) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8734) /* make sure that auto bkops is disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8735) ufshcd_disable_auto_bkops(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8736) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8737) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8738) * If device needs to do BKOP or WB buffer flush during
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8739) * Hibern8, keep device power mode as "active power mode"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8740) * and VCC supply.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8741) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8742) hba->dev_info.b_rpm_dev_flush_capable =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8743) hba->auto_bkops_enabled ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8744) (((req_link_state == UIC_LINK_HIBERN8_STATE) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8745) ((req_link_state == UIC_LINK_ACTIVE_STATE) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8746) ufshcd_is_auto_hibern8_enabled(hba))) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8747) ufshcd_wb_need_flush(hba));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8748) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8750) flush_work(&hba->eeh_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8752) if (req_dev_pwr_mode != hba->curr_dev_pwr_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8753) if ((ufshcd_is_runtime_pm(pm_op) && !hba->auto_bkops_enabled) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8754) !ufshcd_is_runtime_pm(pm_op)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8755) /* ensure that bkops is disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8756) ufshcd_disable_auto_bkops(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8757) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8759) if (!hba->dev_info.b_rpm_dev_flush_capable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8760) ret = ufshcd_set_dev_pwr_mode(hba, req_dev_pwr_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8761) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8762) goto enable_gating;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8763) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8764) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8766) ret = ufshcd_link_state_transition(hba, req_link_state, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8767) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8768) goto set_dev_active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8770) disable_clks:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8771) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8772) * Call vendor specific suspend callback. As these callbacks may access
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8773) * vendor specific host controller register space call them before the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8774) * host clocks are ON.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8775) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8776) ret = ufshcd_vops_suspend(hba, pm_op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8777) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8778) goto set_link_active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8779) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8780) * Disable the host irq as host controller as there won't be any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8781) * host controller transaction expected till resume.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8782) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8783) ufshcd_disable_irq(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8785) ufshcd_setup_clocks(hba, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8787) if (ufshcd_is_clkgating_allowed(hba)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8788) hba->clk_gating.state = CLKS_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8789) trace_ufshcd_clk_gating(dev_name(hba->dev),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8790) hba->clk_gating.state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8791) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8793) ufshcd_vreg_set_lpm(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8795) /* Put the host controller in low power mode if possible */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8796) ufshcd_hba_vreg_set_lpm(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8797) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8799) set_link_active:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8800) ufshcd_vreg_set_hpm(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8801) if (ufshcd_is_link_hibern8(hba) && !ufshcd_uic_hibern8_exit(hba))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8802) ufshcd_set_link_active(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8803) else if (ufshcd_is_link_off(hba))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8804) ufshcd_host_reset_and_restore(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8805) set_dev_active:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8806) if (!ufshcd_set_dev_pwr_mode(hba, UFS_ACTIVE_PWR_MODE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8807) ufshcd_disable_auto_bkops(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8808) enable_gating:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8809) if (ufshcd_is_clkscaling_supported(hba))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8810) ufshcd_clk_scaling_suspend(hba, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8812) hba->clk_gating.is_suspended = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8813) hba->dev_info.b_rpm_dev_flush_capable = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8814) ufshcd_release(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8815) ufshpb_resume(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8816) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8817) if (hba->dev_info.b_rpm_dev_flush_capable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8818) schedule_delayed_work(&hba->rpm_dev_flush_recheck_work,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8819) msecs_to_jiffies(RPM_DEV_FLUSH_RECHECK_WORK_DELAY_MS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8820) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8822) hba->pm_op_in_progress = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8824) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8825) ufshcd_update_evt_hist(hba, UFS_EVT_SUSPEND_ERR, (u32)ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8826) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8827) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8829) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8830) * ufshcd_resume - helper function for resume operations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8831) * @hba: per adapter instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8832) * @pm_op: runtime PM or system PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8833) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8834) * This function basically brings the UFS device, UniPro link and controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8835) * to active state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8836) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8837) * Returns 0 for success and non-zero for failure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8838) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8839) static int ufshcd_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8840) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8841) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8842) enum uic_link_state old_link_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8844) hba->pm_op_in_progress = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8845) old_link_state = hba->uic_link_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8847) ufshcd_hba_vreg_set_hpm(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8848) ret = ufshcd_vreg_set_hpm(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8849) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8850) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8852) /* Make sure clocks are enabled before accessing controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8853) ret = ufshcd_setup_clocks(hba, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8854) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8855) goto disable_vreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8857) /* enable the host irq as host controller would be active soon */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8858) ufshcd_enable_irq(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8860) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8861) * Call vendor specific resume callback. As these callbacks may access
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8862) * vendor specific host controller register space call them when the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8863) * host clocks are ON.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8864) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8865) ret = ufshcd_vops_resume(hba, pm_op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8866) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8867) goto disable_irq_and_vops_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8869) if (ufshcd_is_link_hibern8(hba)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8870) ret = ufshcd_uic_hibern8_exit(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8871) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8872) ufshcd_set_link_active(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8873) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8874) dev_err(hba->dev, "%s: hibern8 exit failed %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8875) __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8876) goto vendor_suspend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8877) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8878) } else if (ufshcd_is_link_off(hba)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8879) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8880) * A full initialization of the host and the device is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8881) * required since the link was put to off during suspend.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8882) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8883) ret = ufshcd_reset_and_restore(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8884) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8885) * ufshcd_reset_and_restore() should have already
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8886) * set the link state as active
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8887) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8888) if (ret || !ufshcd_is_link_active(hba))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8889) goto vendor_suspend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8890) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8892) if (!ufshcd_is_ufs_dev_active(hba)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8893) ret = ufshcd_set_dev_pwr_mode(hba, UFS_ACTIVE_PWR_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8894) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8895) goto set_old_link_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8896) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8898) if (ufshcd_keep_autobkops_enabled_except_suspend(hba))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8899) ufshcd_enable_auto_bkops(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8900) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8901) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8902) * If BKOPs operations are urgently needed at this moment then
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8903) * keep auto-bkops enabled or else disable it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8904) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8905) ufshcd_urgent_bkops(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8907) hba->clk_gating.is_suspended = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8909) if (ufshcd_is_clkscaling_supported(hba))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8910) ufshcd_clk_scaling_suspend(hba, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8912) /* Enable Auto-Hibernate if configured */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8913) ufshcd_auto_hibern8_enable(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8915) ufshpb_resume(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8917) if (hba->dev_info.b_rpm_dev_flush_capable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8918) hba->dev_info.b_rpm_dev_flush_capable = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8919) cancel_delayed_work(&hba->rpm_dev_flush_recheck_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8920) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8922) /* Schedule clock gating in case of no access to UFS device yet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8923) ufshcd_release(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8925) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8927) set_old_link_state:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8928) ufshcd_link_state_transition(hba, old_link_state, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8929) vendor_suspend:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8930) ufshcd_vops_suspend(hba, pm_op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8931) disable_irq_and_vops_clks:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8932) ufshcd_disable_irq(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8933) ufshcd_setup_clocks(hba, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8934) if (ufshcd_is_clkgating_allowed(hba)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8935) hba->clk_gating.state = CLKS_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8936) trace_ufshcd_clk_gating(dev_name(hba->dev),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8937) hba->clk_gating.state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8938) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8939) disable_vreg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8940) ufshcd_vreg_set_lpm(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8941) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8942) hba->pm_op_in_progress = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8943) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8944) ufshcd_update_evt_hist(hba, UFS_EVT_RESUME_ERR, (u32)ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8945) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8946) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8948) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8949) * ufshcd_system_suspend - system suspend routine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8950) * @hba: per adapter instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8951) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8952) * Check the description of ufshcd_suspend() function for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8953) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8954) * Returns 0 for success and non-zero for failure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8955) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8956) int ufshcd_system_suspend(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8957) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8958) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8959) ktime_t start = ktime_get();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8961) down(&hba->host_sem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8963) if (!hba->is_powered)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8964) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8966) cancel_delayed_work_sync(&hba->rpm_dev_flush_recheck_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8968) if ((ufs_get_pm_lvl_to_dev_pwr_mode(hba->spm_lvl) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8969) hba->curr_dev_pwr_mode) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8970) (ufs_get_pm_lvl_to_link_pwr_state(hba->spm_lvl) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8971) hba->uic_link_state) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8972) pm_runtime_suspended(hba->dev) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8973) !hba->dev_info.b_rpm_dev_flush_capable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8974) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8976) if (pm_runtime_suspended(hba->dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8977) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8978) * UFS device and/or UFS link low power states during runtime
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8979) * suspend seems to be different than what is expected during
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8980) * system suspend. Hence runtime resume the devic & link and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8981) * let the system suspend low power states to take effect.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8982) * TODO: If resume takes longer time, we might have optimize
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8983) * it in future by not resuming everything if possible.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8984) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8985) ret = ufshcd_runtime_resume(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8986) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8987) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8988) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8990) ret = ufshcd_suspend(hba, UFS_SYSTEM_PM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8991) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8992) trace_ufshcd_system_suspend(dev_name(hba->dev), ret,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8993) ktime_to_us(ktime_sub(ktime_get(), start)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8994) hba->curr_dev_pwr_mode, hba->uic_link_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8995) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8996) hba->is_sys_suspended = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8997) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8998) up(&hba->host_sem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8999) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9000) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9001) EXPORT_SYMBOL(ufshcd_system_suspend);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9003) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9004) * ufshcd_system_resume - system resume routine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9005) * @hba: per adapter instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9006) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9007) * Returns 0 for success and non-zero for failure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9008) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9010) int ufshcd_system_resume(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9011) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9012) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9013) ktime_t start = ktime_get();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9015) if (!hba->is_powered || pm_runtime_suspended(hba->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9016) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9017) * Let the runtime resume take care of resuming
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9018) * if runtime suspended.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9019) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9020) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9021) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9022) ret = ufshcd_resume(hba, UFS_SYSTEM_PM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9023) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9024) trace_ufshcd_system_resume(dev_name(hba->dev), ret,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9025) ktime_to_us(ktime_sub(ktime_get(), start)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9026) hba->curr_dev_pwr_mode, hba->uic_link_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9027) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9028) hba->is_sys_suspended = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9029) up(&hba->host_sem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9030) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9031) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9032) EXPORT_SYMBOL(ufshcd_system_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9034) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9035) * ufshcd_runtime_suspend - runtime suspend routine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9036) * @hba: per adapter instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9037) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9038) * Check the description of ufshcd_suspend() function for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9039) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9040) * Returns 0 for success and non-zero for failure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9041) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9042) int ufshcd_runtime_suspend(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9043) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9044) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9045) ktime_t start = ktime_get();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9047) if (!hba->is_powered)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9048) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9049) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9050) ret = ufshcd_suspend(hba, UFS_RUNTIME_PM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9051) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9052) trace_ufshcd_runtime_suspend(dev_name(hba->dev), ret,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9053) ktime_to_us(ktime_sub(ktime_get(), start)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9054) hba->curr_dev_pwr_mode, hba->uic_link_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9055) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9056) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9057) EXPORT_SYMBOL(ufshcd_runtime_suspend);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9059) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9060) * ufshcd_runtime_resume - runtime resume routine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9061) * @hba: per adapter instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9062) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9063) * This function basically brings the UFS device, UniPro link and controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9064) * to active state. Following operations are done in this function:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9065) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9066) * 1. Turn on all the controller related clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9067) * 2. Bring the UniPro link out of Hibernate state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9068) * 3. If UFS device is in sleep state, turn ON VCC rail and bring the UFS device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9069) * to active state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9070) * 4. If auto-bkops is enabled on the device, disable it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9071) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9072) * So following would be the possible power state after this function return
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9073) * successfully:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9074) * S1: UFS device in Active state with VCC rail ON
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9075) * UniPro link in Active state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9076) * All the UFS/UniPro controller clocks are ON
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9077) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9078) * Returns 0 for success and non-zero for failure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9079) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9080) int ufshcd_runtime_resume(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9081) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9082) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9083) ktime_t start = ktime_get();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9085) if (!hba->is_powered)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9086) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9087) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9088) ret = ufshcd_resume(hba, UFS_RUNTIME_PM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9089) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9090) trace_ufshcd_runtime_resume(dev_name(hba->dev), ret,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9091) ktime_to_us(ktime_sub(ktime_get(), start)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9092) hba->curr_dev_pwr_mode, hba->uic_link_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9093) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9094) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9095) EXPORT_SYMBOL(ufshcd_runtime_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9097) int ufshcd_runtime_idle(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9098) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9099) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9101) EXPORT_SYMBOL(ufshcd_runtime_idle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9103) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9104) * ufshcd_shutdown - shutdown routine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9105) * @hba: per adapter instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9106) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9107) * This function would power off both UFS device and UFS link.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9108) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9109) * Returns 0 always to allow force shutdown even in case of errors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9110) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9111) int ufshcd_shutdown(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9113) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9115) down(&hba->host_sem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9116) hba->shutting_down = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9117) up(&hba->host_sem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9119) if (!hba->is_powered)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9120) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9122) if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9123) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9125) pm_runtime_get_sync(hba->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9127) ret = ufshcd_suspend(hba, UFS_SHUTDOWN_PM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9128) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9129) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9130) dev_err(hba->dev, "%s failed, err %d\n", __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9131) hba->is_powered = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9132) /* allow force shutdown even in case of errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9133) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9135) EXPORT_SYMBOL(ufshcd_shutdown);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9137) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9138) * ufshcd_remove - de-allocate SCSI host and host memory space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9139) * data structure memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9140) * @hba: per adapter instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9141) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9142) void ufshcd_remove(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9144) ufs_bsg_remove(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9145) ufshpb_remove(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9146) ufs_sysfs_remove_nodes(hba->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9147) blk_cleanup_queue(hba->tmf_queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9148) blk_mq_free_tag_set(&hba->tmf_tag_set);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9149) blk_cleanup_queue(hba->cmd_queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9150) scsi_remove_host(hba->host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9151) /* disable interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9152) ufshcd_disable_intr(hba, hba->intr_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9153) ufshcd_hba_stop(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9154) ufshcd_hba_exit(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9156) EXPORT_SYMBOL_GPL(ufshcd_remove);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9158) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9159) * ufshcd_dealloc_host - deallocate Host Bus Adapter (HBA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9160) * @hba: pointer to Host Bus Adapter (HBA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9161) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9162) void ufshcd_dealloc_host(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9163) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9164) scsi_host_put(hba->host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9166) EXPORT_SYMBOL_GPL(ufshcd_dealloc_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9168) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9169) * ufshcd_set_dma_mask - Set dma mask based on the controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9170) * addressing capability
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9171) * @hba: per adapter instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9172) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9173) * Returns 0 for success, non-zero for failure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9174) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9175) static int ufshcd_set_dma_mask(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9176) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9177) if (hba->capabilities & MASK_64_ADDRESSING_SUPPORT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9178) if (!dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(64)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9179) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9181) return dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9184) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9185) * ufshcd_alloc_host - allocate Host Bus Adapter (HBA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9186) * @dev: pointer to device handle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9187) * @hba_handle: driver private handle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9188) * Returns 0 on success, non-zero value on failure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9189) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9190) int ufshcd_alloc_host(struct device *dev, struct ufs_hba **hba_handle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9191) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9192) struct Scsi_Host *host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9193) struct ufs_hba *hba;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9194) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9196) if (!dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9197) dev_err(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9198) "Invalid memory reference for dev is NULL\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9199) err = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9200) goto out_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9203) host = scsi_host_alloc(&ufshcd_driver_template,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9204) sizeof(struct ufs_hba_add_info));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9205) if (!host) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9206) dev_err(dev, "scsi_host_alloc failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9207) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9208) goto out_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9210) hba = shost_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9211) hba->host = host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9212) hba->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9213) *hba_handle = hba;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9214) hba->dev_ref_clk_freq = REF_CLK_FREQ_INVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9215) hba->sg_entry_size = sizeof(struct ufshcd_sg_entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9217) INIT_LIST_HEAD(&hba->clk_list_head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9219) out_error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9220) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9222) EXPORT_SYMBOL(ufshcd_alloc_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9224) /* This function exists because blk_mq_alloc_tag_set() requires this. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9225) static blk_status_t ufshcd_queue_tmf(struct blk_mq_hw_ctx *hctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9226) const struct blk_mq_queue_data *qd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9227) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9228) WARN_ON_ONCE(true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9229) return BLK_STS_NOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9232) static const struct blk_mq_ops ufshcd_tmf_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9233) .queue_rq = ufshcd_queue_tmf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9234) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9236) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9237) * ufshcd_init - Driver initialization routine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9238) * @hba: per-adapter instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9239) * @mmio_base: base register address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9240) * @irq: Interrupt line of device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9241) * Returns 0 on success, non-zero value on failure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9242) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9243) int ufshcd_init(struct ufs_hba *hba, void __iomem *mmio_base, unsigned int irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9244) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9245) struct request ***tmf_rqs = &ufs_hba_add_info(hba)->tmf_rqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9246) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9247) struct Scsi_Host *host = hba->host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9248) struct device *dev = hba->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9249) char eh_wq_name[sizeof("ufs_eh_wq_00")];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9251) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9252) * dev_set_drvdata() must be called before any callbacks are registered
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9253) * that use dev_get_drvdata() (frequency scaling, clock scaling, hwmon,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9254) * sysfs).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9255) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9256) dev_set_drvdata(dev, hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9258) if (!mmio_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9259) dev_err(hba->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9260) "Invalid memory reference for mmio_base is NULL\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9261) err = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9262) goto out_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9265) hba->mmio_base = mmio_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9266) hba->irq = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9267) hba->vps = &ufs_hba_vps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9269) err = ufshcd_hba_init(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9270) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9271) goto out_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9273) /* Read capabilities registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9274) err = ufshcd_hba_capabilities(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9275) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9276) goto out_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9278) /* Get UFS version supported by the controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9279) hba->ufs_version = ufshcd_get_ufs_version(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9281) if (hba->ufs_version < ufshci_version(1, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9282) dev_err(hba->dev, "invalid UFS version 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9283) hba->ufs_version);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9285) /* Get Interrupt bit mask per version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9286) hba->intr_mask = ufshcd_get_intr_mask(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9288) err = ufshcd_set_dma_mask(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9289) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9290) dev_err(hba->dev, "set dma mask failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9291) goto out_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9294) /* Allocate memory for host memory space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9295) err = ufshcd_memory_alloc(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9296) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9297) dev_err(hba->dev, "Memory allocation failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9298) goto out_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9301) /* Configure LRB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9302) ufshcd_host_memory_configure(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9304) host->can_queue = hba->nutrs - UFSHCD_NUM_RESERVED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9305) host->cmd_per_lun = hba->nutrs - UFSHCD_NUM_RESERVED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9306) host->max_id = UFSHCD_MAX_ID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9307) host->max_lun = UFS_MAX_LUNS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9308) host->max_channel = UFSHCD_MAX_CHANNEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9309) host->unique_id = host->host_no;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9310) host->max_cmd_len = UFS_CDB_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9312) hba->max_pwr_info.is_valid = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9314) /* Initialize work queues */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9315) snprintf(eh_wq_name, sizeof(eh_wq_name), "ufs_eh_wq_%d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9316) hba->host->host_no);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9317) hba->eh_wq = create_singlethread_workqueue(eh_wq_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9318) if (!hba->eh_wq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9319) dev_err(hba->dev, "%s: failed to create eh workqueue\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9320) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9321) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9322) goto out_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9324) INIT_WORK(&hba->eh_work, ufshcd_err_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9325) INIT_WORK(&hba->eeh_work, ufshcd_exception_event_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9327) sema_init(&hba->host_sem, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9329) /* Initialize UIC command mutex */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9330) mutex_init(&hba->uic_cmd_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9332) /* Initialize mutex for device management commands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9333) mutex_init(&hba->dev_cmd.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9335) init_rwsem(&hba->clk_scaling_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9337) ufshcd_init_clk_gating(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9339) ufshcd_init_clk_scaling(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9341) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9342) * In order to avoid any spurious interrupt immediately after
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9343) * registering UFS controller interrupt handler, clear any pending UFS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9344) * interrupt status and disable all the UFS interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9345) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9346) ufshcd_writel(hba, ufshcd_readl(hba, REG_INTERRUPT_STATUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9347) REG_INTERRUPT_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9348) ufshcd_writel(hba, 0, REG_INTERRUPT_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9349) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9350) * Make sure that UFS interrupts are disabled and any pending interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9351) * status is cleared before registering UFS interrupt handler.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9352) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9353) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9355) /* IRQ registration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9356) err = devm_request_irq(dev, irq, ufshcd_intr, IRQF_SHARED, UFSHCD, hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9357) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9358) dev_err(hba->dev, "request irq failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9359) goto out_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9360) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9361) hba->is_irq_enabled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9362) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9364) err = scsi_add_host(host, hba->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9365) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9366) dev_err(hba->dev, "scsi_add_host failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9367) goto out_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9370) hba->cmd_queue = blk_mq_init_queue(&hba->host->tag_set);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9371) if (IS_ERR(hba->cmd_queue)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9372) err = PTR_ERR(hba->cmd_queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9373) goto out_remove_scsi_host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9376) hba->tmf_tag_set = (struct blk_mq_tag_set) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9377) .nr_hw_queues = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9378) .queue_depth = hba->nutmrs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9379) .ops = &ufshcd_tmf_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9380) .flags = BLK_MQ_F_NO_SCHED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9381) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9382) err = blk_mq_alloc_tag_set(&hba->tmf_tag_set);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9383) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9384) goto free_cmd_queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9385) hba->tmf_queue = blk_mq_init_queue(&hba->tmf_tag_set);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9386) if (IS_ERR(hba->tmf_queue)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9387) err = PTR_ERR(hba->tmf_queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9388) goto free_tmf_tag_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9389) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9390) *tmf_rqs = devm_kcalloc(hba->dev, hba->nutmrs, sizeof(**tmf_rqs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9391) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9392) if (!*tmf_rqs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9393) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9394) goto free_tmf_queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9397) /* Reset the attached device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9398) ufshcd_vops_device_reset(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9400) ufshcd_init_crypto(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9402) /* Host controller enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9403) err = ufshcd_hba_enable(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9404) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9405) dev_err(hba->dev, "Host controller enable failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9406) ufshcd_print_evt_hist(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9407) ufshcd_print_host_state(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9408) goto free_tmf_queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9409) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9411) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9412) * Set the default power management level for runtime and system PM.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9413) * Default power saving mode is to keep UFS link in Hibern8 state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9414) * and UFS device in sleep state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9415) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9416) hba->rpm_lvl = ufs_get_desired_pm_lvl_for_dev_link_state(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9417) UFS_SLEEP_PWR_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9418) UIC_LINK_HIBERN8_STATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9419) hba->spm_lvl = ufs_get_desired_pm_lvl_for_dev_link_state(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9420) UFS_SLEEP_PWR_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9421) UIC_LINK_HIBERN8_STATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9423) INIT_DELAYED_WORK(&hba->rpm_dev_flush_recheck_work,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9424) ufshcd_rpm_dev_flush_recheck_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9426) /* Set the default auto-hiberate idle timer value to 150 ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9427) if (ufshcd_is_auto_hibern8_supported(hba) && !hba->ahit) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9428) hba->ahit = FIELD_PREP(UFSHCI_AHIBERN8_TIMER_MASK, 150) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9429) FIELD_PREP(UFSHCI_AHIBERN8_SCALE_MASK, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9432) /* Hold auto suspend until async scan completes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9433) pm_runtime_get_sync(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9434) atomic_set(&hba->scsi_block_reqs_cnt, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9435) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9436) * We are assuming that device wasn't put in sleep/power-down
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9437) * state exclusively during the boot stage before kernel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9438) * This assumption helps avoid doing link startup twice during
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9439) * ufshcd_probe_hba().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9440) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9441) ufshcd_set_ufs_dev_active(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9443) async_schedule(ufshcd_async_scan, hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9444) ufs_sysfs_add_nodes(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9446) device_enable_async_suspend(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9447) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9449) free_tmf_queue:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9450) blk_cleanup_queue(hba->tmf_queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9451) free_tmf_tag_set:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9452) blk_mq_free_tag_set(&hba->tmf_tag_set);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9453) free_cmd_queue:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9454) blk_cleanup_queue(hba->cmd_queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9455) out_remove_scsi_host:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9456) scsi_remove_host(hba->host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9457) out_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9458) hba->is_irq_enabled = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9459) ufshcd_hba_exit(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9460) out_error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9461) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9462) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9463) EXPORT_SYMBOL_GPL(ufshcd_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9465) static int __init ufshcd_core_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9466) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9467) ufs_debugfs_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9468) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9469) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9471) static void __exit ufshcd_core_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9472) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9473) ufs_debugfs_exit();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9474) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9476) module_init(ufshcd_core_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9477) module_exit(ufshcd_core_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9479) MODULE_AUTHOR("Santosh Yaragnavi <santosh.sy@samsung.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9480) MODULE_AUTHOR("Vinayak Holikatti <h.vinayak@samsung.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9481) MODULE_DESCRIPTION("Generic UFS host controller driver Core");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9482) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9483) MODULE_VERSION(UFSHCD_DRIVER_VERSION);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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