^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /* Copyright (c) 2015, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #ifndef UFSHCD_PLTFRM_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #define UFSHCD_PLTFRM_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include "ufshcd.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define UFS_PWM_MODE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define UFS_HS_MODE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) struct ufs_dev_params {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) u32 pwm_rx_gear; /* pwm rx gear to work in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) u32 pwm_tx_gear; /* pwm tx gear to work in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) u32 hs_rx_gear; /* hs rx gear to work in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) u32 hs_tx_gear; /* hs tx gear to work in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) u32 rx_lanes; /* number of rx lanes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) u32 tx_lanes; /* number of tx lanes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) u32 rx_pwr_pwm; /* rx pwm working pwr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) u32 tx_pwr_pwm; /* tx pwm working pwr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) u32 rx_pwr_hs; /* rx hs working pwr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) u32 tx_pwr_hs; /* tx hs working pwr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) u32 hs_rate; /* rate A/B to work in HS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) u32 desired_working_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) int ufshcd_get_pwr_dev_param(struct ufs_dev_params *dev_param,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) struct ufs_pa_layer_attr *dev_max,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) struct ufs_pa_layer_attr *agreed_pwr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) int ufshcd_pltfrm_init(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) const struct ufs_hba_variant_ops *vops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) void ufshcd_pltfrm_shutdown(struct platform_device *pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) int ufshcd_pltfrm_suspend(struct device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) int ufshcd_pltfrm_resume(struct device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) int ufshcd_pltfrm_runtime_suspend(struct device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) int ufshcd_pltfrm_runtime_resume(struct device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) int ufshcd_pltfrm_runtime_idle(struct device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #else /* !CONFIG_PM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define ufshcd_pltfrm_suspend NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define ufshcd_pltfrm_resume NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define ufshcd_pltfrm_runtime_suspend NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define ufshcd_pltfrm_runtime_resume NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define ufshcd_pltfrm_runtime_idle NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #endif /* CONFIG_PM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #endif /* UFSHCD_PLTFRM_H_ */