^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Universal Flash Storage Host controller Platform bus based glue driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2011-2013 Samsung India Software Operations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Authors:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Santosh Yaraganavi <santosh.sy@samsung.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Vinayak Holikatti <h.vinayak@samsung.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "ufshcd.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "ufshcd-pltfrm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "unipro.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define UFSHCD_DEFAULT_LANES_PER_DIRECTION 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) static int ufshcd_parse_clock_info(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) int cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) struct device *dev = hba->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) struct device_node *np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) u32 *clkfreq = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) struct ufs_clk_info *clki;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) int len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) size_t sz = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) if (!np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) cnt = of_property_count_strings(np, "clock-names");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) if (!cnt || (cnt == -EINVAL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) dev_info(dev, "%s: Unable to find clocks, assuming enabled\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) } else if (cnt < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) dev_err(dev, "%s: count clock strings failed, err %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) __func__, cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) ret = cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) if (cnt <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) if (!of_get_property(np, "freq-table-hz", &len)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) dev_info(dev, "freq-table-hz property not specified\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) if (len <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) sz = len / sizeof(*clkfreq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) if (sz != 2 * cnt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) dev_err(dev, "%s len mismatch\n", "freq-table-hz");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) clkfreq = devm_kcalloc(dev, sz, sizeof(*clkfreq),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) if (!clkfreq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) ret = of_property_read_u32_array(np, "freq-table-hz",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) clkfreq, sz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) if (ret && (ret != -EINVAL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) dev_err(dev, "%s: error reading array %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) "freq-table-hz", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) for (i = 0; i < sz; i += 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) ret = of_property_read_string_index(np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) "clock-names", i/2, (const char **)&name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) clki = devm_kzalloc(dev, sizeof(*clki), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) if (!clki) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) clki->min_freq = clkfreq[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) clki->max_freq = clkfreq[i+1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) clki->name = devm_kstrdup(dev, name, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) if (!clki->name) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) if (!strcmp(name, "ref_clk"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) clki->keep_link_active = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) dev_dbg(dev, "%s: min %u max %u name %s\n", "freq-table-hz",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) clki->min_freq, clki->max_freq, clki->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) list_add_tail(&clki->list, &hba->clk_list_head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define MAX_PROP_SIZE 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static int ufshcd_populate_vreg(struct device *dev, const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct ufs_vreg **out_vreg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) char prop_name[MAX_PROP_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct ufs_vreg *vreg = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct device_node *np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) if (!np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) dev_err(dev, "%s: non DT initialization\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) snprintf(prop_name, MAX_PROP_SIZE, "%s-supply", name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) if (!of_parse_phandle(np, prop_name, 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) dev_info(dev, "%s: Unable to find %s regulator, assuming enabled\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) __func__, prop_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) vreg = devm_kzalloc(dev, sizeof(*vreg), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) if (!vreg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) vreg->name = devm_kstrdup(dev, name, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) if (!vreg->name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) snprintf(prop_name, MAX_PROP_SIZE, "%s-max-microamp", name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) if (of_property_read_u32(np, prop_name, &vreg->max_uA)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) dev_info(dev, "%s: unable to find %s\n", __func__, prop_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) vreg->max_uA = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) *out_vreg = vreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) * ufshcd_parse_regulator_info - get regulator info from device tree
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) * @hba: per adapter instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) * Get regulator info from device tree for vcc, vccq, vccq2 power supplies.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * If any of the supplies are not defined it is assumed that they are always-on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) * and hence return zero. If the property is defined but parsing is failed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) * then return corresponding error.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static int ufshcd_parse_regulator_info(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) struct device *dev = hba->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) struct ufs_vreg_info *info = &hba->vreg_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) err = ufshcd_populate_vreg(dev, "vdd-hba", &info->vdd_hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) err = ufshcd_populate_vreg(dev, "vcc", &info->vcc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) err = ufshcd_populate_vreg(dev, "vccq", &info->vccq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) err = ufshcd_populate_vreg(dev, "vccq2", &info->vccq2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) * ufshcd_pltfrm_suspend - suspend power management function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) * @dev: pointer to device handle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) * Returns 0 if successful
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) * Returns non-zero otherwise
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) int ufshcd_pltfrm_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) return ufshcd_system_suspend(dev_get_drvdata(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) EXPORT_SYMBOL_GPL(ufshcd_pltfrm_suspend);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) * ufshcd_pltfrm_resume - resume power management function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) * @dev: pointer to device handle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) * Returns 0 if successful
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) * Returns non-zero otherwise
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) int ufshcd_pltfrm_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) return ufshcd_system_resume(dev_get_drvdata(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) EXPORT_SYMBOL_GPL(ufshcd_pltfrm_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) int ufshcd_pltfrm_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) return ufshcd_runtime_suspend(dev_get_drvdata(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) EXPORT_SYMBOL_GPL(ufshcd_pltfrm_runtime_suspend);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) int ufshcd_pltfrm_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) return ufshcd_runtime_resume(dev_get_drvdata(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) EXPORT_SYMBOL_GPL(ufshcd_pltfrm_runtime_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) int ufshcd_pltfrm_runtime_idle(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) return ufshcd_runtime_idle(dev_get_drvdata(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) EXPORT_SYMBOL_GPL(ufshcd_pltfrm_runtime_idle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #endif /* CONFIG_PM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) void ufshcd_pltfrm_shutdown(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) ufshcd_shutdown((struct ufs_hba *)platform_get_drvdata(pdev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) EXPORT_SYMBOL_GPL(ufshcd_pltfrm_shutdown);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static void ufshcd_init_lanes_per_dir(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) struct device *dev = hba->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) ret = of_property_read_u32(dev->of_node, "lanes-per-direction",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) &hba->lanes_per_direction);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) dev_dbg(hba->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) "%s: failed to read lanes-per-direction, ret=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) hba->lanes_per_direction = UFSHCD_DEFAULT_LANES_PER_DIRECTION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) * ufshcd_get_pwr_dev_param - get finally agreed attributes for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) * power mode change
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) * @pltfrm_param: pointer to platform parameters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) * @dev_max: pointer to device attributes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) * @agreed_pwr: returned agreed attributes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) * Returns 0 on success, non-zero value on failure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) int ufshcd_get_pwr_dev_param(struct ufs_dev_params *pltfrm_param,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) struct ufs_pa_layer_attr *dev_max,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) struct ufs_pa_layer_attr *agreed_pwr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) int min_pltfrm_gear;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) int min_dev_gear;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) bool is_dev_sup_hs = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) bool is_pltfrm_max_hs = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) if (dev_max->pwr_rx == FAST_MODE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) is_dev_sup_hs = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) if (pltfrm_param->desired_working_mode == UFS_HS_MODE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) is_pltfrm_max_hs = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) min_pltfrm_gear = min_t(u32, pltfrm_param->hs_rx_gear,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) pltfrm_param->hs_tx_gear);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) min_pltfrm_gear = min_t(u32, pltfrm_param->pwm_rx_gear,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) pltfrm_param->pwm_tx_gear);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) * device doesn't support HS but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) * pltfrm_param->desired_working_mode is HS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) * thus device and pltfrm_param don't agree
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) if (!is_dev_sup_hs && is_pltfrm_max_hs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) pr_info("%s: device doesn't support HS\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) } else if (is_dev_sup_hs && is_pltfrm_max_hs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) * since device supports HS, it supports FAST_MODE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) * since pltfrm_param->desired_working_mode is also HS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) * then final decision (FAST/FASTAUTO) is done according
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) * to pltfrm_params as it is the restricting factor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) agreed_pwr->pwr_rx = pltfrm_param->rx_pwr_hs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) agreed_pwr->pwr_tx = agreed_pwr->pwr_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) * here pltfrm_param->desired_working_mode is PWM.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) * it doesn't matter whether device supports HS or PWM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) * in both cases pltfrm_param->desired_working_mode will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) * determine the mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) agreed_pwr->pwr_rx = pltfrm_param->rx_pwr_pwm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) agreed_pwr->pwr_tx = agreed_pwr->pwr_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) * we would like tx to work in the minimum number of lanes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) * between device capability and vendor preferences.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) * the same decision will be made for rx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) agreed_pwr->lane_tx = min_t(u32, dev_max->lane_tx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) pltfrm_param->tx_lanes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) agreed_pwr->lane_rx = min_t(u32, dev_max->lane_rx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) pltfrm_param->rx_lanes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) /* device maximum gear is the minimum between device rx and tx gears */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) min_dev_gear = min_t(u32, dev_max->gear_rx, dev_max->gear_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) * if both device capabilities and vendor pre-defined preferences are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) * both HS or both PWM then set the minimum gear to be the chosen
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) * working gear.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) * if one is PWM and one is HS then the one that is PWM get to decide
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) * what is the gear, as it is the one that also decided previously what
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) * pwr the device will be configured to.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) if ((is_dev_sup_hs && is_pltfrm_max_hs) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) (!is_dev_sup_hs && !is_pltfrm_max_hs)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) agreed_pwr->gear_rx =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) min_t(u32, min_dev_gear, min_pltfrm_gear);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) } else if (!is_dev_sup_hs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) agreed_pwr->gear_rx = min_dev_gear;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) agreed_pwr->gear_rx = min_pltfrm_gear;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) agreed_pwr->gear_tx = agreed_pwr->gear_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) agreed_pwr->hs_rate = pltfrm_param->hs_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) EXPORT_SYMBOL_GPL(ufshcd_get_pwr_dev_param);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) * ufshcd_pltfrm_init - probe routine of the driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) * @pdev: pointer to Platform device handle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) * @vops: pointer to variant ops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) * Returns 0 on success, non-zero value on failure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) int ufshcd_pltfrm_init(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) const struct ufs_hba_variant_ops *vops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) struct ufs_hba *hba;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) void __iomem *mmio_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) int irq, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) mmio_base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) if (IS_ERR(mmio_base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) err = PTR_ERR(mmio_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) if (irq < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) err = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) err = ufshcd_alloc_host(dev, &hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) dev_err(&pdev->dev, "Allocation failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) hba->vops = vops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) err = ufshcd_parse_clock_info(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) dev_err(&pdev->dev, "%s: clock parse failed %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) __func__, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) goto dealloc_host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) err = ufshcd_parse_regulator_info(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) dev_err(&pdev->dev, "%s: regulator init failed %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) __func__, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) goto dealloc_host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) ufshcd_init_lanes_per_dir(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) err = ufshcd_init(hba, mmio_base, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) dev_err(dev, "Initialization failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) goto dealloc_host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) pm_runtime_set_active(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) pm_runtime_enable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) dealloc_host:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) ufshcd_dealloc_host(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) EXPORT_SYMBOL_GPL(ufshcd_pltfrm_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) MODULE_AUTHOR("Santosh Yaragnavi <santosh.sy@samsung.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) MODULE_AUTHOR("Vinayak Holikatti <h.vinayak@samsung.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) MODULE_DESCRIPTION("UFS host controller Platform bus based glue driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) MODULE_VERSION(UFSHCD_DRIVER_VERSION);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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