^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Universal Flash Storage Host controller PCI glue driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * This code is based on drivers/scsi/ufs/ufshcd-pci.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2011-2013 Samsung India Software Operations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Authors:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Santosh Yaraganavi <santosh.sy@samsung.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Vinayak Holikatti <h.vinayak@samsung.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include "ufshcd.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/pm_qos.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/debugfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) struct intel_host {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) u32 active_ltr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) u32 idle_ltr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) struct dentry *debugfs_root;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) static int ufs_intel_disable_lcc(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) u32 attr = UIC_ARG_MIB(PA_LOCAL_TX_LCC_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) u32 lcc_enable = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) ufshcd_dme_get(hba, attr, &lcc_enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) if (lcc_enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) ufshcd_disable_host_tx_lcc(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) static int ufs_intel_link_startup_notify(struct ufs_hba *hba,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) enum ufs_notify_change_status status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) switch (status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) case PRE_CHANGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) err = ufs_intel_disable_lcc(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) case POST_CHANGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define INTEL_ACTIVELTR 0x804
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define INTEL_IDLELTR 0x808
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define INTEL_LTR_REQ BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define INTEL_LTR_SCALE_MASK GENMASK(11, 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define INTEL_LTR_SCALE_1US (2 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define INTEL_LTR_SCALE_32US (3 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define INTEL_LTR_VALUE_MASK GENMASK(9, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static void intel_cache_ltr(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct intel_host *host = ufshcd_get_variant(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) host->active_ltr = readl(hba->mmio_base + INTEL_ACTIVELTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) host->idle_ltr = readl(hba->mmio_base + INTEL_IDLELTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static void intel_ltr_set(struct device *dev, s32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct ufs_hba *hba = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct intel_host *host = ufshcd_get_variant(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) u32 ltr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) pm_runtime_get_sync(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * Program latency tolerance (LTR) accordingly what has been asked
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * by the PM QoS layer or disable it in case we were passed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * negative value or PM_QOS_LATENCY_ANY.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) ltr = readl(hba->mmio_base + INTEL_ACTIVELTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) if (val == PM_QOS_LATENCY_ANY || val < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) ltr &= ~INTEL_LTR_REQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) ltr |= INTEL_LTR_REQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) ltr &= ~INTEL_LTR_SCALE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) ltr &= ~INTEL_LTR_VALUE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) if (val > INTEL_LTR_VALUE_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) val >>= 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) if (val > INTEL_LTR_VALUE_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) val = INTEL_LTR_VALUE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) ltr |= INTEL_LTR_SCALE_32US | val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) ltr |= INTEL_LTR_SCALE_1US | val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) if (ltr == host->active_ltr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) writel(ltr, hba->mmio_base + INTEL_ACTIVELTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) writel(ltr, hba->mmio_base + INTEL_IDLELTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /* Cache the values into intel_host structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) intel_cache_ltr(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) pm_runtime_put(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static void intel_ltr_expose(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) dev->power.set_latency_tolerance = intel_ltr_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) dev_pm_qos_expose_latency_tolerance(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static void intel_ltr_hide(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) dev_pm_qos_hide_latency_tolerance(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) dev->power.set_latency_tolerance = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static void intel_add_debugfs(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) struct dentry *dir = debugfs_create_dir(dev_name(hba->dev), NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct intel_host *host = ufshcd_get_variant(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) intel_cache_ltr(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) host->debugfs_root = dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) debugfs_create_x32("active_ltr", 0444, dir, &host->active_ltr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) debugfs_create_x32("idle_ltr", 0444, dir, &host->idle_ltr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static void intel_remove_debugfs(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) struct intel_host *host = ufshcd_get_variant(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) debugfs_remove_recursive(host->debugfs_root);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static int ufs_intel_common_init(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) struct intel_host *host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) hba->caps |= UFSHCD_CAP_RPM_AUTOSUSPEND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) host = devm_kzalloc(hba->dev, sizeof(*host), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) if (!host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) ufshcd_set_variant(hba, host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) intel_ltr_expose(hba->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) intel_add_debugfs(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static void ufs_intel_common_exit(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) intel_remove_debugfs(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) intel_ltr_hide(hba->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static int ufs_intel_resume(struct ufs_hba *hba, enum ufs_pm_op op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * To support S4 (suspend-to-disk) with spm_lvl other than 5, the base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) * address registers must be restored because the restore kernel can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) * have used different addresses.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) ufshcd_writel(hba, lower_32_bits(hba->utrdl_dma_addr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) REG_UTP_TRANSFER_REQ_LIST_BASE_L);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) ufshcd_writel(hba, upper_32_bits(hba->utrdl_dma_addr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) REG_UTP_TRANSFER_REQ_LIST_BASE_H);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) ufshcd_writel(hba, lower_32_bits(hba->utmrdl_dma_addr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) REG_UTP_TASK_REQ_LIST_BASE_L);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) ufshcd_writel(hba, upper_32_bits(hba->utmrdl_dma_addr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) REG_UTP_TASK_REQ_LIST_BASE_H);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) if (ufshcd_is_link_hibern8(hba)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) int ret = ufshcd_uic_hibern8_exit(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) ufshcd_set_link_active(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) dev_err(hba->dev, "%s: hibern8 exit failed %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) * Force reset and restore. Any other actions can lead
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) * to an unrecoverable state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) ufshcd_set_link_off(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static int ufs_intel_ehl_init(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) hba->quirks |= UFSHCD_QUIRK_BROKEN_AUTO_HIBERN8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) return ufs_intel_common_init(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) static struct ufs_hba_variant_ops ufs_intel_cnl_hba_vops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) .name = "intel-pci",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .init = ufs_intel_common_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .exit = ufs_intel_common_exit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) .link_startup_notify = ufs_intel_link_startup_notify,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) .resume = ufs_intel_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) static struct ufs_hba_variant_ops ufs_intel_ehl_hba_vops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) .name = "intel-pci",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) .init = ufs_intel_ehl_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) .exit = ufs_intel_common_exit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) .link_startup_notify = ufs_intel_link_startup_notify,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) .resume = ufs_intel_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) * ufshcd_pci_suspend - suspend power management function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) * @dev: pointer to PCI device handle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) * Returns 0 if successful
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) * Returns non-zero otherwise
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) static int ufshcd_pci_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) return ufshcd_system_suspend(dev_get_drvdata(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) * ufshcd_pci_resume - resume power management function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) * @dev: pointer to PCI device handle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) * Returns 0 if successful
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) * Returns non-zero otherwise
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) static int ufshcd_pci_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) return ufshcd_system_resume(dev_get_drvdata(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) * ufshcd_pci_poweroff - suspend-to-disk poweroff function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) * @dev: pointer to PCI device handle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) * Returns 0 if successful
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) * Returns non-zero otherwise
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) static int ufshcd_pci_poweroff(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) struct ufs_hba *hba = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) int spm_lvl = hba->spm_lvl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) * For poweroff we need to set the UFS device to PowerDown mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) * Force spm_lvl to ensure that.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) hba->spm_lvl = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) ret = ufshcd_system_suspend(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) hba->spm_lvl = spm_lvl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #endif /* !CONFIG_PM_SLEEP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) static int ufshcd_pci_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) return ufshcd_runtime_suspend(dev_get_drvdata(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) static int ufshcd_pci_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) return ufshcd_runtime_resume(dev_get_drvdata(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) static int ufshcd_pci_runtime_idle(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) return ufshcd_runtime_idle(dev_get_drvdata(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #endif /* !CONFIG_PM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) * ufshcd_pci_shutdown - main function to put the controller in reset state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) * @pdev: pointer to PCI device handle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) static void ufshcd_pci_shutdown(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) ufshcd_shutdown((struct ufs_hba *)pci_get_drvdata(pdev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) * ufshcd_pci_remove - de-allocate PCI/SCSI host and host memory space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) * data structure memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) * @pdev: pointer to PCI handle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) static void ufshcd_pci_remove(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) struct ufs_hba *hba = pci_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) pm_runtime_forbid(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) pm_runtime_get_noresume(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) ufshcd_remove(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) ufshcd_dealloc_host(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) * ufshcd_pci_probe - probe routine of the driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) * @pdev: pointer to PCI device handle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) * @id: PCI device id
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) * Returns 0 on success, non-zero value on failure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) ufshcd_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) struct ufs_hba *hba;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) void __iomem *mmio_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) err = pcim_enable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) dev_err(&pdev->dev, "pcim_enable_device failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) pci_set_master(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) err = pcim_iomap_regions(pdev, 1 << 0, UFSHCD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) dev_err(&pdev->dev, "request and iomap failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) mmio_base = pcim_iomap_table(pdev)[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) err = ufshcd_alloc_host(&pdev->dev, &hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) dev_err(&pdev->dev, "Allocation failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) hba->vops = (struct ufs_hba_variant_ops *)id->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) err = ufshcd_init(hba, mmio_base, pdev->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) dev_err(&pdev->dev, "Initialization failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) ufshcd_dealloc_host(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) pm_runtime_put_noidle(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) pm_runtime_allow(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) static const struct dev_pm_ops ufshcd_pci_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) .suspend = ufshcd_pci_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) .resume = ufshcd_pci_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) .freeze = ufshcd_pci_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) .thaw = ufshcd_pci_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) .poweroff = ufshcd_pci_poweroff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) .restore = ufshcd_pci_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) SET_RUNTIME_PM_OPS(ufshcd_pci_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) ufshcd_pci_runtime_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) ufshcd_pci_runtime_idle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) static const struct pci_device_id ufshcd_pci_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) { PCI_VENDOR_ID_SAMSUNG, 0xC00C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) { PCI_VDEVICE(INTEL, 0x9DFA), (kernel_ulong_t)&ufs_intel_cnl_hba_vops },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) { PCI_VDEVICE(INTEL, 0x4B41), (kernel_ulong_t)&ufs_intel_ehl_hba_vops },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) { PCI_VDEVICE(INTEL, 0x4B43), (kernel_ulong_t)&ufs_intel_ehl_hba_vops },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) { } /* terminate list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) MODULE_DEVICE_TABLE(pci, ufshcd_pci_tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) static struct pci_driver ufshcd_pci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) .name = UFSHCD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) .id_table = ufshcd_pci_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) .probe = ufshcd_pci_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) .remove = ufshcd_pci_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) .shutdown = ufshcd_pci_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) .pm = &ufshcd_pci_pm_ops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) module_pci_driver(ufshcd_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) MODULE_AUTHOR("Santosh Yaragnavi <santosh.sy@samsung.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) MODULE_AUTHOR("Vinayak Holikatti <h.vinayak@samsung.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) MODULE_DESCRIPTION("UFS host controller PCI glue driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) MODULE_VERSION(UFSHCD_DRIVER_VERSION);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags