Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) #ifndef UFS_QCOM_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #define UFS_QCOM_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/reset-controller.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #define MAX_UFS_QCOM_HOSTS	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #define MAX_U32                 (~(u32)0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #define MPHY_TX_FSM_STATE       0x41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #define TX_FSM_HIBERN8          0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define HBRN8_POLL_TOUT_MS      100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define DEFAULT_CLK_RATE_HZ     1000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define BUS_VECTOR_NAME_LEN     32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define UFS_HW_VER_MAJOR_SHFT	(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define UFS_HW_VER_MAJOR_MASK	(0x000F << UFS_HW_VER_MAJOR_SHFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define UFS_HW_VER_MINOR_SHFT	(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define UFS_HW_VER_MINOR_MASK	(0x0FFF << UFS_HW_VER_MINOR_SHFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define UFS_HW_VER_STEP_SHFT	(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define UFS_HW_VER_STEP_MASK	(0xFFFF << UFS_HW_VER_STEP_SHFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) /* vendor specific pre-defined parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define SLOW 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define FAST 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define UFS_QCOM_LIMIT_NUM_LANES_RX	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define UFS_QCOM_LIMIT_NUM_LANES_TX	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define UFS_QCOM_LIMIT_HSGEAR_RX	UFS_HS_G3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define UFS_QCOM_LIMIT_HSGEAR_TX	UFS_HS_G3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define UFS_QCOM_LIMIT_PWMGEAR_RX	UFS_PWM_G4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define UFS_QCOM_LIMIT_PWMGEAR_TX	UFS_PWM_G4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define UFS_QCOM_LIMIT_RX_PWR_PWM	SLOW_MODE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define UFS_QCOM_LIMIT_TX_PWR_PWM	SLOW_MODE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define UFS_QCOM_LIMIT_RX_PWR_HS	FAST_MODE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define UFS_QCOM_LIMIT_TX_PWR_HS	FAST_MODE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define UFS_QCOM_LIMIT_HS_RATE		PA_HS_MODE_B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define UFS_QCOM_LIMIT_DESIRED_MODE	FAST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) /* QCOM UFS host controller vendor specific registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	REG_UFS_SYS1CLK_1US                 = 0xC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	REG_UFS_TX_SYMBOL_CLK_NS_US         = 0xC4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	REG_UFS_LOCAL_PORT_ID_REG           = 0xC8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	REG_UFS_PA_ERR_CODE                 = 0xCC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	REG_UFS_RETRY_TIMER_REG             = 0xD0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	REG_UFS_PA_LINK_STARTUP_TIMER       = 0xD8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	REG_UFS_CFG1                        = 0xDC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	REG_UFS_CFG2                        = 0xE0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	REG_UFS_HW_VERSION                  = 0xE4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	UFS_TEST_BUS				= 0xE8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	UFS_TEST_BUS_CTRL_0			= 0xEC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	UFS_TEST_BUS_CTRL_1			= 0xF0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	UFS_TEST_BUS_CTRL_2			= 0xF4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	UFS_UNIPRO_CFG				= 0xF8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	 * QCOM UFS host controller vendor specific registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	 * added in HW Version 3.0.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	UFS_AH8_CFG				= 0xFC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) /* QCOM UFS host controller vendor specific debug registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	UFS_DBG_RD_REG_UAWM			= 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	UFS_DBG_RD_REG_UARM			= 0x200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	UFS_DBG_RD_REG_TXUC			= 0x300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	UFS_DBG_RD_REG_RXUC			= 0x400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	UFS_DBG_RD_REG_DFC			= 0x500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	UFS_DBG_RD_REG_TRLUT			= 0x600,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	UFS_DBG_RD_REG_TMRLUT			= 0x700,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	UFS_UFS_DBG_RD_REG_OCSC			= 0x800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	UFS_UFS_DBG_RD_DESC_RAM			= 0x1500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	UFS_UFS_DBG_RD_PRDT_RAM			= 0x1700,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	UFS_UFS_DBG_RD_RESP_RAM			= 0x1800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	UFS_UFS_DBG_RD_EDTL_RAM			= 0x1900,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define UFS_CNTLR_2_x_x_VEN_REGS_OFFSET(x)	(0x000 + x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define UFS_CNTLR_3_x_x_VEN_REGS_OFFSET(x)	(0x400 + x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) /* bit definitions for REG_UFS_CFG1 register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define QUNIPRO_SEL		0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define UTP_DBG_RAMS_EN		0x20000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define TEST_BUS_EN		BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define TEST_BUS_SEL		GENMASK(22, 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define UFS_REG_TEST_BUS_EN	BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) /* bit definitions for REG_UFS_CFG2 register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define UAWM_HW_CGC_EN		(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define UARM_HW_CGC_EN		(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define TXUC_HW_CGC_EN		(1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define RXUC_HW_CGC_EN		(1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define DFC_HW_CGC_EN		(1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define TRLUT_HW_CGC_EN		(1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define TMRLUT_HW_CGC_EN	(1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define OCSC_HW_CGC_EN		(1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /* bit definition for UFS_UFS_TEST_BUS_CTRL_n */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define TEST_BUS_SUB_SEL_MASK	0x1F  /* All XXX_SEL fields are 5 bits wide */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define REG_UFS_CFG2_CGC_EN_ALL (UAWM_HW_CGC_EN | UARM_HW_CGC_EN |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 				 TXUC_HW_CGC_EN | RXUC_HW_CGC_EN |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 				 DFC_HW_CGC_EN | TRLUT_HW_CGC_EN |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 				 TMRLUT_HW_CGC_EN | OCSC_HW_CGC_EN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /* bit offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	OFFSET_UFS_PHY_SOFT_RESET           = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	OFFSET_CLK_NS_REG                   = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /* bit masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	MASK_UFS_PHY_SOFT_RESET             = 0x2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	MASK_TX_SYMBOL_CLK_1US_REG          = 0x3FF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	MASK_CLK_NS_REG                     = 0xFFFC00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /* QCOM UFS debug print bit mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define UFS_QCOM_DBG_PRINT_REGS_EN	BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define UFS_QCOM_DBG_PRINT_ICE_REGS_EN	BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define UFS_QCOM_DBG_PRINT_TEST_BUS_EN	BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define UFS_QCOM_DBG_PRINT_ALL	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	(UFS_QCOM_DBG_PRINT_REGS_EN | UFS_QCOM_DBG_PRINT_ICE_REGS_EN | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	 UFS_QCOM_DBG_PRINT_TEST_BUS_EN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /* QUniPro Vendor specific attributes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define PA_VS_CONFIG_REG1	0x9000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define DME_VS_CORE_CLK_CTRL	0xD002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /* bit and mask definitions for DME_VS_CORE_CLK_CTRL attribute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT		BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define DME_VS_CORE_CLK_CTRL_MAX_CORE_CLK_1US_CYCLES_MASK	0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) ufs_qcom_get_controller_revision(struct ufs_hba *hba,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 				 u8 *major, u16 *minor, u16 *step)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	u32 ver = ufshcd_readl(hba, REG_UFS_HW_VERSION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	*major = (ver & UFS_HW_VER_MAJOR_MASK) >> UFS_HW_VER_MAJOR_SHFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	*minor = (ver & UFS_HW_VER_MINOR_MASK) >> UFS_HW_VER_MINOR_SHFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	*step = (ver & UFS_HW_VER_STEP_MASK) >> UFS_HW_VER_STEP_SHFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static inline void ufs_qcom_assert_reset(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	ufshcd_rmwl(hba, MASK_UFS_PHY_SOFT_RESET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 			1 << OFFSET_UFS_PHY_SOFT_RESET, REG_UFS_CFG1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	 * Make sure assertion of ufs phy reset is written to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	 * register before returning
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static inline void ufs_qcom_deassert_reset(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	ufshcd_rmwl(hba, MASK_UFS_PHY_SOFT_RESET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 			0 << OFFSET_UFS_PHY_SOFT_RESET, REG_UFS_CFG1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	 * Make sure de-assertion of ufs phy reset is written to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	 * register before returning
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /* Host controller hardware version: major.minor.step */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) struct ufs_hw_version {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	u16 step;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	u16 minor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	u8 major;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) struct ufs_qcom_testbus {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	u8 select_major;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	u8 select_minor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) struct gpio_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) struct ufs_qcom_host {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	 * Set this capability if host controller supports the QUniPro mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	 * and if driver wants the Host controller to operate in QUniPro mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	 * Note: By default this capability will be kept enabled if host
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	 * controller supports the QUniPro mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	#define UFS_QCOM_CAP_QUNIPRO	0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	 * Set this capability if host controller can retain the secure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	 * configuration even after UFS controller core power collapse.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	#define UFS_QCOM_CAP_RETAIN_SEC_CFG_AFTER_PWR_COLLAPSE	0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	u32 caps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	struct phy *generic_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	struct ufs_hba *hba;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	struct ufs_pa_layer_attr dev_req_params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	struct clk *rx_l0_sync_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	struct clk *tx_l0_sync_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	struct clk *rx_l1_sync_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	struct clk *tx_l1_sync_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	bool is_lane_clks_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	void __iomem *dev_ref_clk_ctrl_mmio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	bool is_dev_ref_clk_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	struct ufs_hw_version hw_ver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #ifdef CONFIG_SCSI_UFS_CRYPTO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	void __iomem *ice_mmio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	u32 dev_ref_clk_en_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	/* Bitmask for enabling debug prints */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	u32 dbg_print_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	struct ufs_qcom_testbus testbus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	/* Reset control of HCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	struct reset_control *core_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	struct reset_controller_dev rcdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	struct gpio_desc *device_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) static inline u32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) ufs_qcom_get_debug_reg_offset(struct ufs_qcom_host *host, u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	if (host->hw_ver.major <= 0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 		return UFS_CNTLR_2_x_x_VEN_REGS_OFFSET(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	return UFS_CNTLR_3_x_x_VEN_REGS_OFFSET(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define ufs_qcom_is_link_off(hba) ufshcd_is_link_off(hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define ufs_qcom_is_link_active(hba) ufshcd_is_link_active(hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define ufs_qcom_is_link_hibern8(hba) ufshcd_is_link_hibern8(hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) int ufs_qcom_testbus_config(struct ufs_qcom_host *host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) static inline bool ufs_qcom_cap_qunipro(struct ufs_qcom_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	if (host->caps & UFS_QCOM_CAP_QUNIPRO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 		return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 		return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) /* ufs-qcom-ice.c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #ifdef CONFIG_SCSI_UFS_CRYPTO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) int ufs_qcom_ice_init(struct ufs_qcom_host *host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) int ufs_qcom_ice_enable(struct ufs_qcom_host *host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) int ufs_qcom_ice_resume(struct ufs_qcom_host *host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) int ufs_qcom_ice_program_key(struct ufs_hba *hba,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 			     const union ufs_crypto_cfg_entry *cfg, int slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static inline int ufs_qcom_ice_init(struct ufs_qcom_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) static inline int ufs_qcom_ice_enable(struct ufs_qcom_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) static inline int ufs_qcom_ice_resume(struct ufs_qcom_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define ufs_qcom_ice_program_key NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #endif /* !CONFIG_SCSI_UFS_CRYPTO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #endif /* UFS_QCOM_H_ */