Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Qualcomm ICE (Inline Crypto Engine) support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (c) 2014-2019, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Copyright 2019 Google LLC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/qcom_scm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include "ufshcd-crypto.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include "ufs-qcom.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define AES_256_XTS_KEY_SIZE			64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) /* QCOM ICE registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define QCOM_ICE_REG_CONTROL			0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define QCOM_ICE_REG_RESET			0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define QCOM_ICE_REG_VERSION			0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define QCOM_ICE_REG_FUSE_SETTING		0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define QCOM_ICE_REG_PARAMETERS_1		0x0014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define QCOM_ICE_REG_PARAMETERS_2		0x0018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define QCOM_ICE_REG_PARAMETERS_3		0x001C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define QCOM_ICE_REG_PARAMETERS_4		0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define QCOM_ICE_REG_PARAMETERS_5		0x0024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) /* QCOM ICE v3.X only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define QCOM_ICE_GENERAL_ERR_STTS		0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define QCOM_ICE_INVALID_CCFG_ERR_STTS		0x0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define QCOM_ICE_GENERAL_ERR_MASK		0x0044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) /* QCOM ICE v2.X only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define QCOM_ICE_REG_NON_SEC_IRQ_STTS		0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define QCOM_ICE_REG_NON_SEC_IRQ_MASK		0x0044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define QCOM_ICE_REG_NON_SEC_IRQ_CLR		0x0048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define QCOM_ICE_REG_STREAM1_ERROR_SYNDROME1	0x0050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define QCOM_ICE_REG_STREAM1_ERROR_SYNDROME2	0x0054
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define QCOM_ICE_REG_STREAM2_ERROR_SYNDROME1	0x0058
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define QCOM_ICE_REG_STREAM2_ERROR_SYNDROME2	0x005C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define QCOM_ICE_REG_STREAM1_BIST_ERROR_VEC	0x0060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define QCOM_ICE_REG_STREAM2_BIST_ERROR_VEC	0x0064
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define QCOM_ICE_REG_STREAM1_BIST_FINISH_VEC	0x0068
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define QCOM_ICE_REG_STREAM2_BIST_FINISH_VEC	0x006C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define QCOM_ICE_REG_BIST_STATUS		0x0070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define QCOM_ICE_REG_BYPASS_STATUS		0x0074
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define QCOM_ICE_REG_ADVANCED_CONTROL		0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define QCOM_ICE_REG_ENDIAN_SWAP		0x1004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define QCOM_ICE_REG_TEST_BUS_CONTROL		0x1010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define QCOM_ICE_REG_TEST_BUS_REG		0x1014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) /* BIST ("built-in self-test"?) status flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define QCOM_ICE_BIST_STATUS_MASK		0xF0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define QCOM_ICE_FUSE_SETTING_MASK		0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define QCOM_ICE_FORCE_HW_KEY0_SETTING_MASK	0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define QCOM_ICE_FORCE_HW_KEY1_SETTING_MASK	0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define qcom_ice_writel(host, val, reg)	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	writel((val), (host)->ice_mmio + (reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define qcom_ice_readl(host, reg)	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	readl((host)->ice_mmio + (reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) static bool qcom_ice_supported(struct ufs_qcom_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	struct device *dev = host->hba->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	u32 regval = qcom_ice_readl(host, QCOM_ICE_REG_VERSION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	int major = regval >> 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	int minor = (regval >> 16) & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	int step = regval & 0xFFFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	/* For now this driver only supports ICE version 3. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	if (major != 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 		dev_warn(dev, "Unsupported ICE version: v%d.%d.%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 			 major, minor, step);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 		return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	dev_info(dev, "Found QC Inline Crypto Engine (ICE) v%d.%d.%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 		 major, minor, step);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	/* If fuses are blown, ICE might not work in the standard way. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	regval = qcom_ice_readl(host, QCOM_ICE_REG_FUSE_SETTING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	if (regval & (QCOM_ICE_FUSE_SETTING_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 		      QCOM_ICE_FORCE_HW_KEY0_SETTING_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 		      QCOM_ICE_FORCE_HW_KEY1_SETTING_MASK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 		dev_warn(dev, "Fuses are blown; ICE is unusable!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 		return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) int ufs_qcom_ice_init(struct ufs_qcom_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	struct ufs_hba *hba = host->hba;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	struct device *dev = hba->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	struct platform_device *pdev = to_platform_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	if (!(ufshcd_readl(hba, REG_CONTROLLER_CAPABILITIES) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	      MASK_CRYPTO_SUPPORT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ice");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	if (!res) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 		dev_warn(dev, "ICE registers not found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 		goto disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	if (!qcom_scm_ice_available()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 		dev_warn(dev, "ICE SCM interface not found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 		goto disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	host->ice_mmio = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	if (IS_ERR(host->ice_mmio)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 		err = PTR_ERR(host->ice_mmio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 		dev_err(dev, "Failed to map ICE registers; err=%d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	if (!qcom_ice_supported(host))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		goto disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	dev_warn(dev, "Disabling inline encryption support\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	hba->caps &= ~UFSHCD_CAP_CRYPTO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static void qcom_ice_low_power_mode_enable(struct ufs_qcom_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	u32 regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	regval = qcom_ice_readl(host, QCOM_ICE_REG_ADVANCED_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	 * Enable low power mode sequence
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	 * [0]-0, [1]-0, [2]-0, [3]-E, [4]-0, [5]-0, [6]-0, [7]-0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	regval |= 0x7000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	qcom_ice_writel(host, regval, QCOM_ICE_REG_ADVANCED_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static void qcom_ice_optimization_enable(struct ufs_qcom_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	u32 regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	/* ICE Optimizations Enable Sequence */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	regval = qcom_ice_readl(host, QCOM_ICE_REG_ADVANCED_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	regval |= 0xD807100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	/* ICE HPG requires delay before writing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	udelay(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	qcom_ice_writel(host, regval, QCOM_ICE_REG_ADVANCED_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	udelay(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) int ufs_qcom_ice_enable(struct ufs_qcom_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	if (!(host->hba->caps & UFSHCD_CAP_CRYPTO))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	qcom_ice_low_power_mode_enable(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	qcom_ice_optimization_enable(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	return ufs_qcom_ice_resume(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /* Poll until all BIST bits are reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static int qcom_ice_wait_bist_status(struct ufs_qcom_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	int count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	for (count = 0; count < 100; count++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 		reg = qcom_ice_readl(host, QCOM_ICE_REG_BIST_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		if (!(reg & QCOM_ICE_BIST_STATUS_MASK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		udelay(50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	if (reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 		return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) int ufs_qcom_ice_resume(struct ufs_qcom_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	if (!(host->hba->caps & UFSHCD_CAP_CRYPTO))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	err = qcom_ice_wait_bist_status(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 		dev_err(host->hba->dev, "BIST status error (%d)\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)  * Program a key into a QC ICE keyslot, or evict a keyslot.  QC ICE requires
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)  * vendor-specific SCM calls for this; it doesn't support the standard way.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) int ufs_qcom_ice_program_key(struct ufs_hba *hba,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 			     const union ufs_crypto_cfg_entry *cfg, int slot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	union ufs_crypto_cap_entry cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 		u8 bytes[AES_256_XTS_KEY_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 		u32 words[AES_256_XTS_KEY_SIZE / sizeof(u32)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	} key;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	if (!(cfg->config_enable & UFS_CRYPTO_CONFIGURATION_ENABLE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 		return qcom_scm_ice_invalidate_key(slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	/* Only AES-256-XTS has been tested so far. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	cap = hba->crypto_cap_array[cfg->crypto_cap_idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	if (cap.algorithm_id != UFS_CRYPTO_ALG_AES_XTS ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	    cap.key_size != UFS_CRYPTO_KEY_SIZE_256) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 		dev_err_ratelimited(hba->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 				    "Unhandled crypto capability; algorithm_id=%d, key_size=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 				    cap.algorithm_id, cap.key_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	memcpy(key.bytes, cfg->crypto_key, AES_256_XTS_KEY_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	 * The SCM call byte-swaps the 32-bit words of the key.  So we have to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	 * do the same, in order for the final key be correct.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	for (i = 0; i < ARRAY_SIZE(key.words); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 		__cpu_to_be32s(&key.words[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	err = qcom_scm_ice_set_key(slot, key.bytes, AES_256_XTS_KEY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 				   QCOM_SCM_ICE_CIPHER_AES_256_XTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 				   cfg->data_unit_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	memzero_explicit(&key, sizeof(key));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) }