^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2019 MediaTek Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #ifndef _UFS_MEDIATEK_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define _UFS_MEDIATEK_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/soc/mediatek/mtk_sip_svc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Vendor specific UFSHCI Registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define REG_UFS_REFCLK_CTRL 0x144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define REG_UFS_EXTREG 0x2100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define REG_UFS_MPHYCTRL 0x2200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define REG_UFS_REJECT_MON 0x22AC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define REG_UFS_DEBUG_SEL 0x22C0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define REG_UFS_PROBE 0x22C8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * Ref-clk control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * Values for register REG_UFS_REFCLK_CTRL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define REFCLK_RELEASE 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define REFCLK_REQUEST BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define REFCLK_ACK BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define REFCLK_REQ_TIMEOUT_US 3000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * Vendor specific pre-defined parameters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define UFS_MTK_LIMIT_NUM_LANES_RX 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define UFS_MTK_LIMIT_NUM_LANES_TX 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define UFS_MTK_LIMIT_HSGEAR_RX UFS_HS_G4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define UFS_MTK_LIMIT_HSGEAR_TX UFS_HS_G4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define UFS_MTK_LIMIT_PWMGEAR_RX UFS_PWM_G4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define UFS_MTK_LIMIT_PWMGEAR_TX UFS_PWM_G4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define UFS_MTK_LIMIT_RX_PWR_PWM SLOW_MODE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define UFS_MTK_LIMIT_TX_PWR_PWM SLOW_MODE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define UFS_MTK_LIMIT_RX_PWR_HS FAST_MODE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define UFS_MTK_LIMIT_TX_PWR_HS FAST_MODE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define UFS_MTK_LIMIT_HS_RATE PA_HS_MODE_B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define UFS_MTK_LIMIT_DESIRED_MODE UFS_HS_MODE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * Other attributes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define VS_DEBUGCLOCKENABLE 0xD0A1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define VS_SAVEPOWERCONTROL 0xD0A6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define VS_UNIPROPOWERDOWNCONTROL 0xD0A8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * Vendor specific link state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) VS_LINK_DISABLED = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) VS_LINK_DOWN = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) VS_LINK_UP = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) VS_LINK_HIBERN8 = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) VS_LINK_LOST = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) VS_LINK_CFG = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * SiP commands
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define MTK_SIP_UFS_CONTROL MTK_SIP_SMC_CMD(0x276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define UFS_MTK_SIP_VA09_PWR_CTRL BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define UFS_MTK_SIP_DEVICE_RESET BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define UFS_MTK_SIP_CRYPTO_CTRL BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define UFS_MTK_SIP_REF_CLK_NOTIFICATION BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * VS_DEBUGCLOCKENABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) TX_SYMBOL_CLK_REQ_FORCE = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * VS_SAVEPOWERCONTROL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) RX_SYMBOL_CLK_GATE_EN = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) SYS_CLK_GATE_EN = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) TX_CLK_GATE_EN = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * Host capability
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) enum ufs_mtk_host_caps {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) UFS_MTK_CAP_BOOST_CRYPT_ENGINE = 1 << 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) UFS_MTK_CAP_VA09_PWR_CTRL = 1 << 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) UFS_MTK_CAP_DISABLE_AH8 = 1 << 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) UFS_MTK_CAP_BROKEN_VCC = 1 << 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) struct ufs_mtk_crypt_cfg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) struct regulator *reg_vcore;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) struct clk *clk_crypt_perf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) struct clk *clk_crypt_mux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) struct clk *clk_crypt_lp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) int vcore_volt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) struct ufs_mtk_hw_ver {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) u8 step;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) u8 minor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) u8 major;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct ufs_mtk_host {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) struct phy *mphy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct regulator *reg_va09;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct ufs_mtk_hw_ver hw_ver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct reset_control *hci_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) struct reset_control *unipro_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct reset_control *crypto_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) struct ufs_hba *hba;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) struct ufs_mtk_crypt_cfg *crypt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) enum ufs_mtk_host_caps caps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) bool mphy_powered_on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) bool unipro_lpm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) bool ref_clk_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) u16 ref_clk_ungating_wait_us;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) u16 ref_clk_gating_wait_us;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #endif /* !_UFS_MEDIATEK_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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