^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2017, HiSilicon. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #ifndef UFS_HISI_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define UFS_HISI_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define HBRN8_POLL_TOUT_MS 1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * ufs sysctrl specific define
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define PSW_POWER_CTRL (0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define PHY_ISO_EN (0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define HC_LP_CTRL (0x0C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define PHY_CLK_CTRL (0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define PSW_CLK_CTRL (0x14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define CLOCK_GATE_BYPASS (0x18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define RESET_CTRL_EN (0x1C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define UFS_SYSCTRL (0x5C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define UFS_DEVICE_RESET_CTRL (0x60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define BIT_UFS_PSW_ISO_CTRL (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define BIT_UFS_PSW_MTCMOS_EN (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define BIT_UFS_REFCLK_ISO_EN (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define BIT_UFS_PHY_ISO_CTRL (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define BIT_SYSCTRL_LP_ISOL_EN (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define BIT_SYSCTRL_PWR_READY (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define BIT_SYSCTRL_REF_CLOCK_EN (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define MASK_SYSCTRL_REF_CLOCK_SEL (0x3 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define MASK_SYSCTRL_CFG_CLOCK_FREQ (0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define UFS_FREQ_CFG_CLK (0x39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define BIT_SYSCTRL_PSW_CLK_EN (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define MASK_UFS_CLK_GATE_BYPASS (0x3F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define BIT_SYSCTRL_LP_RESET_N (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define BIT_UFS_REFCLK_SRC_SEl (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define MASK_UFS_SYSCRTL_BYPASS (0x3F << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define MASK_UFS_DEVICE_RESET (0x1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define BIT_UFS_DEVICE_RESET (0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * M-TX Configuration Attributes for Hixxxx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define MPHY_TX_FSM_STATE 0x41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define TX_FSM_HIBERN8 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * Hixxxx UFS HC specific Registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) UFS_REG_OCPTHRTL = 0xc0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) UFS_REG_OOCPR = 0xc4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) UFS_REG_CDACFG = 0xd0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) UFS_REG_CDATX1 = 0xd4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) UFS_REG_CDATX2 = 0xd8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) UFS_REG_CDARX1 = 0xdc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) UFS_REG_CDARX2 = 0xe0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) UFS_REG_CDASTA = 0xe4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) UFS_REG_LBMCFG = 0xf0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) UFS_REG_LBMSTA = 0xf4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) UFS_REG_UFSMODE = 0xf8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) UFS_REG_HCLKDIV = 0xfc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /* AHIT - Auto-Hibernate Idle Timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define UFS_AHIT_AH8ITV_MASK 0x3FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* REG UFS_REG_OCPTHRTL definition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define UFS_HCLKDIV_NORMAL_VALUE 0xE4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* vendor specific pre-defined parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define SLOW 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define FAST 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define UFS_HISI_LIMIT_NUM_LANES_RX 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define UFS_HISI_LIMIT_NUM_LANES_TX 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define UFS_HISI_LIMIT_HSGEAR_RX UFS_HS_G3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define UFS_HISI_LIMIT_HSGEAR_TX UFS_HS_G3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define UFS_HISI_LIMIT_PWMGEAR_RX UFS_PWM_G4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define UFS_HISI_LIMIT_PWMGEAR_TX UFS_PWM_G4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define UFS_HISI_LIMIT_RX_PWR_PWM SLOW_MODE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define UFS_HISI_LIMIT_TX_PWR_PWM SLOW_MODE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define UFS_HISI_LIMIT_RX_PWR_HS FAST_MODE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define UFS_HISI_LIMIT_TX_PWR_HS FAST_MODE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define UFS_HISI_LIMIT_HS_RATE PA_HS_MODE_B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define UFS_HISI_LIMIT_DESIRED_MODE FAST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define UFS_HISI_CAP_RESERVED BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define UFS_HISI_CAP_PHY10nm BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct ufs_hisi_host {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) struct ufs_hba *hba;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) void __iomem *ufs_sys_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) struct reset_control *rst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) uint64_t caps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) bool in_suspend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define ufs_sys_ctrl_writel(host, val, reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) writel((val), (host)->ufs_sys_ctrl + (reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define ufs_sys_ctrl_readl(host, reg) readl((host)->ufs_sys_ctrl + (reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define ufs_sys_ctrl_set_bits(host, mask, reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) ufs_sys_ctrl_writel( \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) (host), ((mask) | (ufs_sys_ctrl_readl((host), (reg)))), (reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define ufs_sys_ctrl_clr_bits(host, mask, reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) ufs_sys_ctrl_writel((host), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) ((~(mask)) & (ufs_sys_ctrl_readl((host), (reg)))), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) (reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #endif /* UFS_HISI_H_ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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