^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * HiSilicon Hixxxx UFS Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2016-2017 Linaro Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/time.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "ufshcd.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "ufshcd-pltfrm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "unipro.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "ufs-hisi.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "ufshci.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "ufs_quirks.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) static int ufs_hisi_check_hibern8(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) u32 tx_fsm_val_0 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) u32 tx_fsm_val_1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) unsigned long timeout = jiffies + msecs_to_jiffies(HBRN8_POLL_TOUT_MS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) err = ufshcd_dme_get(hba, UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) &tx_fsm_val_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) err |= ufshcd_dme_get(hba,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE, 1), &tx_fsm_val_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) if (err || (tx_fsm_val_0 == TX_FSM_HIBERN8 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) tx_fsm_val_1 == TX_FSM_HIBERN8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /* sleep for max. 200us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) usleep_range(100, 200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) } while (time_before(jiffies, timeout));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * we might have scheduled out for long during polling so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * check the state again.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) if (time_after(jiffies, timeout)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) err = ufshcd_dme_get(hba, UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) &tx_fsm_val_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) err |= ufshcd_dme_get(hba,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE, 1), &tx_fsm_val_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) dev_err(hba->dev, "%s: unable to get TX_FSM_STATE, err %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) __func__, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) } else if (tx_fsm_val_0 != TX_FSM_HIBERN8 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) tx_fsm_val_1 != TX_FSM_HIBERN8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) err = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) dev_err(hba->dev, "%s: invalid TX_FSM_STATE, lane0 = %d, lane1 = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) __func__, tx_fsm_val_0, tx_fsm_val_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) static void ufs_hisi_clk_init(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) struct ufs_hisi_host *host = ufshcd_get_variant(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) ufs_sys_ctrl_clr_bits(host, BIT_SYSCTRL_REF_CLOCK_EN, PHY_CLK_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) if (ufs_sys_ctrl_readl(host, PHY_CLK_CTRL) & BIT_SYSCTRL_REF_CLOCK_EN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) mdelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* use abb clk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) ufs_sys_ctrl_clr_bits(host, BIT_UFS_REFCLK_SRC_SEl, UFS_SYSCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) ufs_sys_ctrl_clr_bits(host, BIT_UFS_REFCLK_ISO_EN, PHY_ISO_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* open mphy ref clk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) ufs_sys_ctrl_set_bits(host, BIT_SYSCTRL_REF_CLOCK_EN, PHY_CLK_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) static void ufs_hisi_soc_init(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) struct ufs_hisi_host *host = ufshcd_get_variant(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) if (!IS_ERR(host->rst))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) reset_control_assert(host->rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /* HC_PSW powerup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) ufs_sys_ctrl_set_bits(host, BIT_UFS_PSW_MTCMOS_EN, PSW_POWER_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /* notify PWR ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) ufs_sys_ctrl_set_bits(host, BIT_SYSCTRL_PWR_READY, HC_LP_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) ufs_sys_ctrl_writel(host, MASK_UFS_DEVICE_RESET | 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) UFS_DEVICE_RESET_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) reg = ufs_sys_ctrl_readl(host, PHY_CLK_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) reg = (reg & ~MASK_SYSCTRL_CFG_CLOCK_FREQ) | UFS_FREQ_CFG_CLK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /* set cfg clk freq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) ufs_sys_ctrl_writel(host, reg, PHY_CLK_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /* set ref clk freq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) ufs_sys_ctrl_clr_bits(host, MASK_SYSCTRL_REF_CLOCK_SEL, PHY_CLK_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /* bypass ufs clk gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) ufs_sys_ctrl_set_bits(host, MASK_UFS_CLK_GATE_BYPASS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) CLOCK_GATE_BYPASS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) ufs_sys_ctrl_set_bits(host, MASK_UFS_SYSCRTL_BYPASS, UFS_SYSCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* open psw clk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) ufs_sys_ctrl_set_bits(host, BIT_SYSCTRL_PSW_CLK_EN, PSW_CLK_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /* disable ufshc iso */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) ufs_sys_ctrl_clr_bits(host, BIT_UFS_PSW_ISO_CTRL, PSW_POWER_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /* disable phy iso */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) ufs_sys_ctrl_clr_bits(host, BIT_UFS_PHY_ISO_CTRL, PHY_ISO_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* notice iso disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) ufs_sys_ctrl_clr_bits(host, BIT_SYSCTRL_LP_ISOL_EN, HC_LP_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /* disable lp_reset_n */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) ufs_sys_ctrl_set_bits(host, BIT_SYSCTRL_LP_RESET_N, RESET_CTRL_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) mdelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) ufs_sys_ctrl_writel(host, MASK_UFS_DEVICE_RESET | BIT_UFS_DEVICE_RESET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) UFS_DEVICE_RESET_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) msleep(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * enable the fix of linereset recovery,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * and enable rx_reset/tx_rest beat
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * enable ref_clk_en override(bit5) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * override value = 1(bit4), with mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) ufs_sys_ctrl_writel(host, 0x03300330, UFS_DEVICE_RESET_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) if (!IS_ERR(host->rst))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) reset_control_deassert(host->rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static int ufs_hisi_link_startup_pre_change(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) struct ufs_hisi_host *host = ufshcd_get_variant(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) uint32_t value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) uint32_t reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /* Unipro VS_mphy_disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xD0C1, 0x0), 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /* PA_HSSeries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x156A, 0x0), 0x2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /* MPHY CBRATESEL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8114, 0x0), 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /* MPHY CBOVRCTRL2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8121, 0x0), 0x2D);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /* MPHY CBOVRCTRL3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8122, 0x0), 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) if (host->caps & UFS_HISI_CAP_PHY10nm) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /* MPHY CBOVRCTRL4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8127, 0x0), 0x98);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /* MPHY CBOVRCTRL5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8128, 0x0), 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /* Unipro VS_MphyCfgUpdt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xD085, 0x0), 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /* MPHY RXOVRCTRL4 rx0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x800D, 0x4), 0x58);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /* MPHY RXOVRCTRL4 rx1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x800D, 0x5), 0x58);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /* MPHY RXOVRCTRL5 rx0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x800E, 0x4), 0xB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /* MPHY RXOVRCTRL5 rx1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x800E, 0x5), 0xB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /* MPHY RXSQCONTROL rx0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8009, 0x4), 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /* MPHY RXSQCONTROL rx1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8009, 0x5), 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /* Unipro VS_MphyCfgUpdt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xD085, 0x0), 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8113, 0x0), 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xD085, 0x0), 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) if (host->caps & UFS_HISI_CAP_PHY10nm) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) /* RX_Hibern8Time_Capability*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x0092, 0x4), 0xA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /* RX_Hibern8Time_Capability*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x0092, 0x5), 0xA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /* RX_Min_ActivateTime */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x008f, 0x4), 0xA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /* RX_Min_ActivateTime*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x008f, 0x5), 0xA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) /* Tactive RX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x008F, 0x4), 0x7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /* Tactive RX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x008F, 0x5), 0x7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /* Gear3 Synclength */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x0095, 0x4), 0x4F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) /* Gear3 Synclength */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x0095, 0x5), 0x4F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) /* Gear2 Synclength */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x0094, 0x4), 0x4F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) /* Gear2 Synclength */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x0094, 0x5), 0x4F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /* Gear1 Synclength */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x008B, 0x4), 0x4F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) /* Gear1 Synclength */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x008B, 0x5), 0x4F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /* Thibernate Tx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x000F, 0x0), 0x5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /* Thibernate Tx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x000F, 0x1), 0x5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xD085, 0x0), 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /* Unipro VS_mphy_disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) ufshcd_dme_get(hba, UIC_ARG_MIB_SEL(0xD0C1, 0x0), &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) if (value != 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) dev_info(hba->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) "Warring!!! Unipro VS_mphy_disable is 0x%x\n", value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) /* Unipro VS_mphy_disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xD0C1, 0x0), 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) err = ufs_hisi_check_hibern8(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) dev_err(hba->dev, "ufs_hisi_check_hibern8 error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) if (!(host->caps & UFS_HISI_CAP_PHY10nm))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) ufshcd_writel(hba, UFS_HCLKDIV_NORMAL_VALUE, UFS_REG_HCLKDIV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) /* disable auto H8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) reg = ufshcd_readl(hba, REG_AUTO_HIBERNATE_IDLE_TIMER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) reg = reg & (~UFS_AHIT_AH8ITV_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) ufshcd_writel(hba, reg, REG_AUTO_HIBERNATE_IDLE_TIMER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /* Unipro PA_Local_TX_LCC_Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) ufshcd_disable_host_tx_lcc(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) /* close Unipro VS_Mk2ExtnSupport */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xD0AB, 0x0), 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) ufshcd_dme_get(hba, UIC_ARG_MIB_SEL(0xD0AB, 0x0), &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) if (value != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) /* Ensure close success */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) dev_info(hba->dev, "WARN: close VS_Mk2ExtnSupport failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) static int ufs_hisi_link_startup_post_change(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) struct ufs_hisi_host *host = ufshcd_get_variant(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) /* Unipro DL_AFC0CreditThreshold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) ufshcd_dme_set(hba, UIC_ARG_MIB(0x2044), 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) /* Unipro DL_TC0OutAckThreshold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) ufshcd_dme_set(hba, UIC_ARG_MIB(0x2045), 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) /* Unipro DL_TC0TXFCThreshold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) ufshcd_dme_set(hba, UIC_ARG_MIB(0x2040), 0x9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) /* not bypass ufs clk gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) ufs_sys_ctrl_clr_bits(host, MASK_UFS_CLK_GATE_BYPASS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) CLOCK_GATE_BYPASS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) ufs_sys_ctrl_clr_bits(host, MASK_UFS_SYSCRTL_BYPASS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) UFS_SYSCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) /* select received symbol cnt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) ufshcd_dme_set(hba, UIC_ARG_MIB(0xd09a), 0x80000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) /* reset counter0 and enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) ufshcd_dme_set(hba, UIC_ARG_MIB(0xd09c), 0x00000005);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) static int ufs_hisi_link_startup_notify(struct ufs_hba *hba,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) enum ufs_notify_change_status status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) switch (status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) case PRE_CHANGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) err = ufs_hisi_link_startup_pre_change(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) case POST_CHANGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) err = ufs_hisi_link_startup_post_change(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) static void ufs_hisi_set_dev_cap(struct ufs_dev_params *hisi_param)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) hisi_param->rx_lanes = UFS_HISI_LIMIT_NUM_LANES_RX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) hisi_param->tx_lanes = UFS_HISI_LIMIT_NUM_LANES_TX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) hisi_param->hs_rx_gear = UFS_HISI_LIMIT_HSGEAR_RX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) hisi_param->hs_tx_gear = UFS_HISI_LIMIT_HSGEAR_TX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) hisi_param->pwm_rx_gear = UFS_HISI_LIMIT_PWMGEAR_RX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) hisi_param->pwm_tx_gear = UFS_HISI_LIMIT_PWMGEAR_TX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) hisi_param->rx_pwr_pwm = UFS_HISI_LIMIT_RX_PWR_PWM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) hisi_param->tx_pwr_pwm = UFS_HISI_LIMIT_TX_PWR_PWM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) hisi_param->rx_pwr_hs = UFS_HISI_LIMIT_RX_PWR_HS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) hisi_param->tx_pwr_hs = UFS_HISI_LIMIT_TX_PWR_HS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) hisi_param->hs_rate = UFS_HISI_LIMIT_HS_RATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) hisi_param->desired_working_mode = UFS_HISI_LIMIT_DESIRED_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) static void ufs_hisi_pwr_change_pre_change(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) struct ufs_hisi_host *host = ufshcd_get_variant(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) if (host->caps & UFS_HISI_CAP_PHY10nm) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) * Boston platform need to set SaveConfigTime to 0x13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) * and change sync length to maximum value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) /* VS_DebugSaveConfigTime */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) ufshcd_dme_set(hba, UIC_ARG_MIB((u32)0xD0A0), 0x13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) /* g1 sync length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) ufshcd_dme_set(hba, UIC_ARG_MIB((u32)0x1552), 0x4f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) /* g2 sync length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) ufshcd_dme_set(hba, UIC_ARG_MIB((u32)0x1554), 0x4f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) /* g3 sync length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) ufshcd_dme_set(hba, UIC_ARG_MIB((u32)0x1556), 0x4f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) /* PA_Hibern8Time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) ufshcd_dme_set(hba, UIC_ARG_MIB((u32)0x15a7), 0xA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) /* PA_Tactivate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) ufshcd_dme_set(hba, UIC_ARG_MIB((u32)0x15a8), 0xA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xd085, 0x0), 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) if (hba->dev_quirks & UFS_DEVICE_QUIRK_HOST_VS_DEBUGSAVECONFIGTIME) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) pr_info("ufs flash device must set VS_DebugSaveConfigTime 0x10\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) /* VS_DebugSaveConfigTime */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) ufshcd_dme_set(hba, UIC_ARG_MIB(0xD0A0), 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) /* sync length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) ufshcd_dme_set(hba, UIC_ARG_MIB(0x1556), 0x48);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) /* update */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) ufshcd_dme_set(hba, UIC_ARG_MIB(0x15A8), 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) /* PA_TxSkip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) ufshcd_dme_set(hba, UIC_ARG_MIB(0x155c), 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) /*PA_PWRModeUserData0 = 8191, default is 0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) ufshcd_dme_set(hba, UIC_ARG_MIB(0x15b0), 8191);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) /*PA_PWRModeUserData1 = 65535, default is 0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) ufshcd_dme_set(hba, UIC_ARG_MIB(0x15b1), 65535);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) /*PA_PWRModeUserData2 = 32767, default is 0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) ufshcd_dme_set(hba, UIC_ARG_MIB(0x15b2), 32767);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) /*DME_FC0ProtectionTimeOutVal = 8191, default is 0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) ufshcd_dme_set(hba, UIC_ARG_MIB(0xd041), 8191);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) /*DME_TC0ReplayTimeOutVal = 65535, default is 0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) ufshcd_dme_set(hba, UIC_ARG_MIB(0xd042), 65535);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) /*DME_AFC0ReqTimeOutVal = 32767, default is 0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) ufshcd_dme_set(hba, UIC_ARG_MIB(0xd043), 32767);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) /*PA_PWRModeUserData3 = 8191, default is 0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) ufshcd_dme_set(hba, UIC_ARG_MIB(0x15b3), 8191);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) /*PA_PWRModeUserData4 = 65535, default is 0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) ufshcd_dme_set(hba, UIC_ARG_MIB(0x15b4), 65535);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) /*PA_PWRModeUserData5 = 32767, default is 0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) ufshcd_dme_set(hba, UIC_ARG_MIB(0x15b5), 32767);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) /*DME_FC1ProtectionTimeOutVal = 8191, default is 0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) ufshcd_dme_set(hba, UIC_ARG_MIB(0xd044), 8191);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) /*DME_TC1ReplayTimeOutVal = 65535, default is 0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) ufshcd_dme_set(hba, UIC_ARG_MIB(0xd045), 65535);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) /*DME_AFC1ReqTimeOutVal = 32767, default is 0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) ufshcd_dme_set(hba, UIC_ARG_MIB(0xd046), 32767);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) static int ufs_hisi_pwr_change_notify(struct ufs_hba *hba,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) enum ufs_notify_change_status status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) struct ufs_pa_layer_attr *dev_max_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) struct ufs_pa_layer_attr *dev_req_params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) struct ufs_dev_params ufs_hisi_cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) if (!dev_req_params) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) dev_err(hba->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) "%s: incoming dev_req_params is NULL\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) switch (status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) case PRE_CHANGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) ufs_hisi_set_dev_cap(&ufs_hisi_cap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) ret = ufshcd_get_pwr_dev_param(&ufs_hisi_cap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) dev_max_params, dev_req_params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) dev_err(hba->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) "%s: failed to determine capabilities\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) ufs_hisi_pwr_change_pre_change(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) case POST_CHANGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) static int ufs_hisi_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) struct ufs_hisi_host *host = ufshcd_get_variant(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) if (ufshcd_is_runtime_pm(pm_op))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) if (host->in_suspend) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) WARN_ON(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) ufs_sys_ctrl_clr_bits(host, BIT_SYSCTRL_REF_CLOCK_EN, PHY_CLK_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) /* set ref_dig_clk override of PHY PCS to 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) ufs_sys_ctrl_writel(host, 0x00100000, UFS_DEVICE_RESET_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) host->in_suspend = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) static int ufs_hisi_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) struct ufs_hisi_host *host = ufshcd_get_variant(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) if (!host->in_suspend)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) /* set ref_dig_clk override of PHY PCS to 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) ufs_sys_ctrl_writel(host, 0x00100010, UFS_DEVICE_RESET_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) ufs_sys_ctrl_set_bits(host, BIT_SYSCTRL_REF_CLOCK_EN, PHY_CLK_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) host->in_suspend = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) static int ufs_hisi_get_resource(struct ufs_hisi_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) struct device *dev = host->hba->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) struct platform_device *pdev = to_platform_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) /* get resource of ufs sys ctrl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) host->ufs_sys_ctrl = devm_platform_ioremap_resource(pdev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) return PTR_ERR_OR_ZERO(host->ufs_sys_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) static void ufs_hisi_set_pm_lvl(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) hba->rpm_lvl = UFS_PM_LVL_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) hba->spm_lvl = UFS_PM_LVL_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) * ufs_hisi_init_common
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) * @hba: host controller instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) static int ufs_hisi_init_common(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) struct device *dev = hba->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) struct ufs_hisi_host *host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) if (!host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) host->hba = hba;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) ufshcd_set_variant(hba, host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) host->rst = devm_reset_control_get(dev, "rst");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) if (IS_ERR(host->rst)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) dev_err(dev, "%s: failed to get reset control\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) err = PTR_ERR(host->rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) ufs_hisi_set_pm_lvl(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) err = ufs_hisi_get_resource(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) ufshcd_set_variant(hba, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) static int ufs_hi3660_init(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) struct device *dev = hba->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) ret = ufs_hisi_init_common(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) dev_err(dev, "%s: ufs common init fail\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) ufs_hisi_clk_init(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) ufs_hisi_soc_init(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) static int ufs_hi3670_init(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) struct device *dev = hba->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) struct ufs_hisi_host *host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) ret = ufs_hisi_init_common(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) dev_err(dev, "%s: ufs common init fail\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) ufs_hisi_clk_init(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) ufs_hisi_soc_init(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) /* Add cap for 10nm PHY variant on HI3670 SoC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) host = ufshcd_get_variant(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) host->caps |= UFS_HISI_CAP_PHY10nm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) static const struct ufs_hba_variant_ops ufs_hba_hi3660_vops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) .name = "hi3660",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) .init = ufs_hi3660_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) .link_startup_notify = ufs_hisi_link_startup_notify,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) .pwr_change_notify = ufs_hisi_pwr_change_notify,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) .suspend = ufs_hisi_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) .resume = ufs_hisi_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) static const struct ufs_hba_variant_ops ufs_hba_hi3670_vops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) .name = "hi3670",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) .init = ufs_hi3670_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) .link_startup_notify = ufs_hisi_link_startup_notify,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) .pwr_change_notify = ufs_hisi_pwr_change_notify,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) .suspend = ufs_hisi_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) .resume = ufs_hisi_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) static const struct of_device_id ufs_hisi_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) { .compatible = "hisilicon,hi3660-ufs", .data = &ufs_hba_hi3660_vops },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) { .compatible = "hisilicon,hi3670-ufs", .data = &ufs_hba_hi3670_vops },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) MODULE_DEVICE_TABLE(of, ufs_hisi_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) static int ufs_hisi_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) const struct of_device_id *of_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) of_id = of_match_node(ufs_hisi_of_match, pdev->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) return ufshcd_pltfrm_init(pdev, of_id->data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) static int ufs_hisi_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) struct ufs_hba *hba = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) ufshcd_remove(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) static const struct dev_pm_ops ufs_hisi_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) .suspend = ufshcd_pltfrm_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) .resume = ufshcd_pltfrm_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) .runtime_suspend = ufshcd_pltfrm_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) .runtime_resume = ufshcd_pltfrm_runtime_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) .runtime_idle = ufshcd_pltfrm_runtime_idle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) static struct platform_driver ufs_hisi_pltform = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) .probe = ufs_hisi_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) .remove = ufs_hisi_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) .shutdown = ufshcd_pltfrm_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) .name = "ufshcd-hisi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) .pm = &ufs_hisi_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) .of_match_table = of_match_ptr(ufs_hisi_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) module_platform_driver(ufs_hisi_pltform);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) MODULE_ALIAS("platform:ufshcd-hisi");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) MODULE_DESCRIPTION("HiSilicon Hixxxx UFS Driver");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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