Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * UFS Host Controller driver for Exynos specific extensions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2014-2015 Samsung Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #ifndef _UFS_EXYNOS_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #define _UFS_EXYNOS_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  * UNIPRO registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define UNIPRO_DBG_FORCE_DME_CTRL_STATE		0x150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18)  * MIBs for PA debug registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define PA_DBG_CLK_PERIOD	0x9514
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define PA_DBG_TXPHY_CFGUPDT	0x9518
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define PA_DBG_RXPHY_CFGUPDT	0x9519
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define PA_DBG_MODE		0x9529
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define PA_DBG_SKIP_RESET_PHY	0x9539
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define PA_DBG_OV_TM		0x9540
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define PA_DBG_SKIP_LINE_RESET	0x9541
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define PA_DBG_LINE_RESET_REQ	0x9543
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define PA_DBG_OPTION_SUITE	0x9564
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define PA_DBG_OPTION_SUITE_DYN	0x9565
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32)  * MIBs for Transport Layer debug registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define T_DBG_SKIP_INIT_HIBERN8_EXIT	0xc001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37)  * Exynos MPHY attributes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define TX_LINERESET_N_VAL	0x0277
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define TX_LINERESET_N(v)	(((v) >> 10) & 0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define TX_LINERESET_P_VAL	0x027D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define TX_LINERESET_P(v)	(((v) >> 12) & 0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define TX_OV_SLEEP_CNT_TIMER	0x028E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define TX_OV_H8_ENTER_EN	(1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define TX_OV_SLEEP_CNT(v)	(((v) >> 5) & 0x7F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define TX_HIGH_Z_CNT_11_08	0x028C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define TX_HIGH_Z_CNT_H(v)	(((v) >> 8) & 0xF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define TX_HIGH_Z_CNT_07_00	0x028D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define TX_HIGH_Z_CNT_L(v)	((v) & 0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define TX_BASE_NVAL_07_00	0x0293
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define TX_BASE_NVAL_L(v)	((v) & 0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define TX_BASE_NVAL_15_08	0x0294
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define TX_BASE_NVAL_H(v)	(((v) >> 8) & 0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define TX_GRAN_NVAL_07_00	0x0295
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define TX_GRAN_NVAL_L(v)	((v) & 0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define TX_GRAN_NVAL_10_08	0x0296
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define TX_GRAN_NVAL_H(v)	(((v) >> 8) & 0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define RX_FILLER_ENABLE	0x0316
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define RX_FILLER_EN		(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define RX_LINERESET_VAL	0x0317
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define RX_LINERESET(v)	(((v) >> 12) & 0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define RX_LCC_IGNORE		0x0318
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define RX_SYNC_MASK_LENGTH	0x0321
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define RX_HIBERN8_WAIT_VAL_BIT_20_16	0x0331
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define RX_HIBERN8_WAIT_VAL_BIT_15_08	0x0332
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define RX_HIBERN8_WAIT_VAL_BIT_07_00	0x0333
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define RX_OV_SLEEP_CNT_TIMER	0x0340
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define RX_OV_SLEEP_CNT(v)	(((v) >> 6) & 0x1F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define RX_OV_STALL_CNT_TIMER	0x0341
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define RX_OV_STALL_CNT(v)	(((v) >> 4) & 0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define RX_BASE_NVAL_07_00	0x0355
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define RX_BASE_NVAL_L(v)	((v) & 0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define RX_BASE_NVAL_15_08	0x0354
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define RX_BASE_NVAL_H(v)	(((v) >> 8) & 0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define RX_GRAN_NVAL_07_00	0x0353
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define RX_GRAN_NVAL_L(v)	((v) & 0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define RX_GRAN_NVAL_10_08	0x0352
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define RX_GRAN_NVAL_H(v)	(((v) >> 8) & 0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define CMN_PWM_CLK_CTRL	0x0402
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define PWM_CLK_CTRL_MASK	0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define IATOVAL_NSEC		20000	/* unit: ns */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define UNIPRO_PCLK_PERIOD(ufs) (NSEC_PER_SEC / ufs->pclk_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) struct exynos_ufs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) /* vendor specific pre-defined parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define SLOW 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define FAST 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define UFS_EXYNOS_LIMIT_NUM_LANES_RX	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define UFS_EXYNOS_LIMIT_NUM_LANES_TX	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define UFS_EXYNOS_LIMIT_HSGEAR_RX	UFS_HS_G3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define UFS_EXYNOS_LIMIT_HSGEAR_TX	UFS_HS_G3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define UFS_EXYNOS_LIMIT_PWMGEAR_RX	UFS_PWM_G4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define UFS_EXYNOS_LIMIT_PWMGEAR_TX	UFS_PWM_G4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define UFS_EXYNOS_LIMIT_RX_PWR_PWM	SLOW_MODE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define UFS_EXYNOS_LIMIT_TX_PWR_PWM	SLOW_MODE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define UFS_EXYNOS_LIMIT_RX_PWR_HS	FAST_MODE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define UFS_EXYNOS_LIMIT_TX_PWR_HS	FAST_MODE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define UFS_EXYNOS_LIMIT_HS_RATE		PA_HS_MODE_B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define UFS_EXYNOS_LIMIT_DESIRED_MODE	FAST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define RX_ADV_FINE_GRAN_SUP_EN	0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define RX_ADV_FINE_GRAN_STEP_VAL	0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define RX_ADV_MIN_ACTV_TIME_CAP	0x9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define PA_GRANULARITY_VAL	0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define PA_TACTIVATE_VAL	0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define PA_HIBERN8TIME_VAL	0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define PCLK_AVAIL_MIN	70000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define PCLK_AVAIL_MAX	133000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct exynos_ufs_uic_attr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	/* TX Attributes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	unsigned int tx_trailingclks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	unsigned int tx_dif_p_nsec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	unsigned int tx_dif_n_nsec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	unsigned int tx_high_z_cnt_nsec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	unsigned int tx_base_unit_nsec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	unsigned int tx_gran_unit_nsec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	unsigned int tx_sleep_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	unsigned int tx_min_activatetime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	/* RX Attributes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	unsigned int rx_filler_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	unsigned int rx_dif_p_nsec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	unsigned int rx_hibern8_wait_nsec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	unsigned int rx_base_unit_nsec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	unsigned int rx_gran_unit_nsec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	unsigned int rx_sleep_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	unsigned int rx_stall_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	unsigned int rx_hs_g1_sync_len_cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	unsigned int rx_hs_g2_sync_len_cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	unsigned int rx_hs_g3_sync_len_cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	unsigned int rx_hs_g1_prep_sync_len_cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	unsigned int rx_hs_g2_prep_sync_len_cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	unsigned int rx_hs_g3_prep_sync_len_cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	/* Common Attributes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	unsigned int cmn_pwm_clk_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	/* Internal Attributes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	unsigned int pa_dbg_option_suite;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	/* Changeable Attributes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	unsigned int rx_adv_fine_gran_sup_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	unsigned int rx_adv_fine_gran_step;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	unsigned int rx_min_actv_time_cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	unsigned int rx_hibern8_time_cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	unsigned int rx_adv_min_actv_time_cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	unsigned int rx_adv_hibern8_time_cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	unsigned int pa_granularity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	unsigned int pa_tactivate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	unsigned int pa_hibern8time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) struct exynos_ufs_drv_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	char *compatible;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	struct exynos_ufs_uic_attr *uic_attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	unsigned int quirks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	unsigned int opts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	/* SoC's specific operations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	int (*drv_init)(struct device *dev, struct exynos_ufs *ufs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	int (*pre_link)(struct exynos_ufs *ufs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	int (*post_link)(struct exynos_ufs *ufs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	int (*pre_pwr_change)(struct exynos_ufs *ufs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 				struct ufs_pa_layer_attr *pwr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	int (*post_pwr_change)(struct exynos_ufs *ufs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 				struct ufs_pa_layer_attr *pwr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) struct ufs_phy_time_cfg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	u32 tx_linereset_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	u32 tx_linereset_n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	u32 tx_high_z_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	u32 tx_base_n_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	u32 tx_gran_n_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	u32 tx_sleep_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	u32 rx_linereset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	u32 rx_hibern8_wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	u32 rx_base_n_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	u32 rx_gran_n_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	u32 rx_sleep_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	u32 rx_stall_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) struct exynos_ufs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	struct ufs_hba *hba;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	struct phy *phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	void __iomem *reg_hci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	void __iomem *reg_unipro;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	void __iomem *reg_ufsp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	struct clk *clk_hci_core;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	struct clk *clk_unipro_main;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	struct clk *clk_apb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	u32 pclk_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	u32 pclk_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	u32 pclk_avail_min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	u32 pclk_avail_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	unsigned long mclk_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	int avail_ln_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	int avail_ln_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	int rx_sel_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	struct ufs_pa_layer_attr dev_req_params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	struct ufs_phy_time_cfg t_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	ktime_t entry_hibern8_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	struct exynos_ufs_drv_data *drv_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	u32 opts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define EXYNOS_UFS_OPT_HAS_APB_CLK_CTRL		BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define EXYNOS_UFS_OPT_SKIP_CONNECTION_ESTAB	BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL	BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define EXYNOS_UFS_OPT_BROKEN_RX_SEL_IDX	BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define EXYNOS_UFS_OPT_USE_SW_HIBERN8_TIMER	BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define for_each_ufs_rx_lane(ufs, i) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	for (i = (ufs)->rx_sel_idx; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 		i < (ufs)->rx_sel_idx + (ufs)->avail_ln_rx; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define for_each_ufs_tx_lane(ufs, i) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	for (i = 0; i < (ufs)->avail_ln_tx; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define EXYNOS_UFS_MMIO_FUNC(name)					  \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) static inline void name##_writel(struct exynos_ufs *ufs, u32 val, u32 reg)\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {									  \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	writel(val, ufs->reg_##name + reg);				  \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) }									  \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 									  \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) static inline u32 name##_readl(struct exynos_ufs *ufs, u32 reg)		  \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {									  \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	return readl(ufs->reg_##name + reg);				  \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) EXYNOS_UFS_MMIO_FUNC(hci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) EXYNOS_UFS_MMIO_FUNC(unipro);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) EXYNOS_UFS_MMIO_FUNC(ufsp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #undef EXYNOS_UFS_MMIO_FUNC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) long exynos_ufs_calc_time_cntr(struct exynos_ufs *, long);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) static inline void exynos_ufs_enable_ov_tm(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_OV_TM), TRUE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) static inline void exynos_ufs_disable_ov_tm(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_OV_TM), FALSE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) static inline void exynos_ufs_enable_dbg_mode(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_MODE), TRUE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) static inline void exynos_ufs_disable_dbg_mode(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_MODE), FALSE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) struct exynos_ufs_drv_data exynos_ufs_drvs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) struct exynos_ufs_uic_attr exynos7_uic_attr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	.tx_trailingclks		= 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	.tx_dif_p_nsec			= 3000000,	/* unit: ns */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	.tx_dif_n_nsec			= 1000000,	/* unit: ns */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	.tx_high_z_cnt_nsec		= 20000,	/* unit: ns */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	.tx_base_unit_nsec		= 100000,	/* unit: ns */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	.tx_gran_unit_nsec		= 4000,		/* unit: ns */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	.tx_sleep_cnt			= 1000,		/* unit: ns */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	.tx_min_activatetime		= 0xa,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	.rx_filler_enable		= 0x2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	.rx_dif_p_nsec			= 1000000,	/* unit: ns */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	.rx_hibern8_wait_nsec		= 4000000,	/* unit: ns */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	.rx_base_unit_nsec		= 100000,	/* unit: ns */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	.rx_gran_unit_nsec		= 4000,		/* unit: ns */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	.rx_sleep_cnt			= 1280,		/* unit: ns */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	.rx_stall_cnt			= 320,		/* unit: ns */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	.rx_hs_g1_sync_len_cap		= SYNC_LEN_COARSE(0xf),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	.rx_hs_g2_sync_len_cap		= SYNC_LEN_COARSE(0xf),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	.rx_hs_g3_sync_len_cap		= SYNC_LEN_COARSE(0xf),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	.rx_hs_g1_prep_sync_len_cap	= PREP_LEN(0xf),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	.rx_hs_g2_prep_sync_len_cap	= PREP_LEN(0xf),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	.rx_hs_g3_prep_sync_len_cap	= PREP_LEN(0xf),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	.pa_dbg_option_suite		= 0x30103,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #endif /* _UFS_EXYNOS_H_ */