^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Synopsys G210 Test Chip driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2015-2016 Synopsys, Inc. (www.synopsys.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Authors: Joao Pinto <jpinto@synopsys.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include "ufshcd.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include "unipro.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include "ufshcd-dwc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "ufshci-dwc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "tc-dwc-g210.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * tc_dwc_g210_setup_40bit_rmmi()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * This function configures Synopsys TC specific atributes (40-bit RMMI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * @hba: Pointer to drivers structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * Returns 0 on success or non-zero value on failure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) static int tc_dwc_g210_setup_40bit_rmmi(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) static const struct ufshcd_dme_attr_val setup_attrs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) { UIC_ARG_MIB(TX_GLOBALHIBERNATE), 0x00, DME_LOCAL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) { UIC_ARG_MIB(REFCLKMODE), 0x01, DME_LOCAL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) { UIC_ARG_MIB(CDIRECTCTRL6), 0x80, DME_LOCAL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) { UIC_ARG_MIB(CBDIVFACTOR), 0x08, DME_LOCAL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) { UIC_ARG_MIB(CBDCOCTRL5), 0x64, DME_LOCAL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) { UIC_ARG_MIB(CBPRGTUNING), 0x09, DME_LOCAL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) { UIC_ARG_MIB(RTOBSERVESELECT), 0x00, DME_LOCAL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) { UIC_ARG_MIB_SEL(TX_REFCLKFREQ, SELIND_LN0_TX), 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) DME_LOCAL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) { UIC_ARG_MIB_SEL(TX_CFGCLKFREQVAL, SELIND_LN0_TX), 0x19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) DME_LOCAL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) { UIC_ARG_MIB_SEL(CFGEXTRATTR, SELIND_LN0_TX), 0x14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) DME_LOCAL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) { UIC_ARG_MIB_SEL(DITHERCTRL2, SELIND_LN0_TX), 0xd6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) DME_LOCAL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) { UIC_ARG_MIB_SEL(RX_REFCLKFREQ, SELIND_LN0_RX), 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) DME_LOCAL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) { UIC_ARG_MIB_SEL(RX_CFGCLKFREQVAL, SELIND_LN0_RX), 0x19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) DME_LOCAL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) { UIC_ARG_MIB_SEL(CFGWIDEINLN, SELIND_LN0_RX), 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) DME_LOCAL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) { UIC_ARG_MIB_SEL(CFGRXCDR8, SELIND_LN0_RX), 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) DME_LOCAL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) { UIC_ARG_MIB(DIRECTCTRL10), 0x04, DME_LOCAL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) { UIC_ARG_MIB(DIRECTCTRL19), 0x02, DME_LOCAL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) { UIC_ARG_MIB_SEL(CFGRXCDR8, SELIND_LN0_RX), 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) DME_LOCAL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) { UIC_ARG_MIB_SEL(ENARXDIRECTCFG4, SELIND_LN0_RX), 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) DME_LOCAL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) { UIC_ARG_MIB_SEL(CFGRXOVR8, SELIND_LN0_RX), 0x16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) DME_LOCAL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) { UIC_ARG_MIB_SEL(RXDIRECTCTRL2, SELIND_LN0_RX), 0x42,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) DME_LOCAL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) { UIC_ARG_MIB_SEL(ENARXDIRECTCFG3, SELIND_LN0_RX), 0xa4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) DME_LOCAL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) { UIC_ARG_MIB_SEL(RXCALCTRL, SELIND_LN0_RX), 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) DME_LOCAL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) { UIC_ARG_MIB_SEL(ENARXDIRECTCFG2, SELIND_LN0_RX), 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) DME_LOCAL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) { UIC_ARG_MIB_SEL(CFGRXOVR4, SELIND_LN0_RX), 0x28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) DME_LOCAL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) { UIC_ARG_MIB_SEL(RXSQCTRL, SELIND_LN0_RX), 0x1E,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) DME_LOCAL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) { UIC_ARG_MIB_SEL(CFGRXOVR6, SELIND_LN0_RX), 0x2f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) DME_LOCAL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) { UIC_ARG_MIB_SEL(CFGRXOVR6, SELIND_LN0_RX), 0x2f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) DME_LOCAL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) { UIC_ARG_MIB(CBPRGPLL2), 0x00, DME_LOCAL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) return ufshcd_dwc_dme_set_attrs(hba, setup_attrs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) ARRAY_SIZE(setup_attrs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * tc_dwc_g210_setup_20bit_rmmi_lane0()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * This function configures Synopsys TC 20-bit RMMI Lane 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * @hba: Pointer to drivers structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * Returns 0 on success or non-zero value on failure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static int tc_dwc_g210_setup_20bit_rmmi_lane0(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) static const struct ufshcd_dme_attr_val setup_attrs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) { UIC_ARG_MIB_SEL(TX_REFCLKFREQ, SELIND_LN0_TX), 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) DME_LOCAL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) { UIC_ARG_MIB_SEL(TX_CFGCLKFREQVAL, SELIND_LN0_TX), 0x19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) DME_LOCAL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) { UIC_ARG_MIB_SEL(RX_CFGCLKFREQVAL, SELIND_LN0_RX), 0x19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) DME_LOCAL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) { UIC_ARG_MIB_SEL(CFGEXTRATTR, SELIND_LN0_TX), 0x12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) DME_LOCAL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) { UIC_ARG_MIB_SEL(DITHERCTRL2, SELIND_LN0_TX), 0xd6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) DME_LOCAL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) { UIC_ARG_MIB_SEL(RX_REFCLKFREQ, SELIND_LN0_RX), 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) DME_LOCAL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) { UIC_ARG_MIB_SEL(CFGWIDEINLN, SELIND_LN0_RX), 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) DME_LOCAL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) { UIC_ARG_MIB_SEL(CFGRXCDR8, SELIND_LN0_RX), 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) DME_LOCAL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) { UIC_ARG_MIB(DIRECTCTRL10), 0x04, DME_LOCAL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) { UIC_ARG_MIB(DIRECTCTRL19), 0x02, DME_LOCAL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) { UIC_ARG_MIB_SEL(ENARXDIRECTCFG4, SELIND_LN0_RX), 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) DME_LOCAL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) { UIC_ARG_MIB_SEL(CFGRXOVR8, SELIND_LN0_RX), 0x16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) DME_LOCAL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) { UIC_ARG_MIB_SEL(RXDIRECTCTRL2, SELIND_LN0_RX), 0x42,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) DME_LOCAL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) { UIC_ARG_MIB_SEL(ENARXDIRECTCFG3, SELIND_LN0_RX), 0xa4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) DME_LOCAL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) { UIC_ARG_MIB_SEL(RXCALCTRL, SELIND_LN0_RX), 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) DME_LOCAL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) { UIC_ARG_MIB_SEL(ENARXDIRECTCFG2, SELIND_LN0_RX), 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) DME_LOCAL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) { UIC_ARG_MIB_SEL(CFGRXOVR4, SELIND_LN0_RX), 0x28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) DME_LOCAL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) { UIC_ARG_MIB_SEL(RXSQCTRL, SELIND_LN0_RX), 0x1E,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) DME_LOCAL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) { UIC_ARG_MIB_SEL(CFGRXOVR6, SELIND_LN0_RX), 0x2f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) DME_LOCAL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) { UIC_ARG_MIB(CBPRGPLL2), 0x00, DME_LOCAL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) return ufshcd_dwc_dme_set_attrs(hba, setup_attrs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) ARRAY_SIZE(setup_attrs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * tc_dwc_g210_setup_20bit_rmmi_lane1()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * This function configures Synopsys TC 20-bit RMMI Lane 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) * @hba: Pointer to drivers structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * Returns 0 on success or non-zero value on failure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static int tc_dwc_g210_setup_20bit_rmmi_lane1(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) int connected_rx_lanes = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) int connected_tx_lanes = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static const struct ufshcd_dme_attr_val setup_tx_attrs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) { UIC_ARG_MIB_SEL(TX_REFCLKFREQ, SELIND_LN1_TX), 0x0d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) DME_LOCAL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) { UIC_ARG_MIB_SEL(TX_CFGCLKFREQVAL, SELIND_LN1_TX), 0x19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) DME_LOCAL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) { UIC_ARG_MIB_SEL(CFGEXTRATTR, SELIND_LN1_TX), 0x12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) DME_LOCAL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) { UIC_ARG_MIB_SEL(DITHERCTRL2, SELIND_LN0_TX), 0xd6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) DME_LOCAL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static const struct ufshcd_dme_attr_val setup_rx_attrs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) { UIC_ARG_MIB_SEL(RX_REFCLKFREQ, SELIND_LN1_RX), 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) DME_LOCAL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) { UIC_ARG_MIB_SEL(RX_CFGCLKFREQVAL, SELIND_LN1_RX), 0x19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) DME_LOCAL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) { UIC_ARG_MIB_SEL(CFGWIDEINLN, SELIND_LN1_RX), 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) DME_LOCAL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) { UIC_ARG_MIB_SEL(CFGRXCDR8, SELIND_LN1_RX), 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) DME_LOCAL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) { UIC_ARG_MIB_SEL(ENARXDIRECTCFG4, SELIND_LN1_RX), 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) DME_LOCAL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) { UIC_ARG_MIB_SEL(CFGRXOVR8, SELIND_LN1_RX), 0x16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) DME_LOCAL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) { UIC_ARG_MIB_SEL(RXDIRECTCTRL2, SELIND_LN1_RX), 0x42,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) DME_LOCAL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) { UIC_ARG_MIB_SEL(ENARXDIRECTCFG3, SELIND_LN1_RX), 0xa4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) DME_LOCAL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) { UIC_ARG_MIB_SEL(RXCALCTRL, SELIND_LN1_RX), 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) DME_LOCAL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) { UIC_ARG_MIB_SEL(ENARXDIRECTCFG2, SELIND_LN1_RX), 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) DME_LOCAL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) { UIC_ARG_MIB_SEL(CFGRXOVR4, SELIND_LN1_RX), 0x28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) DME_LOCAL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) { UIC_ARG_MIB_SEL(RXSQCTRL, SELIND_LN1_RX), 0x1E,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) DME_LOCAL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) { UIC_ARG_MIB_SEL(CFGRXOVR6, SELIND_LN1_RX), 0x2f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) DME_LOCAL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) /* Get the available lane count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) ufshcd_dme_get(hba, UIC_ARG_MIB(PA_AVAILRXDATALANES),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) &connected_rx_lanes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) ufshcd_dme_get(hba, UIC_ARG_MIB(PA_AVAILTXDATALANES),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) &connected_tx_lanes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) if (connected_tx_lanes == 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) ret = ufshcd_dwc_dme_set_attrs(hba, setup_tx_attrs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) ARRAY_SIZE(setup_tx_attrs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) if (connected_rx_lanes == 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) ret = ufshcd_dwc_dme_set_attrs(hba, setup_rx_attrs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) ARRAY_SIZE(setup_rx_attrs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) * tc_dwc_g210_setup_20bit_rmmi()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) * This function configures Synopsys TC specific atributes (20-bit RMMI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) * @hba: Pointer to drivers structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) * Returns 0 on success or non-zero value on failure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) static int tc_dwc_g210_setup_20bit_rmmi(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static const struct ufshcd_dme_attr_val setup_attrs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) { UIC_ARG_MIB(TX_GLOBALHIBERNATE), 0x00, DME_LOCAL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) { UIC_ARG_MIB(REFCLKMODE), 0x01, DME_LOCAL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) { UIC_ARG_MIB(CDIRECTCTRL6), 0xc0, DME_LOCAL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) { UIC_ARG_MIB(CBDIVFACTOR), 0x44, DME_LOCAL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) { UIC_ARG_MIB(CBDCOCTRL5), 0x64, DME_LOCAL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) { UIC_ARG_MIB(CBPRGTUNING), 0x09, DME_LOCAL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) { UIC_ARG_MIB(RTOBSERVESELECT), 0x00, DME_LOCAL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) ret = ufshcd_dwc_dme_set_attrs(hba, setup_attrs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) ARRAY_SIZE(setup_attrs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /* Lane 0 configuration*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) ret = tc_dwc_g210_setup_20bit_rmmi_lane0(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) /* Lane 1 configuration*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) ret = tc_dwc_g210_setup_20bit_rmmi_lane1(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) * tc_dwc_g210_config_40_bit()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) * This function configures Local (host) Synopsys 40-bit TC specific attributes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) * @hba: Pointer to drivers structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) * Returns 0 on success non-zero value on failure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) int tc_dwc_g210_config_40_bit(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) dev_info(hba->dev, "Configuring Test Chip 40-bit RMMI\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) ret = tc_dwc_g210_setup_40bit_rmmi(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) dev_err(hba->dev, "Configuration failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) /* To write Shadow register bank to effective configuration block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) ret = ufshcd_dme_set(hba, UIC_ARG_MIB(VS_MPHYCFGUPDT), 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) /* To configure Debug OMC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) ret = ufshcd_dme_set(hba, UIC_ARG_MIB(VS_DEBUGOMC), 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) EXPORT_SYMBOL(tc_dwc_g210_config_40_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) * tc_dwc_g210_config_20_bit()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) * This function configures Local (host) Synopsys 20-bit TC specific attributes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) * @hba: Pointer to drivers structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) * Returns 0 on success non-zero value on failure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) int tc_dwc_g210_config_20_bit(struct ufs_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) dev_info(hba->dev, "Configuring Test Chip 20-bit RMMI\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) ret = tc_dwc_g210_setup_20bit_rmmi(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) dev_err(hba->dev, "Configuration failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) /* To write Shadow register bank to effective configuration block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) ret = ufshcd_dme_set(hba, UIC_ARG_MIB(VS_MPHYCFGUPDT), 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) /* To configure Debug OMC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) ret = ufshcd_dme_set(hba, UIC_ARG_MIB(VS_DEBUGOMC), 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) EXPORT_SYMBOL(tc_dwc_g210_config_20_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) MODULE_AUTHOR("Joao Pinto <Joao.Pinto@synopsys.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) MODULE_DESCRIPTION("Synopsys G210 Test Chip driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) MODULE_LICENSE("Dual BSD/GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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