^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /* sun3x_esp.c: ESP front-end for Sun3x systems.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2007,2008 Thomas Bogendoerfer (tsbogend@alpha.franken.de)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/gfp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <asm/sun3x.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <asm/dma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <asm/dvma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /* DMA controller reg offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define DMA_CSR 0x00UL /* rw DMA control/status register 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define DMA_ADDR 0x04UL /* rw DMA transfer address register 0x04 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define DMA_COUNT 0x08UL /* rw DMA transfer count register 0x08 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define DMA_TEST 0x0cUL /* rw DMA test/debug register 0x0c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <scsi/scsi_host.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include "esp_scsi.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define DRV_MODULE_NAME "sun3x_esp"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define PFX DRV_MODULE_NAME ": "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define DRV_VERSION "1.000"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define DRV_MODULE_RELDATE "Nov 1, 2007"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * m68k always assumes readl/writel operate on little endian
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * mmio space; this is wrong at least for Sun3x, so we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * need to workaround this until a proper way is found
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define dma_read32(REG) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) readl(esp->dma_regs + (REG))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define dma_write32(VAL, REG) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) writel((VAL), esp->dma_regs + (REG))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define dma_read32(REG) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) *(volatile u32 *)(esp->dma_regs + (REG))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define dma_write32(VAL, REG) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) do { *(volatile u32 *)(esp->dma_regs + (REG)) = (VAL); } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) static void sun3x_esp_write8(struct esp *esp, u8 val, unsigned long reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) writeb(val, esp->regs + (reg * 4UL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) static u8 sun3x_esp_read8(struct esp *esp, unsigned long reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) return readb(esp->regs + (reg * 4UL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static int sun3x_esp_irq_pending(struct esp *esp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) if (dma_read32(DMA_CSR) & (DMA_HNDL_INTR | DMA_HNDL_ERROR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static void sun3x_esp_reset_dma(struct esp *esp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) val = dma_read32(DMA_CSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) dma_write32(val | DMA_RST_SCSI, DMA_CSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) dma_write32(val & ~DMA_RST_SCSI, DMA_CSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* Enable interrupts. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) val = dma_read32(DMA_CSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) dma_write32(val | DMA_INT_ENAB, DMA_CSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) static void sun3x_esp_dma_drain(struct esp *esp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) u32 csr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) int lim;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) csr = dma_read32(DMA_CSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) if (!(csr & DMA_FIFO_ISDRAIN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) dma_write32(csr | DMA_FIFO_STDRAIN, DMA_CSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) lim = 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) while (dma_read32(DMA_CSR) & DMA_FIFO_ISDRAIN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) if (--lim == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) printk(KERN_ALERT PFX "esp%d: DMA will not drain!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) esp->host->unique_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static void sun3x_esp_dma_invalidate(struct esp *esp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) int lim;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) lim = 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) while ((val = dma_read32(DMA_CSR)) & DMA_PEND_READ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) if (--lim == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) printk(KERN_ALERT PFX "esp%d: DMA will not "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) "invalidate!\n", esp->host->unique_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) val &= ~(DMA_ENABLE | DMA_ST_WRITE | DMA_BCNT_ENAB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) val |= DMA_FIFO_INV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) dma_write32(val, DMA_CSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) val &= ~DMA_FIFO_INV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) dma_write32(val, DMA_CSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static void sun3x_esp_send_dma_cmd(struct esp *esp, u32 addr, u32 esp_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) u32 dma_count, int write, u8 cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) u32 csr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) BUG_ON(!(cmd & ESP_CMD_DMA));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) sun3x_esp_write8(esp, (esp_count >> 0) & 0xff, ESP_TCLOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) sun3x_esp_write8(esp, (esp_count >> 8) & 0xff, ESP_TCMED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) csr = dma_read32(DMA_CSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) csr |= DMA_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) if (write)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) csr |= DMA_ST_WRITE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) csr &= ~DMA_ST_WRITE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) dma_write32(csr, DMA_CSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) dma_write32(addr, DMA_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) scsi_esp_cmd(esp, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static int sun3x_esp_dma_error(struct esp *esp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) u32 csr = dma_read32(DMA_CSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) if (csr & DMA_HNDL_ERROR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static const struct esp_driver_ops sun3x_esp_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) .esp_write8 = sun3x_esp_write8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .esp_read8 = sun3x_esp_read8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) .irq_pending = sun3x_esp_irq_pending,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .reset_dma = sun3x_esp_reset_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) .dma_drain = sun3x_esp_dma_drain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) .dma_invalidate = sun3x_esp_dma_invalidate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) .send_dma_cmd = sun3x_esp_send_dma_cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) .dma_error = sun3x_esp_dma_error,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static int esp_sun3x_probe(struct platform_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) struct scsi_host_template *tpnt = &scsi_esp_template;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) struct Scsi_Host *host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) struct esp *esp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) int err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) host = scsi_host_alloc(tpnt, sizeof(struct esp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) if (!host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) host->max_id = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) esp = shost_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) esp->host = host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) esp->dev = &dev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) esp->ops = &sun3x_esp_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) res = platform_get_resource(dev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) if (!res || !res->start)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) goto fail_unlink;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) esp->regs = ioremap(res->start, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) if (!esp->regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) goto fail_unmap_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) res = platform_get_resource(dev, IORESOURCE_MEM, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) if (!res || !res->start)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) goto fail_unmap_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) esp->dma_regs = ioremap(res->start, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) esp->command_block = dma_alloc_coherent(esp->dev, 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) &esp->command_block_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) if (!esp->command_block)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) goto fail_unmap_regs_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) host->irq = err = platform_get_irq(dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) goto fail_unmap_command_block;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) err = request_irq(host->irq, scsi_esp_intr, IRQF_SHARED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) "SUN3X ESP", esp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) goto fail_unmap_command_block;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) esp->scsi_id = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) esp->host->this_id = esp->scsi_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) esp->scsi_id_mask = (1 << esp->scsi_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) esp->cfreq = 20000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) dev_set_drvdata(&dev->dev, esp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) err = scsi_esp_register(esp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) goto fail_free_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) fail_free_irq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) free_irq(host->irq, esp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) fail_unmap_command_block:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) dma_free_coherent(esp->dev, 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) esp->command_block,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) esp->command_block_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) fail_unmap_regs_dma:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) iounmap(esp->dma_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) fail_unmap_regs:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) iounmap(esp->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) fail_unlink:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) scsi_host_put(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) static int esp_sun3x_remove(struct platform_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) struct esp *esp = dev_get_drvdata(&dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) unsigned int irq = esp->host->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) scsi_esp_unregister(esp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) /* Disable interrupts. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) val = dma_read32(DMA_CSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) dma_write32(val & ~DMA_INT_ENAB, DMA_CSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) free_irq(irq, esp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) dma_free_coherent(esp->dev, 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) esp->command_block,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) esp->command_block_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) scsi_host_put(esp->host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static struct platform_driver esp_sun3x_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) .probe = esp_sun3x_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) .remove = esp_sun3x_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) .name = "sun3x_esp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) module_platform_driver(esp_sun3x_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) MODULE_DESCRIPTION("Sun3x ESP SCSI driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) MODULE_AUTHOR("Thomas Bogendoerfer (tsbogend@alpha.franken.de)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) MODULE_VERSION(DRV_VERSION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) MODULE_ALIAS("platform:sun3x_esp");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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