^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Sun3 SCSI stuff by Erik Verbruggen (erik@bigmama.xtdnet.nl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Sun3 DMA routines added by Sam Creasey (sammy@sammy.net)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * VME support added by Sam Creasey
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * TODO: modify this driver to support multiple Sun3 SCSI VME boards
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Adapted from mac_scsinew.c:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * Generic Macintosh NCR5380 driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * Copyright 1998, Michael Schmitz <mschmitz@lbl.gov>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * derived in part from:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * Generic Generic NCR5380 driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * Copyright 1995, Russell King
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/blkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <asm/dvma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <scsi/scsi_host.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /* minimum number of bytes to do dma on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define DMA_MIN_SIZE 129
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /* Definitions for the core NCR5380 driver. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define NCR5380_implementation_fields /* none */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define NCR5380_read(reg) in_8(hostdata->io + (reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define NCR5380_write(reg, value) out_8(hostdata->io + (reg), value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define NCR5380_queue_command sun3scsi_queue_command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define NCR5380_host_reset sun3scsi_host_reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define NCR5380_abort sun3scsi_abort
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define NCR5380_info sun3scsi_info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define NCR5380_dma_xfer_len sun3scsi_dma_xfer_len
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define NCR5380_dma_recv_setup sun3scsi_dma_count
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define NCR5380_dma_send_setup sun3scsi_dma_count
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define NCR5380_dma_residual sun3scsi_dma_residual
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #include "NCR5380.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /* dma regs start at regbase + 8, directly after the NCR regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) struct sun3_dma_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) unsigned short dma_addr_hi; /* vme only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) unsigned short dma_addr_lo; /* vme only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) unsigned short dma_count_hi; /* vme only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) unsigned short dma_count_lo; /* vme only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) unsigned short udc_data; /* udc dma data reg (obio only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) unsigned short udc_addr; /* uda dma addr reg (obio only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) unsigned short fifo_data; /* fifo data reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * holds extra byte on odd dma reads
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) unsigned short fifo_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) unsigned short csr; /* control/status reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) unsigned short bpack_hi; /* vme only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) unsigned short bpack_lo; /* vme only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) unsigned short ivect; /* vme only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) unsigned short fifo_count_hi; /* vme only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* ucd chip specific regs - live in dvma space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct sun3_udc_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) unsigned short rsel; /* select regs to load */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) unsigned short addr_hi; /* high word of addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) unsigned short addr_lo; /* low word */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) unsigned short count; /* words to be xfer'd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) unsigned short mode_hi; /* high word of channel mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) unsigned short mode_lo; /* low word of channel mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /* addresses of the udc registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define UDC_MODE 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define UDC_CSR 0x2e /* command/status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define UDC_CHN_HI 0x26 /* chain high word */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define UDC_CHN_LO 0x22 /* chain lo word */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define UDC_CURA_HI 0x1a /* cur reg A high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define UDC_CURA_LO 0x0a /* cur reg A low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define UDC_CURB_HI 0x12 /* cur reg B high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define UDC_CURB_LO 0x02 /* cur reg B low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define UDC_MODE_HI 0x56 /* mode reg high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define UDC_MODE_LO 0x52 /* mode reg low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define UDC_COUNT 0x32 /* words to xfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /* some udc commands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define UDC_RESET 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define UDC_CHN_START 0xa0 /* start chain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define UDC_INT_ENABLE 0x32 /* channel 1 int on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* udc mode words */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define UDC_MODE_HIWORD 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define UDC_MODE_LSEND 0xc2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define UDC_MODE_LRECV 0xd2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /* udc reg selections */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define UDC_RSEL_SEND 0x282
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define UDC_RSEL_RECV 0x182
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /* bits in csr reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define CSR_DMA_ACTIVE 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define CSR_DMA_CONFLICT 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define CSR_DMA_BUSERR 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define CSR_FIFO_EMPTY 0x400 /* fifo flushed? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define CSR_SDB_INT 0x200 /* sbc interrupt pending */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define CSR_DMA_INT 0x100 /* dma interrupt pending */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define CSR_LEFT 0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define CSR_LEFT_3 0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define CSR_LEFT_2 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define CSR_LEFT_1 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define CSR_PACK_ENABLE 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define CSR_DMA_ENABLE 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define CSR_SEND 0x8 /* 1 = send 0 = recv */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define CSR_FIFO 0x2 /* reset fifo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define CSR_INTR 0x4 /* interrupt enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define CSR_SCSI 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define VME_DATA24 0x3d00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) extern int sun3_map_test(unsigned long, char *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static int setup_can_queue = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) module_param(setup_can_queue, int, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static int setup_cmd_per_lun = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) module_param(setup_cmd_per_lun, int, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static int setup_sg_tablesize = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) module_param(setup_sg_tablesize, int, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static int setup_hostid = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) module_param(setup_hostid, int, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /* ms to wait after hitting dma regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define SUN3_DMA_DELAY 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /* dvma buffer to allocate -- 32k should hopefully be more than sufficient */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define SUN3_DVMA_BUFSIZE 0xe000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static struct scsi_cmnd *sun3_dma_setup_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static volatile struct sun3_dma_regs *dregs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static struct sun3_udc_regs *udc_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static unsigned char *sun3_dma_orig_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static unsigned long sun3_dma_orig_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static int sun3_dma_active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static unsigned long last_residual;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #ifndef SUN3_SCSI_VME
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /* dma controller register access functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static inline unsigned short sun3_udc_read(unsigned char reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) unsigned short ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) dregs->udc_addr = UDC_CSR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) udelay(SUN3_DMA_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) ret = dregs->udc_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) udelay(SUN3_DMA_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static inline void sun3_udc_write(unsigned short val, unsigned char reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) dregs->udc_addr = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) udelay(SUN3_DMA_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) dregs->udc_data = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) udelay(SUN3_DMA_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) // safe bits for the CSR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define CSR_GOOD 0x060f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) static irqreturn_t scsi_sun3_intr(int irq, void *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) struct Scsi_Host *instance = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) unsigned short csr = dregs->csr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) int handled = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #ifdef SUN3_SCSI_VME
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) dregs->csr &= ~CSR_DMA_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) if(csr & ~CSR_GOOD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) if (csr & CSR_DMA_BUSERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) shost_printk(KERN_ERR, instance, "bus error in DMA\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) if (csr & CSR_DMA_CONFLICT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) shost_printk(KERN_ERR, instance, "DMA conflict\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) handled = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) if(csr & (CSR_SDB_INT | CSR_DMA_INT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) NCR5380_intr(irq, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) handled = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) return IRQ_RETVAL(handled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) /* sun3scsi_dma_setup() -- initialize the dma controller for a read/write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static int sun3scsi_dma_setup(struct NCR5380_hostdata *hostdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) unsigned char *data, int count, int write_flag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) void *addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) if(sun3_dma_orig_addr != NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) dvma_unmap(sun3_dma_orig_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #ifdef SUN3_SCSI_VME
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) addr = (void *)dvma_map_vme((unsigned long) data, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) addr = (void *)dvma_map((unsigned long) data, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) sun3_dma_orig_addr = addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) sun3_dma_orig_count = count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #ifndef SUN3_SCSI_VME
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) dregs->fifo_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) sun3_udc_write(UDC_RESET, UDC_CSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) /* reset fifo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) dregs->csr &= ~CSR_FIFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) dregs->csr |= CSR_FIFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /* set direction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) if(write_flag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) dregs->csr |= CSR_SEND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) dregs->csr &= ~CSR_SEND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #ifdef SUN3_SCSI_VME
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) dregs->csr |= CSR_PACK_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) dregs->dma_addr_hi = ((unsigned long)addr >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) dregs->dma_addr_lo = ((unsigned long)addr & 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) dregs->dma_count_hi = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) dregs->dma_count_lo = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) dregs->fifo_count_hi = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) dregs->fifo_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) /* byte count for fifo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) dregs->fifo_count = count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) sun3_udc_write(UDC_RESET, UDC_CSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) /* reset fifo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) dregs->csr &= ~CSR_FIFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) dregs->csr |= CSR_FIFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) if(dregs->fifo_count != count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) shost_printk(KERN_ERR, hostdata->host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) "FIFO mismatch %04x not %04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) dregs->fifo_count, (unsigned int) count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) NCR5380_dprint(NDEBUG_DMA, hostdata->host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) /* setup udc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) udc_regs->addr_hi = (((unsigned long)(addr) & 0xff0000) >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) udc_regs->addr_lo = ((unsigned long)(addr) & 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) udc_regs->count = count/2; /* count in words */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) udc_regs->mode_hi = UDC_MODE_HIWORD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) if(write_flag) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) if(count & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) udc_regs->count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) udc_regs->mode_lo = UDC_MODE_LSEND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) udc_regs->rsel = UDC_RSEL_SEND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) udc_regs->mode_lo = UDC_MODE_LRECV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) udc_regs->rsel = UDC_RSEL_RECV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) /* announce location of regs block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) sun3_udc_write(((dvma_vtob(udc_regs) & 0xff0000) >> 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) UDC_CHN_HI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) sun3_udc_write((dvma_vtob(udc_regs) & 0xffff), UDC_CHN_LO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) /* set dma master on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) sun3_udc_write(0xd, UDC_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) /* interrupt enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) sun3_udc_write(UDC_INT_ENABLE, UDC_CSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) static int sun3scsi_dma_count(struct NCR5380_hostdata *hostdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) unsigned char *data, int count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) static inline int sun3scsi_dma_recv_setup(struct NCR5380_hostdata *hostdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) unsigned char *data, int count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) return sun3scsi_dma_setup(hostdata, data, count, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) static inline int sun3scsi_dma_send_setup(struct NCR5380_hostdata *hostdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) unsigned char *data, int count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) return sun3scsi_dma_setup(hostdata, data, count, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) static int sun3scsi_dma_residual(struct NCR5380_hostdata *hostdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) return last_residual;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) static int sun3scsi_dma_xfer_len(struct NCR5380_hostdata *hostdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) struct scsi_cmnd *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) int wanted_len = cmd->SCp.this_residual;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) if (wanted_len < DMA_MIN_SIZE || blk_rq_is_passthrough(cmd->request))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) return wanted_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) static inline int sun3scsi_dma_start(unsigned long count, unsigned char *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #ifdef SUN3_SCSI_VME
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) unsigned short csr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) csr = dregs->csr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) dregs->dma_count_hi = (sun3_dma_orig_count >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) dregs->dma_count_lo = (sun3_dma_orig_count & 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) dregs->fifo_count_hi = (sun3_dma_orig_count >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) dregs->fifo_count = (sun3_dma_orig_count & 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) /* if(!(csr & CSR_DMA_ENABLE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) * dregs->csr |= CSR_DMA_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) sun3_udc_write(UDC_CHN_START, UDC_CSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) /* clean up after our dma is done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) static int sun3scsi_dma_finish(int write_flag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) unsigned short __maybe_unused count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) unsigned short fifo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) sun3_dma_active = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #ifdef SUN3_SCSI_VME
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) dregs->csr &= ~CSR_DMA_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) fifo = dregs->fifo_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) if (write_flag) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) if ((fifo > 0) && (fifo < sun3_dma_orig_count))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) fifo++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) last_residual = fifo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) /* empty bytes from the fifo which didn't make it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) if ((!write_flag) && (dregs->csr & CSR_LEFT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) unsigned char *vaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) vaddr = (unsigned char *)dvma_vmetov(sun3_dma_orig_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) vaddr += (sun3_dma_orig_count - fifo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) vaddr--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) switch (dregs->csr & CSR_LEFT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) case CSR_LEFT_3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) *vaddr = (dregs->bpack_lo & 0xff00) >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) vaddr--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) case CSR_LEFT_2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) *vaddr = (dregs->bpack_hi & 0x00ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) vaddr--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) case CSR_LEFT_1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) *vaddr = (dregs->bpack_hi & 0xff00) >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) // check to empty the fifo on a read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) if(!write_flag) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) int tmo = 20000; /* .2 sec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) while(1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) if(dregs->csr & CSR_FIFO_EMPTY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) if(--tmo <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) printk("sun3scsi: fifo failed to empty!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) dregs->udc_addr = 0x32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) udelay(SUN3_DMA_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) count = 2 * dregs->udc_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) udelay(SUN3_DMA_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) fifo = dregs->fifo_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) last_residual = fifo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) /* empty bytes from the fifo which didn't make it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) if((!write_flag) && (count - fifo) == 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) unsigned short data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) unsigned char *vaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) data = dregs->fifo_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) vaddr = (unsigned char *)dvma_btov(sun3_dma_orig_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) vaddr += (sun3_dma_orig_count - fifo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) vaddr[-2] = (data & 0xff00) >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) vaddr[-1] = (data & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) dvma_unmap(sun3_dma_orig_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) sun3_dma_orig_addr = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) #ifdef SUN3_SCSI_VME
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) dregs->dma_addr_hi = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) dregs->dma_addr_lo = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) dregs->dma_count_hi = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) dregs->dma_count_lo = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) dregs->fifo_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) dregs->fifo_count_hi = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) dregs->csr &= ~CSR_SEND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) /* dregs->csr |= CSR_DMA_ENABLE; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) sun3_udc_write(UDC_RESET, UDC_CSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) dregs->fifo_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) dregs->csr &= ~CSR_SEND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) /* reset fifo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) dregs->csr &= ~CSR_FIFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) dregs->csr |= CSR_FIFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) sun3_dma_setup_done = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) #include "NCR5380.c"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) #ifdef SUN3_SCSI_VME
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) #define SUN3_SCSI_NAME "Sun3 NCR5380 VME SCSI"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) #define DRV_MODULE_NAME "sun3_scsi_vme"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) #define SUN3_SCSI_NAME "Sun3 NCR5380 SCSI"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) #define DRV_MODULE_NAME "sun3_scsi"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) #define PFX DRV_MODULE_NAME ": "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) static struct scsi_host_template sun3_scsi_template = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) .module = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) .proc_name = DRV_MODULE_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) .name = SUN3_SCSI_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) .info = sun3scsi_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) .queuecommand = sun3scsi_queue_command,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) .eh_abort_handler = sun3scsi_abort,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) .eh_host_reset_handler = sun3scsi_host_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) .can_queue = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) .this_id = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) .sg_tablesize = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) .cmd_per_lun = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) .dma_boundary = PAGE_SIZE - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) .cmd_size = NCR5380_CMD_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) static int __init sun3_scsi_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) struct Scsi_Host *instance;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) struct NCR5380_hostdata *hostdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) struct resource *irq, *mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) void __iomem *ioaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) int host_flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) #ifdef SUN3_SCSI_VME
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) if (setup_can_queue > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) sun3_scsi_template.can_queue = setup_can_queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) if (setup_cmd_per_lun > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) sun3_scsi_template.cmd_per_lun = setup_cmd_per_lun;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) if (setup_sg_tablesize > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) sun3_scsi_template.sg_tablesize = setup_sg_tablesize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) if (setup_hostid >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) sun3_scsi_template.this_id = setup_hostid & 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) #ifdef SUN3_SCSI_VME
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) ioaddr = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) for (i = 0; i < 2; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) unsigned char x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) irq = platform_get_resource(pdev, IORESOURCE_IRQ, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) mem = platform_get_resource(pdev, IORESOURCE_MEM, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) if (!irq || !mem)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) ioaddr = sun3_ioremap(mem->start, resource_size(mem),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) SUN3_PAGE_TYPE_VME16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) dregs = (struct sun3_dma_regs *)(ioaddr + 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) if (sun3_map_test((unsigned long)dregs, &x)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) unsigned short oldcsr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) oldcsr = dregs->csr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) dregs->csr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) udelay(SUN3_DMA_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) if (dregs->csr == 0x1400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) dregs->csr = oldcsr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) iounmap(ioaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) ioaddr = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) if (!ioaddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) if (!irq || !mem)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) ioaddr = ioremap(mem->start, resource_size(mem));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) dregs = (struct sun3_dma_regs *)(ioaddr + 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) udc_regs = dvma_malloc(sizeof(struct sun3_udc_regs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) if (!udc_regs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) pr_err(PFX "couldn't allocate DVMA memory!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) iounmap(ioaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) instance = scsi_host_alloc(&sun3_scsi_template,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) sizeof(struct NCR5380_hostdata));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) if (!instance) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) error = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) goto fail_alloc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) instance->irq = irq->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) hostdata = shost_priv(instance);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) hostdata->base = mem->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) hostdata->io = ioaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) error = NCR5380_init(instance, host_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) goto fail_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) error = request_irq(instance->irq, scsi_sun3_intr, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) "NCR5380", instance);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) if (error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) pr_err(PFX "scsi%d: IRQ %d not free, bailing out\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) instance->host_no, instance->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) goto fail_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) dregs->csr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) udelay(SUN3_DMA_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) dregs->csr = CSR_SCSI | CSR_FIFO | CSR_INTR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) udelay(SUN3_DMA_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) dregs->fifo_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) #ifdef SUN3_SCSI_VME
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) dregs->fifo_count_hi = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) dregs->dma_addr_hi = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) dregs->dma_addr_lo = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) dregs->dma_count_hi = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) dregs->dma_count_lo = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) dregs->ivect = VME_DATA24 | (instance->irq & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) NCR5380_maybe_reset_bus(instance);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) error = scsi_add_host(instance, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) goto fail_host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) platform_set_drvdata(pdev, instance);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) scsi_scan_host(instance);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) fail_host:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) free_irq(instance->irq, instance);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) fail_irq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) NCR5380_exit(instance);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) fail_init:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) scsi_host_put(instance);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) fail_alloc:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) if (udc_regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) dvma_free(udc_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) iounmap(ioaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) static int __exit sun3_scsi_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) struct Scsi_Host *instance = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) struct NCR5380_hostdata *hostdata = shost_priv(instance);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) void __iomem *ioaddr = hostdata->io;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) scsi_remove_host(instance);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) free_irq(instance->irq, instance);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) NCR5380_exit(instance);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) scsi_host_put(instance);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) if (udc_regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) dvma_free(udc_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) iounmap(ioaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) static struct platform_driver sun3_scsi_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) .remove = __exit_p(sun3_scsi_remove),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) .name = DRV_MODULE_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) module_platform_driver_probe(sun3_scsi_driver, sun3_scsi_probe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) MODULE_ALIAS("platform:" DRV_MODULE_NAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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