^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * SuperTrak EX Series Storage Controller driver for Linux
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2005-2015 Promise Technology Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Written By:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Ed Lin <promise_linux@promise.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/time.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/blkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/ktime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/reboot.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <asm/byteorder.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <scsi/scsi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <scsi/scsi_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <scsi/scsi_cmnd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <scsi/scsi_host.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <scsi/scsi_tcq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <scsi/scsi_dbg.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <scsi/scsi_eh.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define DRV_NAME "stex"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define ST_DRIVER_VERSION "6.02.0000.01"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define ST_VER_MAJOR 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define ST_VER_MINOR 02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define ST_OEM 0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define ST_BUILD_VER 01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* MU register offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) IMR0 = 0x10, /* MU_INBOUND_MESSAGE_REG0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) IMR1 = 0x14, /* MU_INBOUND_MESSAGE_REG1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) OMR0 = 0x18, /* MU_OUTBOUND_MESSAGE_REG0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) OMR1 = 0x1c, /* MU_OUTBOUND_MESSAGE_REG1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) IDBL = 0x20, /* MU_INBOUND_DOORBELL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) IIS = 0x24, /* MU_INBOUND_INTERRUPT_STATUS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) IIM = 0x28, /* MU_INBOUND_INTERRUPT_MASK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) ODBL = 0x2c, /* MU_OUTBOUND_DOORBELL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) OIS = 0x30, /* MU_OUTBOUND_INTERRUPT_STATUS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) OIM = 0x3c, /* MU_OUTBOUND_INTERRUPT_MASK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) YIOA_STATUS = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) YH2I_INT = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) YINT_EN = 0x34,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) YI2H_INT = 0x9c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) YI2H_INT_C = 0xa0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) YH2I_REQ = 0xc0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) YH2I_REQ_HI = 0xc4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) PSCRATCH0 = 0xb0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) PSCRATCH1 = 0xb4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) PSCRATCH2 = 0xb8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) PSCRATCH3 = 0xbc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) PSCRATCH4 = 0xc8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) MAILBOX_BASE = 0x1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) MAILBOX_HNDSHK_STS = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /* MU register value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) MU_INBOUND_DOORBELL_HANDSHAKE = (1 << 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) MU_INBOUND_DOORBELL_REQHEADCHANGED = (1 << 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) MU_INBOUND_DOORBELL_STATUSTAILCHANGED = (1 << 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) MU_INBOUND_DOORBELL_HMUSTOPPED = (1 << 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) MU_INBOUND_DOORBELL_RESET = (1 << 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) MU_OUTBOUND_DOORBELL_HANDSHAKE = (1 << 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) MU_OUTBOUND_DOORBELL_REQUESTTAILCHANGED = (1 << 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) MU_OUTBOUND_DOORBELL_STATUSHEADCHANGED = (1 << 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) MU_OUTBOUND_DOORBELL_BUSCHANGE = (1 << 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) MU_OUTBOUND_DOORBELL_HASEVENT = (1 << 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) MU_OUTBOUND_DOORBELL_REQUEST_RESET = (1 << 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /* MU status code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) MU_STATE_STARTING = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) MU_STATE_STARTED = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) MU_STATE_RESETTING = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) MU_STATE_FAILED = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) MU_STATE_STOP = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) MU_STATE_NOCONNECT = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) MU_MAX_DELAY = 50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) MU_HANDSHAKE_SIGNATURE = 0x55aaaa55,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) MU_HANDSHAKE_SIGNATURE_HALF = 0x5a5a0000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) MU_HARD_RESET_WAIT = 30000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) HMU_PARTNER_TYPE = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /* firmware returned values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) SRB_STATUS_SUCCESS = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) SRB_STATUS_ERROR = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) SRB_STATUS_BUSY = 0x05,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) SRB_STATUS_INVALID_REQUEST = 0x06,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) SRB_STATUS_SELECTION_TIMEOUT = 0x0A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) SRB_SEE_SENSE = 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /* task attribute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) TASK_ATTRIBUTE_SIMPLE = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) TASK_ATTRIBUTE_HEADOFQUEUE = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) TASK_ATTRIBUTE_ORDERED = 0x2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) TASK_ATTRIBUTE_ACA = 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) SS_STS_NORMAL = 0x80000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) SS_STS_DONE = 0x40000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) SS_STS_HANDSHAKE = 0x20000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) SS_HEAD_HANDSHAKE = 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) SS_H2I_INT_RESET = 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) SS_I2H_REQUEST_RESET = 0x2000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) SS_MU_OPERATIONAL = 0x80000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) STEX_CDB_LENGTH = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) STATUS_VAR_LEN = 128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /* sg flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) SG_CF_EOT = 0x80, /* end of table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) SG_CF_64B = 0x40, /* 64 bit item */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) SG_CF_HOST = 0x20, /* sg in host memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) MSG_DATA_DIR_ND = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) MSG_DATA_DIR_IN = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) MSG_DATA_DIR_OUT = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) st_shasta = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) st_vsc = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) st_yosemite = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) st_seq = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) st_yel = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) st_P3 = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) PASSTHRU_REQ_TYPE = 0x00000001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) PASSTHRU_REQ_NO_WAKEUP = 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) ST_INTERNAL_TIMEOUT = 180,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) ST_TO_CMD = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) ST_FROM_CMD = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) /* vendor specific commands of Promise */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) MGT_CMD = 0xd8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) SINBAND_MGT_CMD = 0xd9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) ARRAY_CMD = 0xe0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) CONTROLLER_CMD = 0xe1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) DEBUGGING_CMD = 0xe2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) PASSTHRU_CMD = 0xe3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) PASSTHRU_GET_ADAPTER = 0x05,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) PASSTHRU_GET_DRVVER = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) CTLR_CONFIG_CMD = 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) CTLR_SHUTDOWN = 0x0d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) CTLR_POWER_STATE_CHANGE = 0x0e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) CTLR_POWER_SAVING = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) PASSTHRU_SIGNATURE = 0x4e415041,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) MGT_CMD_SIGNATURE = 0xba,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) INQUIRY_EVPD = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) ST_ADDITIONAL_MEM = 0x200000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) ST_ADDITIONAL_MEM_MIN = 0x80000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) PMIC_SHUTDOWN = 0x0D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) PMIC_REUMSE = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) ST_IGNORED = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) ST_NOTHANDLED = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) ST_S3 = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) ST_S4 = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) ST_S5 = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) ST_S6 = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) struct st_sgitem {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) u8 ctrl; /* SG_CF_xxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) u8 reserved[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) __le32 count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) __le64 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) struct st_ss_sgitem {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) __le32 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) __le32 addr_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) __le32 count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) struct st_sgtable {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) __le16 sg_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) __le16 max_sg_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) __le32 sz_in_byte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) struct st_msg_header {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) __le64 handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) u8 flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) u8 channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) __le16 timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) u32 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) struct handshake_frame {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) __le64 rb_phy; /* request payload queue physical address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) __le16 req_sz; /* size of each request payload */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) __le16 req_cnt; /* count of reqs the buffer can hold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) __le16 status_sz; /* size of each status payload */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) __le16 status_cnt; /* count of status the buffer can hold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) __le64 hosttime; /* seconds from Jan 1, 1970 (GMT) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) u8 partner_type; /* who sends this frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) u8 reserved0[7];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) __le32 partner_ver_major;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) __le32 partner_ver_minor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) __le32 partner_ver_oem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) __le32 partner_ver_build;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) __le32 extra_offset; /* NEW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) __le32 extra_size; /* NEW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) __le32 scratch_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) u32 reserved1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) struct req_msg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) __le16 tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) u8 lun;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) u8 target;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) u8 task_attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) u8 task_manage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) u8 data_dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) u8 payload_sz; /* payload size in 4-byte, not used */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) u8 cdb[STEX_CDB_LENGTH];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) u32 variable[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) struct status_msg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) __le16 tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) u8 lun;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) u8 target;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) u8 srb_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) u8 scsi_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) u8 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) u8 payload_sz; /* payload size in 4-byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) u8 variable[STATUS_VAR_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) struct ver_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) u32 major;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) u32 minor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) u32 oem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) u32 build;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) u32 reserved[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) struct st_frame {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) u32 base[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) u32 rom_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) struct ver_info drv_ver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) struct ver_info bios_ver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) u32 bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) u32 slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) u32 irq_level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) u32 irq_vec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) u32 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) u32 subid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) u32 dimm_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) u8 dimm_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) u8 reserved[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) u32 channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) u32 reserved1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) struct st_drvver {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) u32 major;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) u32 minor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) u32 oem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) u32 build;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) u32 signature[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) u8 console_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) u8 host_no;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) u8 reserved0[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) u32 reserved[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) struct st_ccb {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) struct req_msg *req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) struct scsi_cmnd *cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) void *sense_buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) unsigned int sense_bufflen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) int sg_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) u32 req_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) u8 srb_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) u8 scsi_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) u8 reserved[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) struct st_hba {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) void __iomem *mmio_base; /* iomapped PCI memory space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) void *dma_mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) dma_addr_t dma_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) size_t dma_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) struct Scsi_Host *host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) struct pci_dev *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) struct req_msg * (*alloc_rq) (struct st_hba *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) int (*map_sg)(struct st_hba *, struct req_msg *, struct st_ccb *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) void (*send) (struct st_hba *, struct req_msg *, u16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) u32 req_head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) u32 req_tail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) u32 status_head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) u32 status_tail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) struct status_msg *status_buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) void *copy_buffer; /* temp buffer for driver-handled commands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) struct st_ccb *ccb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) struct st_ccb *wait_ccb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) __le32 *scratch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) char work_q_name[20];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) struct workqueue_struct *work_q;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) struct work_struct reset_work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) wait_queue_head_t reset_waitq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) unsigned int mu_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) unsigned int cardtype;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) int msi_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) int out_req_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) u32 extra_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) u16 rq_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) u16 rq_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) u16 sts_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) u8 supports_pm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) int msi_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) struct st_card_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) struct req_msg * (*alloc_rq) (struct st_hba *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) int (*map_sg)(struct st_hba *, struct req_msg *, struct st_ccb *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) void (*send) (struct st_hba *, struct req_msg *, u16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) unsigned int max_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) unsigned int max_lun;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) unsigned int max_channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) u16 rq_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) u16 rq_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) u16 sts_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) static int S6flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) static int stex_halt(struct notifier_block *nb, ulong event, void *buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) static struct notifier_block stex_notifier = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) stex_halt, NULL, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) static int msi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) module_param(msi, int, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) MODULE_PARM_DESC(msi, "Enable Message Signaled Interrupts(0=off, 1=on)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) static const char console_inq_page[] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 0x03,0x00,0x03,0x03,0xFA,0x00,0x00,0x30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 0x50,0x72,0x6F,0x6D,0x69,0x73,0x65,0x20, /* "Promise " */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 0x52,0x41,0x49,0x44,0x20,0x43,0x6F,0x6E, /* "RAID Con" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 0x73,0x6F,0x6C,0x65,0x20,0x20,0x20,0x20, /* "sole " */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 0x31,0x2E,0x30,0x30,0x20,0x20,0x20,0x20, /* "1.00 " */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 0x53,0x58,0x2F,0x52,0x53,0x41,0x46,0x2D, /* "SX/RSAF-" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 0x54,0x45,0x31,0x2E,0x30,0x30,0x20,0x20, /* "TE1.00 " */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 0x0C,0x20,0x20,0x20,0x20,0x20,0x20,0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) MODULE_AUTHOR("Ed Lin");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) MODULE_DESCRIPTION("Promise Technology SuperTrak EX Controllers");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) MODULE_VERSION(ST_DRIVER_VERSION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) static struct status_msg *stex_get_status(struct st_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) struct status_msg *status = hba->status_buffer + hba->status_tail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) ++hba->status_tail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) hba->status_tail %= hba->sts_count+1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) static void stex_invalid_field(struct scsi_cmnd *cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) void (*done)(struct scsi_cmnd *))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) cmd->result = (DRIVER_SENSE << 24) | SAM_STAT_CHECK_CONDITION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) /* "Invalid field in cdb" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) scsi_build_sense_buffer(0, cmd->sense_buffer, ILLEGAL_REQUEST, 0x24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) done(cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) static struct req_msg *stex_alloc_req(struct st_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) struct req_msg *req = hba->dma_mem + hba->req_head * hba->rq_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) ++hba->req_head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) hba->req_head %= hba->rq_count+1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) return req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) static struct req_msg *stex_ss_alloc_req(struct st_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) return (struct req_msg *)(hba->dma_mem +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) hba->req_head * hba->rq_size + sizeof(struct st_msg_header));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) static int stex_map_sg(struct st_hba *hba,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) struct req_msg *req, struct st_ccb *ccb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) struct scsi_cmnd *cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) struct scatterlist *sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) struct st_sgtable *dst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) struct st_sgitem *table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) int i, nseg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) cmd = ccb->cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) nseg = scsi_dma_map(cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) BUG_ON(nseg < 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) if (nseg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) dst = (struct st_sgtable *)req->variable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) ccb->sg_count = nseg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) dst->sg_count = cpu_to_le16((u16)nseg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) dst->max_sg_count = cpu_to_le16(hba->host->sg_tablesize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) dst->sz_in_byte = cpu_to_le32(scsi_bufflen(cmd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) table = (struct st_sgitem *)(dst + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) scsi_for_each_sg(cmd, sg, nseg, i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) table[i].count = cpu_to_le32((u32)sg_dma_len(sg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) table[i].addr = cpu_to_le64(sg_dma_address(sg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) table[i].ctrl = SG_CF_64B | SG_CF_HOST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) table[--i].ctrl |= SG_CF_EOT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) return nseg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) static int stex_ss_map_sg(struct st_hba *hba,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) struct req_msg *req, struct st_ccb *ccb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) struct scsi_cmnd *cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) struct scatterlist *sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) struct st_sgtable *dst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) struct st_ss_sgitem *table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) int i, nseg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) cmd = ccb->cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) nseg = scsi_dma_map(cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) BUG_ON(nseg < 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) if (nseg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) dst = (struct st_sgtable *)req->variable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) ccb->sg_count = nseg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) dst->sg_count = cpu_to_le16((u16)nseg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) dst->max_sg_count = cpu_to_le16(hba->host->sg_tablesize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) dst->sz_in_byte = cpu_to_le32(scsi_bufflen(cmd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) table = (struct st_ss_sgitem *)(dst + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) scsi_for_each_sg(cmd, sg, nseg, i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) table[i].count = cpu_to_le32((u32)sg_dma_len(sg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) table[i].addr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) cpu_to_le32(sg_dma_address(sg) & 0xffffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) table[i].addr_hi =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) cpu_to_le32((sg_dma_address(sg) >> 16) >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) return nseg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) static void stex_controller_info(struct st_hba *hba, struct st_ccb *ccb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) struct st_frame *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) size_t count = sizeof(struct st_frame);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) p = hba->copy_buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) scsi_sg_copy_to_buffer(ccb->cmd, p, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) memset(p->base, 0, sizeof(u32)*6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) *(unsigned long *)(p->base) = pci_resource_start(hba->pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) p->rom_addr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) p->drv_ver.major = ST_VER_MAJOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) p->drv_ver.minor = ST_VER_MINOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) p->drv_ver.oem = ST_OEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) p->drv_ver.build = ST_BUILD_VER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) p->bus = hba->pdev->bus->number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) p->slot = hba->pdev->devfn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) p->irq_level = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) p->irq_vec = hba->pdev->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) p->id = hba->pdev->vendor << 16 | hba->pdev->device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) p->subid =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) hba->pdev->subsystem_vendor << 16 | hba->pdev->subsystem_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) scsi_sg_copy_from_buffer(ccb->cmd, p, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) stex_send_cmd(struct st_hba *hba, struct req_msg *req, u16 tag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) req->tag = cpu_to_le16(tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) hba->ccb[tag].req = req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) hba->out_req_cnt++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) writel(hba->req_head, hba->mmio_base + IMR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) writel(MU_INBOUND_DOORBELL_REQHEADCHANGED, hba->mmio_base + IDBL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) readl(hba->mmio_base + IDBL); /* flush */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) stex_ss_send_cmd(struct st_hba *hba, struct req_msg *req, u16 tag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) struct scsi_cmnd *cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) struct st_msg_header *msg_h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) dma_addr_t addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) req->tag = cpu_to_le16(tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) hba->ccb[tag].req = req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) hba->out_req_cnt++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) cmd = hba->ccb[tag].cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) msg_h = (struct st_msg_header *)req - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) if (likely(cmd)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) msg_h->channel = (u8)cmd->device->channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) msg_h->timeout = cpu_to_le16(cmd->request->timeout/HZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) addr = hba->dma_handle + hba->req_head * hba->rq_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) addr += (hba->ccb[tag].sg_count+4)/11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) msg_h->handle = cpu_to_le64(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) ++hba->req_head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) hba->req_head %= hba->rq_count+1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) if (hba->cardtype == st_P3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) writel((addr >> 16) >> 16, hba->mmio_base + YH2I_REQ_HI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) writel(addr, hba->mmio_base + YH2I_REQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) writel((addr >> 16) >> 16, hba->mmio_base + YH2I_REQ_HI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) readl(hba->mmio_base + YH2I_REQ_HI); /* flush */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) writel(addr, hba->mmio_base + YH2I_REQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) readl(hba->mmio_base + YH2I_REQ); /* flush */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) static void return_abnormal_state(struct st_hba *hba, int status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) struct st_ccb *ccb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) u16 tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) spin_lock_irqsave(hba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) for (tag = 0; tag < hba->host->can_queue; tag++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) ccb = &hba->ccb[tag];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) if (ccb->req == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) ccb->req = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) if (ccb->cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) scsi_dma_unmap(ccb->cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) ccb->cmd->result = status << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) ccb->cmd->scsi_done(ccb->cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) ccb->cmd = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) spin_unlock_irqrestore(hba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) stex_slave_config(struct scsi_device *sdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) sdev->use_10_for_rw = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) sdev->use_10_for_ms = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) blk_queue_rq_timeout(sdev->request_queue, 60 * HZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) stex_queuecommand_lck(struct scsi_cmnd *cmd, void (*done)(struct scsi_cmnd *))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) struct st_hba *hba;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) struct Scsi_Host *host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) unsigned int id, lun;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) struct req_msg *req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) u16 tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) host = cmd->device->host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) id = cmd->device->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) lun = cmd->device->lun;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) hba = (struct st_hba *) &host->hostdata[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) if (hba->mu_status == MU_STATE_NOCONNECT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) cmd->result = DID_NO_CONNECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) done(cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) if (unlikely(hba->mu_status != MU_STATE_STARTED))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) return SCSI_MLQUEUE_HOST_BUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) switch (cmd->cmnd[0]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) case MODE_SENSE_10:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) static char ms10_caching_page[12] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) { 0, 0x12, 0, 0, 0, 0, 0, 0, 0x8, 0xa, 0x4, 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) unsigned char page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) page = cmd->cmnd[2] & 0x3f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) if (page == 0x8 || page == 0x3f) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) scsi_sg_copy_from_buffer(cmd, ms10_caching_page,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) sizeof(ms10_caching_page));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) cmd->result = DID_OK << 16 | COMMAND_COMPLETE << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) done(cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) stex_invalid_field(cmd, done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) case REPORT_LUNS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) * The shasta firmware does not report actual luns in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) * target, so fail the command to force sequential lun scan.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) * Also, the console device does not support this command.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) if (hba->cardtype == st_shasta || id == host->max_id - 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) stex_invalid_field(cmd, done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) case TEST_UNIT_READY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) if (id == host->max_id - 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) cmd->result = DID_OK << 16 | COMMAND_COMPLETE << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) done(cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) case INQUIRY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) if (lun >= host->max_lun) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) cmd->result = DID_NO_CONNECT << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) done(cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) if (id != host->max_id - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) if (!lun && !cmd->device->channel &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) (cmd->cmnd[1] & INQUIRY_EVPD) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) scsi_sg_copy_from_buffer(cmd, (void *)console_inq_page,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) sizeof(console_inq_page));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) cmd->result = DID_OK << 16 | COMMAND_COMPLETE << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) done(cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) stex_invalid_field(cmd, done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) case PASSTHRU_CMD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) if (cmd->cmnd[1] == PASSTHRU_GET_DRVVER) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) struct st_drvver ver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) size_t cp_len = sizeof(ver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) ver.major = ST_VER_MAJOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) ver.minor = ST_VER_MINOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) ver.oem = ST_OEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) ver.build = ST_BUILD_VER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) ver.signature[0] = PASSTHRU_SIGNATURE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) ver.console_id = host->max_id - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) ver.host_no = hba->host->host_no;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) cp_len = scsi_sg_copy_from_buffer(cmd, &ver, cp_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) cmd->result = sizeof(ver) == cp_len ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) DID_OK << 16 | COMMAND_COMPLETE << 8 :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) DID_ERROR << 16 | COMMAND_COMPLETE << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) done(cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) cmd->scsi_done = done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) tag = cmd->request->tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) if (unlikely(tag >= host->can_queue))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) return SCSI_MLQUEUE_HOST_BUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) req = hba->alloc_rq(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) req->lun = lun;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) req->target = id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) /* cdb */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) memcpy(req->cdb, cmd->cmnd, STEX_CDB_LENGTH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) if (cmd->sc_data_direction == DMA_FROM_DEVICE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) req->data_dir = MSG_DATA_DIR_IN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) else if (cmd->sc_data_direction == DMA_TO_DEVICE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) req->data_dir = MSG_DATA_DIR_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) req->data_dir = MSG_DATA_DIR_ND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) hba->ccb[tag].cmd = cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) hba->ccb[tag].sense_bufflen = SCSI_SENSE_BUFFERSIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) hba->ccb[tag].sense_buffer = cmd->sense_buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) if (!hba->map_sg(hba, req, &hba->ccb[tag])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) hba->ccb[tag].sg_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) memset(&req->variable[0], 0, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) hba->send(hba, req, tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) static DEF_SCSI_QCMD(stex_queuecommand)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) static void stex_scsi_done(struct st_ccb *ccb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) struct scsi_cmnd *cmd = ccb->cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) int result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) if (ccb->srb_status == SRB_STATUS_SUCCESS || ccb->srb_status == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) result = ccb->scsi_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) switch (ccb->scsi_status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) case SAM_STAT_GOOD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) result |= DID_OK << 16 | COMMAND_COMPLETE << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) case SAM_STAT_CHECK_CONDITION:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) result |= DRIVER_SENSE << 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) case SAM_STAT_BUSY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) result |= DID_BUS_BUSY << 16 | COMMAND_COMPLETE << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) result |= DID_ERROR << 16 | COMMAND_COMPLETE << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) else if (ccb->srb_status & SRB_SEE_SENSE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) result = DRIVER_SENSE << 24 | SAM_STAT_CHECK_CONDITION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) else switch (ccb->srb_status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) case SRB_STATUS_SELECTION_TIMEOUT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) result = DID_NO_CONNECT << 16 | COMMAND_COMPLETE << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) case SRB_STATUS_BUSY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) result = DID_BUS_BUSY << 16 | COMMAND_COMPLETE << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) case SRB_STATUS_INVALID_REQUEST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) case SRB_STATUS_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) result = DID_ERROR << 16 | COMMAND_COMPLETE << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) cmd->result = result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) cmd->scsi_done(cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) static void stex_copy_data(struct st_ccb *ccb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) struct status_msg *resp, unsigned int variable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) if (resp->scsi_status != SAM_STAT_GOOD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) if (ccb->sense_buffer != NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) memcpy(ccb->sense_buffer, resp->variable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) min(variable, ccb->sense_bufflen));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) if (ccb->cmd == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) scsi_sg_copy_from_buffer(ccb->cmd, resp->variable, variable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) static void stex_check_cmd(struct st_hba *hba,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) struct st_ccb *ccb, struct status_msg *resp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) if (ccb->cmd->cmnd[0] == MGT_CMD &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) resp->scsi_status != SAM_STAT_CHECK_CONDITION)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) scsi_set_resid(ccb->cmd, scsi_bufflen(ccb->cmd) -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) le32_to_cpu(*(__le32 *)&resp->variable[0]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) static void stex_mu_intr(struct st_hba *hba, u32 doorbell)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) void __iomem *base = hba->mmio_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) struct status_msg *resp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) struct st_ccb *ccb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) unsigned int size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) u16 tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) if (unlikely(!(doorbell & MU_OUTBOUND_DOORBELL_STATUSHEADCHANGED)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) /* status payloads */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) hba->status_head = readl(base + OMR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) if (unlikely(hba->status_head > hba->sts_count)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) printk(KERN_WARNING DRV_NAME "(%s): invalid status head\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) pci_name(hba->pdev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) * it's not a valid status payload if:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) * 1. there are no pending requests(e.g. during init stage)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) * 2. there are some pending requests, but the controller is in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) * reset status, and its type is not st_yosemite
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) * firmware of st_yosemite in reset status will return pending requests
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) * to driver, so we allow it to pass
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) if (unlikely(hba->out_req_cnt <= 0 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) (hba->mu_status == MU_STATE_RESETTING &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) hba->cardtype != st_yosemite))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) hba->status_tail = hba->status_head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) goto update_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) while (hba->status_tail != hba->status_head) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) resp = stex_get_status(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) tag = le16_to_cpu(resp->tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) if (unlikely(tag >= hba->host->can_queue)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) printk(KERN_WARNING DRV_NAME
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) "(%s): invalid tag\n", pci_name(hba->pdev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) hba->out_req_cnt--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) ccb = &hba->ccb[tag];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) if (unlikely(hba->wait_ccb == ccb))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) hba->wait_ccb = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) if (unlikely(ccb->req == NULL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) printk(KERN_WARNING DRV_NAME
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) "(%s): lagging req\n", pci_name(hba->pdev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) size = resp->payload_sz * sizeof(u32); /* payload size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) if (unlikely(size < sizeof(*resp) - STATUS_VAR_LEN ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) size > sizeof(*resp))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) printk(KERN_WARNING DRV_NAME "(%s): bad status size\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) pci_name(hba->pdev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) size -= sizeof(*resp) - STATUS_VAR_LEN; /* copy size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) if (size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) stex_copy_data(ccb, resp, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) ccb->req = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) ccb->srb_status = resp->srb_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) ccb->scsi_status = resp->scsi_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) if (likely(ccb->cmd != NULL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) if (hba->cardtype == st_yosemite)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) stex_check_cmd(hba, ccb, resp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) if (unlikely(ccb->cmd->cmnd[0] == PASSTHRU_CMD &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) ccb->cmd->cmnd[1] == PASSTHRU_GET_ADAPTER))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) stex_controller_info(hba, ccb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) scsi_dma_unmap(ccb->cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) stex_scsi_done(ccb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) ccb->req_type = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) update_status:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) writel(hba->status_head, base + IMR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) readl(base + IMR1); /* flush */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) static irqreturn_t stex_intr(int irq, void *__hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) struct st_hba *hba = __hba;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) void __iomem *base = hba->mmio_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) u32 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) spin_lock_irqsave(hba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) data = readl(base + ODBL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) if (data && data != 0xffffffff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) /* clear the interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) writel(data, base + ODBL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) readl(base + ODBL); /* flush */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) stex_mu_intr(hba, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) spin_unlock_irqrestore(hba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) if (unlikely(data & MU_OUTBOUND_DOORBELL_REQUEST_RESET &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) hba->cardtype == st_shasta))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) queue_work(hba->work_q, &hba->reset_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) spin_unlock_irqrestore(hba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) static void stex_ss_mu_intr(struct st_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) struct status_msg *resp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) struct st_ccb *ccb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) __le32 *scratch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) unsigned int size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) int count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) u16 tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) if (unlikely(hba->out_req_cnt <= 0 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) hba->mu_status == MU_STATE_RESETTING))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) while (count < hba->sts_count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) scratch = hba->scratch + hba->status_tail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) value = le32_to_cpu(*scratch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) if (unlikely(!(value & SS_STS_NORMAL)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) resp = hba->status_buffer + hba->status_tail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) *scratch = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) ++count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) ++hba->status_tail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) hba->status_tail %= hba->sts_count+1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) tag = (u16)value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) if (unlikely(tag >= hba->host->can_queue)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) printk(KERN_WARNING DRV_NAME
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) "(%s): invalid tag\n", pci_name(hba->pdev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) hba->out_req_cnt--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) ccb = &hba->ccb[tag];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) if (unlikely(hba->wait_ccb == ccb))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) hba->wait_ccb = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) if (unlikely(ccb->req == NULL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) printk(KERN_WARNING DRV_NAME
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) "(%s): lagging req\n", pci_name(hba->pdev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) ccb->req = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) if (likely(value & SS_STS_DONE)) { /* normal case */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) ccb->srb_status = SRB_STATUS_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) ccb->scsi_status = SAM_STAT_GOOD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) ccb->srb_status = resp->srb_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) ccb->scsi_status = resp->scsi_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) size = resp->payload_sz * sizeof(u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) if (unlikely(size < sizeof(*resp) - STATUS_VAR_LEN ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) size > sizeof(*resp))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) printk(KERN_WARNING DRV_NAME
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) "(%s): bad status size\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) pci_name(hba->pdev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) size -= sizeof(*resp) - STATUS_VAR_LEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) if (size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) stex_copy_data(ccb, resp, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) if (likely(ccb->cmd != NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) stex_check_cmd(hba, ccb, resp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) if (likely(ccb->cmd != NULL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) scsi_dma_unmap(ccb->cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) stex_scsi_done(ccb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) ccb->req_type = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) static irqreturn_t stex_ss_intr(int irq, void *__hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) struct st_hba *hba = __hba;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) void __iomem *base = hba->mmio_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) u32 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) spin_lock_irqsave(hba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) if (hba->cardtype == st_yel) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) data = readl(base + YI2H_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) if (data && data != 0xffffffff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) /* clear the interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) writel(data, base + YI2H_INT_C);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) stex_ss_mu_intr(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) spin_unlock_irqrestore(hba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) if (unlikely(data & SS_I2H_REQUEST_RESET))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) queue_work(hba->work_q, &hba->reset_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) data = readl(base + PSCRATCH4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) if (data != 0xffffffff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) if (data != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) /* clear the interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) writel(data, base + PSCRATCH1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) writel((1 << 22), base + YH2I_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) stex_ss_mu_intr(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) spin_unlock_irqrestore(hba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) if (unlikely(data & SS_I2H_REQUEST_RESET))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) queue_work(hba->work_q, &hba->reset_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) spin_unlock_irqrestore(hba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) static int stex_common_handshake(struct st_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) void __iomem *base = hba->mmio_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) struct handshake_frame *h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) dma_addr_t status_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) u32 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) unsigned long before;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) if (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) writel(MU_INBOUND_DOORBELL_HANDSHAKE, base + IDBL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) readl(base + IDBL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) before = jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) while (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) printk(KERN_ERR DRV_NAME
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) "(%s): no handshake signature\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) pci_name(hba->pdev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) rmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) data = readl(base + OMR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) if ((data & 0xffff0000) == MU_HANDSHAKE_SIGNATURE_HALF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) data &= 0x0000ffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) if (hba->host->can_queue > data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) hba->host->can_queue = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) hba->host->cmd_per_lun = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) h = (struct handshake_frame *)hba->status_buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) h->rb_phy = cpu_to_le64(hba->dma_handle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) h->req_sz = cpu_to_le16(hba->rq_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) h->req_cnt = cpu_to_le16(hba->rq_count+1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) h->status_sz = cpu_to_le16(sizeof(struct status_msg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) h->status_cnt = cpu_to_le16(hba->sts_count+1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) h->hosttime = cpu_to_le64(ktime_get_real_seconds());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) h->partner_type = HMU_PARTNER_TYPE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) if (hba->extra_offset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) h->extra_offset = cpu_to_le32(hba->extra_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) h->extra_size = cpu_to_le32(hba->dma_size - hba->extra_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) h->extra_offset = h->extra_size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) status_phys = hba->dma_handle + (hba->rq_count+1) * hba->rq_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) writel(status_phys, base + IMR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) readl(base + IMR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) writel((status_phys >> 16) >> 16, base + IMR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) readl(base + IMR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) writel((status_phys >> 16) >> 16, base + OMR0); /* old fw compatible */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) readl(base + OMR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) writel(MU_INBOUND_DOORBELL_HANDSHAKE, base + IDBL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) readl(base + IDBL); /* flush */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) before = jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) while (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) printk(KERN_ERR DRV_NAME
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) "(%s): no signature after handshake frame\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) pci_name(hba->pdev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) rmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) writel(0, base + IMR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) readl(base + IMR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) writel(0, base + OMR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) readl(base + OMR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) writel(0, base + IMR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) readl(base + IMR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) writel(0, base + OMR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) readl(base + OMR1); /* flush */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) static int stex_ss_handshake(struct st_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) void __iomem *base = hba->mmio_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) struct st_msg_header *msg_h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) struct handshake_frame *h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) __le32 *scratch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) u32 data, scratch_size, mailboxdata, operationaldata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) unsigned long before;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) before = jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) if (hba->cardtype == st_yel) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) operationaldata = readl(base + YIOA_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) while (operationaldata != SS_MU_OPERATIONAL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) printk(KERN_ERR DRV_NAME
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) "(%s): firmware not operational\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) pci_name(hba->pdev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) operationaldata = readl(base + YIOA_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) operationaldata = readl(base + PSCRATCH3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) while (operationaldata != SS_MU_OPERATIONAL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) printk(KERN_ERR DRV_NAME
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) "(%s): firmware not operational\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) pci_name(hba->pdev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) operationaldata = readl(base + PSCRATCH3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) msg_h = (struct st_msg_header *)hba->dma_mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) msg_h->handle = cpu_to_le64(hba->dma_handle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) msg_h->flag = SS_HEAD_HANDSHAKE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) h = (struct handshake_frame *)(msg_h + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) h->rb_phy = cpu_to_le64(hba->dma_handle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) h->req_sz = cpu_to_le16(hba->rq_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) h->req_cnt = cpu_to_le16(hba->rq_count+1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) h->status_sz = cpu_to_le16(sizeof(struct status_msg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) h->status_cnt = cpu_to_le16(hba->sts_count+1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) h->hosttime = cpu_to_le64(ktime_get_real_seconds());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) h->partner_type = HMU_PARTNER_TYPE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) h->extra_offset = h->extra_size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) scratch_size = (hba->sts_count+1)*sizeof(u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) h->scratch_size = cpu_to_le32(scratch_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) if (hba->cardtype == st_yel) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) data = readl(base + YINT_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) data &= ~4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) writel(data, base + YINT_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) writel((hba->dma_handle >> 16) >> 16, base + YH2I_REQ_HI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) readl(base + YH2I_REQ_HI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) writel(hba->dma_handle, base + YH2I_REQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) readl(base + YH2I_REQ); /* flush */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) data = readl(base + YINT_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) data &= ~(1 << 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) data &= ~(1 << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) writel(data, base + YINT_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) if (hba->msi_lock == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) /* P3 MSI Register cannot access twice */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) writel((1 << 6), base + YH2I_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) hba->msi_lock = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) writel((hba->dma_handle >> 16) >> 16, base + YH2I_REQ_HI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) writel(hba->dma_handle, base + YH2I_REQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) before = jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) scratch = hba->scratch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) if (hba->cardtype == st_yel) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) while (!(le32_to_cpu(*scratch) & SS_STS_HANDSHAKE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) printk(KERN_ERR DRV_NAME
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) "(%s): no signature after handshake frame\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) pci_name(hba->pdev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) ret = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) rmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) mailboxdata = readl(base + MAILBOX_BASE + MAILBOX_HNDSHK_STS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) while (mailboxdata != SS_STS_HANDSHAKE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) printk(KERN_ERR DRV_NAME
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) "(%s): no signature after handshake frame\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) pci_name(hba->pdev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) ret = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) rmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) mailboxdata = readl(base + MAILBOX_BASE + MAILBOX_HNDSHK_STS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) memset(scratch, 0, scratch_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) msg_h->flag = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) static int stex_handshake(struct st_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) unsigned int mu_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) if (hba->cardtype == st_yel || hba->cardtype == st_P3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) err = stex_ss_handshake(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) err = stex_common_handshake(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) spin_lock_irqsave(hba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) mu_status = hba->mu_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) if (err == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) hba->req_head = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) hba->req_tail = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) hba->status_head = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) hba->status_tail = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) hba->out_req_cnt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) hba->mu_status = MU_STATE_STARTED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) hba->mu_status = MU_STATE_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) if (mu_status == MU_STATE_RESETTING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) wake_up_all(&hba->reset_waitq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) spin_unlock_irqrestore(hba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) static int stex_abort(struct scsi_cmnd *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) struct Scsi_Host *host = cmd->device->host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) struct st_hba *hba = (struct st_hba *)host->hostdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) u16 tag = cmd->request->tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) u32 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) int result = SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) scmd_printk(KERN_INFO, cmd, "aborting command\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) base = hba->mmio_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) spin_lock_irqsave(host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) if (tag < host->can_queue &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) hba->ccb[tag].req && hba->ccb[tag].cmd == cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) hba->wait_ccb = &hba->ccb[tag];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) if (hba->cardtype == st_yel) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) data = readl(base + YI2H_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) if (data == 0 || data == 0xffffffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) goto fail_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) writel(data, base + YI2H_INT_C);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) stex_ss_mu_intr(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) } else if (hba->cardtype == st_P3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) data = readl(base + PSCRATCH4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) if (data == 0xffffffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) goto fail_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) if (data != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) writel(data, base + PSCRATCH1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) writel((1 << 22), base + YH2I_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) stex_ss_mu_intr(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) data = readl(base + ODBL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) if (data == 0 || data == 0xffffffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) goto fail_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) writel(data, base + ODBL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) readl(base + ODBL); /* flush */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) stex_mu_intr(hba, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) if (hba->wait_ccb == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) printk(KERN_WARNING DRV_NAME
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) "(%s): lost interrupt\n", pci_name(hba->pdev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) fail_out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) scsi_dma_unmap(cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) hba->wait_ccb->req = NULL; /* nullify the req's future return */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) hba->wait_ccb = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) result = FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) spin_unlock_irqrestore(host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) static void stex_hard_reset(struct st_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) struct pci_bus *bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) u16 pci_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) u8 pci_bctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) for (i = 0; i < 16; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) pci_read_config_dword(hba->pdev, i * 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) &hba->pdev->saved_config_space[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) /* Reset secondary bus. Our controller(MU/ATU) is the only device on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) secondary bus. Consult Intel 80331/3 developer's manual for detail */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) bus = hba->pdev->bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) pci_read_config_byte(bus->self, PCI_BRIDGE_CONTROL, &pci_bctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) pci_bctl |= PCI_BRIDGE_CTL_BUS_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) pci_write_config_byte(bus->self, PCI_BRIDGE_CONTROL, pci_bctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) * 1 ms may be enough for 8-port controllers. But 16-port controllers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) * require more time to finish bus reset. Use 100 ms here for safety
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) msleep(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) pci_bctl &= ~PCI_BRIDGE_CTL_BUS_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) pci_write_config_byte(bus->self, PCI_BRIDGE_CONTROL, pci_bctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) for (i = 0; i < MU_HARD_RESET_WAIT; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) pci_read_config_word(hba->pdev, PCI_COMMAND, &pci_cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) if (pci_cmd != 0xffff && (pci_cmd & PCI_COMMAND_MASTER))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) ssleep(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) for (i = 0; i < 16; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) pci_write_config_dword(hba->pdev, i * 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) hba->pdev->saved_config_space[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) static int stex_yos_reset(struct st_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) unsigned long flags, before;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) base = hba->mmio_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) writel(MU_INBOUND_DOORBELL_RESET, base + IDBL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) readl(base + IDBL); /* flush */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) before = jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) while (hba->out_req_cnt > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) if (time_after(jiffies, before + ST_INTERNAL_TIMEOUT * HZ)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) printk(KERN_WARNING DRV_NAME
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) "(%s): reset timeout\n", pci_name(hba->pdev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) ret = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) spin_lock_irqsave(hba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) if (ret == -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) hba->mu_status = MU_STATE_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) hba->mu_status = MU_STATE_STARTED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) wake_up_all(&hba->reset_waitq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) spin_unlock_irqrestore(hba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) static void stex_ss_reset(struct st_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) writel(SS_H2I_INT_RESET, hba->mmio_base + YH2I_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) readl(hba->mmio_base + YH2I_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) ssleep(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) static void stex_p3_reset(struct st_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) writel(SS_H2I_INT_RESET, hba->mmio_base + YH2I_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) ssleep(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) static int stex_do_reset(struct st_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) unsigned int mu_status = MU_STATE_RESETTING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) spin_lock_irqsave(hba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) if (hba->mu_status == MU_STATE_STARTING) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) spin_unlock_irqrestore(hba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) printk(KERN_INFO DRV_NAME "(%s): request reset during init\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) pci_name(hba->pdev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) while (hba->mu_status == MU_STATE_RESETTING) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) spin_unlock_irqrestore(hba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) wait_event_timeout(hba->reset_waitq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) hba->mu_status != MU_STATE_RESETTING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) MU_MAX_DELAY * HZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) spin_lock_irqsave(hba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) mu_status = hba->mu_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) if (mu_status != MU_STATE_RESETTING) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) spin_unlock_irqrestore(hba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) return (mu_status == MU_STATE_STARTED) ? 0 : -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) hba->mu_status = MU_STATE_RESETTING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) spin_unlock_irqrestore(hba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) if (hba->cardtype == st_yosemite)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) return stex_yos_reset(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) if (hba->cardtype == st_shasta)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) stex_hard_reset(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) else if (hba->cardtype == st_yel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) stex_ss_reset(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) else if (hba->cardtype == st_P3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) stex_p3_reset(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) return_abnormal_state(hba, DID_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) if (stex_handshake(hba) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) printk(KERN_WARNING DRV_NAME "(%s): resetting: handshake failed\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) pci_name(hba->pdev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) static int stex_reset(struct scsi_cmnd *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) struct st_hba *hba;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) hba = (struct st_hba *) &cmd->device->host->hostdata[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) shost_printk(KERN_INFO, cmd->device->host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) "resetting host\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) return stex_do_reset(hba) ? FAILED : SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) static void stex_reset_work(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) struct st_hba *hba = container_of(work, struct st_hba, reset_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) stex_do_reset(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) static int stex_biosparam(struct scsi_device *sdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) struct block_device *bdev, sector_t capacity, int geom[])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) int heads = 255, sectors = 63;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) if (capacity < 0x200000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) heads = 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) sectors = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) sector_div(capacity, heads * sectors);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) geom[0] = heads;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) geom[1] = sectors;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) geom[2] = capacity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) static struct scsi_host_template driver_template = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) .module = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) .name = DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) .proc_name = DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) .bios_param = stex_biosparam,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) .queuecommand = stex_queuecommand,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) .slave_configure = stex_slave_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) .eh_abort_handler = stex_abort,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) .eh_host_reset_handler = stex_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) .this_id = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) .dma_boundary = PAGE_SIZE - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) static struct pci_device_id stex_pci_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) /* st_shasta */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) { 0x105a, 0x8350, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) st_shasta }, /* SuperTrak EX8350/8300/16350/16300 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) { 0x105a, 0xc350, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) st_shasta }, /* SuperTrak EX12350 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) { 0x105a, 0x4302, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) st_shasta }, /* SuperTrak EX4350 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) { 0x105a, 0xe350, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) st_shasta }, /* SuperTrak EX24350 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) /* st_vsc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) { 0x105a, 0x7250, PCI_ANY_ID, PCI_ANY_ID, 0, 0, st_vsc },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) /* st_yosemite */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) { 0x105a, 0x8650, 0x105a, PCI_ANY_ID, 0, 0, st_yosemite },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) /* st_seq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) { 0x105a, 0x3360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, st_seq },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) /* st_yel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) { 0x105a, 0x8650, 0x1033, PCI_ANY_ID, 0, 0, st_yel },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) { 0x105a, 0x8760, PCI_ANY_ID, PCI_ANY_ID, 0, 0, st_yel },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) /* st_P3, pluto */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) { PCI_VENDOR_ID_PROMISE, 0x8870, PCI_VENDOR_ID_PROMISE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) 0x8870, 0, 0, st_P3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) /* st_P3, p3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) { PCI_VENDOR_ID_PROMISE, 0x8870, PCI_VENDOR_ID_PROMISE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) 0x4300, 0, 0, st_P3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) /* st_P3, SymplyStor4E */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) { PCI_VENDOR_ID_PROMISE, 0x8871, PCI_VENDOR_ID_PROMISE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) 0x4311, 0, 0, st_P3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) /* st_P3, SymplyStor8E */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) { PCI_VENDOR_ID_PROMISE, 0x8871, PCI_VENDOR_ID_PROMISE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) 0x4312, 0, 0, st_P3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) /* st_P3, SymplyStor4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) { PCI_VENDOR_ID_PROMISE, 0x8871, PCI_VENDOR_ID_PROMISE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) 0x4321, 0, 0, st_P3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) /* st_P3, SymplyStor8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) { PCI_VENDOR_ID_PROMISE, 0x8871, PCI_VENDOR_ID_PROMISE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) 0x4322, 0, 0, st_P3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) { } /* terminate list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) static struct st_card_info stex_card_info[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) /* st_shasta */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) .max_id = 17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) .max_lun = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) .max_channel = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) .rq_count = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) .rq_size = 1048,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) .sts_count = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) .alloc_rq = stex_alloc_req,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) .map_sg = stex_map_sg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) .send = stex_send_cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) /* st_vsc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) .max_id = 129,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) .max_lun = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) .max_channel = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) .rq_count = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) .rq_size = 1048,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) .sts_count = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) .alloc_rq = stex_alloc_req,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) .map_sg = stex_map_sg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) .send = stex_send_cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) /* st_yosemite */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) .max_id = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) .max_lun = 256,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) .max_channel = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) .rq_count = 256,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) .rq_size = 1048,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) .sts_count = 256,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) .alloc_rq = stex_alloc_req,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) .map_sg = stex_map_sg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) .send = stex_send_cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) /* st_seq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) .max_id = 129,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) .max_lun = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) .max_channel = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) .rq_count = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) .rq_size = 1048,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) .sts_count = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) .alloc_rq = stex_alloc_req,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) .map_sg = stex_map_sg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) .send = stex_send_cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) /* st_yel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) .max_id = 129,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) .max_lun = 256,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) .max_channel = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) .rq_count = 801,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) .rq_size = 512,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) .sts_count = 801,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) .alloc_rq = stex_ss_alloc_req,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) .map_sg = stex_ss_map_sg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) .send = stex_ss_send_cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) /* st_P3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) .max_id = 129,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) .max_lun = 256,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) .max_channel = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) .rq_count = 801,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) .rq_size = 512,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) .sts_count = 801,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) .alloc_rq = stex_ss_alloc_req,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) .map_sg = stex_ss_map_sg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) .send = stex_ss_send_cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) static int stex_request_irq(struct st_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) struct pci_dev *pdev = hba->pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) if (msi || hba->cardtype == st_P3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) status = pci_enable_msi(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) if (status != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) printk(KERN_ERR DRV_NAME
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) "(%s): error %d setting up MSI\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) pci_name(pdev), status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) hba->msi_enabled = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) hba->msi_enabled = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) status = request_irq(pdev->irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) (hba->cardtype == st_yel || hba->cardtype == st_P3) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) stex_ss_intr : stex_intr, IRQF_SHARED, DRV_NAME, hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) if (status != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) if (hba->msi_enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) pci_disable_msi(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) static void stex_free_irq(struct st_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) struct pci_dev *pdev = hba->pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) free_irq(pdev->irq, hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) if (hba->msi_enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) pci_disable_msi(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) static int stex_probe(struct pci_dev *pdev, const struct pci_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) struct st_hba *hba;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) struct Scsi_Host *host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) const struct st_card_info *ci = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) u32 sts_offset, cp_offset, scratch_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) err = pci_enable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) pci_set_master(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) S6flag = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) register_reboot_notifier(&stex_notifier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) host = scsi_host_alloc(&driver_template, sizeof(struct st_hba));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) if (!host) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) printk(KERN_ERR DRV_NAME "(%s): scsi_host_alloc failed\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) pci_name(pdev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) goto out_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) hba = (struct st_hba *)host->hostdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) memset(hba, 0, sizeof(struct st_hba));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) err = pci_request_regions(pdev, DRV_NAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) printk(KERN_ERR DRV_NAME "(%s): request regions failed\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) pci_name(pdev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) goto out_scsi_host_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) hba->mmio_base = pci_ioremap_bar(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) if ( !hba->mmio_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) printk(KERN_ERR DRV_NAME "(%s): memory map failed\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) pci_name(pdev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) goto out_release_regions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) printk(KERN_ERR DRV_NAME "(%s): set dma mask failed\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) pci_name(pdev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) goto out_iounmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) hba->cardtype = (unsigned int) id->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) ci = &stex_card_info[hba->cardtype];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) switch (id->subdevice) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) case 0x4221:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) case 0x4222:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) case 0x4223:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) case 0x4224:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) case 0x4225:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) case 0x4226:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) case 0x4227:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) case 0x4261:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) case 0x4262:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) case 0x4263:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) case 0x4264:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) case 0x4265:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) if (hba->cardtype == st_yel || hba->cardtype == st_P3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) hba->supports_pm = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) sts_offset = scratch_offset = (ci->rq_count+1) * ci->rq_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) if (hba->cardtype == st_yel || hba->cardtype == st_P3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) sts_offset += (ci->sts_count+1) * sizeof(u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) cp_offset = sts_offset + (ci->sts_count+1) * sizeof(struct status_msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) hba->dma_size = cp_offset + sizeof(struct st_frame);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) if (hba->cardtype == st_seq ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) (hba->cardtype == st_vsc && (pdev->subsystem_device & 1))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) hba->extra_offset = hba->dma_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) hba->dma_size += ST_ADDITIONAL_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) hba->dma_mem = dma_alloc_coherent(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) hba->dma_size, &hba->dma_handle, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) if (!hba->dma_mem) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) /* Retry minimum coherent mapping for st_seq and st_vsc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) if (hba->cardtype == st_seq ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) (hba->cardtype == st_vsc && (pdev->subsystem_device & 1))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) printk(KERN_WARNING DRV_NAME
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) "(%s): allocating min buffer for controller\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) pci_name(pdev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) hba->dma_size = hba->extra_offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) + ST_ADDITIONAL_MEM_MIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) hba->dma_mem = dma_alloc_coherent(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) hba->dma_size, &hba->dma_handle, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) if (!hba->dma_mem) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) printk(KERN_ERR DRV_NAME "(%s): dma mem alloc failed\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) pci_name(pdev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) goto out_iounmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) hba->ccb = kcalloc(ci->rq_count, sizeof(struct st_ccb), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) if (!hba->ccb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) printk(KERN_ERR DRV_NAME "(%s): ccb alloc failed\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) pci_name(pdev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) goto out_pci_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) if (hba->cardtype == st_yel || hba->cardtype == st_P3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) hba->scratch = (__le32 *)(hba->dma_mem + scratch_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) hba->status_buffer = (struct status_msg *)(hba->dma_mem + sts_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) hba->copy_buffer = hba->dma_mem + cp_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) hba->rq_count = ci->rq_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) hba->rq_size = ci->rq_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) hba->sts_count = ci->sts_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) hba->alloc_rq = ci->alloc_rq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) hba->map_sg = ci->map_sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) hba->send = ci->send;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) hba->mu_status = MU_STATE_STARTING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) hba->msi_lock = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) if (hba->cardtype == st_yel || hba->cardtype == st_P3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) host->sg_tablesize = 38;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) host->sg_tablesize = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) host->can_queue = ci->rq_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) host->cmd_per_lun = ci->rq_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) host->max_id = ci->max_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) host->max_lun = ci->max_lun;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) host->max_channel = ci->max_channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) host->unique_id = host->host_no;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) host->max_cmd_len = STEX_CDB_LENGTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) hba->host = host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) hba->pdev = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) init_waitqueue_head(&hba->reset_waitq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) snprintf(hba->work_q_name, sizeof(hba->work_q_name),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) "stex_wq_%d", host->host_no);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) hba->work_q = create_singlethread_workqueue(hba->work_q_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) if (!hba->work_q) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) printk(KERN_ERR DRV_NAME "(%s): create workqueue failed\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) pci_name(pdev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) goto out_ccb_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) INIT_WORK(&hba->reset_work, stex_reset_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) err = stex_request_irq(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) printk(KERN_ERR DRV_NAME "(%s): request irq failed\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) pci_name(pdev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) goto out_free_wq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) err = stex_handshake(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) goto out_free_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) pci_set_drvdata(pdev, hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) err = scsi_add_host(host, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) printk(KERN_ERR DRV_NAME "(%s): scsi_add_host failed\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) pci_name(pdev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) goto out_free_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) scsi_scan_host(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) out_free_irq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) stex_free_irq(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) out_free_wq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) destroy_workqueue(hba->work_q);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) out_ccb_free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) kfree(hba->ccb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) out_pci_free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) dma_free_coherent(&pdev->dev, hba->dma_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) hba->dma_mem, hba->dma_handle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) out_iounmap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) iounmap(hba->mmio_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) out_release_regions:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) pci_release_regions(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) out_scsi_host_put:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) scsi_host_put(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) out_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) pci_disable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) static void stex_hba_stop(struct st_hba *hba, int st_sleep_mic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) struct req_msg *req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) struct st_msg_header *msg_h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) unsigned long before;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) u16 tag = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) spin_lock_irqsave(hba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) if ((hba->cardtype == st_yel || hba->cardtype == st_P3) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) hba->supports_pm == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) if (st_sleep_mic == ST_NOTHANDLED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) spin_unlock_irqrestore(hba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) req = hba->alloc_rq(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) if (hba->cardtype == st_yel || hba->cardtype == st_P3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) msg_h = (struct st_msg_header *)req - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) memset(msg_h, 0, hba->rq_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) memset(req, 0, hba->rq_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) if ((hba->cardtype == st_yosemite || hba->cardtype == st_yel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) || hba->cardtype == st_P3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) && st_sleep_mic == ST_IGNORED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) req->cdb[0] = MGT_CMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) req->cdb[1] = MGT_CMD_SIGNATURE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) req->cdb[2] = CTLR_CONFIG_CMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) req->cdb[3] = CTLR_SHUTDOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) } else if ((hba->cardtype == st_yel || hba->cardtype == st_P3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) && st_sleep_mic != ST_IGNORED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) req->cdb[0] = MGT_CMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) req->cdb[1] = MGT_CMD_SIGNATURE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) req->cdb[2] = CTLR_CONFIG_CMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) req->cdb[3] = PMIC_SHUTDOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) req->cdb[4] = st_sleep_mic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) req->cdb[0] = CONTROLLER_CMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) req->cdb[1] = CTLR_POWER_STATE_CHANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) req->cdb[2] = CTLR_POWER_SAVING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) hba->ccb[tag].cmd = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) hba->ccb[tag].sg_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) hba->ccb[tag].sense_bufflen = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) hba->ccb[tag].sense_buffer = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) hba->ccb[tag].req_type = PASSTHRU_REQ_TYPE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) hba->send(hba, req, tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) spin_unlock_irqrestore(hba->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) before = jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) while (hba->ccb[tag].req_type & PASSTHRU_REQ_TYPE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) if (time_after(jiffies, before + ST_INTERNAL_TIMEOUT * HZ)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) hba->ccb[tag].req_type = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) hba->mu_status = MU_STATE_STOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) hba->mu_status = MU_STATE_STOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) static void stex_hba_free(struct st_hba *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) stex_free_irq(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) destroy_workqueue(hba->work_q);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) iounmap(hba->mmio_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) pci_release_regions(hba->pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) kfree(hba->ccb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) dma_free_coherent(&hba->pdev->dev, hba->dma_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) hba->dma_mem, hba->dma_handle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) static void stex_remove(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) struct st_hba *hba = pci_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) hba->mu_status = MU_STATE_NOCONNECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) return_abnormal_state(hba, DID_NO_CONNECT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) scsi_remove_host(hba->host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) scsi_block_requests(hba->host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) stex_hba_free(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) scsi_host_put(hba->host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) pci_disable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) unregister_reboot_notifier(&stex_notifier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) static void stex_shutdown(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) struct st_hba *hba = pci_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) if (hba->supports_pm == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) stex_hba_stop(hba, ST_IGNORED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) } else if (hba->supports_pm == 1 && S6flag) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) unregister_reboot_notifier(&stex_notifier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) stex_hba_stop(hba, ST_S6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) stex_hba_stop(hba, ST_S5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) static int stex_choice_sleep_mic(struct st_hba *hba, pm_message_t state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) switch (state.event) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) case PM_EVENT_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) return ST_S3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) case PM_EVENT_HIBERNATE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) hba->msi_lock = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) return ST_S4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) return ST_NOTHANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) static int stex_suspend(struct pci_dev *pdev, pm_message_t state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) struct st_hba *hba = pci_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) if ((hba->cardtype == st_yel || hba->cardtype == st_P3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) && hba->supports_pm == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) stex_hba_stop(hba, stex_choice_sleep_mic(hba, state));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) stex_hba_stop(hba, ST_IGNORED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) static int stex_resume(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) struct st_hba *hba = pci_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) hba->mu_status = MU_STATE_STARTING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) stex_handshake(hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) static int stex_halt(struct notifier_block *nb, unsigned long event, void *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) S6flag = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) return NOTIFY_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) MODULE_DEVICE_TABLE(pci, stex_pci_tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) static struct pci_driver stex_pci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) .name = DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) .id_table = stex_pci_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) .probe = stex_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) .remove = stex_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) .shutdown = stex_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) .suspend = stex_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) .resume = stex_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) static int __init stex_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) printk(KERN_INFO DRV_NAME
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) ": Promise SuperTrak EX Driver version: %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) ST_DRIVER_VERSION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) return pci_register_driver(&stex_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) static void __exit stex_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) pci_unregister_driver(&stex_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) module_init(stex_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) module_exit(stex_exit);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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