^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Copyright 2014 Cisco Systems, Inc. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * This program is free software; you may redistribute it and/or modify
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * it under the terms of the GNU General Public License as published by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * the Free Software Foundation; version 2 of the License.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * SOFTWARE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #ifndef __SNIC_STATS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define __SNIC_STATS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) struct snic_io_stats {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) atomic64_t active; /* Active IOs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) atomic64_t max_active; /* Max # active IOs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) atomic64_t max_sgl; /* Max # SGLs for any IO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) atomic64_t max_time; /* Max time to process IO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) atomic64_t max_qtime; /* Max time to Queue the IO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) atomic64_t max_cmpl_time; /* Max time to complete the IO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) atomic64_t sgl_cnt[SNIC_MAX_SG_DESC_CNT]; /* SGL Counters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) atomic64_t max_io_sz; /* Max IO Size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) atomic64_t compl; /* IO Completions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) atomic64_t fail; /* IO Failures */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) atomic64_t req_null; /* req or req info is NULL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) atomic64_t alloc_fail; /* Alloc Failures */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) atomic64_t sc_null;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) atomic64_t io_not_found; /* IO Not Found */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) atomic64_t num_ios; /* Number of IOs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) struct snic_abort_stats {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) atomic64_t num; /* Abort counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) atomic64_t fail; /* Abort Failure Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) atomic64_t drv_tmo; /* Abort Driver Timeouts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) atomic64_t fw_tmo; /* Abort Firmware Timeouts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) atomic64_t io_not_found;/* Abort IO Not Found */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) atomic64_t q_fail; /* Abort Queuing Failed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) struct snic_reset_stats {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) atomic64_t dev_resets; /* Device Reset Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) atomic64_t dev_reset_fail; /* Device Reset Failures */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) atomic64_t dev_reset_aborts; /* Device Reset Aborts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) atomic64_t dev_reset_tmo; /* Device Reset Timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) atomic64_t dev_reset_terms; /* Device Reset terminate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) atomic64_t hba_resets; /* hba/firmware resets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) atomic64_t hba_reset_cmpl; /* hba/firmware reset completions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) atomic64_t hba_reset_fail; /* hba/firmware failures */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) atomic64_t snic_resets; /* snic resets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) atomic64_t snic_reset_compl; /* snic reset completions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) atomic64_t snic_reset_fail; /* snic reset failures */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) struct snic_fw_stats {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) atomic64_t actv_reqs; /* Active Requests */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) atomic64_t max_actv_reqs; /* Max Active Requests */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) atomic64_t out_of_res; /* Firmware Out Of Resources */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) atomic64_t io_errs; /* Firmware IO Firmware Errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) atomic64_t scsi_errs; /* Target hits check condition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) struct snic_misc_stats {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) u64 last_isr_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) u64 last_ack_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) atomic64_t ack_isr_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) atomic64_t cmpl_isr_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) atomic64_t errnotify_isr_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) atomic64_t max_cq_ents; /* Max CQ Entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) atomic64_t data_cnt_mismat; /* Data Count Mismatch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) atomic64_t io_tmo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) atomic64_t io_aborted;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) atomic64_t sgl_inval; /* SGL Invalid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) atomic64_t abts_wq_alloc_fail; /* Abort Path WQ desc alloc failure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) atomic64_t devrst_wq_alloc_fail;/* Device Reset - WQ desc alloc fail */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) atomic64_t wq_alloc_fail; /* IO WQ desc alloc failure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) atomic64_t no_icmnd_itmf_cmpls;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) atomic64_t io_under_run;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) atomic64_t qfull;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) atomic64_t qsz_rampup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) atomic64_t qsz_rampdown;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) atomic64_t last_qsz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) atomic64_t tgt_not_rdy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) struct snic_stats {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct snic_io_stats io;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct snic_abort_stats abts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) struct snic_reset_stats reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) struct snic_fw_stats fw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) struct snic_misc_stats misc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) atomic64_t io_cmpl_skip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) void snic_stats_debugfs_init(struct snic *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) void snic_stats_debugfs_remove(struct snic *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /* Auxillary function to update active IO counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) snic_stats_update_active_ios(struct snic_stats *s_stats)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) struct snic_io_stats *io = &s_stats->io;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) int nr_active_ios;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) nr_active_ios = atomic64_read(&io->active);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) if (atomic64_read(&io->max_active) < nr_active_ios)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) atomic64_set(&io->max_active, nr_active_ios);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) atomic64_inc(&io->num_ios);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /* Auxillary function to update IO completion counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) snic_stats_update_io_cmpl(struct snic_stats *s_stats)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) atomic64_dec(&s_stats->io.active);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) if (unlikely(atomic64_read(&s_stats->io_cmpl_skip)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) atomic64_dec(&s_stats->io_cmpl_skip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) atomic64_inc(&s_stats->io.compl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #endif /* __SNIC_STATS_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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