^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * driver for Microsemi PQI-based storage controllers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (c) 2019-2020 Microchip Technology Inc. and its subsidiaries
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2016-2018 Microsemi Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (c) 2016 PMC-Sierra, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Questions/Comments/Bugfixes to storagedev@microchip.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <scsi/scsi_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <asm/unaligned.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "smartpqi.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "smartpqi_sis.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /* legacy SIS interface commands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define SIS_CMD_GET_ADAPTER_PROPERTIES 0x19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define SIS_CMD_INIT_BASE_STRUCT_ADDRESS 0x1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define SIS_CMD_GET_PQI_CAPABILITIES 0x3000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* for submission of legacy SIS commands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SIS_REENABLE_SIS_MODE 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SIS_ENABLE_MSIX 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define SIS_ENABLE_INTX 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define SIS_SOFT_RESET 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define SIS_CMD_READY 0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SIS_TRIGGER_SHUTDOWN 0x800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SIS_PQI_RESET_QUIESCE 0x1000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SIS_CMD_COMPLETE 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SIS_CLEAR_CTRL_TO_HOST_DOORBELL 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SIS_CMD_STATUS_SUCCESS 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SIS_CMD_COMPLETE_TIMEOUT_SECS 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SIS_CMD_COMPLETE_POLL_INTERVAL_MSECS 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /* used with SIS_CMD_GET_ADAPTER_PROPERTIES command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SIS_EXTENDED_PROPERTIES_SUPPORTED 0x800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SIS_SMARTARRAY_FEATURES_SUPPORTED 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SIS_PQI_MODE_SUPPORTED 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SIS_PQI_RESET_QUIESCE_SUPPORTED 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SIS_REQUIRED_EXTENDED_PROPERTIES \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) (SIS_SMARTARRAY_FEATURES_SUPPORTED | SIS_PQI_MODE_SUPPORTED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* used with SIS_CMD_INIT_BASE_STRUCT_ADDRESS command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SIS_BASE_STRUCT_REVISION 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SIS_BASE_STRUCT_ALIGNMENT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define SIS_CTRL_KERNEL_UP 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define SIS_CTRL_KERNEL_PANIC 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define SIS_CTRL_READY_TIMEOUT_SECS 180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define SIS_CTRL_READY_RESUME_TIMEOUT_SECS 90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define SIS_CTRL_READY_POLL_INTERVAL_MSECS 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #pragma pack(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /* for use with SIS_CMD_INIT_BASE_STRUCT_ADDRESS command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct sis_base_struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) __le32 revision; /* revision of this structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) __le32 flags; /* reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) __le32 error_buffer_paddr_low; /* lower 32 bits of physical memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /* buffer for PQI error response */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /* data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) __le32 error_buffer_paddr_high; /* upper 32 bits of physical */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /* memory buffer for PQI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /* error response data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) __le32 error_buffer_element_length; /* length of each PQI error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /* response buffer element */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* in bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) __le32 error_buffer_num_elements; /* total number of PQI error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /* response buffers available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #pragma pack()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) static int sis_wait_for_ctrl_ready_with_timeout(struct pqi_ctrl_info *ctrl_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) unsigned int timeout_secs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) unsigned long timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) timeout = (timeout_secs * PQI_HZ) + jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) while (1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) status = readl(&ctrl_info->registers->sis_firmware_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) if (status != ~0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) if (status & SIS_CTRL_KERNEL_PANIC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) dev_err(&ctrl_info->pci_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) "controller is offline: status code 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) readl(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) &ctrl_info->registers->sis_mailbox[7]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) if (status & SIS_CTRL_KERNEL_UP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) if (time_after(jiffies, timeout)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) dev_err(&ctrl_info->pci_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) "controller not ready after %u seconds\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) timeout_secs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) msleep(SIS_CTRL_READY_POLL_INTERVAL_MSECS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) int sis_wait_for_ctrl_ready(struct pqi_ctrl_info *ctrl_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) return sis_wait_for_ctrl_ready_with_timeout(ctrl_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) SIS_CTRL_READY_TIMEOUT_SECS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) int sis_wait_for_ctrl_ready_resume(struct pqi_ctrl_info *ctrl_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) return sis_wait_for_ctrl_ready_with_timeout(ctrl_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) SIS_CTRL_READY_RESUME_TIMEOUT_SECS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) bool sis_is_firmware_running(struct pqi_ctrl_info *ctrl_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) bool running;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) status = readl(&ctrl_info->registers->sis_firmware_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) if (status & SIS_CTRL_KERNEL_PANIC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) running = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) running = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) if (!running)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) dev_err(&ctrl_info->pci_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) "controller is offline: status code 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) readl(&ctrl_info->registers->sis_mailbox[7]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) return running;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) bool sis_is_kernel_up(struct pqi_ctrl_info *ctrl_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) return readl(&ctrl_info->registers->sis_firmware_status) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) SIS_CTRL_KERNEL_UP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /* used for passing command parameters/results when issuing SIS commands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct sis_sync_cmd_params {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) u32 mailbox[6]; /* mailboxes 0-5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static int sis_send_sync_cmd(struct pqi_ctrl_info *ctrl_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) u32 cmd, struct sis_sync_cmd_params *params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) struct pqi_ctrl_registers __iomem *registers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) unsigned long timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) u32 doorbell;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) u32 cmd_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) registers = ctrl_info->registers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) /* Write the command to mailbox 0. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) writel(cmd, ®isters->sis_mailbox[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) * Write the command parameters to mailboxes 1-4 (mailbox 5 is not used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) * when sending a command to the controller).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) for (i = 1; i <= 4; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) writel(params->mailbox[i], ®isters->sis_mailbox[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /* Clear the command doorbell. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) writel(SIS_CLEAR_CTRL_TO_HOST_DOORBELL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) ®isters->sis_ctrl_to_host_doorbell_clear);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /* Disable doorbell interrupts by masking all interrupts. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) writel(~0, ®isters->sis_interrupt_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) * Force the completion of the interrupt mask register write before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) * submitting the command.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) readl(®isters->sis_interrupt_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) /* Submit the command to the controller. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) writel(SIS_CMD_READY, ®isters->sis_host_to_ctrl_doorbell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) * Poll for command completion. Note that the call to msleep() is at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) * the top of the loop in order to give the controller time to start
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) * processing the command before we start polling.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) timeout = (SIS_CMD_COMPLETE_TIMEOUT_SECS * PQI_HZ) + jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) while (1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) msleep(SIS_CMD_COMPLETE_POLL_INTERVAL_MSECS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) doorbell = readl(®isters->sis_ctrl_to_host_doorbell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) if (doorbell & SIS_CMD_COMPLETE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) if (time_after(jiffies, timeout))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) /* Read the command status from mailbox 0. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) cmd_status = readl(®isters->sis_mailbox[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) if (cmd_status != SIS_CMD_STATUS_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) dev_err(&ctrl_info->pci_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) "SIS command failed for command 0x%x: status = 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) cmd, cmd_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) * The command completed successfully, so save the command status and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) * read the values returned in mailboxes 1-5.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) params->mailbox[0] = cmd_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) for (i = 1; i < ARRAY_SIZE(params->mailbox); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) params->mailbox[i] = readl(®isters->sis_mailbox[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) * This function verifies that we are talking to a controller that speaks PQI.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) int sis_get_ctrl_properties(struct pqi_ctrl_info *ctrl_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) u32 properties;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) u32 extended_properties;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) struct sis_sync_cmd_params params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) memset(¶ms, 0, sizeof(params));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) rc = sis_send_sync_cmd(ctrl_info, SIS_CMD_GET_ADAPTER_PROPERTIES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) ¶ms);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) properties = params.mailbox[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) if (!(properties & SIS_EXTENDED_PROPERTIES_SUPPORTED))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) extended_properties = params.mailbox[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) if ((extended_properties & SIS_REQUIRED_EXTENDED_PROPERTIES) !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) SIS_REQUIRED_EXTENDED_PROPERTIES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) if (extended_properties & SIS_PQI_RESET_QUIESCE_SUPPORTED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) ctrl_info->pqi_reset_quiesce_supported = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) int sis_get_pqi_capabilities(struct pqi_ctrl_info *ctrl_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) struct sis_sync_cmd_params params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) memset(¶ms, 0, sizeof(params));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) rc = sis_send_sync_cmd(ctrl_info, SIS_CMD_GET_PQI_CAPABILITIES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) ¶ms);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) ctrl_info->max_sg_entries = params.mailbox[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) ctrl_info->max_transfer_size = params.mailbox[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) ctrl_info->max_outstanding_requests = params.mailbox[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) ctrl_info->config_table_offset = params.mailbox[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) ctrl_info->config_table_length = params.mailbox[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) int sis_init_base_struct_addr(struct pqi_ctrl_info *ctrl_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) void *base_struct_unaligned;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) struct sis_base_struct *base_struct;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) struct sis_sync_cmd_params params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) unsigned long error_buffer_paddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) dma_addr_t bus_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) base_struct_unaligned = kzalloc(sizeof(*base_struct)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) + SIS_BASE_STRUCT_ALIGNMENT - 1, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) if (!base_struct_unaligned)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) base_struct = PTR_ALIGN(base_struct_unaligned,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) SIS_BASE_STRUCT_ALIGNMENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) error_buffer_paddr = (unsigned long)ctrl_info->error_buffer_dma_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) put_unaligned_le32(SIS_BASE_STRUCT_REVISION, &base_struct->revision);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) put_unaligned_le32(lower_32_bits(error_buffer_paddr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) &base_struct->error_buffer_paddr_low);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) put_unaligned_le32(upper_32_bits(error_buffer_paddr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) &base_struct->error_buffer_paddr_high);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) put_unaligned_le32(PQI_ERROR_BUFFER_ELEMENT_LENGTH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) &base_struct->error_buffer_element_length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) put_unaligned_le32(ctrl_info->max_io_slots,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) &base_struct->error_buffer_num_elements);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) bus_address = dma_map_single(&ctrl_info->pci_dev->dev, base_struct,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) sizeof(*base_struct), DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) if (dma_mapping_error(&ctrl_info->pci_dev->dev, bus_address)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) rc = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) memset(¶ms, 0, sizeof(params));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) params.mailbox[1] = lower_32_bits((u64)bus_address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) params.mailbox[2] = upper_32_bits((u64)bus_address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) params.mailbox[3] = sizeof(*base_struct);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) rc = sis_send_sync_cmd(ctrl_info, SIS_CMD_INIT_BASE_STRUCT_ADDRESS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) ¶ms);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) dma_unmap_single(&ctrl_info->pci_dev->dev, bus_address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) sizeof(*base_struct), DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) kfree(base_struct_unaligned);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define SIS_DOORBELL_BIT_CLEAR_TIMEOUT_SECS 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) static int sis_wait_for_doorbell_bit_to_clear(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) struct pqi_ctrl_info *ctrl_info, u32 bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) int rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) u32 doorbell_register;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) unsigned long timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) timeout = (SIS_DOORBELL_BIT_CLEAR_TIMEOUT_SECS * PQI_HZ) + jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) while (1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) doorbell_register =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) readl(&ctrl_info->registers->sis_host_to_ctrl_doorbell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) if ((doorbell_register & bit) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) if (readl(&ctrl_info->registers->sis_firmware_status) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) SIS_CTRL_KERNEL_PANIC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) rc = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) if (time_after(jiffies, timeout)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) dev_err(&ctrl_info->pci_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) "doorbell register bit 0x%x not cleared\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) rc = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) usleep_range(1000, 2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) static inline int sis_set_doorbell_bit(struct pqi_ctrl_info *ctrl_info, u32 bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) writel(bit, &ctrl_info->registers->sis_host_to_ctrl_doorbell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) return sis_wait_for_doorbell_bit_to_clear(ctrl_info, bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) void sis_enable_msix(struct pqi_ctrl_info *ctrl_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) sis_set_doorbell_bit(ctrl_info, SIS_ENABLE_MSIX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) void sis_enable_intx(struct pqi_ctrl_info *ctrl_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) sis_set_doorbell_bit(ctrl_info, SIS_ENABLE_INTX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) void sis_shutdown_ctrl(struct pqi_ctrl_info *ctrl_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) if (readl(&ctrl_info->registers->sis_firmware_status) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) SIS_CTRL_KERNEL_PANIC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) writel(SIS_TRIGGER_SHUTDOWN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) &ctrl_info->registers->sis_host_to_ctrl_doorbell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) int sis_pqi_reset_quiesce(struct pqi_ctrl_info *ctrl_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) return sis_set_doorbell_bit(ctrl_info, SIS_PQI_RESET_QUIESCE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) int sis_reenable_sis_mode(struct pqi_ctrl_info *ctrl_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) return sis_set_doorbell_bit(ctrl_info, SIS_REENABLE_SIS_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) void sis_write_driver_scratch(struct pqi_ctrl_info *ctrl_info, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) writel(value, &ctrl_info->registers->sis_driver_scratch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) u32 sis_read_driver_scratch(struct pqi_ctrl_info *ctrl_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) return readl(&ctrl_info->registers->sis_driver_scratch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) void sis_soft_reset(struct pqi_ctrl_info *ctrl_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) writel(SIS_SOFT_RESET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) &ctrl_info->registers->sis_host_to_ctrl_doorbell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) static void __attribute__((unused)) verify_structures(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) BUILD_BUG_ON(offsetof(struct sis_base_struct,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) revision) != 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) BUILD_BUG_ON(offsetof(struct sis_base_struct,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) flags) != 0x4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) BUILD_BUG_ON(offsetof(struct sis_base_struct,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) error_buffer_paddr_low) != 0x8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) BUILD_BUG_ON(offsetof(struct sis_base_struct,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) error_buffer_paddr_high) != 0xc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) BUILD_BUG_ON(offsetof(struct sis_base_struct,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) error_buffer_element_length) != 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) BUILD_BUG_ON(offsetof(struct sis_base_struct,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) error_buffer_num_elements) != 0x14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) BUILD_BUG_ON(sizeof(struct sis_base_struct) != 0x18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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