^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /* qlogicpti.h: Performance Technologies QlogicISP sbus card defines.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 1996 David S. Miller (davem@caipfs.rutgers.edu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #ifndef _QLOGICPTI_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define _QLOGICPTI_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) /* Qlogic/SBUS controller registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define SBUS_CFG1 0x006UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define SBUS_CTRL 0x008UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define SBUS_STAT 0x00aUL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define SBUS_SEMAPHORE 0x00cUL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define CMD_DMA_CTRL 0x022UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define DATA_DMA_CTRL 0x042UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define MBOX0 0x080UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define MBOX1 0x082UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define MBOX2 0x084UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define MBOX3 0x086UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define MBOX4 0x088UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define MBOX5 0x08aUL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define CPU_CMD 0x214UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define CPU_ORIDE 0x224UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define CPU_PCTRL 0x272UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define CPU_PDIFF 0x276UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define RISC_PSR 0x420UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define RISC_MTREG 0x42EUL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define HCCTRL 0x440UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /* SCSI parameters for this driver. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define MAX_TARGETS 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define MAX_LUNS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /* With the qlogic interface, every queue slot can hold a SCSI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * command with up to 4 scatter/gather entries. If we need more
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * than 4 entries, continuation entries can be used that hold
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * another 7 entries each. Unlike for other drivers, this means
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * that the maximum number of scatter/gather entries we can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * support at any given time is a function of the number of queue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * slots available. That is, host->can_queue and host->sg_tablesize
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * are dynamic and _not_ independent. This all works fine because
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * requests are queued serially and the scatter/gather limit is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * determined for each queue request anew.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define QLOGICPTI_REQ_QUEUE_LEN 255 /* must be power of two - 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define QLOGICPTI_MAX_SG(ql) (4 + (((ql) > 0) ? 7*((ql) - 1) : 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* mailbox command complete status codes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define MBOX_COMMAND_COMPLETE 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define INVALID_COMMAND 0x4001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define HOST_INTERFACE_ERROR 0x4002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define TEST_FAILED 0x4003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define COMMAND_ERROR 0x4005
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define COMMAND_PARAM_ERROR 0x4006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* async event status codes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define ASYNC_SCSI_BUS_RESET 0x8001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define SYSTEM_ERROR 0x8002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define REQUEST_TRANSFER_ERROR 0x8003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define RESPONSE_TRANSFER_ERROR 0x8004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define REQUEST_QUEUE_WAKEUP 0x8005
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define EXECUTION_TIMEOUT_RESET 0x8006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* Am I fucking pedantic or what? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct Entry_header {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #ifdef __BIG_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) u8 entry_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) u8 entry_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) u8 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) u8 sys_def_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #else /* __LITTLE_ENDIAN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) u8 entry_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) u8 entry_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) u8 sys_def_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) u8 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* entry header type commands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define ENTRY_COMMAND 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define ENTRY_CONTINUATION 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define ENTRY_STATUS 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define ENTRY_MARKER 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define ENTRY_EXTENDED_COMMAND 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* entry header flag definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define EFLAG_CONTINUATION 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define EFLAG_BUSY 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define EFLAG_BAD_HEADER 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define EFLAG_BAD_PAYLOAD 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) struct dataseg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) u32 d_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) u32 d_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) struct Command_Entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) struct Entry_header hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) u32 handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #ifdef __BIG_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) u8 target_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) u8 target_lun;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #else /* __LITTLE_ENDIAN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) u8 target_lun;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) u8 target_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) u16 cdb_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) u16 control_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) u16 rsvd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) u16 time_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) u16 segment_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) u8 cdb[12];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) struct dataseg dataseg[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /* command entry control flag definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define CFLAG_NODISC 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define CFLAG_HEAD_TAG 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define CFLAG_ORDERED_TAG 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define CFLAG_SIMPLE_TAG 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define CFLAG_TAR_RTN 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define CFLAG_READ 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define CFLAG_WRITE 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct Ext_Command_Entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) struct Entry_header hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) u32 handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #ifdef __BIG_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) u8 target_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) u8 target_lun;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #else /* __LITTLE_ENDIAN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) u8 target_lun;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) u8 target_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) u16 cdb_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) u16 control_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) u16 rsvd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) u16 time_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) u16 segment_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) u8 cdb[44];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct Continuation_Entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) struct Entry_header hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) u32 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) struct dataseg dataseg[7];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) struct Marker_Entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) struct Entry_header hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) u32 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #ifdef __BIG_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) u8 target_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) u8 target_lun;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #else /* __LITTLE_ENDIAN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) u8 target_lun;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) u8 target_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #ifdef __BIG_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) u8 rsvd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) u8 modifier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #else /* __LITTLE_ENDIAN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) u8 modifier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) u8 rsvd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) u8 rsvds[52];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /* marker entry modifier definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define SYNC_DEVICE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define SYNC_TARGET 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define SYNC_ALL 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) struct Status_Entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) struct Entry_header hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) u32 handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) u16 scsi_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) u16 completion_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) u16 state_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) u16 status_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) u16 time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) u16 req_sense_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) u32 residual;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) u8 rsvd[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) u8 req_sense_data[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /* status entry completion status definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define CS_COMPLETE 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define CS_INCOMPLETE 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define CS_DMA_ERROR 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define CS_TRANSPORT_ERROR 0x0003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define CS_RESET_OCCURRED 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define CS_ABORTED 0x0005
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define CS_TIMEOUT 0x0006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define CS_DATA_OVERRUN 0x0007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define CS_COMMAND_OVERRUN 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define CS_STATUS_OVERRUN 0x0009
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define CS_BAD_MESSAGE 0x000a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define CS_NO_MESSAGE_OUT 0x000b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define CS_EXT_ID_FAILED 0x000c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define CS_IDE_MSG_FAILED 0x000d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define CS_ABORT_MSG_FAILED 0x000e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define CS_REJECT_MSG_FAILED 0x000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define CS_NOP_MSG_FAILED 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define CS_PARITY_ERROR_MSG_FAILED 0x0011
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define CS_DEVICE_RESET_MSG_FAILED 0x0012
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define CS_ID_MSG_FAILED 0x0013
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define CS_UNEXP_BUS_FREE 0x0014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define CS_DATA_UNDERRUN 0x0015
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define CS_BUS_RESET 0x001c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) /* status entry state flag definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define SF_GOT_BUS 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define SF_GOT_TARGET 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define SF_SENT_CDB 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define SF_TRANSFERRED_DATA 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define SF_GOT_STATUS 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define SF_GOT_SENSE 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) /* status entry status flag definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define STF_DISCONNECT 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define STF_SYNCHRONOUS 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define STF_PARITY_ERROR 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define STF_BUS_RESET 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define STF_DEVICE_RESET 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define STF_ABORTED 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define STF_TIMEOUT 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define STF_NEGOTIATION 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) /* mailbox commands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define MBOX_NO_OP 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define MBOX_LOAD_RAM 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define MBOX_EXEC_FIRMWARE 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define MBOX_DUMP_RAM 0x0003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define MBOX_WRITE_RAM_WORD 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define MBOX_READ_RAM_WORD 0x0005
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define MBOX_MAILBOX_REG_TEST 0x0006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define MBOX_VERIFY_CHECKSUM 0x0007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define MBOX_ABOUT_FIRMWARE 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define MBOX_CHECK_FIRMWARE 0x000e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define MBOX_INIT_REQ_QUEUE 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define MBOX_INIT_RES_QUEUE 0x0011
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define MBOX_EXECUTE_IOCB 0x0012
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define MBOX_WAKE_UP 0x0013
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define MBOX_STOP_FIRMWARE 0x0014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define MBOX_ABORT 0x0015
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define MBOX_ABORT_DEVICE 0x0016
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define MBOX_ABORT_TARGET 0x0017
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define MBOX_BUS_RESET 0x0018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define MBOX_STOP_QUEUE 0x0019
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define MBOX_START_QUEUE 0x001a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define MBOX_SINGLE_STEP_QUEUE 0x001b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define MBOX_ABORT_QUEUE 0x001c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define MBOX_GET_DEV_QUEUE_STATUS 0x001d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define MBOX_GET_FIRMWARE_STATUS 0x001f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define MBOX_GET_INIT_SCSI_ID 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define MBOX_GET_SELECT_TIMEOUT 0x0021
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define MBOX_GET_RETRY_COUNT 0x0022
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define MBOX_GET_TAG_AGE_LIMIT 0x0023
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define MBOX_GET_CLOCK_RATE 0x0024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define MBOX_GET_ACT_NEG_STATE 0x0025
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define MBOX_GET_ASYNC_DATA_SETUP_TIME 0x0026
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define MBOX_GET_SBUS_PARAMS 0x0027
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define MBOX_GET_TARGET_PARAMS 0x0028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define MBOX_GET_DEV_QUEUE_PARAMS 0x0029
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define MBOX_SET_INIT_SCSI_ID 0x0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define MBOX_SET_SELECT_TIMEOUT 0x0031
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define MBOX_SET_RETRY_COUNT 0x0032
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define MBOX_SET_TAG_AGE_LIMIT 0x0033
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define MBOX_SET_CLOCK_RATE 0x0034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define MBOX_SET_ACTIVE_NEG_STATE 0x0035
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define MBOX_SET_ASYNC_DATA_SETUP_TIME 0x0036
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define MBOX_SET_SBUS_CONTROL_PARAMS 0x0037
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define MBOX_SET_TARGET_PARAMS 0x0038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define MBOX_SET_DEV_QUEUE_PARAMS 0x0039
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) struct host_param {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) u_short initiator_scsi_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) u_short bus_reset_delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) u_short retry_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) u_short retry_delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) u_short async_data_setup_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) u_short req_ack_active_negation;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) u_short data_line_active_negation;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) u_short data_dma_burst_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) u_short command_dma_burst_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) u_short tag_aging;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) u_short selection_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) u_short max_queue_depth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) * Device Flags:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) * Bit Name
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) * ---------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) * 7 Disconnect Privilege
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) * 6 Parity Checking
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) * 5 Wide Data Transfers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) * 4 Synchronous Data Transfers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) * 3 Tagged Queuing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) * 2 Automatic Request Sense
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) * 1 Stop Queue on Check Condition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) * 0 Renegotiate on Error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) struct dev_param {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) u_short device_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) u_short execution_throttle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) u_short synchronous_period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) u_short synchronous_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) u_short device_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) u_short reserved; /* pad */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) * The result queue can be quite a bit smaller since continuation entries
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) * do not show up there:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define RES_QUEUE_LEN 255 /* Must be power of two - 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define QUEUE_ENTRY_LEN 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define NEXT_REQ_PTR(wheee) (((wheee) + 1) & QLOGICPTI_REQ_QUEUE_LEN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define NEXT_RES_PTR(wheee) (((wheee) + 1) & RES_QUEUE_LEN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define PREV_REQ_PTR(wheee) (((wheee) - 1) & QLOGICPTI_REQ_QUEUE_LEN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define PREV_RES_PTR(wheee) (((wheee) - 1) & RES_QUEUE_LEN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) struct pti_queue_entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) char __opaque[QUEUE_ENTRY_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) struct scsi_cmnd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) /* Software state for the driver. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) struct qlogicpti {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) /* These are the hot elements in the cache, so they come first. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) void __iomem *qregs; /* Adapter registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) struct pti_queue_entry *res_cpu; /* Ptr to RESPONSE bufs (CPU) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) struct pti_queue_entry *req_cpu; /* Ptr to REQUEST bufs (CPU) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) u_int req_in_ptr; /* index of next request slot */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) u_int res_out_ptr; /* index of next result slot */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) long send_marker; /* must we send a marker? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) struct platform_device *op;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) unsigned long __pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) int cmd_count[MAX_TARGETS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) unsigned long tag_ages[MAX_TARGETS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) /* The cmd->handler is only 32-bits, so that things work even on monster
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) * Ex000 sparc64 machines with >4GB of ram we just keep track of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) * scsi command pointers here. This is essentially what Matt Jacob does. -DaveM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) struct scsi_cmnd *cmd_slots[QLOGICPTI_REQ_QUEUE_LEN + 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) /* The rest of the elements are unimportant for performance. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) struct qlogicpti *next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) dma_addr_t res_dvma; /* Ptr to RESPONSE bufs (DVMA)*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) dma_addr_t req_dvma; /* Ptr to REQUEST bufs (DVMA) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) u_char fware_majrev, fware_minrev, fware_micrev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) struct Scsi_Host *qhost;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) int qpti_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) int scsi_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) int prom_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) char differential, ultra, clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) unsigned char bursts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) struct host_param host_param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) struct dev_param dev_param[MAX_TARGETS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) void __iomem *sreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define SREG_TPOWER 0x80 /* State of termpwr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define SREG_FUSE 0x40 /* State of on board fuse */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define SREG_PDISAB 0x20 /* Disable state for power on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define SREG_DSENSE 0x10 /* Sense for differential */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define SREG_IMASK 0x0c /* Interrupt level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define SREG_SPMASK 0x03 /* Mask for switch pack */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) unsigned char swsreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) unsigned int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) gotirq : 1, /* this instance got an irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) is_pti : 1; /* Non-zero if this is a PTI board. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) /* How to twiddle them bits... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) /* SBUS config register one. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define SBUS_CFG1_EPAR 0x0100 /* Enable parity checking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define SBUS_CFG1_FMASK 0x00f0 /* Forth code cycle mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define SBUS_CFG1_BENAB 0x0004 /* Burst dvma enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define SBUS_CFG1_B64 0x0003 /* Enable 64byte bursts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define SBUS_CFG1_B32 0x0002 /* Enable 32byte bursts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define SBUS_CFG1_B16 0x0001 /* Enable 16byte bursts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define SBUS_CFG1_B8 0x0008 /* Enable 8byte bursts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) /* SBUS control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define SBUS_CTRL_EDIRQ 0x0020 /* Enable Data DVMA Interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define SBUS_CTRL_ECIRQ 0x0010 /* Enable Command DVMA Interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define SBUS_CTRL_ESIRQ 0x0008 /* Enable SCSI Processor Interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define SBUS_CTRL_ERIRQ 0x0004 /* Enable RISC Processor Interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define SBUS_CTRL_GENAB 0x0002 /* Global Interrupt Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define SBUS_CTRL_RESET 0x0001 /* Soft Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) /* SBUS status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define SBUS_STAT_DINT 0x0020 /* Data DVMA IRQ pending */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #define SBUS_STAT_CINT 0x0010 /* Command DVMA IRQ pending */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #define SBUS_STAT_SINT 0x0008 /* SCSI Processor IRQ pending */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define SBUS_STAT_RINT 0x0004 /* RISC Processor IRQ pending */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define SBUS_STAT_GINT 0x0002 /* Global IRQ pending */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) /* SBUS semaphore register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define SBUS_SEMAPHORE_STAT 0x0002 /* Semaphore status bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #define SBUS_SEMAPHORE_LCK 0x0001 /* Semaphore lock bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) /* DVMA control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #define DMA_CTRL_CSUSPEND 0x0010 /* DMA channel suspend */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) #define DMA_CTRL_CCLEAR 0x0008 /* DMA channel clear and reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) #define DMA_CTRL_FCLEAR 0x0004 /* DMA fifo clear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #define DMA_CTRL_CIRQ 0x0002 /* DMA irq clear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) #define DMA_CTRL_DMASTART 0x0001 /* DMA transfer start */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) /* SCSI processor override register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #define CPU_ORIDE_ETRIG 0x8000 /* External trigger enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #define CPU_ORIDE_STEP 0x4000 /* Single step mode enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #define CPU_ORIDE_BKPT 0x2000 /* Breakpoint reg enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) #define CPU_ORIDE_PWRITE 0x1000 /* SCSI pin write enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) #define CPU_ORIDE_OFORCE 0x0800 /* Force outputs on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) #define CPU_ORIDE_LBACK 0x0400 /* SCSI loopback enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #define CPU_ORIDE_PTEST 0x0200 /* Parity test enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) #define CPU_ORIDE_TENAB 0x0100 /* SCSI pins tristate enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) #define CPU_ORIDE_TPINS 0x0080 /* SCSI pins enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) #define CPU_ORIDE_FRESET 0x0008 /* FIFO reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) #define CPU_ORIDE_CTERM 0x0004 /* Command terminate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) #define CPU_ORIDE_RREG 0x0002 /* Reset SCSI processor regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) #define CPU_ORIDE_RMOD 0x0001 /* Reset SCSI processor module */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) /* SCSI processor commands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) #define CPU_CMD_BRESET 0x300b /* Reset SCSI bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) /* SCSI processor pin control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) #define CPU_PCTRL_PVALID 0x8000 /* Phase bits are valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) #define CPU_PCTRL_PHI 0x0400 /* Parity bit high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) #define CPU_PCTRL_PLO 0x0200 /* Parity bit low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) #define CPU_PCTRL_REQ 0x0100 /* REQ bus signal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) #define CPU_PCTRL_ACK 0x0080 /* ACK bus signal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) #define CPU_PCTRL_RST 0x0040 /* RST bus signal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) #define CPU_PCTRL_BSY 0x0020 /* BSY bus signal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) #define CPU_PCTRL_SEL 0x0010 /* SEL bus signal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) #define CPU_PCTRL_ATN 0x0008 /* ATN bus signal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) #define CPU_PCTRL_MSG 0x0004 /* MSG bus signal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) #define CPU_PCTRL_CD 0x0002 /* CD bus signal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) #define CPU_PCTRL_IO 0x0001 /* IO bus signal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) /* SCSI processor differential pins register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) #define CPU_PDIFF_SENSE 0x0200 /* Differential sense */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) #define CPU_PDIFF_MODE 0x0100 /* Differential mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) #define CPU_PDIFF_OENAB 0x0080 /* Outputs enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) #define CPU_PDIFF_PMASK 0x007c /* Differential control pins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) #define CPU_PDIFF_TGT 0x0002 /* Target mode enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) #define CPU_PDIFF_INIT 0x0001 /* Initiator mode enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) /* RISC processor status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) #define RISC_PSR_FTRUE 0x8000 /* Force true */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) #define RISC_PSR_LCD 0x4000 /* Loop counter shows done status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) #define RISC_PSR_RIRQ 0x2000 /* RISC irq status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) #define RISC_PSR_TOFLOW 0x1000 /* Timer overflow (rollover) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) #define RISC_PSR_AOFLOW 0x0800 /* Arithmetic overflow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) #define RISC_PSR_AMSB 0x0400 /* Arithmetic big endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) #define RISC_PSR_ACARRY 0x0200 /* Arithmetic carry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) #define RISC_PSR_AZERO 0x0100 /* Arithmetic zero */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) #define RISC_PSR_ULTRA 0x0020 /* Ultra mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) #define RISC_PSR_DIRQ 0x0010 /* DVMA interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) #define RISC_PSR_SIRQ 0x0008 /* SCSI processor interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) #define RISC_PSR_HIRQ 0x0004 /* Host interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) #define RISC_PSR_IPEND 0x0002 /* Interrupt pending */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) #define RISC_PSR_FFALSE 0x0001 /* Force false */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) /* RISC processor memory timing register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) #define RISC_MTREG_P1DFLT 0x1200 /* Default read/write timing, pg1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) #define RISC_MTREG_P0DFLT 0x0012 /* Default read/write timing, pg0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) #define RISC_MTREG_P1ULTRA 0x2300 /* Ultra-mode rw timing, pg1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) #define RISC_MTREG_P0ULTRA 0x0023 /* Ultra-mode rw timing, pg0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) /* Host command/ctrl register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) #define HCCTRL_NOP 0x0000 /* CMD: No operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) #define HCCTRL_RESET 0x1000 /* CMD: Reset RISC cpu */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) #define HCCTRL_PAUSE 0x2000 /* CMD: Pause RISC cpu */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) #define HCCTRL_REL 0x3000 /* CMD: Release paused RISC cpu */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) #define HCCTRL_STEP 0x4000 /* CMD: Single step RISC cpu */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) #define HCCTRL_SHIRQ 0x5000 /* CMD: Set host irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) #define HCCTRL_CHIRQ 0x6000 /* CMD: Clear host irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) #define HCCTRL_CRIRQ 0x7000 /* CMD: Clear RISC cpu irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) #define HCCTRL_BKPT 0x8000 /* CMD: Breakpoint enables change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) #define HCCTRL_TMODE 0xf000 /* CMD: Enable test mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) #define HCCTRL_HIRQ 0x0080 /* Host IRQ pending */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) #define HCCTRL_RRIP 0x0040 /* RISC cpu reset in happening now */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) #define HCCTRL_RPAUSED 0x0020 /* RISC cpu is paused now */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) #define HCCTRL_EBENAB 0x0010 /* External breakpoint enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) #define HCCTRL_B1ENAB 0x0008 /* Breakpoint 1 enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) #define HCCTRL_B0ENAB 0x0004 /* Breakpoint 0 enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) /* For our interrupt engine. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) #define for_each_qlogicpti(qp) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) for((qp) = qptichain; (qp); (qp) = (qp)->next)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) #endif /* !(_QLOGICPTI_H) */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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