^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /* to be used by qlogicfas and qlogic_cs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #ifndef __QLOGICFAS408_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #define __QLOGICFAS408_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) /*----------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) /* Configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) /* Set the following to max out the speed of the PIO PseudoDMA transfers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) again, 0 tends to be slower, but more stable. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define QL_TURBO_PDMA 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) /* This should be 1 to enable parity detection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define QL_ENABLE_PARITY 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) /* This will reset all devices when the driver is initialized (during bootup).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) The other linux drivers don't do this, but the DOS drivers do, and after
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) using DOS or some kind of crash or lockup this will bring things back
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) without requiring a cold boot. It does take some time to recover from a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) reset, so it is slower, and I have seen timeouts so that devices weren't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) recognized when this was set. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define QL_RESET_AT_START 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /* crystal frequency in megahertz (for offset 5 and 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) Please set this for your card. Most Qlogic cards are 40 Mhz. The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) Control Concepts ISA (not VLB) is 24 Mhz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define XTALFREQ 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /**********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* DANGER! modify these at your own risk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /* SLOWCABLE can usually be reset to zero if you have a clean setup and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) proper termination. The rest are for synchronous transfers and other
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) advanced features if your device can transfer faster than 5Mb/sec.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) If you are really curious, email me for a quick howto until I have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) something official */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /**********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /*****/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* config register 1 (offset 8) options */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* This needs to be set to 1 if your cabling is long or noisy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SLOWCABLE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /*****/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /* offset 0xc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* This will set fast (10Mhz) synchronous timing when set to 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) For this to have an effect, FASTCLK must also be 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define FASTSCSI 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /* This when set to 1 will set a faster sync transfer rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define FASTCLK 0 /*(XTALFREQ>25?1:0)*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /*****/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* offset 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* This is the sync transfer divisor, XTALFREQ/X will be the maximum
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) achievable data rate (assuming the rest of the system is capable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) and set properly) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define SYNCXFRPD 5 /*(XTALFREQ/5)*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /*****/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /* offset 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* This is the count of how many synchronous transfers can take place
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) i.e. how many reqs can occur before an ack is given.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) The maximum value for this is 15, the upper bits can modify
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) REQ/ACK assertion and deassertion during synchronous transfers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) If this is 0, the bus will only transfer asynchronously */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define SYNCOFFST 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /* for the curious, bits 7&6 control the deassertion delay in 1/2 cycles
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) of the 40Mhz clock. If FASTCLK is 1, specifying 01 (1/2) will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) cause the deassertion to be early by 1/2 clock. Bits 5&4 control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) the assertion delay, also in 1/2 clocks (FASTCLK is ignored here). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /*----------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) struct qlogicfas408_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) int qbase; /* Port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) int qinitid; /* initiator ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) int qabort; /* Flag to cause an abort */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) int qlirq; /* IRQ being used */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) int int_type; /* type of irq, 2 for ISA board, 0 for PCMCIA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) char qinfo[80]; /* description */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) struct scsi_cmnd *qlcmd; /* current command being processed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) struct Scsi_Host *shost; /* pointer back to host */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) struct qlogicfas408_priv *next; /* next private struct */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /* The qlogic card uses two register maps - These macros select which one */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define REG0 ( outb( inb( qbase + 0xd ) & 0x7f , qbase + 0xd ), outb( 4 , qbase + 0xd ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define REG1 ( outb( inb( qbase + 0xd ) | 0x80 , qbase + 0xd ), outb( 0xb4 | int_type, qbase + 0xd ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /* following is watchdog timeout in microseconds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define WATCHDOG 5000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /*----------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /* the following will set the monitor border color (useful to find
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) where something crashed or gets stuck at and as a simple profiler) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define rtrc(i) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define get_priv_by_cmd(x) (struct qlogicfas408_priv *)&((x)->device->host->hostdata[0])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define get_priv_by_host(x) (struct qlogicfas408_priv *)&((x)->hostdata[0])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) irqreturn_t qlogicfas408_ihandl(int irq, void *dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) int qlogicfas408_queuecommand(struct Scsi_Host *h, struct scsi_cmnd * cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) int qlogicfas408_biosparam(struct scsi_device * disk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) struct block_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) sector_t capacity, int ip[]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) int qlogicfas408_abort(struct scsi_cmnd * cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) extern int qlogicfas408_host_reset(struct scsi_cmnd *cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) const char *qlogicfas408_info(struct Scsi_Host *host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) int qlogicfas408_get_chip_type(int qbase, int int_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) void qlogicfas408_setup(int qbase, int id, int int_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) int qlogicfas408_detect(int qbase, int int_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) void qlogicfas408_disable_ints(struct qlogicfas408_priv *priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #endif /* __QLOGICFAS408_H */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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