^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*----------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) Qlogic linux driver - work in progress. No Warranty express or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) Use at your own risk. Support Tort Reform so you won't have to read all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) these silly disclaimers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) Copyright 1994, Tom Zerucha.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) tz@execpc.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) Additional Code, and much appreciated help by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) Michael A. Griffith
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) grif@cs.ucr.edu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) Thanks to Eric Youngdale and Dave Hinds for loadable module and PCMCIA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) help respectively, and for suffering through my foolishness during the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) debugging process.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) Reference Qlogic FAS408 Technical Manual, 53408-510-00A, May 10, 1994
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) (you can reference it, but it is incomplete and inaccurate in places)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) Version 0.46 1/30/97 - kernel 1.2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) Functions as standalone, loadable, and PCMCIA driver, the latter from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) Dave Hinds' PCMCIA package.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) Cleaned up 26/10/2002 by Alan Cox <alan@lxorguk.ukuu.org.uk> as part of the 2.5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) SCSI driver cleanup and audit. This driver still needs work on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) following
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) - Non terminating hardware waits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) - Some layering violations with its pcmcia stub
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) Redistributable under terms of the GNU General Public License
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) For the avoidance of doubt the "preferred form" of this code is one which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) is in an open non patent encumbered format. Where cryptographic key signing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) forms part of the process of creating an executable the information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) including keys needed to generate an equivalently functional executable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) are deemed to be part of the source code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #include <linux/blkdev.h> /* to get disk capacity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #include <linux/proc_fs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #include <linux/unistd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #include <linux/stat.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #include <asm/dma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #include "scsi.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #include <scsi/scsi_host.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #include "qlogicfas408.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /*----------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static int qlcfg5 = (XTALFREQ << 5); /* 15625/512 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static int qlcfg6 = SYNCXFRPD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static int qlcfg7 = SYNCOFFST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) static int qlcfg8 = (SLOWCABLE << 7) | (QL_ENABLE_PARITY << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) static int qlcfg9 = ((XTALFREQ + 4) / 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) static int qlcfgc = (FASTCLK << 3) | (FASTSCSI << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /*----------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /*----------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /* local functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /*----------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /* error recovery - reset everything */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) static void ql_zap(struct qlogicfas408_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) int x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) int qbase = priv->qbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) int int_type = priv->int_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) x = inb(qbase + 0xd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) REG0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) outb(3, qbase + 3); /* reset SCSI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) outb(2, qbase + 3); /* reset chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) if (x & 0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) REG1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * Do a pseudo-dma tranfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) static int ql_pdma(struct qlogicfas408_priv *priv, int phase, char *request, int reqlen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) int j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) int qbase = priv->qbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) j = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) if (phase & 1) { /* in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #if QL_TURBO_PDMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) rtrc(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* empty fifo in large chunks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) if (reqlen >= 128 && (inb(qbase + 8) & 2)) { /* full */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) insl(qbase + 4, request, 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) reqlen -= 128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) request += 128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) while (reqlen >= 84 && !(j & 0xc0)) /* 2/3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) if ((j = inb(qbase + 8)) & 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) insl(qbase + 4, request, 21);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) reqlen -= 84;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) request += 84;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) if (reqlen >= 44 && (inb(qbase + 8) & 8)) { /* 1/3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) insl(qbase + 4, request, 11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) reqlen -= 44;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) request += 44;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /* until both empty and int (or until reclen is 0) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) rtrc(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) j = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) while (reqlen && !((j & 0x10) && (j & 0xc0)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /* while bytes to receive and not empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) j &= 0xc0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) while (reqlen && !((j = inb(qbase + 8)) & 0x10))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) *request++ = inb(qbase + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) reqlen--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) if (j & 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) j = inb(qbase + 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) } else { /* out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #if QL_TURBO_PDMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) rtrc(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) if (reqlen >= 128 && inb(qbase + 8) & 0x10) { /* empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) outsl(qbase + 4, request, 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) reqlen -= 128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) request += 128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) while (reqlen >= 84 && !(j & 0xc0)) /* 1/3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) if (!((j = inb(qbase + 8)) & 8)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) outsl(qbase + 4, request, 21);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) reqlen -= 84;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) request += 84;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) if (reqlen >= 40 && !(inb(qbase + 8) & 4)) { /* 2/3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) outsl(qbase + 4, request, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) reqlen -= 40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) request += 40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /* until full and int (or until reclen is 0) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) rtrc(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) j = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) while (reqlen && !((j & 2) && (j & 0xc0))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /* while bytes to send and not full */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) while (reqlen && !((j = inb(qbase + 8)) & 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) outb(*request++, qbase + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) reqlen--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) if (j & 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) j = inb(qbase + 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /* maybe return reqlen */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) return inb(qbase + 8) & 0xc0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) * Wait for interrupt flag (polled - not real hardware interrupt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static int ql_wai(struct qlogicfas408_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) int k;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) int qbase = priv->qbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) unsigned long i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) k = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) i = jiffies + WATCHDOG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) while (time_before(jiffies, i) && !priv->qabort &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) !((k = inb(qbase + 4)) & 0xe0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) barrier();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) if (time_after_eq(jiffies, i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) return (DID_TIME_OUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) if (priv->qabort)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) return (priv->qabort == 1 ? DID_ABORT : DID_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) if (k & 0x60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) ql_zap(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) if (k & 0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) return (DID_PARITY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) if (k & 0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) return (DID_ERROR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) * Initiate scsi command - queueing handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) * caller must hold host lock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static void ql_icmd(struct scsi_cmnd *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) struct qlogicfas408_priv *priv = get_priv_by_cmd(cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) int qbase = priv->qbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) int int_type = priv->int_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) priv->qabort = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) REG0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) /* clearing of interrupts and the fifo is needed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) inb(qbase + 5); /* clear interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) if (inb(qbase + 5)) /* if still interrupting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) outb(2, qbase + 3); /* reset chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) else if (inb(qbase + 7) & 0x1f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) outb(1, qbase + 3); /* clear fifo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) while (inb(qbase + 5)); /* clear ints */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) REG1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) outb(1, qbase + 8); /* set for PIO pseudo DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) outb(0, qbase + 0xb); /* disable ints */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) inb(qbase + 8); /* clear int bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) REG0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) outb(0x40, qbase + 0xb); /* enable features */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /* configurables */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) outb(qlcfgc, qbase + 0xc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) /* config: no reset interrupt, (initiator) bus id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) outb(0x40 | qlcfg8 | priv->qinitid, qbase + 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) outb(qlcfg7, qbase + 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) outb(qlcfg6, qbase + 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) outb(qlcfg5, qbase + 5); /* select timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) outb(qlcfg9 & 7, qbase + 9); /* prescaler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) /* outb(0x99, qbase + 5); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) outb(scmd_id(cmd), qbase + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) for (i = 0; i < cmd->cmd_len; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) outb(cmd->cmnd[i], qbase + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) priv->qlcmd = cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) outb(0x41, qbase + 3); /* select and send command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) * Process scsi command - usually after interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) static unsigned int ql_pcmd(struct scsi_cmnd *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) unsigned int i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) unsigned long k;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) unsigned int result; /* ultimate return result */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) unsigned int status; /* scsi returned status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) unsigned int message; /* scsi returned message */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) unsigned int phase; /* recorded scsi phase */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) unsigned int reqlen; /* total length of transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) char *buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) struct qlogicfas408_priv *priv = get_priv_by_cmd(cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) int qbase = priv->qbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) int int_type = priv->int_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) rtrc(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) j = inb(qbase + 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) i = inb(qbase + 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) if (i == 0x20) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) return (DID_NO_CONNECT << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) i |= inb(qbase + 5); /* the 0x10 bit can be set after the 0x08 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) if (i != 0x18) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) printk(KERN_ERR "Ql:Bad Interrupt status:%02x\n", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) ql_zap(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) return (DID_BAD_INTR << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) j &= 7; /* j = inb( qbase + 7 ) >> 5; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) /* correct status is supposed to be step 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) /* it sometimes returns step 3 but with 0 bytes left to send */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) /* We can try stuffing the FIFO with the max each time, but we will get a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) sequence of 3 if any bytes are left (but we do flush the FIFO anyway */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) if (j != 3 && j != 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) printk(KERN_ERR "Ql:Bad sequence for command %d, int %02X, cmdleft = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) j, i, inb(qbase + 7) & 0x1f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) ql_zap(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) return (DID_ERROR << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) result = DID_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) if (inb(qbase + 7) & 0x1f) /* if some bytes in fifo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) outb(1, qbase + 3); /* clear fifo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) /* note that request_bufflen is the total xfer size when sg is used */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) reqlen = scsi_bufflen(cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) /* note that it won't work if transfers > 16M are requested */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) if (reqlen && !((phase = inb(qbase + 4)) & 6)) { /* data phase */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) struct scatterlist *sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) rtrc(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) outb(reqlen, qbase); /* low-mid xfer cnt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) outb(reqlen >> 8, qbase + 1); /* low-mid xfer cnt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) outb(reqlen >> 16, qbase + 0xe); /* high xfer cnt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) outb(0x90, qbase + 3); /* command do xfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) /* PIO pseudo DMA to buffer or sglist */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) REG1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) scsi_for_each_sg(cmd, sg, scsi_sg_count(cmd), i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) if (priv->qabort) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) REG0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) return ((priv->qabort == 1 ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) DID_ABORT : DID_RESET) << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) buf = sg_virt(sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) if (ql_pdma(priv, phase, buf, sg->length))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) REG0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) rtrc(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) * Wait for irq (split into second state of irq handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) * if this can take time)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) if ((k = ql_wai(priv)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) return (k << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) k = inb(qbase + 5); /* should be 0x10, bus service */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) * Enter Status (and Message In) Phase
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) k = jiffies + WATCHDOG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) while (time_before(jiffies, k) && !priv->qabort &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) !(inb(qbase + 4) & 6))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) cpu_relax(); /* wait for status phase */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) if (time_after_eq(jiffies, k)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) ql_zap(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) return (DID_TIME_OUT << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) /* FIXME: timeout ?? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) while (inb(qbase + 5))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) cpu_relax(); /* clear pending ints */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) if (priv->qabort)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) return ((priv->qabort == 1 ? DID_ABORT : DID_RESET) << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) outb(0x11, qbase + 3); /* get status and message */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) if ((k = ql_wai(priv)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) return (k << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) i = inb(qbase + 5); /* get chip irq stat */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) j = inb(qbase + 7) & 0x1f; /* and bytes rec'd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) status = inb(qbase + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) message = inb(qbase + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) * Should get function complete int if Status and message, else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) * bus serv if only status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) if (!((i == 8 && j == 2) || (i == 0x10 && j == 1))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) printk(KERN_ERR "Ql:Error during status phase, int=%02X, %d bytes recd\n", i, j);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) result = DID_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) outb(0x12, qbase + 3); /* done, disconnect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) rtrc(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) if ((k = ql_wai(priv)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) return (k << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) * Should get bus service interrupt and disconnect interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) i = inb(qbase + 5); /* should be bus service */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) while (!priv->qabort && ((i & 0x20) != 0x20)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) barrier();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) i |= inb(qbase + 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) rtrc(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) if (priv->qabort)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) return ((priv->qabort == 1 ? DID_ABORT : DID_RESET) << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) return (result << 16) | (message << 8) | (status & STATUS_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) * Interrupt handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) static void ql_ihandl(void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) struct scsi_cmnd *icmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) struct Scsi_Host *host = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) struct qlogicfas408_priv *priv = get_priv_by_host(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) int qbase = priv->qbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) REG0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) if (!(inb(qbase + 4) & 0x80)) /* false alarm? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) if (priv->qlcmd == NULL) { /* no command to process? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) i = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) while (i-- && inb(qbase + 5)); /* maybe also ql_zap() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) icmd = priv->qlcmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) icmd->result = ql_pcmd(icmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) priv->qlcmd = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) * If result is CHECK CONDITION done calls qcommand to request
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) * sense
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) (icmd->scsi_done) (icmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) irqreturn_t qlogicfas408_ihandl(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) struct Scsi_Host *host = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) spin_lock_irqsave(host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) ql_ihandl(dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) spin_unlock_irqrestore(host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) * Queued command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) static int qlogicfas408_queuecommand_lck(struct scsi_cmnd *cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) void (*done) (struct scsi_cmnd *))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) struct qlogicfas408_priv *priv = get_priv_by_cmd(cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) if (scmd_id(cmd) == priv->qinitid) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) cmd->result = DID_BAD_TARGET << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) done(cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) cmd->scsi_done = done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) /* wait for the last command's interrupt to finish */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) while (priv->qlcmd != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) barrier();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) ql_icmd(cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) DEF_SCSI_QCMD(qlogicfas408_queuecommand)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) * Return bios parameters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) int qlogicfas408_biosparam(struct scsi_device *disk, struct block_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) sector_t capacity, int ip[])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) /* This should mimic the DOS Qlogic driver's behavior exactly */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) ip[0] = 0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) ip[1] = 0x20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) ip[2] = (unsigned long) capacity / (ip[0] * ip[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) if (ip[2] > 1024) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) ip[0] = 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) ip[1] = 0x3f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) ip[2] = (unsigned long) capacity / (ip[0] * ip[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) if (ip[2] > 1023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) ip[2] = 1023;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) * Abort a command in progress
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) int qlogicfas408_abort(struct scsi_cmnd *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) struct qlogicfas408_priv *priv = get_priv_by_cmd(cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) priv->qabort = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) ql_zap(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) return SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) * Reset SCSI bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) * FIXME: This function is invoked with cmd = NULL directly by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) * the PCMCIA qlogic_stub code. This wants fixing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) int qlogicfas408_host_reset(struct scsi_cmnd *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) struct qlogicfas408_priv *priv = get_priv_by_cmd(cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) priv->qabort = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) spin_lock_irqsave(cmd->device->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) ql_zap(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) spin_unlock_irqrestore(cmd->device->host->host_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) return SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) * Return info string
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) const char *qlogicfas408_info(struct Scsi_Host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) struct qlogicfas408_priv *priv = get_priv_by_host(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) return priv->qinfo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) * Get type of chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) int qlogicfas408_get_chip_type(int qbase, int int_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) REG1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) return inb(qbase + 0xe) & 0xf8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) * Perform initialization tasks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) void qlogicfas408_setup(int qbase, int id, int int_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) outb(1, qbase + 8); /* set for PIO pseudo DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) REG0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) outb(0x40 | qlcfg8 | id, qbase + 8); /* (ini) bus id, disable scsi rst */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) outb(qlcfg5, qbase + 5); /* select timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) outb(qlcfg9, qbase + 9); /* prescaler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) #if QL_RESET_AT_START
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) outb(3, qbase + 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) REG1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) /* FIXME: timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) while (inb(qbase + 0xf) & 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) REG0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) * Checks if this is a QLogic FAS 408
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) int qlogicfas408_detect(int qbase, int int_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) REG1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) return (((inb(qbase + 0xe) ^ inb(qbase + 0xe)) == 7) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) ((inb(qbase + 0xe) ^ inb(qbase + 0xe)) == 7));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) * Disable interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) void qlogicfas408_disable_ints(struct qlogicfas408_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) int qbase = priv->qbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) int int_type = priv->int_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) REG1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) outb(0, qbase + 0xb); /* disable ints */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) * Init and exit functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) static int __init qlogicfas408_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) static void __exit qlogicfas408_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) MODULE_AUTHOR("Tom Zerucha, Michael Griffith");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) MODULE_DESCRIPTION("Driver for the Qlogic FAS SCSI controllers");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) module_init(qlogicfas408_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) module_exit(qlogicfas408_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) EXPORT_SYMBOL(qlogicfas408_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) EXPORT_SYMBOL(qlogicfas408_queuecommand);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) EXPORT_SYMBOL(qlogicfas408_abort);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) EXPORT_SYMBOL(qlogicfas408_host_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) EXPORT_SYMBOL(qlogicfas408_biosparam);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) EXPORT_SYMBOL(qlogicfas408_ihandl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) EXPORT_SYMBOL(qlogicfas408_get_chip_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) EXPORT_SYMBOL(qlogicfas408_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) EXPORT_SYMBOL(qlogicfas408_detect);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) EXPORT_SYMBOL(qlogicfas408_disable_ints);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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