^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * QLogic iSCSI HBA Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (c) 2003-2013 QLogic Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #ifndef __QLA_NX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define __QLA_NX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Following are the states of the Phantom. Phantom will set them and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Host will read to check if the fields are correct.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define PHAN_INITIALIZE_FAILED 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define PHAN_INITIALIZE_COMPLETE 0xff01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) /* Host writes the following to notify that it has done the init-handshake */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define PHAN_INITIALIZE_ACK 0xf00f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define PHAN_PEG_RCV_INITIALIZED 0xff01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /*CRB_RELATED*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define QLA82XX_CRB_BASE (QLA82XX_CAM_RAM(0x200))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define QLA82XX_REG(X) (QLA82XX_CRB_BASE+(X))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define CRB_CMDPEG_STATE QLA82XX_REG(0x50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define CRB_RCVPEG_STATE QLA82XX_REG(0x13c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define CRB_DMA_SHIFT QLA82XX_REG(0xcc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define CRB_TEMP_STATE QLA82XX_REG(0x1b4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define CRB_CMDPEG_CHECK_RETRY_COUNT 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define CRB_CMDPEG_CHECK_DELAY 500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define qla82xx_get_temp_val(x) ((x) >> 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define qla82xx_get_temp_state(x) ((x) & 0xffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define qla82xx_encode_temp(val, state) (((val) << 16) | (state))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * Temperature control.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) QLA82XX_TEMP_NORMAL = 0x1, /* Normal operating range */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) QLA82XX_TEMP_WARN, /* Sound alert, temperature getting high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) QLA82XX_TEMP_PANIC /* Fatal error, hardware has shut down. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define CRB_NIU_XG_PAUSE_CTL_P0 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define CRB_NIU_XG_PAUSE_CTL_P1 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define QLA82XX_HW_H0_CH_HUB_ADR 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define QLA82XX_HW_H1_CH_HUB_ADR 0x0E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define QLA82XX_HW_H2_CH_HUB_ADR 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define QLA82XX_HW_H3_CH_HUB_ADR 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define QLA82XX_HW_H4_CH_HUB_ADR 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define QLA82XX_HW_H5_CH_HUB_ADR 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define QLA82XX_HW_H6_CH_HUB_ADR 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* Hub 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define QLA82XX_HW_MN_CRB_AGT_ADR 0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define QLA82XX_HW_MS_CRB_AGT_ADR 0x25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* Hub 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define QLA82XX_HW_PS_CRB_AGT_ADR 0x73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define QLA82XX_HW_QMS_CRB_AGT_ADR 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define QLA82XX_HW_RPMX3_CRB_AGT_ADR 0x0b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define QLA82XX_HW_SQGS0_CRB_AGT_ADR 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define QLA82XX_HW_SQGS1_CRB_AGT_ADR 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define QLA82XX_HW_SQGS2_CRB_AGT_ADR 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define QLA82XX_HW_SQGS3_CRB_AGT_ADR 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define QLA82XX_HW_C2C0_CRB_AGT_ADR 0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define QLA82XX_HW_C2C1_CRB_AGT_ADR 0x59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define QLA82XX_HW_C2C2_CRB_AGT_ADR 0x5a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define QLA82XX_HW_RPMX2_CRB_AGT_ADR 0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define QLA82XX_HW_RPMX4_CRB_AGT_ADR 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define QLA82XX_HW_RPMX7_CRB_AGT_ADR 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define QLA82XX_HW_RPMX9_CRB_AGT_ADR 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define QLA82XX_HW_SMB_CRB_AGT_ADR 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* Hub 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define QLA82XX_HW_NIU_CRB_AGT_ADR 0x31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define QLA82XX_HW_I2C0_CRB_AGT_ADR 0x19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define QLA82XX_HW_I2C1_CRB_AGT_ADR 0x29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define QLA82XX_HW_SN_CRB_AGT_ADR 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define QLA82XX_HW_I2Q_CRB_AGT_ADR 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define QLA82XX_HW_LPC_CRB_AGT_ADR 0x22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define QLA82XX_HW_ROMUSB_CRB_AGT_ADR 0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define QLA82XX_HW_QM_CRB_AGT_ADR 0x66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define QLA82XX_HW_SQG0_CRB_AGT_ADR 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define QLA82XX_HW_SQG1_CRB_AGT_ADR 0x61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define QLA82XX_HW_SQG2_CRB_AGT_ADR 0x62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define QLA82XX_HW_SQG3_CRB_AGT_ADR 0x63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define QLA82XX_HW_RPMX1_CRB_AGT_ADR 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define QLA82XX_HW_RPMX5_CRB_AGT_ADR 0x0d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define QLA82XX_HW_RPMX6_CRB_AGT_ADR 0x0e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define QLA82XX_HW_RPMX8_CRB_AGT_ADR 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /* Hub 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define QLA82XX_HW_PH_CRB_AGT_ADR 0x1A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define QLA82XX_HW_SRE_CRB_AGT_ADR 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define QLA82XX_HW_EG_CRB_AGT_ADR 0x51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define QLA82XX_HW_RPMX0_CRB_AGT_ADR 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* Hub 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define QLA82XX_HW_PEGN0_CRB_AGT_ADR 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define QLA82XX_HW_PEGN1_CRB_AGT_ADR 0x41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define QLA82XX_HW_PEGN2_CRB_AGT_ADR 0x42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define QLA82XX_HW_PEGN3_CRB_AGT_ADR 0x43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define QLA82XX_HW_PEGNI_CRB_AGT_ADR 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define QLA82XX_HW_PEGND_CRB_AGT_ADR 0x45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define QLA82XX_HW_PEGNC_CRB_AGT_ADR 0x46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define QLA82XX_HW_PEGR0_CRB_AGT_ADR 0x47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define QLA82XX_HW_PEGR1_CRB_AGT_ADR 0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define QLA82XX_HW_PEGR2_CRB_AGT_ADR 0x49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define QLA82XX_HW_PEGR3_CRB_AGT_ADR 0x4a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define QLA82XX_HW_PEGN4_CRB_AGT_ADR 0x4b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* Hub 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define QLA82XX_HW_PEGS0_CRB_AGT_ADR 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define QLA82XX_HW_PEGS1_CRB_AGT_ADR 0x41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define QLA82XX_HW_PEGS2_CRB_AGT_ADR 0x42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define QLA82XX_HW_PEGS3_CRB_AGT_ADR 0x43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define QLA82XX_HW_PEGSI_CRB_AGT_ADR 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define QLA82XX_HW_PEGSD_CRB_AGT_ADR 0x45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define QLA82XX_HW_PEGSC_CRB_AGT_ADR 0x46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /* Hub 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define QLA82XX_HW_CAS0_CRB_AGT_ADR 0x46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define QLA82XX_HW_CAS1_CRB_AGT_ADR 0x47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define QLA82XX_HW_CAS2_CRB_AGT_ADR 0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define QLA82XX_HW_CAS3_CRB_AGT_ADR 0x49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define QLA82XX_HW_NCM_CRB_AGT_ADR 0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define QLA82XX_HW_TMR_CRB_AGT_ADR 0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define QLA82XX_HW_XDMA_CRB_AGT_ADR 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define QLA82XX_HW_OCM0_CRB_AGT_ADR 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define QLA82XX_HW_OCM1_CRB_AGT_ADR 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /* This field defines PCI/X adr [25:20] of agents on the CRB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define QLA82XX_HW_PX_MAP_CRB_PH 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define QLA82XX_HW_PX_MAP_CRB_PS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define QLA82XX_HW_PX_MAP_CRB_MN 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define QLA82XX_HW_PX_MAP_CRB_MS 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define QLA82XX_HW_PX_MAP_CRB_SRE 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define QLA82XX_HW_PX_MAP_CRB_NIU 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define QLA82XX_HW_PX_MAP_CRB_QMN 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define QLA82XX_HW_PX_MAP_CRB_SQN0 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define QLA82XX_HW_PX_MAP_CRB_SQN1 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define QLA82XX_HW_PX_MAP_CRB_SQN2 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define QLA82XX_HW_PX_MAP_CRB_SQN3 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define QLA82XX_HW_PX_MAP_CRB_QMS 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define QLA82XX_HW_PX_MAP_CRB_SQS0 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define QLA82XX_HW_PX_MAP_CRB_SQS1 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define QLA82XX_HW_PX_MAP_CRB_SQS2 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define QLA82XX_HW_PX_MAP_CRB_SQS3 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define QLA82XX_HW_PX_MAP_CRB_PGN0 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define QLA82XX_HW_PX_MAP_CRB_PGN1 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define QLA82XX_HW_PX_MAP_CRB_PGN2 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define QLA82XX_HW_PX_MAP_CRB_PGN3 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define QLA82XX_HW_PX_MAP_CRB_PGN4 QLA82XX_HW_PX_MAP_CRB_SQS2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define QLA82XX_HW_PX_MAP_CRB_PGND 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define QLA82XX_HW_PX_MAP_CRB_PGNI 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define QLA82XX_HW_PX_MAP_CRB_PGS0 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define QLA82XX_HW_PX_MAP_CRB_PGS1 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define QLA82XX_HW_PX_MAP_CRB_PGS2 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define QLA82XX_HW_PX_MAP_CRB_PGS3 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define QLA82XX_HW_PX_MAP_CRB_PGSD 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define QLA82XX_HW_PX_MAP_CRB_PGSI 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define QLA82XX_HW_PX_MAP_CRB_SN 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define QLA82XX_HW_PX_MAP_CRB_EG 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define QLA82XX_HW_PX_MAP_CRB_PH2 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define QLA82XX_HW_PX_MAP_CRB_PS2 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define QLA82XX_HW_PX_MAP_CRB_CAM 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define QLA82XX_HW_PX_MAP_CRB_CAS0 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define QLA82XX_HW_PX_MAP_CRB_CAS1 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define QLA82XX_HW_PX_MAP_CRB_CAS2 37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define QLA82XX_HW_PX_MAP_CRB_C2C0 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define QLA82XX_HW_PX_MAP_CRB_C2C1 39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define QLA82XX_HW_PX_MAP_CRB_TIMR 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define QLA82XX_HW_PX_MAP_CRB_RPMX1 42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define QLA82XX_HW_PX_MAP_CRB_RPMX2 43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define QLA82XX_HW_PX_MAP_CRB_RPMX3 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define QLA82XX_HW_PX_MAP_CRB_RPMX4 45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define QLA82XX_HW_PX_MAP_CRB_RPMX5 46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define QLA82XX_HW_PX_MAP_CRB_RPMX6 47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define QLA82XX_HW_PX_MAP_CRB_RPMX7 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define QLA82XX_HW_PX_MAP_CRB_XDMA 49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define QLA82XX_HW_PX_MAP_CRB_I2Q 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define QLA82XX_HW_PX_MAP_CRB_ROMUSB 51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define QLA82XX_HW_PX_MAP_CRB_CAS3 52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define QLA82XX_HW_PX_MAP_CRB_RPMX0 53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define QLA82XX_HW_PX_MAP_CRB_RPMX8 54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define QLA82XX_HW_PX_MAP_CRB_RPMX9 55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define QLA82XX_HW_PX_MAP_CRB_OCM0 56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define QLA82XX_HW_PX_MAP_CRB_OCM1 57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define QLA82XX_HW_PX_MAP_CRB_SMB 58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define QLA82XX_HW_PX_MAP_CRB_I2C0 59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define QLA82XX_HW_PX_MAP_CRB_I2C1 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define QLA82XX_HW_PX_MAP_CRB_LPC 61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define QLA82XX_HW_PX_MAP_CRB_PGNC 62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define QLA82XX_HW_PX_MAP_CRB_PGR0 63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define QLA82XX_HW_PX_MAP_CRB_PGR1 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define QLA82XX_HW_PX_MAP_CRB_PGR2 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define QLA82XX_HW_PX_MAP_CRB_PGR3 41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) /* This field defines CRB adr [31:20] of the agents */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define QLA82XX_HW_CRB_HUB_AGT_ADR_MN ((QLA82XX_HW_H0_CH_HUB_ADR << 7) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) QLA82XX_HW_MN_CRB_AGT_ADR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define QLA82XX_HW_CRB_HUB_AGT_ADR_PH ((QLA82XX_HW_H0_CH_HUB_ADR << 7) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) QLA82XX_HW_PH_CRB_AGT_ADR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define QLA82XX_HW_CRB_HUB_AGT_ADR_MS ((QLA82XX_HW_H0_CH_HUB_ADR << 7) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) QLA82XX_HW_MS_CRB_AGT_ADR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define QLA82XX_HW_CRB_HUB_AGT_ADR_PS ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) QLA82XX_HW_PS_CRB_AGT_ADR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define QLA82XX_HW_CRB_HUB_AGT_ADR_SS ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) QLA82XX_HW_SS_CRB_AGT_ADR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX3 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) QLA82XX_HW_RPMX3_CRB_AGT_ADR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define QLA82XX_HW_CRB_HUB_AGT_ADR_QMS ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) QLA82XX_HW_QMS_CRB_AGT_ADR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define QLA82XX_HW_CRB_HUB_AGT_ADR_SQS0 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) QLA82XX_HW_SQGS0_CRB_AGT_ADR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define QLA82XX_HW_CRB_HUB_AGT_ADR_SQS1 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) QLA82XX_HW_SQGS1_CRB_AGT_ADR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define QLA82XX_HW_CRB_HUB_AGT_ADR_SQS2 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) QLA82XX_HW_SQGS2_CRB_AGT_ADR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define QLA82XX_HW_CRB_HUB_AGT_ADR_SQS3 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) QLA82XX_HW_SQGS3_CRB_AGT_ADR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define QLA82XX_HW_CRB_HUB_AGT_ADR_C2C0 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) QLA82XX_HW_C2C0_CRB_AGT_ADR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define QLA82XX_HW_CRB_HUB_AGT_ADR_C2C1 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) QLA82XX_HW_C2C1_CRB_AGT_ADR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX2 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) QLA82XX_HW_RPMX2_CRB_AGT_ADR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX4 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) QLA82XX_HW_RPMX4_CRB_AGT_ADR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX7 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) QLA82XX_HW_RPMX7_CRB_AGT_ADR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX9 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) QLA82XX_HW_RPMX9_CRB_AGT_ADR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define QLA82XX_HW_CRB_HUB_AGT_ADR_SMB ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) QLA82XX_HW_SMB_CRB_AGT_ADR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define QLA82XX_HW_CRB_HUB_AGT_ADR_NIU ((QLA82XX_HW_H2_CH_HUB_ADR << 7) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) QLA82XX_HW_NIU_CRB_AGT_ADR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define QLA82XX_HW_CRB_HUB_AGT_ADR_I2C0 ((QLA82XX_HW_H2_CH_HUB_ADR << 7) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) QLA82XX_HW_I2C0_CRB_AGT_ADR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define QLA82XX_HW_CRB_HUB_AGT_ADR_I2C1 ((QLA82XX_HW_H2_CH_HUB_ADR << 7) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) QLA82XX_HW_I2C1_CRB_AGT_ADR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define QLA82XX_HW_CRB_HUB_AGT_ADR_SRE ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) QLA82XX_HW_SRE_CRB_AGT_ADR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define QLA82XX_HW_CRB_HUB_AGT_ADR_EG ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) QLA82XX_HW_EG_CRB_AGT_ADR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX0 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) QLA82XX_HW_RPMX0_CRB_AGT_ADR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define QLA82XX_HW_CRB_HUB_AGT_ADR_QMN ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) QLA82XX_HW_QM_CRB_AGT_ADR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define QLA82XX_HW_CRB_HUB_AGT_ADR_SQN0 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) QLA82XX_HW_SQG0_CRB_AGT_ADR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define QLA82XX_HW_CRB_HUB_AGT_ADR_SQN1 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) QLA82XX_HW_SQG1_CRB_AGT_ADR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define QLA82XX_HW_CRB_HUB_AGT_ADR_SQN2 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) QLA82XX_HW_SQG2_CRB_AGT_ADR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define QLA82XX_HW_CRB_HUB_AGT_ADR_SQN3 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) QLA82XX_HW_SQG3_CRB_AGT_ADR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX1 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) QLA82XX_HW_RPMX1_CRB_AGT_ADR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX5 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) QLA82XX_HW_RPMX5_CRB_AGT_ADR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX6 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) QLA82XX_HW_RPMX6_CRB_AGT_ADR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX8 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) QLA82XX_HW_RPMX8_CRB_AGT_ADR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define QLA82XX_HW_CRB_HUB_AGT_ADR_CAS0 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) QLA82XX_HW_CAS0_CRB_AGT_ADR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define QLA82XX_HW_CRB_HUB_AGT_ADR_CAS1 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) QLA82XX_HW_CAS1_CRB_AGT_ADR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define QLA82XX_HW_CRB_HUB_AGT_ADR_CAS2 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) QLA82XX_HW_CAS2_CRB_AGT_ADR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define QLA82XX_HW_CRB_HUB_AGT_ADR_CAS3 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) QLA82XX_HW_CAS3_CRB_AGT_ADR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGNI ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) QLA82XX_HW_PEGNI_CRB_AGT_ADR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGND ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) QLA82XX_HW_PEGND_CRB_AGT_ADR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGN0 ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) QLA82XX_HW_PEGN0_CRB_AGT_ADR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGN1 ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) QLA82XX_HW_PEGN1_CRB_AGT_ADR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGN2 ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) QLA82XX_HW_PEGN2_CRB_AGT_ADR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGN3 ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) QLA82XX_HW_PEGN3_CRB_AGT_ADR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGN4 ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) QLA82XX_HW_PEGN4_CRB_AGT_ADR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGNC ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) QLA82XX_HW_PEGNC_CRB_AGT_ADR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGR0 ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) QLA82XX_HW_PEGR0_CRB_AGT_ADR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGR1 ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) QLA82XX_HW_PEGR1_CRB_AGT_ADR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGR2 ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) QLA82XX_HW_PEGR2_CRB_AGT_ADR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGR3 ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) QLA82XX_HW_PEGR3_CRB_AGT_ADR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGSI ((QLA82XX_HW_H5_CH_HUB_ADR << 7) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) QLA82XX_HW_PEGSI_CRB_AGT_ADR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGSD ((QLA82XX_HW_H5_CH_HUB_ADR << 7) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) QLA82XX_HW_PEGSD_CRB_AGT_ADR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGS0 ((QLA82XX_HW_H5_CH_HUB_ADR << 7) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) QLA82XX_HW_PEGS0_CRB_AGT_ADR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGS1 ((QLA82XX_HW_H5_CH_HUB_ADR << 7) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) QLA82XX_HW_PEGS1_CRB_AGT_ADR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGS2 ((QLA82XX_HW_H5_CH_HUB_ADR << 7) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) QLA82XX_HW_PEGS2_CRB_AGT_ADR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGS3 ((QLA82XX_HW_H5_CH_HUB_ADR << 7) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) QLA82XX_HW_PEGS3_CRB_AGT_ADR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGSC ((QLA82XX_HW_H5_CH_HUB_ADR << 7) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) QLA82XX_HW_PEGSC_CRB_AGT_ADR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define QLA82XX_HW_CRB_HUB_AGT_ADR_CAM ((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) QLA82XX_HW_NCM_CRB_AGT_ADR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR ((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) QLA82XX_HW_TMR_CRB_AGT_ADR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA ((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) QLA82XX_HW_XDMA_CRB_AGT_ADR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define QLA82XX_HW_CRB_HUB_AGT_ADR_SN ((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) QLA82XX_HW_SN_CRB_AGT_ADR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q ((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) QLA82XX_HW_I2Q_CRB_AGT_ADR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB ((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) QLA82XX_HW_ROMUSB_CRB_AGT_ADR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define QLA82XX_HW_CRB_HUB_AGT_ADR_OCM0 ((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) QLA82XX_HW_OCM0_CRB_AGT_ADR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define QLA82XX_HW_CRB_HUB_AGT_ADR_OCM1 ((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) QLA82XX_HW_OCM1_CRB_AGT_ADR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define QLA82XX_HW_CRB_HUB_AGT_ADR_LPC ((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) QLA82XX_HW_LPC_CRB_AGT_ADR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define ROMUSB_GLB (QLA82XX_CRB_ROMUSB + 0x00000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define QLA82XX_ROMUSB_GLB_PEGTUNE_DONE (ROMUSB_GLB + 0x005c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define QLA82XX_ROMUSB_GLB_STATUS (ROMUSB_GLB + 0x0004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define QLA82XX_ROMUSB_GLB_SW_RESET (ROMUSB_GLB + 0x0008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define QLA82XX_ROMUSB_ROM_ADDRESS (ROMUSB_ROM + 0x0008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define QLA82XX_ROMUSB_ROM_WDATA (ROMUSB_ROM + 0x000c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define QLA82XX_ROMUSB_ROM_ABYTE_CNT (ROMUSB_ROM + 0x0010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define QLA82XX_ROMUSB_ROM_DUMMY_BYTE_CNT (ROMUSB_ROM + 0x0014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define QLA82XX_ROMUSB_ROM_RDATA (ROMUSB_ROM + 0x0018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define ROMUSB_ROM (QLA82XX_CRB_ROMUSB + 0x10000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define QLA82XX_ROMUSB_ROM_INSTR_OPCODE (ROMUSB_ROM + 0x0004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define QLA82XX_ROMUSB_GLB_CAS_RST (ROMUSB_GLB + 0x0038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) /* Lock IDs for ROM lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define ROM_LOCK_DRIVER 0x0d417340
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define QLA82XX_PCI_CRB_WINDOWSIZE 0x00100000 /* all are 1MB windows */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define QLA82XX_PCI_CRB_WINDOW(A) (QLA82XX_PCI_CRBSPACE + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) (A)*QLA82XX_PCI_CRB_WINDOWSIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define QLA82XX_CRB_C2C_0 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_C2C0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define QLA82XX_CRB_C2C_1 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_C2C1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define QLA82XX_CRB_C2C_2 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_C2C2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define QLA82XX_CRB_CAM \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_CAM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define QLA82XX_CRB_CASPER \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_CAS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define QLA82XX_CRB_CASPER_0 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_CAS0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define QLA82XX_CRB_CASPER_1 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_CAS1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define QLA82XX_CRB_CASPER_2 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_CAS2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define QLA82XX_CRB_DDR_MD \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_MS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define QLA82XX_CRB_DDR_NET \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_MN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define QLA82XX_CRB_EPG \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_EG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define QLA82XX_CRB_I2Q \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_I2Q)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define QLA82XX_CRB_NIU \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_NIU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) /* HACK upon HACK upon HACK (for PCIE builds) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define QLA82XX_CRB_PCIX_HOST \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define QLA82XX_CRB_PCIX_HOST2 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PH2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define QLA82XX_CRB_PCIX_MD \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define QLA82XX_CRB_PCIE QLA82XX_CRB_PCIX_MD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) /* window 1 pcie slot */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define QLA82XX_CRB_PCIE2 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PS2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define QLA82XX_CRB_PEG_MD_0 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGS0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define QLA82XX_CRB_PEG_MD_1 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGS1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define QLA82XX_CRB_PEG_MD_2 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGS2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #define QLA82XX_CRB_PEG_MD_3 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGS3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define QLA82XX_CRB_PEG_MD_3 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGS3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #define QLA82XX_CRB_PEG_MD_D \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGSD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #define QLA82XX_CRB_PEG_MD_I \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGSI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #define QLA82XX_CRB_PEG_NET_0 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGN0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) #define QLA82XX_CRB_PEG_NET_1 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGN1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #define QLA82XX_CRB_PEG_NET_2 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGN2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #define QLA82XX_CRB_PEG_NET_3 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGN3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #define QLA82XX_CRB_PEG_NET_4 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGN4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #define QLA82XX_CRB_PEG_NET_D \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGND)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) #define QLA82XX_CRB_PEG_NET_I \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGNI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #define QLA82XX_CRB_PQM_MD \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_QMS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) #define QLA82XX_CRB_PQM_NET \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_QMN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) #define QLA82XX_CRB_QDR_MD \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) #define QLA82XX_CRB_QDR_NET \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) #define QLA82XX_CRB_ROMUSB \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_ROMUSB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) #define QLA82XX_CRB_RPMX_0 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_RPMX0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) #define QLA82XX_CRB_RPMX_1 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_RPMX1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) #define QLA82XX_CRB_RPMX_2 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_RPMX2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) #define QLA82XX_CRB_RPMX_3 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_RPMX3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) #define QLA82XX_CRB_RPMX_4 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_RPMX4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) #define QLA82XX_CRB_RPMX_5 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_RPMX5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) #define QLA82XX_CRB_RPMX_6 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_RPMX6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) #define QLA82XX_CRB_RPMX_7 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_RPMX7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) #define QLA82XX_CRB_SQM_MD_0 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SQS0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) #define QLA82XX_CRB_SQM_MD_1 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SQS1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) #define QLA82XX_CRB_SQM_MD_2 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SQS2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) #define QLA82XX_CRB_SQM_MD_3 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SQS3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) #define QLA82XX_CRB_SQM_NET_0 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SQN0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) #define QLA82XX_CRB_SQM_NET_1 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SQN1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) #define QLA82XX_CRB_SQM_NET_2 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SQN2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) #define QLA82XX_CRB_SQM_NET_3 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SQN3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) #define QLA82XX_CRB_SRE \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SRE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) #define QLA82XX_CRB_TIMER \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_TIMR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) #define QLA82XX_CRB_XDMA \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_XDMA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) #define QLA82XX_CRB_I2C0 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_I2C0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) #define QLA82XX_CRB_I2C1 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_I2C1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) #define QLA82XX_CRB_OCM0 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_OCM0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) #define QLA82XX_CRB_SMB \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SMB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) #define QLA82XX_CRB_MAX QLA82XX_PCI_CRB_WINDOW(64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) * ====================== BASE ADDRESSES ON-CHIP ======================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) * Base addresses of major components on-chip.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) * ====================== BASE ADDRESSES ON-CHIP ======================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) #define QLA8XXX_ADDR_DDR_NET (0x0000000000000000ULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) #define QLA8XXX_ADDR_DDR_NET_MAX (0x000000000fffffffULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) /* Imbus address bit used to indicate a host address. This bit is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) * eliminated by the pcie bar and bar select before presentation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) * over pcie. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) /* host memory via IMBUS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) #define QLA82XX_P2_ADDR_PCIE (0x0000000800000000ULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) #define QLA82XX_P3_ADDR_PCIE (0x0000008000000000ULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) #define QLA82XX_ADDR_PCIE_MAX (0x0000000FFFFFFFFFULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) #define QLA8XXX_ADDR_OCM0 (0x0000000200000000ULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) #define QLA8XXX_ADDR_OCM0_MAX (0x00000002000fffffULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) #define QLA8XXX_ADDR_OCM1 (0x0000000200400000ULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) #define QLA8XXX_ADDR_OCM1_MAX (0x00000002004fffffULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) #define QLA8XXX_ADDR_QDR_NET (0x0000000300000000ULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) #define QLA82XX_P2_ADDR_QDR_NET_MAX (0x00000003001fffffULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) #define QLA82XX_P3_ADDR_QDR_NET_MAX (0x0000000303ffffffULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) #define QLA8XXX_ADDR_QDR_NET_MAX (0x0000000307ffffffULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) #define QLA82XX_PCI_CRBSPACE (unsigned long)0x06000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) #define QLA82XX_PCI_DIRECT_CRB (unsigned long)0x04400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) #define QLA82XX_PCI_CAMQM (unsigned long)0x04800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) #define QLA82XX_PCI_CAMQM_MAX (unsigned long)0x04ffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) #define QLA82XX_PCI_DDR_NET (unsigned long)0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) #define QLA82XX_PCI_QDR_NET (unsigned long)0x04000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) #define QLA82XX_PCI_QDR_NET_MAX (unsigned long)0x043fffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) /* PCI Windowing for DDR regions. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) #define QLA8XXX_ADDR_IN_RANGE(addr, low, high) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) (((addr) <= (high)) && ((addr) >= (low)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) * Register offsets for MN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) #define MIU_CONTROL (0x000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) #define MIU_TAG (0x004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) #define MIU_TEST_AGT_CTRL (0x090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) #define MIU_TEST_AGT_ADDR_LO (0x094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) #define MIU_TEST_AGT_ADDR_HI (0x098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) #define MIU_TEST_AGT_WRDATA_LO (0x0a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) #define MIU_TEST_AGT_WRDATA_HI (0x0a4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) #define MIU_TEST_AGT_WRDATA(i) (0x0a0+(4*(i)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) #define MIU_TEST_AGT_RDDATA_LO (0x0a8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) #define MIU_TEST_AGT_RDDATA_HI (0x0ac)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) #define MIU_TEST_AGT_RDDATA(i) (0x0a8+(4*(i)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) #define MIU_TEST_AGT_ADDR_MASK 0xfffffff8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) #define MIU_TEST_AGT_UPPER_ADDR(off) (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) /* MIU_TEST_AGT_CTRL flags. work for SIU as well */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) #define MIU_TA_CTL_START 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) #define MIU_TA_CTL_ENABLE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) #define MIU_TA_CTL_WRITE 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) #define MIU_TA_CTL_BUSY 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) #define MIU_TA_CTL_WRITE_ENABLE (MIU_TA_CTL_WRITE | MIU_TA_CTL_ENABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) #define MIU_TA_CTL_WRITE_START (MIU_TA_CTL_WRITE | MIU_TA_CTL_ENABLE |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) MIU_TA_CTL_START)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) #define MIU_TA_CTL_START_ENABLE (MIU_TA_CTL_START | MIU_TA_CTL_ENABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) /*CAM RAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) # define QLA82XX_CAM_RAM_BASE (QLA82XX_CRB_CAM + 0x02000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) # define QLA82XX_CAM_RAM(reg) (QLA82XX_CAM_RAM_BASE + (reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) #define QLA82XX_PORT_MODE_ADDR (QLA82XX_CAM_RAM(0x24))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) #define QLA82XX_PEG_HALT_STATUS1 (QLA82XX_CAM_RAM(0xa8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) #define QLA82XX_PEG_HALT_STATUS2 (QLA82XX_CAM_RAM(0xac))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) #define QLA82XX_PEG_ALIVE_COUNTER (QLA82XX_CAM_RAM(0xb0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) #define QLA82XX_CAM_RAM_DB1 (QLA82XX_CAM_RAM(0x1b0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) #define QLA82XX_CAM_RAM_DB2 (QLA82XX_CAM_RAM(0x1b4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) #define HALT_STATUS_UNRECOVERABLE 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) #define HALT_STATUS_RECOVERABLE 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) #define QLA82XX_ROM_LOCK_ID (QLA82XX_CAM_RAM(0x100))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) #define QLA82XX_CRB_WIN_LOCK_ID (QLA82XX_CAM_RAM(0x124))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) #define QLA82XX_FW_VERSION_MAJOR (QLA82XX_CAM_RAM(0x150))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) #define QLA82XX_FW_VERSION_MINOR (QLA82XX_CAM_RAM(0x154))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) #define QLA82XX_FW_VERSION_SUB (QLA82XX_CAM_RAM(0x158))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) #define QLA82XX_PCIE_REG(reg) (QLA82XX_CRB_PCIE + (reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) /* Driver Coexistence Defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) #define QLA82XX_CRB_DRV_ACTIVE (QLA82XX_CAM_RAM(0x138))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) #define QLA82XX_CRB_DEV_STATE (QLA82XX_CAM_RAM(0x140))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) #define QLA82XX_CRB_DRV_STATE (QLA82XX_CAM_RAM(0x144))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) #define QLA82XX_CRB_DRV_SCRATCH (QLA82XX_CAM_RAM(0x148))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) #define QLA82XX_CRB_DEV_PART_INFO (QLA82XX_CAM_RAM(0x14c))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) #define QLA82XX_CRB_DRV_IDC_VERSION (QLA82XX_CAM_RAM(0x174))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) enum qla_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) QLA8XXX_PEG_HALT_STATUS1 = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) QLA8XXX_PEG_HALT_STATUS2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) QLA8XXX_PEG_ALIVE_COUNTER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) QLA8XXX_CRB_DRV_ACTIVE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) QLA8XXX_CRB_DEV_STATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) QLA8XXX_CRB_DRV_STATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) QLA8XXX_CRB_DRV_SCRATCH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) QLA8XXX_CRB_DEV_PART_INFO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) QLA8XXX_CRB_DRV_IDC_VERSION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) QLA8XXX_FW_VERSION_MAJOR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) QLA8XXX_FW_VERSION_MINOR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) QLA8XXX_FW_VERSION_SUB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) QLA8XXX_CRB_CMDPEG_STATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) QLA8XXX_CRB_TEMP_STATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) /* Every driver should use these Device State */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) #define QLA8XXX_DEV_COLD 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) #define QLA8XXX_DEV_INITIALIZING 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) #define QLA8XXX_DEV_READY 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) #define QLA8XXX_DEV_NEED_RESET 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) #define QLA8XXX_DEV_NEED_QUIESCENT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) #define QLA8XXX_DEV_FAILED 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) #define QLA8XXX_DEV_QUIESCENT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) #define MAX_STATES 8 /* Increment if new state added */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) #define QLA82XX_IDC_VERSION 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) #define ROM_DEV_INIT_TIMEOUT 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) #define ROM_DRV_RESET_ACK_TIMEOUT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) #define PCIE_SETUP_FUNCTION (0x12040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) #define PCIE_SETUP_FUNCTION2 (0x12048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) #define QLA82XX_PCIX_PS_REG(reg) (QLA82XX_CRB_PCIX_MD + (reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) #define QLA82XX_PCIX_PS2_REG(reg) (QLA82XX_CRB_PCIE2 + (reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) #define PCIE_SEM2_LOCK (0x1c010) /* Flash lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) #define PCIE_SEM2_UNLOCK (0x1c014) /* Flash unlock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) #define PCIE_SEM5_LOCK (0x1c028) /* Coexistence lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) #define PCIE_SEM5_UNLOCK (0x1c02c) /* Coexistence unlock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) #define PCIE_SEM7_LOCK (0x1c038) /* crb win lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) #define PCIE_SEM7_UNLOCK (0x1c03c) /* crbwin unlock*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) * The PCI VendorID and DeviceID for our board.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) #define QLA82XX_MSIX_TBL_SPACE 8192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) #define QLA82XX_PCI_REG_MSIX_TBL 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) #define QLA82XX_PCI_MSIX_CONTROL 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) struct crb_128M_2M_sub_block_map {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) unsigned valid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) unsigned start_128M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) unsigned end_128M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) unsigned start_2M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) struct crb_128M_2M_block_map {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) struct crb_128M_2M_sub_block_map sub_block[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) struct crb_addr_pair {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) long addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) long data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) #define ADDR_ERROR ((unsigned long) 0xffffffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) #define MAX_CTL_CHECK 1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) #define QLA82XX_FWERROR_CODE(code) ((code >> 8) & 0x1fffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) /***************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) * PCI related defines.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) **************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) * Interrupt related defines.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) #define PCIX_TARGET_STATUS (0x10118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) #define PCIX_TARGET_STATUS_F1 (0x10160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) #define PCIX_TARGET_STATUS_F2 (0x10164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) #define PCIX_TARGET_STATUS_F3 (0x10168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) #define PCIX_TARGET_STATUS_F4 (0x10360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) #define PCIX_TARGET_STATUS_F5 (0x10364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) #define PCIX_TARGET_STATUS_F6 (0x10368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) #define PCIX_TARGET_STATUS_F7 (0x1036c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) #define PCIX_TARGET_MASK (0x10128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) #define PCIX_TARGET_MASK_F1 (0x10170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) #define PCIX_TARGET_MASK_F2 (0x10174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) #define PCIX_TARGET_MASK_F3 (0x10178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) #define PCIX_TARGET_MASK_F4 (0x10370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) #define PCIX_TARGET_MASK_F5 (0x10374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) #define PCIX_TARGET_MASK_F6 (0x10378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) #define PCIX_TARGET_MASK_F7 (0x1037c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) * Message Signaled Interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) #define PCIX_MSI_F0 (0x13000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) #define PCIX_MSI_F1 (0x13004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) #define PCIX_MSI_F2 (0x13008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) #define PCIX_MSI_F3 (0x1300c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) #define PCIX_MSI_F4 (0x13010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) #define PCIX_MSI_F5 (0x13014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) #define PCIX_MSI_F6 (0x13018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) #define PCIX_MSI_F7 (0x1301c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) #define PCIX_MSI_F(FUNC) (0x13000 + ((FUNC) * 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) #define PCIX_INT_VECTOR (0x10100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) #define PCIX_INT_MASK (0x10104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) * Interrupt state machine and other bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) #define PCIE_MISCCFG_RC (0x1206c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) #define ISR_INT_TARGET_STATUS \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) (QLA82XX_PCIX_PS_REG(PCIX_TARGET_STATUS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) #define ISR_INT_TARGET_STATUS_F1 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) (QLA82XX_PCIX_PS_REG(PCIX_TARGET_STATUS_F1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) #define ISR_INT_TARGET_STATUS_F2 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) (QLA82XX_PCIX_PS_REG(PCIX_TARGET_STATUS_F2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) #define ISR_INT_TARGET_STATUS_F3 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) (QLA82XX_PCIX_PS_REG(PCIX_TARGET_STATUS_F3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) #define ISR_INT_TARGET_STATUS_F4 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) (QLA82XX_PCIX_PS_REG(PCIX_TARGET_STATUS_F4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) #define ISR_INT_TARGET_STATUS_F5 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) (QLA82XX_PCIX_PS_REG(PCIX_TARGET_STATUS_F5))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) #define ISR_INT_TARGET_STATUS_F6 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) (QLA82XX_PCIX_PS_REG(PCIX_TARGET_STATUS_F6))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) #define ISR_INT_TARGET_STATUS_F7 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) (QLA82XX_PCIX_PS_REG(PCIX_TARGET_STATUS_F7))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) #define ISR_INT_TARGET_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) (QLA82XX_PCIX_PS_REG(PCIX_TARGET_MASK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) #define ISR_INT_TARGET_MASK_F1 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) (QLA82XX_PCIX_PS_REG(PCIX_TARGET_MASK_F1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) #define ISR_INT_TARGET_MASK_F2 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) (QLA82XX_PCIX_PS_REG(PCIX_TARGET_MASK_F2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) #define ISR_INT_TARGET_MASK_F3 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) (QLA82XX_PCIX_PS_REG(PCIX_TARGET_MASK_F3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) #define ISR_INT_TARGET_MASK_F4 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) (QLA82XX_PCIX_PS_REG(PCIX_TARGET_MASK_F4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) #define ISR_INT_TARGET_MASK_F5 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) (QLA82XX_PCIX_PS_REG(PCIX_TARGET_MASK_F5))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) #define ISR_INT_TARGET_MASK_F6 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) (QLA82XX_PCIX_PS_REG(PCIX_TARGET_MASK_F6))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) #define ISR_INT_TARGET_MASK_F7 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) (QLA82XX_PCIX_PS_REG(PCIX_TARGET_MASK_F7))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) #define ISR_INT_VECTOR (QLA82XX_PCIX_PS_REG(PCIX_INT_VECTOR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) #define ISR_INT_MASK (QLA82XX_PCIX_PS_REG(PCIX_INT_MASK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) #define ISR_INT_STATE_REG (QLA82XX_PCIX_PS_REG(PCIE_MISCCFG_RC))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) #define ISR_MSI_INT_TRIGGER(FUNC) (QLA82XX_PCIX_PS_REG(PCIX_MSI_F(FUNC)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) #define ISR_IS_LEGACY_INTR_IDLE(VAL) (((VAL) & 0x300) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) #define ISR_IS_LEGACY_INTR_TRIGGERED(VAL) (((VAL) & 0x300) == 0x200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) * PCI Interrupt Vector Values.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) #define PCIX_INT_VECTOR_BIT_F0 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) #define PCIX_INT_VECTOR_BIT_F1 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) #define PCIX_INT_VECTOR_BIT_F2 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) #define PCIX_INT_VECTOR_BIT_F3 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) #define PCIX_INT_VECTOR_BIT_F4 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) #define PCIX_INT_VECTOR_BIT_F5 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) #define PCIX_INT_VECTOR_BIT_F6 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) #define PCIX_INT_VECTOR_BIT_F7 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) /* struct qla4_8xxx_legacy_intr_set defined in ql4_def.h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) #define QLA82XX_LEGACY_INTR_CONFIG \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) .int_vec_bit = PCIX_INT_VECTOR_BIT_F0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) .tgt_status_reg = ISR_INT_TARGET_STATUS, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) .tgt_mask_reg = ISR_INT_TARGET_MASK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) .pci_int_reg = ISR_MSI_INT_TRIGGER(0) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) .int_vec_bit = PCIX_INT_VECTOR_BIT_F1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) .tgt_status_reg = ISR_INT_TARGET_STATUS_F1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) .tgt_mask_reg = ISR_INT_TARGET_MASK_F1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) .pci_int_reg = ISR_MSI_INT_TRIGGER(1) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) .int_vec_bit = PCIX_INT_VECTOR_BIT_F2, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) .tgt_status_reg = ISR_INT_TARGET_STATUS_F2, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) .tgt_mask_reg = ISR_INT_TARGET_MASK_F2, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) .pci_int_reg = ISR_MSI_INT_TRIGGER(2) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) .int_vec_bit = PCIX_INT_VECTOR_BIT_F3, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) .tgt_status_reg = ISR_INT_TARGET_STATUS_F3, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) .tgt_mask_reg = ISR_INT_TARGET_MASK_F3, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) .pci_int_reg = ISR_MSI_INT_TRIGGER(3) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) .int_vec_bit = PCIX_INT_VECTOR_BIT_F4, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) .tgt_status_reg = ISR_INT_TARGET_STATUS_F4, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) .tgt_mask_reg = ISR_INT_TARGET_MASK_F4, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) .pci_int_reg = ISR_MSI_INT_TRIGGER(4) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) .int_vec_bit = PCIX_INT_VECTOR_BIT_F5, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) .tgt_status_reg = ISR_INT_TARGET_STATUS_F5, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) .tgt_mask_reg = ISR_INT_TARGET_MASK_F5, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) .pci_int_reg = ISR_MSI_INT_TRIGGER(5) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) .int_vec_bit = PCIX_INT_VECTOR_BIT_F6, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) .tgt_status_reg = ISR_INT_TARGET_STATUS_F6, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) .tgt_mask_reg = ISR_INT_TARGET_MASK_F6, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) .pci_int_reg = ISR_MSI_INT_TRIGGER(6) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) .int_vec_bit = PCIX_INT_VECTOR_BIT_F7, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) .tgt_status_reg = ISR_INT_TARGET_STATUS_F7, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) .tgt_mask_reg = ISR_INT_TARGET_MASK_F7, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) .pci_int_reg = ISR_MSI_INT_TRIGGER(7) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) /* Magic number to let user know flash is programmed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) #define QLA82XX_BDINFO_MAGIC 0x12345678
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) #define FW_SIZE_OFFSET (0x3e840c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) /* QLA82XX additions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) #define MIU_TEST_AGT_WRDATA_UPPER_LO (0x0b0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) #define MIU_TEST_AGT_WRDATA_UPPER_HI (0x0b4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) /* Minidump related */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) /* Entry Type Defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) #define QLA8XXX_RDNOP 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) #define QLA8XXX_RDCRB 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) #define QLA8XXX_RDMUX 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) #define QLA8XXX_QUEUE 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) #define QLA8XXX_BOARD 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) #define QLA8XXX_RDOCM 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) #define QLA8XXX_PREGS 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) #define QLA8XXX_L1DTG 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) #define QLA8XXX_L1ITG 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) #define QLA8XXX_L1DAT 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) #define QLA8XXX_L1INS 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) #define QLA8XXX_L2DTG 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) #define QLA8XXX_L2ITG 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) #define QLA8XXX_L2DAT 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) #define QLA8XXX_L2INS 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) #define QLA83XX_POLLRD 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) #define QLA83XX_RDMUX2 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) #define QLA83XX_POLLRDMWR 37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) #define QLA8044_RDDFE 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) #define QLA8044_RDMDIO 39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) #define QLA8044_POLLWR 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) #define QLA8XXX_RDROM 71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) #define QLA8XXX_RDMEM 72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) #define QLA8XXX_CNTRL 98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) #define QLA83XX_TLHDR 99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) #define QLA8XXX_RDEND 255
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) /* Opcodes for Control Entries.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) * These Flags are bit fields.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) #define QLA8XXX_DBG_OPCODE_WR 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) #define QLA8XXX_DBG_OPCODE_RW 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) #define QLA8XXX_DBG_OPCODE_AND 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) #define QLA8XXX_DBG_OPCODE_OR 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) #define QLA8XXX_DBG_OPCODE_POLL 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) #define QLA8XXX_DBG_OPCODE_RDSTATE 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) #define QLA8XXX_DBG_OPCODE_WRSTATE 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) #define QLA8XXX_DBG_OPCODE_MDSTATE 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) /* Driver Flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) #define QLA8XXX_DBG_SKIPPED_FLAG 0x80 /* driver skipped this entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) #define QLA8XXX_DBG_SIZE_ERR_FLAG 0x40 /* Entry vs Capture size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) * mismatch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) /* Driver_code is for driver to write some info about the entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) * currently not used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) struct qla8xxx_minidump_entry_hdr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) uint32_t entry_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) uint32_t entry_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) uint32_t entry_capture_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) uint8_t entry_capture_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) uint8_t entry_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) uint8_t driver_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) uint8_t driver_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) } d_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) /* Read CRB entry header */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) struct qla8xxx_minidump_entry_crb {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) struct qla8xxx_minidump_entry_hdr h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) uint32_t addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) uint8_t addr_stride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) uint8_t state_index_a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) uint16_t poll_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) } crb_strd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) uint32_t data_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) uint32_t op_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) uint8_t opcode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) uint8_t state_index_v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) uint8_t shl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) uint8_t shr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) } crb_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) uint32_t value_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) uint32_t value_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) uint32_t value_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) struct qla8xxx_minidump_entry_cache {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) struct qla8xxx_minidump_entry_hdr h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) uint32_t tag_reg_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) uint16_t tag_value_stride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) uint16_t init_tag_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) } addr_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) uint32_t data_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) uint32_t op_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) uint32_t control_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) uint16_t write_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) uint8_t poll_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) uint8_t poll_wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) } cache_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) uint32_t read_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) uint8_t read_addr_stride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) uint8_t read_addr_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) uint16_t rsvd_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) } read_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) /* Read OCM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) struct qla8xxx_minidump_entry_rdocm {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) struct qla8xxx_minidump_entry_hdr h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) uint32_t rsvd_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) uint32_t rsvd_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) uint32_t data_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) uint32_t op_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) uint32_t rsvd_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) uint32_t rsvd_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) uint32_t read_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) uint32_t read_addr_stride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) /* Read Memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) struct qla8xxx_minidump_entry_rdmem {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) struct qla8xxx_minidump_entry_hdr h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) uint32_t rsvd[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) uint32_t read_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) uint32_t read_data_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) /* Read ROM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) struct qla8xxx_minidump_entry_rdrom {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) struct qla8xxx_minidump_entry_hdr h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) uint32_t rsvd[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) uint32_t read_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) uint32_t read_data_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) /* Mux entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) struct qla8xxx_minidump_entry_mux {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) struct qla8xxx_minidump_entry_hdr h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) uint32_t select_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) uint32_t rsvd_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) uint32_t data_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) uint32_t op_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) uint32_t select_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) uint32_t select_value_stride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) uint32_t read_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) uint32_t rsvd_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) /* Queue entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) struct qla8xxx_minidump_entry_queue {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) struct qla8xxx_minidump_entry_hdr h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) uint32_t select_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) uint16_t queue_id_stride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) uint16_t rsvd_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) } q_strd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) uint32_t data_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) uint32_t op_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) uint32_t rsvd_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) uint32_t rsvd_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) uint32_t read_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) uint8_t read_addr_stride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) uint8_t read_addr_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) uint16_t rsvd_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) } rd_strd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) #define MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE 0x129
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) #define RQST_TMPLT_SIZE 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) #define RQST_TMPLT 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) #define MD_DIRECT_ROM_WINDOW 0x42110030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) #define MD_DIRECT_ROM_READ_BASE 0x42150000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) #define MD_MIU_TEST_AGT_CTRL 0x41000090
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) #define MD_MIU_TEST_AGT_ADDR_LO 0x41000094
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) #define MD_MIU_TEST_AGT_ADDR_HI 0x41000098
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) #define MD_MIU_TEST_AGT_WRDATA_LO 0x410000A0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) #define MD_MIU_TEST_AGT_WRDATA_HI 0x410000A4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) #define MD_MIU_TEST_AGT_WRDATA_ULO 0x410000B0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) #define MD_MIU_TEST_AGT_WRDATA_UHI 0x410000B4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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