^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * QLogic iSCSI HBA Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (c) 2003-2013 QLogic Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/ratelimit.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include "ql4_def.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include "ql4_glbl.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include "ql4_inline.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/io-64-nonatomic-lo-hi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define TIMEOUT_100_MS 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define MASK(n) DMA_BIT_MASK(n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | ((addr >> 25) & 0x3ff))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | ((addr >> 25) & 0x3ff))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define MS_WIN(addr) (addr & 0x0ffc0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define QLA82XX_PCI_MN_2M (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define QLA82XX_PCI_MS_2M (0x80000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define QLA82XX_PCI_OCM0_2M (0xc0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define VALID_OCM_ADDR(addr) (((addr) & 0x3f800) != 0x3f800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define GET_MEM_OFFS_2M(addr) (addr & MASK(18))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /* CRB window related */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define CRB_BLK(off) ((off >> 20) & 0x3f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define CRB_SUBBLK(off) ((off >> 16) & 0xf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define CRB_WINDOW_2M (0x130060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define CRB_HI(off) ((qla4_82xx_crb_hub_agt[CRB_BLK(off)] << 20) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) ((off) & 0xf0000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define QLA82XX_PCI_CAMQM_2M_END (0x04800800UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define QLA82XX_PCI_CAMQM_2M_BASE (0x000ff800UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define CRB_INDIRECT_2M (0x1e0000UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) static inline void __iomem *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) qla4_8xxx_pci_base_offsetfset(struct scsi_qla_host *ha, unsigned long off)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) if ((off < ha->first_page_group_end) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) (off >= ha->first_page_group_start))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) return (void __iomem *)(ha->nx_pcibase + off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) static const int MD_MIU_TEST_AGT_RDDATA[] = { 0x410000A8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 0x410000AC, 0x410000B8, 0x410000BC };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define MAX_CRB_XFORM 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) static unsigned long crb_addr_xform[MAX_CRB_XFORM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) static int qla4_8xxx_crb_table_initialized;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define qla4_8xxx_crb_addr_transform(name) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) (crb_addr_xform[QLA82XX_HW_PX_MAP_CRB_##name] = \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) QLA82XX_HW_CRB_HUB_AGT_ADR_##name << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) qla4_82xx_crb_addr_transform_setup(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) qla4_8xxx_crb_addr_transform(XDMA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) qla4_8xxx_crb_addr_transform(TIMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) qla4_8xxx_crb_addr_transform(SRE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) qla4_8xxx_crb_addr_transform(SQN3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) qla4_8xxx_crb_addr_transform(SQN2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) qla4_8xxx_crb_addr_transform(SQN1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) qla4_8xxx_crb_addr_transform(SQN0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) qla4_8xxx_crb_addr_transform(SQS3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) qla4_8xxx_crb_addr_transform(SQS2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) qla4_8xxx_crb_addr_transform(SQS1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) qla4_8xxx_crb_addr_transform(SQS0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) qla4_8xxx_crb_addr_transform(RPMX7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) qla4_8xxx_crb_addr_transform(RPMX6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) qla4_8xxx_crb_addr_transform(RPMX5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) qla4_8xxx_crb_addr_transform(RPMX4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) qla4_8xxx_crb_addr_transform(RPMX3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) qla4_8xxx_crb_addr_transform(RPMX2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) qla4_8xxx_crb_addr_transform(RPMX1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) qla4_8xxx_crb_addr_transform(RPMX0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) qla4_8xxx_crb_addr_transform(ROMUSB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) qla4_8xxx_crb_addr_transform(SN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) qla4_8xxx_crb_addr_transform(QMN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) qla4_8xxx_crb_addr_transform(QMS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) qla4_8xxx_crb_addr_transform(PGNI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) qla4_8xxx_crb_addr_transform(PGND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) qla4_8xxx_crb_addr_transform(PGN3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) qla4_8xxx_crb_addr_transform(PGN2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) qla4_8xxx_crb_addr_transform(PGN1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) qla4_8xxx_crb_addr_transform(PGN0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) qla4_8xxx_crb_addr_transform(PGSI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) qla4_8xxx_crb_addr_transform(PGSD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) qla4_8xxx_crb_addr_transform(PGS3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) qla4_8xxx_crb_addr_transform(PGS2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) qla4_8xxx_crb_addr_transform(PGS1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) qla4_8xxx_crb_addr_transform(PGS0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) qla4_8xxx_crb_addr_transform(PS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) qla4_8xxx_crb_addr_transform(PH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) qla4_8xxx_crb_addr_transform(NIU);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) qla4_8xxx_crb_addr_transform(I2Q);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) qla4_8xxx_crb_addr_transform(EG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) qla4_8xxx_crb_addr_transform(MN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) qla4_8xxx_crb_addr_transform(MS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) qla4_8xxx_crb_addr_transform(CAS2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) qla4_8xxx_crb_addr_transform(CAS1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) qla4_8xxx_crb_addr_transform(CAS0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) qla4_8xxx_crb_addr_transform(CAM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) qla4_8xxx_crb_addr_transform(C2C1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) qla4_8xxx_crb_addr_transform(C2C0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) qla4_8xxx_crb_addr_transform(SMB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) qla4_8xxx_crb_addr_transform(OCM0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) qla4_8xxx_crb_addr_transform(I2C0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) qla4_8xxx_crb_table_initialized = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static struct crb_128M_2M_block_map crb_128M_2M_map[64] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) {{{0, 0, 0, 0} } }, /* 0: PCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) {{{1, 0x0100000, 0x0102000, 0x120000}, /* 1: PCIE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {1, 0x0110000, 0x0120000, 0x130000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) {1, 0x0120000, 0x0122000, 0x124000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) {1, 0x0130000, 0x0132000, 0x126000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) {1, 0x0140000, 0x0142000, 0x128000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {1, 0x0150000, 0x0152000, 0x12a000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) {1, 0x0160000, 0x0170000, 0x110000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {1, 0x0170000, 0x0172000, 0x12e000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) {1, 0x01e0000, 0x01e0800, 0x122000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) {0, 0x0000000, 0x0000000, 0x000000} } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) {{{1, 0x0200000, 0x0210000, 0x180000} } },/* 2: MN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) {{{0, 0, 0, 0} } }, /* 3: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {{{1, 0x0400000, 0x0401000, 0x169000} } },/* 4: P2NR1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) {{{1, 0x0500000, 0x0510000, 0x140000} } },/* 5: SRE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) {{{1, 0x0600000, 0x0610000, 0x1c0000} } },/* 6: NIU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) {{{1, 0x0700000, 0x0704000, 0x1b8000} } },/* 7: QM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) {{{1, 0x0800000, 0x0802000, 0x170000}, /* 8: SQM0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) {1, 0x08f0000, 0x08f2000, 0x172000} } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) {{{1, 0x0900000, 0x0902000, 0x174000}, /* 9: SQM1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {1, 0x09f0000, 0x09f2000, 0x176000} } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {{{0, 0x0a00000, 0x0a02000, 0x178000}, /* 10: SQM2*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {1, 0x0af0000, 0x0af2000, 0x17a000} } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {{{0, 0x0b00000, 0x0b02000, 0x17c000}, /* 11: SQM3*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {1, 0x0bf0000, 0x0bf2000, 0x17e000} } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },/* 12: I2Q */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },/* 13: TMR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },/* 14: ROMUSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {{{1, 0x0f00000, 0x0f01000, 0x164000} } },/* 15: PEG4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {{{0, 0x1000000, 0x1004000, 0x1a8000} } },/* 16: XDMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {{{1, 0x1100000, 0x1101000, 0x160000} } },/* 17: PEG0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {{{1, 0x1200000, 0x1201000, 0x161000} } },/* 18: PEG1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {{{1, 0x1300000, 0x1301000, 0x162000} } },/* 19: PEG2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {{{1, 0x1400000, 0x1401000, 0x163000} } },/* 20: PEG3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {{{1, 0x1500000, 0x1501000, 0x165000} } },/* 21: P2ND */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {{{1, 0x1600000, 0x1601000, 0x166000} } },/* 22: P2NI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {{{0, 0, 0, 0} } }, /* 23: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {{{0, 0, 0, 0} } }, /* 24: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {{{0, 0, 0, 0} } }, /* 25: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {{{0, 0, 0, 0} } }, /* 26: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {{{0, 0, 0, 0} } }, /* 27: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {{{0, 0, 0, 0} } }, /* 28: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {{{1, 0x1d00000, 0x1d10000, 0x190000} } },/* 29: MS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },/* 30: P2NR2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {{{1, 0x1f00000, 0x1f10000, 0x150000} } },/* 31: EPG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {{{0} } }, /* 32: PCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {{{1, 0x2100000, 0x2102000, 0x120000}, /* 33: PCIE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {1, 0x2110000, 0x2120000, 0x130000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {1, 0x2120000, 0x2122000, 0x124000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {1, 0x2130000, 0x2132000, 0x126000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {1, 0x2140000, 0x2142000, 0x128000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {1, 0x2150000, 0x2152000, 0x12a000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {1, 0x2160000, 0x2170000, 0x110000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {1, 0x2170000, 0x2172000, 0x12e000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {0, 0x0000000, 0x0000000, 0x000000} } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {{{1, 0x2200000, 0x2204000, 0x1b0000} } },/* 34: CAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {{{0} } }, /* 35: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {{{0} } }, /* 36: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {{{0} } }, /* 37: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {{{0} } }, /* 38: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {{{0} } }, /* 39: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {{{1, 0x2800000, 0x2804000, 0x1a4000} } },/* 40: TMR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {{{1, 0x2900000, 0x2901000, 0x16b000} } },/* 41: P2NR3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },/* 42: RPMX1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },/* 43: RPMX2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },/* 44: RPMX3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },/* 45: RPMX4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },/* 46: RPMX5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },/* 47: RPMX6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {{{1, 0x3000000, 0x3000400, 0x1adc00} } },/* 48: RPMX7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {{{0, 0x3100000, 0x3104000, 0x1a8000} } },/* 49: XDMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {{{1, 0x3200000, 0x3204000, 0x1d4000} } },/* 50: I2Q */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {{{1, 0x3300000, 0x3304000, 0x1a0000} } },/* 51: ROMUSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {{{0} } }, /* 52: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {{{1, 0x3500000, 0x3500400, 0x1ac000} } },/* 53: RPMX0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {{{1, 0x3600000, 0x3600400, 0x1ae000} } },/* 54: RPMX8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {{{1, 0x3700000, 0x3700400, 0x1ae400} } },/* 55: RPMX9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {{{1, 0x3800000, 0x3804000, 0x1d0000} } },/* 56: OCM0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {{{1, 0x3900000, 0x3904000, 0x1b4000} } },/* 57: CRYPTO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },/* 58: SMB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {{{0} } }, /* 59: I2C0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {{{0} } }, /* 60: I2C1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {{{1, 0x3d00000, 0x3d04000, 0x1dc000} } },/* 61: LPC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {{{1, 0x3e00000, 0x3e01000, 0x167000} } },/* 62: P2NC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {{{1, 0x3f00000, 0x3f01000, 0x168000} } } /* 63: P2NR0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) * top 12 bits of crb internal address (hub, agent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) static unsigned qla4_82xx_crb_hub_agt[64] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) QLA82XX_HW_CRB_HUB_AGT_ADR_PS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) QLA82XX_HW_CRB_HUB_AGT_ADR_MN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) QLA82XX_HW_CRB_HUB_AGT_ADR_MS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) QLA82XX_HW_CRB_HUB_AGT_ADR_SRE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) QLA82XX_HW_CRB_HUB_AGT_ADR_NIU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) QLA82XX_HW_CRB_HUB_AGT_ADR_QMN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) QLA82XX_HW_CRB_HUB_AGT_ADR_SQN0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) QLA82XX_HW_CRB_HUB_AGT_ADR_SQN1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) QLA82XX_HW_CRB_HUB_AGT_ADR_SQN2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) QLA82XX_HW_CRB_HUB_AGT_ADR_SQN3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) QLA82XX_HW_CRB_HUB_AGT_ADR_PGN4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) QLA82XX_HW_CRB_HUB_AGT_ADR_PGN0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) QLA82XX_HW_CRB_HUB_AGT_ADR_PGN1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) QLA82XX_HW_CRB_HUB_AGT_ADR_PGN2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) QLA82XX_HW_CRB_HUB_AGT_ADR_PGN3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) QLA82XX_HW_CRB_HUB_AGT_ADR_PGND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) QLA82XX_HW_CRB_HUB_AGT_ADR_PGNI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) QLA82XX_HW_CRB_HUB_AGT_ADR_PGS0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) QLA82XX_HW_CRB_HUB_AGT_ADR_PGS1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) QLA82XX_HW_CRB_HUB_AGT_ADR_PGS2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) QLA82XX_HW_CRB_HUB_AGT_ADR_PGS3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) QLA82XX_HW_CRB_HUB_AGT_ADR_PGSI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) QLA82XX_HW_CRB_HUB_AGT_ADR_SN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) QLA82XX_HW_CRB_HUB_AGT_ADR_EG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) QLA82XX_HW_CRB_HUB_AGT_ADR_PS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) QLA82XX_HW_CRB_HUB_AGT_ADR_CAM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) QLA82XX_HW_CRB_HUB_AGT_ADR_OCM0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) QLA82XX_HW_CRB_HUB_AGT_ADR_SMB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) QLA82XX_HW_CRB_HUB_AGT_ADR_I2C0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) QLA82XX_HW_CRB_HUB_AGT_ADR_I2C1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) QLA82XX_HW_CRB_HUB_AGT_ADR_PGNC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) /* Device states */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) static char *qdev_state[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) "Unknown",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) "Cold",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) "Initializing",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) "Ready",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) "Need Reset",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) "Need Quiescent",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) "Failed",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) "Quiescent",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) * In: 'off' is offset from CRB space in 128M pci map
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) * Out: 'off' is 2M pci map addr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) * side effect: lock crb window
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) qla4_82xx_pci_set_crbwindow_2M(struct scsi_qla_host *ha, ulong *off)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) u32 win_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) ha->crb_win = CRB_HI(*off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) writel(ha->crb_win,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) (void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) /* Read back value to make sure write has gone through before trying
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) * to use it. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) win_read = readl((void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) if (win_read != ha->crb_win) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) DEBUG2(ql4_printk(KERN_INFO, ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) "%s: Written crbwin (0x%x) != Read crbwin (0x%x),"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) " off=0x%lx\n", __func__, ha->crb_win, win_read, *off));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) *off = (*off & MASK(16)) + CRB_INDIRECT_2M + ha->nx_pcibase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) qla4_82xx_wr_32(struct scsi_qla_host *ha, ulong off, u32 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) unsigned long flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) int rv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) rv = qla4_82xx_pci_get_crb_addr_2M(ha, &off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) BUG_ON(rv == -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) if (rv == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) write_lock_irqsave(&ha->hw_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) qla4_82xx_crb_win_lock(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) qla4_82xx_pci_set_crbwindow_2M(ha, &off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) writel(data, (void __iomem *)off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) if (rv == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) qla4_82xx_crb_win_unlock(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) write_unlock_irqrestore(&ha->hw_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) uint32_t qla4_82xx_rd_32(struct scsi_qla_host *ha, ulong off)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) unsigned long flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) int rv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) u32 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) rv = qla4_82xx_pci_get_crb_addr_2M(ha, &off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) BUG_ON(rv == -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) if (rv == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) write_lock_irqsave(&ha->hw_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) qla4_82xx_crb_win_lock(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) qla4_82xx_pci_set_crbwindow_2M(ha, &off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) data = readl((void __iomem *)off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) if (rv == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) qla4_82xx_crb_win_unlock(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) write_unlock_irqrestore(&ha->hw_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) return data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) /* Minidump related functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) int qla4_82xx_md_rd_32(struct scsi_qla_host *ha, uint32_t off, uint32_t *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) uint32_t win_read, off_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) int rval = QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) off_value = off & 0xFFFF0000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) writel(off_value, (void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) * Read back value to make sure write has gone through before trying
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) * to use it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) win_read = readl((void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) if (win_read != off_value) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) DEBUG2(ql4_printk(KERN_INFO, ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) "%s: Written (0x%x) != Read (0x%x), off=0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) __func__, off_value, win_read, off));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) rval = QLA_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) off_value = off & 0x0000FFFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) *data = readl((void __iomem *)(off_value + CRB_INDIRECT_2M +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) ha->nx_pcibase));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) int qla4_82xx_md_wr_32(struct scsi_qla_host *ha, uint32_t off, uint32_t data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) uint32_t win_read, off_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) int rval = QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) off_value = off & 0xFFFF0000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) writel(off_value, (void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) /* Read back value to make sure write has gone through before trying
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) * to use it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) win_read = readl((void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) if (win_read != off_value) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) DEBUG2(ql4_printk(KERN_INFO, ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) "%s: Written (0x%x) != Read (0x%x), off=0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) __func__, off_value, win_read, off));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) rval = QLA_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) off_value = off & 0x0000FFFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) writel(data, (void __iomem *)(off_value + CRB_INDIRECT_2M +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) ha->nx_pcibase));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) #define CRB_WIN_LOCK_TIMEOUT 100000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) int qla4_82xx_crb_win_lock(struct scsi_qla_host *ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) int done = 0, timeout = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) while (!done) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) /* acquire semaphore3 from PCI HW block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) done = qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_LOCK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) if (done == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) if (timeout >= CRB_WIN_LOCK_TIMEOUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) timeout++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) /* Yield CPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) if (!in_interrupt())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) schedule();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) for (i = 0; i < 20; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) cpu_relax(); /*This a nop instr on i386*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) qla4_82xx_wr_32(ha, QLA82XX_CRB_WIN_LOCK_ID, ha->func_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) void qla4_82xx_crb_win_unlock(struct scsi_qla_host *ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) #define IDC_LOCK_TIMEOUT 100000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) * qla4_82xx_idc_lock - hw_lock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) * @ha: pointer to adapter structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) * General purpose lock used to synchronize access to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) * CRB_DEV_STATE, CRB_DEV_REF_COUNT, etc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) **/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) int qla4_82xx_idc_lock(struct scsi_qla_host *ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) int done = 0, timeout = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) while (!done) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) /* acquire semaphore5 from PCI HW block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) done = qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_LOCK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) if (done == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) if (timeout >= IDC_LOCK_TIMEOUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) timeout++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) /* Yield CPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) if (!in_interrupt())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) schedule();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) for (i = 0; i < 20; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) cpu_relax(); /*This a nop instr on i386*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) void qla4_82xx_idc_unlock(struct scsi_qla_host *ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_UNLOCK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) qla4_82xx_pci_get_crb_addr_2M(struct scsi_qla_host *ha, ulong *off)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) struct crb_128M_2M_sub_block_map *m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) if (*off >= QLA82XX_CRB_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) if (*off >= QLA82XX_PCI_CAMQM && (*off < QLA82XX_PCI_CAMQM_2M_END)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) *off = (*off - QLA82XX_PCI_CAMQM) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) QLA82XX_PCI_CAMQM_2M_BASE + ha->nx_pcibase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) if (*off < QLA82XX_PCI_CRBSPACE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) *off -= QLA82XX_PCI_CRBSPACE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) * Try direct map
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) m = &crb_128M_2M_map[CRB_BLK(*off)].sub_block[CRB_SUBBLK(*off)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) if (m->valid && (m->start_128M <= *off) && (m->end_128M > *off)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) *off = *off + m->start_2M - m->start_128M + ha->nx_pcibase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) * Not in direct map, use crb window
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) * check memory access boundary.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) * used by test agent. support ddr access only for now
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) static unsigned long
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) qla4_82xx_pci_mem_bound_check(struct scsi_qla_host *ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) unsigned long long addr, int size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) if (!QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_DDR_NET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) QLA8XXX_ADDR_DDR_NET_MAX) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) !QLA8XXX_ADDR_IN_RANGE(addr + size - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) QLA8XXX_ADDR_DDR_NET, QLA8XXX_ADDR_DDR_NET_MAX) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) ((size != 1) && (size != 2) && (size != 4) && (size != 8))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) static int qla4_82xx_pci_set_window_warning_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) static unsigned long
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) qla4_82xx_pci_set_window(struct scsi_qla_host *ha, unsigned long long addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) int window;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) u32 win_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_DDR_NET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) QLA8XXX_ADDR_DDR_NET_MAX)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) /* DDR network side */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) window = MN_WIN(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) ha->ddr_mn_window = window;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) qla4_82xx_wr_32(ha, ha->mn_win_crb |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) QLA82XX_PCI_CRBSPACE, window);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) win_read = qla4_82xx_rd_32(ha, ha->mn_win_crb |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) QLA82XX_PCI_CRBSPACE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) if ((win_read << 17) != window) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) ql4_printk(KERN_WARNING, ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) "%s: Written MNwin (0x%x) != Read MNwin (0x%x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) __func__, window, win_read);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_DDR_NET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) } else if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_OCM0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) QLA8XXX_ADDR_OCM0_MAX)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) unsigned int temp1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) /* if bits 19:18&17:11 are on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) if ((addr & 0x00ff800) == 0xff800) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) printk("%s: QM access not handled.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) addr = -1UL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) window = OCM_WIN(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) ha->ddr_mn_window = window;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) qla4_82xx_wr_32(ha, ha->mn_win_crb |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) QLA82XX_PCI_CRBSPACE, window);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) win_read = qla4_82xx_rd_32(ha, ha->mn_win_crb |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) QLA82XX_PCI_CRBSPACE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) temp1 = ((window & 0x1FF) << 7) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) ((window & 0x0FFFE0000) >> 17);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) if (win_read != temp1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) printk("%s: Written OCMwin (0x%x) != Read"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) " OCMwin (0x%x)\n", __func__, temp1, win_read);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_OCM0_2M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) } else if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_QDR_NET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) QLA82XX_P3_ADDR_QDR_NET_MAX)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) /* QDR network side */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) window = MS_WIN(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) ha->qdr_sn_window = window;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) qla4_82xx_wr_32(ha, ha->ms_win_crb |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) QLA82XX_PCI_CRBSPACE, window);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) win_read = qla4_82xx_rd_32(ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) ha->ms_win_crb | QLA82XX_PCI_CRBSPACE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) if (win_read != window) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) printk("%s: Written MSwin (0x%x) != Read "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) "MSwin (0x%x)\n", __func__, window, win_read);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_QDR_NET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) * peg gdb frequently accesses memory that doesn't exist,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) * this limits the chit chat so debugging isn't slowed down.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) if ((qla4_82xx_pci_set_window_warning_count++ < 8) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) (qla4_82xx_pci_set_window_warning_count%64 == 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) printk("%s: Warning:%s Unknown address range!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) __func__, DRIVER_NAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) addr = -1UL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) return addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) /* check if address is in the same windows as the previous access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) static int qla4_82xx_pci_is_same_window(struct scsi_qla_host *ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) unsigned long long addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) int window;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) unsigned long long qdr_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) qdr_max = QLA82XX_P3_ADDR_QDR_NET_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_DDR_NET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) QLA8XXX_ADDR_DDR_NET_MAX)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) /* DDR network side */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) BUG(); /* MN access can not come here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) } else if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_OCM0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) QLA8XXX_ADDR_OCM0_MAX)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) } else if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_OCM1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) QLA8XXX_ADDR_OCM1_MAX)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) } else if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_QDR_NET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) qdr_max)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) /* QDR network side */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) window = ((addr - QLA8XXX_ADDR_QDR_NET) >> 22) & 0x3f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) if (ha->qdr_sn_window == window)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) static int qla4_82xx_pci_mem_read_direct(struct scsi_qla_host *ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) u64 off, void *data, int size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) void __iomem *addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) u64 start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) void __iomem *mem_ptr = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) unsigned long mem_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) unsigned long mem_page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) write_lock_irqsave(&ha->hw_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) * If attempting to access unknown address or straddle hw windows,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) * do not access.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) start = qla4_82xx_pci_set_window(ha, off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) if ((start == -1UL) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) (qla4_82xx_pci_is_same_window(ha, off + size - 1) == 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) write_unlock_irqrestore(&ha->hw_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) printk(KERN_ERR"%s out of bound pci memory access. "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) "offset is 0x%llx\n", DRIVER_NAME, off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) addr = qla4_8xxx_pci_base_offsetfset(ha, start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) if (!addr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) write_unlock_irqrestore(&ha->hw_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) mem_base = pci_resource_start(ha->pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) mem_page = start & PAGE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) /* Map two pages whenever user tries to access addresses in two
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) consecutive pages.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) if (mem_page != ((start + size - 1) & PAGE_MASK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) if (mem_ptr == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) *(u8 *)data = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) addr = mem_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) addr += start & (PAGE_SIZE - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) write_lock_irqsave(&ha->hw_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) switch (size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) *(u8 *)data = readb(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) *(u16 *)data = readw(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) *(u32 *)data = readl(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) *(u64 *)data = readq(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) ret = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) write_unlock_irqrestore(&ha->hw_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) if (mem_ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) iounmap(mem_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) qla4_82xx_pci_mem_write_direct(struct scsi_qla_host *ha, u64 off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) void *data, int size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) void __iomem *addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) u64 start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) void __iomem *mem_ptr = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) unsigned long mem_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) unsigned long mem_page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) write_lock_irqsave(&ha->hw_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) * If attempting to access unknown address or straddle hw windows,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) * do not access.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) start = qla4_82xx_pci_set_window(ha, off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) if ((start == -1UL) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) (qla4_82xx_pci_is_same_window(ha, off + size - 1) == 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) write_unlock_irqrestore(&ha->hw_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) printk(KERN_ERR"%s out of bound pci memory access. "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) "offset is 0x%llx\n", DRIVER_NAME, off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) addr = qla4_8xxx_pci_base_offsetfset(ha, start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) if (!addr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) write_unlock_irqrestore(&ha->hw_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) mem_base = pci_resource_start(ha->pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) mem_page = start & PAGE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) /* Map two pages whenever user tries to access addresses in two
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) consecutive pages.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) if (mem_page != ((start + size - 1) & PAGE_MASK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE*2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) if (mem_ptr == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) addr = mem_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) addr += start & (PAGE_SIZE - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) write_lock_irqsave(&ha->hw_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) switch (size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) writeb(*(u8 *)data, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) writew(*(u16 *)data, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) writel(*(u32 *)data, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) writeq(*(u64 *)data, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) ret = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) write_unlock_irqrestore(&ha->hw_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) if (mem_ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) iounmap(mem_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) #define MTU_FUDGE_FACTOR 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) static unsigned long
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) qla4_82xx_decode_crb_addr(unsigned long addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) unsigned long base_addr, offset, pci_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) if (!qla4_8xxx_crb_table_initialized)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) qla4_82xx_crb_addr_transform_setup();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) pci_base = ADDR_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) base_addr = addr & 0xfff00000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) offset = addr & 0x000fffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) for (i = 0; i < MAX_CRB_XFORM; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) if (crb_addr_xform[i] == base_addr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) pci_base = i << 20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) if (pci_base == ADDR_ERROR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) return pci_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) return pci_base + offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) static long rom_max_timeout = 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) static long qla4_82xx_rom_lock_timeout = 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) qla4_82xx_rom_lock(struct scsi_qla_host *ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) int done = 0, timeout = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) while (!done) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) /* acquire semaphore2 from PCI HW block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) done = qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_LOCK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) if (done == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) if (timeout >= qla4_82xx_rom_lock_timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) timeout++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) /* Yield CPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) if (!in_interrupt())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) schedule();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) for (i = 0; i < 20; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) cpu_relax(); /*This a nop instr on i386*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) qla4_82xx_wr_32(ha, QLA82XX_ROM_LOCK_ID, ROM_LOCK_DRIVER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) qla4_82xx_rom_unlock(struct scsi_qla_host *ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_UNLOCK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) qla4_82xx_wait_rom_done(struct scsi_qla_host *ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) long timeout = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) long done = 0 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) while (done == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) done = qla4_82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) done &= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) timeout++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) if (timeout >= rom_max_timeout) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) printk("%s: Timeout reached waiting for rom done",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) DRIVER_NAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) qla4_82xx_do_rom_fast_read(struct scsi_qla_host *ha, int addr, int *valp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, 0xb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) if (qla4_82xx_wait_rom_done(ha)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) printk("%s: Error waiting for rom done\n", DRIVER_NAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) /* reset abyte_cnt and dummy_byte_cnt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) *valp = qla4_82xx_rd_32(ha, QLA82XX_ROMUSB_ROM_RDATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) qla4_82xx_rom_fast_read(struct scsi_qla_host *ha, int addr, int *valp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) int ret, loops = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) while ((qla4_82xx_rom_lock(ha) != 0) && (loops < 50000)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) loops++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) if (loops >= 50000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) ql4_printk(KERN_WARNING, ha, "%s: qla4_82xx_rom_lock failed\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) DRIVER_NAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) ret = qla4_82xx_do_rom_fast_read(ha, addr, valp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) qla4_82xx_rom_unlock(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) * This routine does CRB initialize sequence
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) * to put the ISP into operational state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) qla4_82xx_pinit_from_rom(struct scsi_qla_host *ha, int verbose)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) int addr, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) int i ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) struct crb_addr_pair *buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) unsigned long off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) unsigned offset, n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) struct crb_addr_pair {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) long addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) long data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) /* Halt all the indiviual PEGs and other blocks of the ISP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) qla4_82xx_rom_lock(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) /* disable all I2Q */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x10, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x14, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x18, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x1c, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x20, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x24, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) /* disable all niu interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x40, 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) /* disable xge rx/tx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x70000, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) /* disable xg1 rx/tx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x80000, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) /* disable sideband mac */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x90000, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) /* disable ap0 mac */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0xa0000, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) /* disable ap1 mac */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0xb0000, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) /* halt sre */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) val = qla4_82xx_rd_32(ha, QLA82XX_CRB_SRE + 0x1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) qla4_82xx_wr_32(ha, QLA82XX_CRB_SRE + 0x1000, val & (~(0x1)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) /* halt epg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) qla4_82xx_wr_32(ha, QLA82XX_CRB_EPG + 0x1300, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) /* halt timers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x0, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x8, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x10, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x18, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x100, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x200, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) /* halt pegs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x3c, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1 + 0x3c, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2 + 0x3c, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3 + 0x3c, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_4 + 0x3c, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) msleep(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) /* big hammer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) if (test_bit(DPC_RESET_HA, &ha->dpc_flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) /* don't reset CAM block on reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xfeffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xffffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) qla4_82xx_rom_unlock(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) /* Read the signature value from the flash.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) * Offset 0: Contain signature (0xcafecafe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) * Offset 4: Offset and number of addr/value pairs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) * that present in CRB initialize sequence
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) if (qla4_82xx_rom_fast_read(ha, 0, &n) != 0 || n != 0xcafecafeUL ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) qla4_82xx_rom_fast_read(ha, 4, &n) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) ql4_printk(KERN_WARNING, ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) "[ERROR] Reading crb_init area: n: %08x\n", n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) /* Offset in flash = lower 16 bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) * Number of enteries = upper 16 bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) offset = n & 0xffffU;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) n = (n >> 16) & 0xffffU;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) /* number of addr/value pair should not exceed 1024 enteries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) if (n >= 1024) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) ql4_printk(KERN_WARNING, ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) "%s: %s:n=0x%x [ERROR] Card flash not initialized.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) DRIVER_NAME, __func__, n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) ql4_printk(KERN_INFO, ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) "%s: %d CRB init values found in ROM.\n", DRIVER_NAME, n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) buf = kmalloc_array(n, sizeof(struct crb_addr_pair), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) if (buf == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) ql4_printk(KERN_WARNING, ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) "%s: [ERROR] Unable to malloc memory.\n", DRIVER_NAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) for (i = 0; i < n; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) if (qla4_82xx_rom_fast_read(ha, 8*i + 4*offset, &val) != 0 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) qla4_82xx_rom_fast_read(ha, 8*i + 4*offset + 4, &addr) !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) kfree(buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) buf[i].addr = addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) buf[i].data = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) for (i = 0; i < n; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) /* Translate internal CRB initialization
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) * address to PCI bus address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) off = qla4_82xx_decode_crb_addr((unsigned long)buf[i].addr) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) QLA82XX_PCI_CRBSPACE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) /* Not all CRB addr/value pair to be written,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) * some of them are skipped
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) /* skip if LS bit is set*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) if (off & 0x1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) DEBUG2(ql4_printk(KERN_WARNING, ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) "Skip CRB init replay for offset = 0x%lx\n", off));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) /* skipping cold reboot MAGIC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) if (off == QLA82XX_CAM_RAM(0x1fc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) /* do not reset PCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) if (off == (ROMUSB_GLB + 0xbc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) /* skip core clock, so that firmware can increase the clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) if (off == (ROMUSB_GLB + 0xc8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) /* skip the function enable register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) if ((off & 0x0ff00000) == QLA82XX_CRB_SMB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) if ((off & 0x0ff00000) == QLA82XX_CRB_DDR_NET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) if (off == ADDR_ERROR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) ql4_printk(KERN_WARNING, ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) "%s: [ERROR] Unknown addr: 0x%08lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) DRIVER_NAME, buf[i].addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) qla4_82xx_wr_32(ha, off, buf[i].data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) /* ISP requires much bigger delay to settle down,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) * else crb_window returns 0xffffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) if (off == QLA82XX_ROMUSB_GLB_SW_RESET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) msleep(1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) /* ISP requires millisec delay between
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) * successive CRB register updation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) kfree(buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) /* Resetting the data and instruction cache */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0xec, 0x1e);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0x4c, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_I+0x4c, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) /* Clear all protocol processing engines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0x8, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0xc, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0x8, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0xc, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0x8, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0xc, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0x8, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0xc, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) * qla4_8xxx_ms_mem_write_128b - Writes data to MS/off-chip memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) * @ha: Pointer to adapter structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) * @addr: Flash address to write to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) * @data: Data to be written
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) * @count: word_count to be written
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) * Return: On success return QLA_SUCCESS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) * On error return QLA_ERROR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) **/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) int qla4_8xxx_ms_mem_write_128b(struct scsi_qla_host *ha, uint64_t addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) uint32_t *data, uint32_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) int i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) uint32_t agt_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) int ret_val = QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) /* Only 128-bit aligned access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) if (addr & 0xF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) ret_val = QLA_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) goto exit_ms_mem_write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) write_lock_irqsave(&ha->hw_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) /* Write address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) ret_val = ha->isp_ops->wr_reg_indirect(ha, MD_MIU_TEST_AGT_ADDR_HI, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) if (ret_val == QLA_ERROR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) ql4_printk(KERN_ERR, ha, "%s: write to AGT_ADDR_HI failed\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) goto exit_ms_mem_write_unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) for (i = 0; i < count; i++, addr += 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) if (!((QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_QDR_NET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) QLA8XXX_ADDR_QDR_NET_MAX)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_DDR_NET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) QLA8XXX_ADDR_DDR_NET_MAX)))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) ret_val = QLA_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) goto exit_ms_mem_write_unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) ret_val = ha->isp_ops->wr_reg_indirect(ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) MD_MIU_TEST_AGT_ADDR_LO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) /* Write data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) ret_val |= ha->isp_ops->wr_reg_indirect(ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) MD_MIU_TEST_AGT_WRDATA_LO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) *data++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) ret_val |= ha->isp_ops->wr_reg_indirect(ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) MD_MIU_TEST_AGT_WRDATA_HI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) *data++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) ret_val |= ha->isp_ops->wr_reg_indirect(ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) MD_MIU_TEST_AGT_WRDATA_ULO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) *data++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) ret_val |= ha->isp_ops->wr_reg_indirect(ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) MD_MIU_TEST_AGT_WRDATA_UHI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) *data++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) if (ret_val == QLA_ERROR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) ql4_printk(KERN_ERR, ha, "%s: write to AGT_WRDATA failed\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) goto exit_ms_mem_write_unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) /* Check write status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) ret_val = ha->isp_ops->wr_reg_indirect(ha, MD_MIU_TEST_AGT_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) MIU_TA_CTL_WRITE_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) ret_val |= ha->isp_ops->wr_reg_indirect(ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) MD_MIU_TEST_AGT_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) MIU_TA_CTL_WRITE_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) if (ret_val == QLA_ERROR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) ql4_printk(KERN_ERR, ha, "%s: write to AGT_CTRL failed\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) goto exit_ms_mem_write_unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) for (j = 0; j < MAX_CTL_CHECK; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) ret_val = ha->isp_ops->rd_reg_indirect(ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) MD_MIU_TEST_AGT_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) &agt_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) if (ret_val == QLA_ERROR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) ql4_printk(KERN_ERR, ha, "%s: failed to read MD_MIU_TEST_AGT_CTRL\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) goto exit_ms_mem_write_unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) if ((agt_ctrl & MIU_TA_CTL_BUSY) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) /* Status check failed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) if (j >= MAX_CTL_CHECK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) printk_ratelimited(KERN_ERR "%s: MS memory write failed!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) ret_val = QLA_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) goto exit_ms_mem_write_unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) exit_ms_mem_write_unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) write_unlock_irqrestore(&ha->hw_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) exit_ms_mem_write:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) return ret_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) qla4_82xx_load_from_flash(struct scsi_qla_host *ha, uint32_t image_start)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) int i, rval = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) long size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) long flashaddr, memaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) u64 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) u32 high, low;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) flashaddr = memaddr = ha->hw.flt_region_bootload;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) size = (image_start - flashaddr) / 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) DEBUG2(printk("scsi%ld: %s: bootldr=0x%lx, fw_image=0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) ha->host_no, __func__, flashaddr, image_start));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) for (i = 0; i < size; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) if ((qla4_82xx_rom_fast_read(ha, flashaddr, (int *)&low)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) (qla4_82xx_rom_fast_read(ha, flashaddr + 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) (int *)&high))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) rval = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) goto exit_load_from_flash;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) data = ((u64)high << 32) | low ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) rval = qla4_82xx_pci_mem_write_2M(ha, memaddr, &data, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) if (rval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) goto exit_load_from_flash;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) flashaddr += 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) memaddr += 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) if (i % 0x1000 == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) read_lock(&ha->hw_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x18, 0x1020);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001e);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) read_unlock(&ha->hw_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) exit_load_from_flash:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) static int qla4_82xx_load_fw(struct scsi_qla_host *ha, uint32_t image_start)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) u32 rst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) qla4_82xx_wr_32(ha, CRB_CMDPEG_STATE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) if (qla4_82xx_pinit_from_rom(ha, 0) != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) printk(KERN_WARNING "%s: Error during CRB Initialization\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) return QLA_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) udelay(500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) /* at this point, QM is in reset. This could be a problem if there are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) * incoming d* transition queue messages. QM/PCIE could wedge.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) * To get around this, QM is brought out of reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) rst = qla4_82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) /* unreset qm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) rst &= ~(1 << 28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) if (qla4_82xx_load_from_flash(ha, image_start)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) printk("%s: Error trying to load fw from flash!\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) return QLA_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) return QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) qla4_82xx_pci_mem_read_2M(struct scsi_qla_host *ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) u64 off, void *data, int size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) int i, j = 0, k, start, end, loop, sz[2], off0[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) int shift_amount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) uint32_t temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) uint64_t off8, val, mem_crb, word[2] = {0, 0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) * If not MN, go check for MS or invalid.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) if (off >= QLA8XXX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) mem_crb = QLA82XX_CRB_QDR_NET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) mem_crb = QLA82XX_CRB_DDR_NET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) if (qla4_82xx_pci_mem_bound_check(ha, off, size) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) return qla4_82xx_pci_mem_read_direct(ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) off, data, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) off8 = off & 0xfffffff0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) off0[0] = off & 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) sz[0] = (size < (16 - off0[0])) ? size : (16 - off0[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) shift_amount = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) loop = ((off0[0] + size - 1) >> shift_amount) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) off0[1] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) sz[1] = size - sz[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) for (i = 0; i < loop; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) temp = off8 + (i << shift_amount);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_LO, temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) temp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_HI, temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) temp = MIU_TA_CTL_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) temp = MIU_TA_CTL_START_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) for (j = 0; j < MAX_CTL_CHECK; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) temp = qla4_82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) if ((temp & MIU_TA_CTL_BUSY) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) if (j >= MAX_CTL_CHECK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) printk_ratelimited(KERN_ERR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) "%s: failed to read through agent\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) start = off0[i] >> 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) end = (off0[i] + sz[i] - 1) >> 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) for (k = start; k <= end; k++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) temp = qla4_82xx_rd_32(ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) mem_crb + MIU_TEST_AGT_RDDATA(k));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) word[i] |= ((uint64_t)temp << (32 * (k & 1)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) if (j >= MAX_CTL_CHECK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) if ((off0[0] & 7) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) val = word[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) switch (size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) *(uint8_t *)data = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) *(uint16_t *)data = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) *(uint32_t *)data = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) *(uint64_t *)data = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) qla4_82xx_pci_mem_write_2M(struct scsi_qla_host *ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) u64 off, void *data, int size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) int i, j, ret = 0, loop, sz[2], off0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) int scale, shift_amount, startword;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) uint32_t temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) uint64_t off8, mem_crb, tmpw, word[2] = {0, 0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) * If not MN, go check for MS or invalid.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) if (off >= QLA8XXX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) mem_crb = QLA82XX_CRB_QDR_NET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) mem_crb = QLA82XX_CRB_DDR_NET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) if (qla4_82xx_pci_mem_bound_check(ha, off, size) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) return qla4_82xx_pci_mem_write_direct(ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) off, data, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) off0 = off & 0x7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) sz[0] = (size < (8 - off0)) ? size : (8 - off0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) sz[1] = size - sz[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) off8 = off & 0xfffffff0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) loop = (((off & 0xf) + size - 1) >> 4) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) shift_amount = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) scale = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) startword = (off & 0xf)/8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) for (i = 0; i < loop; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) if (qla4_82xx_pci_mem_read_2M(ha, off8 +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) (i << shift_amount), &word[i * scale], 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) switch (size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) tmpw = *((uint8_t *)data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) tmpw = *((uint16_t *)data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) tmpw = *((uint32_t *)data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) tmpw = *((uint64_t *)data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) if (sz[0] == 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) word[startword] = tmpw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) word[startword] &=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) word[startword] |= tmpw << (off0 * 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) if (sz[1] != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) word[startword+1] &= ~(~0ULL << (sz[1] * 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) word[startword+1] |= tmpw >> (sz[0] * 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) for (i = 0; i < loop; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) temp = off8 + (i << shift_amount);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_LO, temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) temp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_HI, temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) temp = word[i * scale] & 0xffffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_LO, temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) temp = (word[i * scale] >> 32) & 0xffffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_HI, temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) temp = word[i*scale + 1] & 0xffffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_WRDATA_UPPER_LO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) temp = (word[i*scale + 1] >> 32) & 0xffffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_WRDATA_UPPER_HI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) temp = MIU_TA_CTL_WRITE_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_CTRL, temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) temp = MIU_TA_CTL_WRITE_START;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_CTRL, temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) for (j = 0; j < MAX_CTL_CHECK; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) temp = qla4_82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) if ((temp & MIU_TA_CTL_BUSY) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) if (j >= MAX_CTL_CHECK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) if (printk_ratelimit())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) ql4_printk(KERN_ERR, ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) "%s: failed to read through agent\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) ret = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) static int qla4_82xx_cmdpeg_ready(struct scsi_qla_host *ha, int pegtune_val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) int retries = 60;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) if (!pegtune_val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) val = qla4_82xx_rd_32(ha, CRB_CMDPEG_STATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) if ((val == PHAN_INITIALIZE_COMPLETE) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) (val == PHAN_INITIALIZE_ACK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) set_current_state(TASK_UNINTERRUPTIBLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) schedule_timeout(500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) } while (--retries);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) if (!retries) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) pegtune_val = qla4_82xx_rd_32(ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) QLA82XX_ROMUSB_GLB_PEGTUNE_DONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) printk(KERN_WARNING "%s: init failed, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) "pegtune_val = %x\n", __func__, pegtune_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) static int qla4_82xx_rcvpeg_ready(struct scsi_qla_host *ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) uint32_t state = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) int loops = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) /* Window 1 call */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) read_lock(&ha->hw_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) state = qla4_82xx_rd_32(ha, CRB_RCVPEG_STATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) read_unlock(&ha->hw_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) while ((state != PHAN_PEG_RCV_INITIALIZED) && (loops < 30000)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) /* Window 1 call */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) read_lock(&ha->hw_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) state = qla4_82xx_rd_32(ha, CRB_RCVPEG_STATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) read_unlock(&ha->hw_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) loops++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) if (loops >= 30000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) DEBUG2(ql4_printk(KERN_INFO, ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) "Receive Peg initialization not complete: 0x%x.\n", state));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) return QLA_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) return QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) qla4_8xxx_set_drv_active(struct scsi_qla_host *ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) uint32_t drv_active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) drv_active = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_ACTIVE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) * For ISP8324 and ISP8042, drv_active register has 1 bit per function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) * shift 1 by func_num to set a bit for the function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) * For ISP8022, drv_active has 4 bits per function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) if (is_qla8032(ha) || is_qla8042(ha))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) drv_active |= (1 << ha->func_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) drv_active |= (1 << (ha->func_num * 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) ql4_printk(KERN_INFO, ha, "%s(%ld): drv_active: 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) __func__, ha->host_no, drv_active);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_ACTIVE, drv_active);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) qla4_8xxx_clear_drv_active(struct scsi_qla_host *ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) uint32_t drv_active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) drv_active = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_ACTIVE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) * For ISP8324 and ISP8042, drv_active register has 1 bit per function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) * shift 1 by func_num to set a bit for the function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) * For ISP8022, drv_active has 4 bits per function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) if (is_qla8032(ha) || is_qla8042(ha))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) drv_active &= ~(1 << (ha->func_num));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) drv_active &= ~(1 << (ha->func_num * 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) ql4_printk(KERN_INFO, ha, "%s(%ld): drv_active: 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) __func__, ha->host_no, drv_active);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_ACTIVE, drv_active);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) inline int qla4_8xxx_need_reset(struct scsi_qla_host *ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) uint32_t drv_state, drv_active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) int rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) drv_active = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_ACTIVE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) drv_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_STATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) * For ISP8324 and ISP8042, drv_active register has 1 bit per function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) * shift 1 by func_num to set a bit for the function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) * For ISP8022, drv_active has 4 bits per function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) if (is_qla8032(ha) || is_qla8042(ha))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) rval = drv_state & (1 << ha->func_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) rval = drv_state & (1 << (ha->func_num * 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) if ((test_bit(AF_EEH_BUSY, &ha->flags)) && drv_active)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) rval = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) void qla4_8xxx_set_rst_ready(struct scsi_qla_host *ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) uint32_t drv_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) drv_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_STATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) * For ISP8324 and ISP8042, drv_active register has 1 bit per function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) * shift 1 by func_num to set a bit for the function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) * For ISP8022, drv_active has 4 bits per function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) if (is_qla8032(ha) || is_qla8042(ha))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) drv_state |= (1 << ha->func_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) drv_state |= (1 << (ha->func_num * 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) ql4_printk(KERN_INFO, ha, "%s(%ld): drv_state: 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) __func__, ha->host_no, drv_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_STATE, drv_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) void qla4_8xxx_clear_rst_ready(struct scsi_qla_host *ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) uint32_t drv_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) drv_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_STATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) * For ISP8324 and ISP8042, drv_active register has 1 bit per function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) * shift 1 by func_num to set a bit for the function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) * For ISP8022, drv_active has 4 bits per function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) if (is_qla8032(ha) || is_qla8042(ha))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) drv_state &= ~(1 << ha->func_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) drv_state &= ~(1 << (ha->func_num * 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) ql4_printk(KERN_INFO, ha, "%s(%ld): drv_state: 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) __func__, ha->host_no, drv_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_STATE, drv_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) qla4_8xxx_set_qsnt_ready(struct scsi_qla_host *ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) uint32_t qsnt_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) qsnt_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_STATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) * For ISP8324 and ISP8042, drv_active register has 1 bit per function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) * shift 1 by func_num to set a bit for the function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) * For ISP8022, drv_active has 4 bits per function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) if (is_qla8032(ha) || is_qla8042(ha))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) qsnt_state |= (1 << ha->func_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) qsnt_state |= (2 << (ha->func_num * 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_STATE, qsnt_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) qla4_82xx_start_firmware(struct scsi_qla_host *ha, uint32_t image_start)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) uint16_t lnk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) /* scrub dma mask expansion register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) qla4_82xx_wr_32(ha, CRB_DMA_SHIFT, 0x55555555);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) /* Overwrite stale initialization register values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) qla4_82xx_wr_32(ha, CRB_CMDPEG_STATE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) qla4_82xx_wr_32(ha, CRB_RCVPEG_STATE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) qla4_82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) qla4_82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) if (qla4_82xx_load_fw(ha, image_start) != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) printk("%s: Error trying to start fw!\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) return QLA_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) /* Handshake with the card before we register the devices. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) if (qla4_82xx_cmdpeg_ready(ha, 0) != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) printk("%s: Error during card handshake!\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) return QLA_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) /* Negotiated Link width */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) pcie_capability_read_word(ha->pdev, PCI_EXP_LNKSTA, &lnk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) ha->link_width = (lnk >> 4) & 0x3f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) /* Synchronize with Receive peg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) return qla4_82xx_rcvpeg_ready(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) int qla4_82xx_try_start_fw(struct scsi_qla_host *ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) int rval = QLA_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) * FW Load priority:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) * 1) Operational firmware residing in flash.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) * 2) Fail
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) ql4_printk(KERN_INFO, ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) "FW: Retrieving flash offsets from FLT/FDT ...\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) rval = qla4_8xxx_get_flash_info(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) if (rval != QLA_SUCCESS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) ql4_printk(KERN_INFO, ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) "FW: Attempting to load firmware from flash...\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) rval = qla4_82xx_start_firmware(ha, ha->hw.flt_region_fw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) if (rval != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) ql4_printk(KERN_ERR, ha, "FW: Load firmware from flash"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) " FAILED...\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) void qla4_82xx_rom_lock_recovery(struct scsi_qla_host *ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) if (qla4_82xx_rom_lock(ha)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) /* Someone else is holding the lock. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) dev_info(&ha->pdev->dev, "Resetting rom_lock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) * Either we got the lock, or someone
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) * else died while holding it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) * In either case, unlock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) qla4_82xx_rom_unlock(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) static uint32_t ql4_84xx_poll_wait_for_ready(struct scsi_qla_host *ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) uint32_t addr1, uint32_t mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) unsigned long timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) uint32_t rval = QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) uint32_t temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) timeout = jiffies + msecs_to_jiffies(TIMEOUT_100_MS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) ha->isp_ops->rd_reg_indirect(ha, addr1, &temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) if ((temp & mask) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) if (time_after_eq(jiffies, timeout)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) ql4_printk(KERN_INFO, ha, "Error in processing rdmdio entry\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) return QLA_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) } while (1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) static uint32_t ql4_84xx_ipmdio_rd_reg(struct scsi_qla_host *ha, uint32_t addr1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) uint32_t addr3, uint32_t mask, uint32_t addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) uint32_t *data_ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) int rval = QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) uint32_t temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) uint32_t data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) rval = ql4_84xx_poll_wait_for_ready(ha, addr1, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) if (rval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) goto exit_ipmdio_rd_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) temp = (0x40000000 | addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) ha->isp_ops->wr_reg_indirect(ha, addr1, temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) rval = ql4_84xx_poll_wait_for_ready(ha, addr1, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) if (rval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) goto exit_ipmdio_rd_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) ha->isp_ops->rd_reg_indirect(ha, addr3, &data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) *data_ptr = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) exit_ipmdio_rd_reg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) static uint32_t ql4_84xx_poll_wait_ipmdio_bus_idle(struct scsi_qla_host *ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) uint32_t addr1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) uint32_t addr2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) uint32_t addr3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) uint32_t mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) unsigned long timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) uint32_t temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) uint32_t rval = QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) timeout = jiffies + msecs_to_jiffies(TIMEOUT_100_MS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) ql4_84xx_ipmdio_rd_reg(ha, addr1, addr3, mask, addr2, &temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) if ((temp & 0x1) != 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) if (time_after_eq(jiffies, timeout)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) ql4_printk(KERN_INFO, ha, "Error in processing mdiobus idle\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) return QLA_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) } while (1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) static int ql4_84xx_ipmdio_wr_reg(struct scsi_qla_host *ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) uint32_t addr1, uint32_t addr3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) uint32_t mask, uint32_t addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) uint32_t value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) int rval = QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) rval = ql4_84xx_poll_wait_for_ready(ha, addr1, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) if (rval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) goto exit_ipmdio_wr_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) ha->isp_ops->wr_reg_indirect(ha, addr3, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) ha->isp_ops->wr_reg_indirect(ha, addr1, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) rval = ql4_84xx_poll_wait_for_ready(ha, addr1, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) if (rval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) goto exit_ipmdio_wr_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) exit_ipmdio_wr_reg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) static void qla4_8xxx_minidump_process_rdcrb(struct scsi_qla_host *ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) struct qla8xxx_minidump_entry_hdr *entry_hdr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) uint32_t **d_ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) uint32_t r_addr, r_stride, loop_cnt, i, r_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) struct qla8xxx_minidump_entry_crb *crb_hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) uint32_t *data_ptr = *d_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) crb_hdr = (struct qla8xxx_minidump_entry_crb *)entry_hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) r_addr = crb_hdr->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) r_stride = crb_hdr->crb_strd.addr_stride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) loop_cnt = crb_hdr->op_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) for (i = 0; i < loop_cnt; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) ha->isp_ops->rd_reg_indirect(ha, r_addr, &r_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) *data_ptr++ = cpu_to_le32(r_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) *data_ptr++ = cpu_to_le32(r_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) r_addr += r_stride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) *d_ptr = data_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) static int qla4_83xx_check_dma_engine_state(struct scsi_qla_host *ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) int rval = QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) uint32_t dma_eng_num = 0, cmd_sts_and_cntrl = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) uint64_t dma_base_addr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) struct qla4_8xxx_minidump_template_hdr *tmplt_hdr = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) tmplt_hdr = (struct qla4_8xxx_minidump_template_hdr *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) ha->fw_dump_tmplt_hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) dma_eng_num =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) tmplt_hdr->saved_state_array[QLA83XX_PEX_DMA_ENGINE_INDEX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) dma_base_addr = QLA83XX_PEX_DMA_BASE_ADDRESS +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) (dma_eng_num * QLA83XX_PEX_DMA_NUM_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) /* Read the pex-dma's command-status-and-control register. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) rval = ha->isp_ops->rd_reg_indirect(ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) (dma_base_addr + QLA83XX_PEX_DMA_CMD_STS_AND_CNTRL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) &cmd_sts_and_cntrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) if (rval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) return QLA_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) /* Check if requested pex-dma engine is available. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) if (cmd_sts_and_cntrl & BIT_31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) return QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) return QLA_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) static int qla4_83xx_start_pex_dma(struct scsi_qla_host *ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) struct qla4_83xx_minidump_entry_rdmem_pex_dma *m_hdr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) int rval = QLA_SUCCESS, wait = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) uint32_t dma_eng_num = 0, cmd_sts_and_cntrl = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) uint64_t dma_base_addr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) struct qla4_8xxx_minidump_template_hdr *tmplt_hdr = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) tmplt_hdr = (struct qla4_8xxx_minidump_template_hdr *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) ha->fw_dump_tmplt_hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) dma_eng_num =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) tmplt_hdr->saved_state_array[QLA83XX_PEX_DMA_ENGINE_INDEX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) dma_base_addr = QLA83XX_PEX_DMA_BASE_ADDRESS +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) (dma_eng_num * QLA83XX_PEX_DMA_NUM_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) rval = ha->isp_ops->wr_reg_indirect(ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) dma_base_addr + QLA83XX_PEX_DMA_CMD_ADDR_LOW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) m_hdr->desc_card_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) if (rval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) goto error_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) rval = ha->isp_ops->wr_reg_indirect(ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) dma_base_addr + QLA83XX_PEX_DMA_CMD_ADDR_HIGH, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) if (rval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) goto error_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) rval = ha->isp_ops->wr_reg_indirect(ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) dma_base_addr + QLA83XX_PEX_DMA_CMD_STS_AND_CNTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) m_hdr->start_dma_cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) if (rval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) goto error_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) /* Wait for dma operation to complete. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) for (wait = 0; wait < QLA83XX_PEX_DMA_MAX_WAIT; wait++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) rval = ha->isp_ops->rd_reg_indirect(ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) (dma_base_addr + QLA83XX_PEX_DMA_CMD_STS_AND_CNTRL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) &cmd_sts_and_cntrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) if (rval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) goto error_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) if ((cmd_sts_and_cntrl & BIT_1) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) /* Wait a max of 100 ms, otherwise fallback to rdmem entry read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) if (wait >= QLA83XX_PEX_DMA_MAX_WAIT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) rval = QLA_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) goto error_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) error_exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) static int qla4_8xxx_minidump_pex_dma_read(struct scsi_qla_host *ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) struct qla8xxx_minidump_entry_hdr *entry_hdr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) uint32_t **d_ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) int rval = QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) struct qla4_83xx_minidump_entry_rdmem_pex_dma *m_hdr = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) uint32_t size, read_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) uint8_t *data_ptr = (uint8_t *)*d_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) void *rdmem_buffer = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) dma_addr_t rdmem_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) struct qla4_83xx_pex_dma_descriptor dma_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) rval = qla4_83xx_check_dma_engine_state(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) if (rval != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) DEBUG2(ql4_printk(KERN_INFO, ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) "%s: DMA engine not available. Fallback to rdmem-read.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) __func__));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) return QLA_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) m_hdr = (struct qla4_83xx_minidump_entry_rdmem_pex_dma *)entry_hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) rdmem_buffer = dma_alloc_coherent(&ha->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) QLA83XX_PEX_DMA_READ_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) &rdmem_dma, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) if (!rdmem_buffer) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) DEBUG2(ql4_printk(KERN_INFO, ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) "%s: Unable to allocate rdmem dma buffer\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) __func__));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) return QLA_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) /* Prepare pex-dma descriptor to be written to MS memory. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) /* dma-desc-cmd layout:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) * 0-3: dma-desc-cmd 0-3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) * 4-7: pcid function number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) * 8-15: dma-desc-cmd 8-15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) dma_desc.cmd.dma_desc_cmd = (m_hdr->dma_desc_cmd & 0xff0f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) dma_desc.cmd.dma_desc_cmd |= ((PCI_FUNC(ha->pdev->devfn) & 0xf) << 0x4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) dma_desc.dma_bus_addr = rdmem_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) read_size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) * Perform rdmem operation using pex-dma.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) * Prepare dma in chunks of QLA83XX_PEX_DMA_READ_SIZE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) while (read_size < m_hdr->read_data_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) if (m_hdr->read_data_size - read_size >=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) QLA83XX_PEX_DMA_READ_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) size = QLA83XX_PEX_DMA_READ_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) size = (m_hdr->read_data_size - read_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) if (rdmem_buffer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) dma_free_coherent(&ha->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) QLA83XX_PEX_DMA_READ_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) rdmem_buffer, rdmem_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) rdmem_buffer = dma_alloc_coherent(&ha->pdev->dev, size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) &rdmem_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) if (!rdmem_buffer) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) DEBUG2(ql4_printk(KERN_INFO, ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) "%s: Unable to allocate rdmem dma buffer\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) __func__));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) return QLA_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) dma_desc.dma_bus_addr = rdmem_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) dma_desc.src_addr = m_hdr->read_addr + read_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) dma_desc.cmd.read_data_size = size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) /* Prepare: Write pex-dma descriptor to MS memory. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) rval = qla4_8xxx_ms_mem_write_128b(ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) (uint64_t)m_hdr->desc_card_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) (uint32_t *)&dma_desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) (sizeof(struct qla4_83xx_pex_dma_descriptor)/16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) if (rval != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) ql4_printk(KERN_INFO, ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) "%s: Error writing rdmem-dma-init to MS !!!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) goto error_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) DEBUG2(ql4_printk(KERN_INFO, ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) "%s: Dma-desc: Instruct for rdmem dma (size 0x%x).\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) __func__, size));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) /* Execute: Start pex-dma operation. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) rval = qla4_83xx_start_pex_dma(ha, m_hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) if (rval != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) DEBUG2(ql4_printk(KERN_INFO, ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) "scsi(%ld): start-pex-dma failed rval=0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) ha->host_no, rval));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) goto error_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) memcpy(data_ptr, rdmem_buffer, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) data_ptr += size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) read_size += size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) DEBUG2(ql4_printk(KERN_INFO, ha, "Leaving fn: %s\n", __func__));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) *d_ptr = (uint32_t *)data_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) error_exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) if (rdmem_buffer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) dma_free_coherent(&ha->pdev->dev, size, rdmem_buffer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) rdmem_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) static int qla4_8xxx_minidump_process_l2tag(struct scsi_qla_host *ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) struct qla8xxx_minidump_entry_hdr *entry_hdr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) uint32_t **d_ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) uint32_t addr, r_addr, c_addr, t_r_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) uint32_t i, k, loop_count, t_value, r_cnt, r_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) unsigned long p_wait, w_time, p_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) uint32_t c_value_w, c_value_r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) struct qla8xxx_minidump_entry_cache *cache_hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) int rval = QLA_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) uint32_t *data_ptr = *d_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) cache_hdr = (struct qla8xxx_minidump_entry_cache *)entry_hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) loop_count = cache_hdr->op_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) r_addr = cache_hdr->read_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) c_addr = cache_hdr->control_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) c_value_w = cache_hdr->cache_ctrl.write_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) t_r_addr = cache_hdr->tag_reg_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) t_value = cache_hdr->addr_ctrl.init_tag_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) r_cnt = cache_hdr->read_ctrl.read_addr_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) p_wait = cache_hdr->cache_ctrl.poll_wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) p_mask = cache_hdr->cache_ctrl.poll_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) for (i = 0; i < loop_count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) ha->isp_ops->wr_reg_indirect(ha, t_r_addr, t_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) if (c_value_w)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) ha->isp_ops->wr_reg_indirect(ha, c_addr, c_value_w);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) if (p_mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) w_time = jiffies + p_wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) ha->isp_ops->rd_reg_indirect(ha, c_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) &c_value_r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) if ((c_value_r & p_mask) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) } else if (time_after_eq(jiffies, w_time)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) /* capturing dump failed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) } while (1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) addr = r_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) for (k = 0; k < r_cnt; k++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) ha->isp_ops->rd_reg_indirect(ha, addr, &r_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) *data_ptr++ = cpu_to_le32(r_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) addr += cache_hdr->read_ctrl.read_addr_stride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) t_value += cache_hdr->addr_ctrl.tag_value_stride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) *d_ptr = data_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) return QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) static int qla4_8xxx_minidump_process_control(struct scsi_qla_host *ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) struct qla8xxx_minidump_entry_hdr *entry_hdr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) struct qla8xxx_minidump_entry_crb *crb_entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) uint32_t read_value, opcode, poll_time, addr, index, rval = QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) uint32_t crb_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) unsigned long wtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) struct qla4_8xxx_minidump_template_hdr *tmplt_hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) tmplt_hdr = (struct qla4_8xxx_minidump_template_hdr *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) ha->fw_dump_tmplt_hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) crb_entry = (struct qla8xxx_minidump_entry_crb *)entry_hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) crb_addr = crb_entry->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) for (i = 0; i < crb_entry->op_count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) opcode = crb_entry->crb_ctrl.opcode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) if (opcode & QLA8XXX_DBG_OPCODE_WR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) ha->isp_ops->wr_reg_indirect(ha, crb_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) crb_entry->value_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) opcode &= ~QLA8XXX_DBG_OPCODE_WR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) if (opcode & QLA8XXX_DBG_OPCODE_RW) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) ha->isp_ops->rd_reg_indirect(ha, crb_addr, &read_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) ha->isp_ops->wr_reg_indirect(ha, crb_addr, read_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) opcode &= ~QLA8XXX_DBG_OPCODE_RW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) if (opcode & QLA8XXX_DBG_OPCODE_AND) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) ha->isp_ops->rd_reg_indirect(ha, crb_addr, &read_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) read_value &= crb_entry->value_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) opcode &= ~QLA8XXX_DBG_OPCODE_AND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) if (opcode & QLA8XXX_DBG_OPCODE_OR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) read_value |= crb_entry->value_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) opcode &= ~QLA8XXX_DBG_OPCODE_OR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) ha->isp_ops->wr_reg_indirect(ha, crb_addr, read_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) if (opcode & QLA8XXX_DBG_OPCODE_OR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) ha->isp_ops->rd_reg_indirect(ha, crb_addr, &read_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) read_value |= crb_entry->value_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) ha->isp_ops->wr_reg_indirect(ha, crb_addr, read_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) opcode &= ~QLA8XXX_DBG_OPCODE_OR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) if (opcode & QLA8XXX_DBG_OPCODE_POLL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) poll_time = crb_entry->crb_strd.poll_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) wtime = jiffies + poll_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) ha->isp_ops->rd_reg_indirect(ha, crb_addr, &read_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) if ((read_value & crb_entry->value_2) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) crb_entry->value_1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) } else if (time_after_eq(jiffies, wtime)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) /* capturing dump failed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) rval = QLA_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) ha->isp_ops->rd_reg_indirect(ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) crb_addr, &read_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) } while (1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) opcode &= ~QLA8XXX_DBG_OPCODE_POLL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) if (opcode & QLA8XXX_DBG_OPCODE_RDSTATE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) if (crb_entry->crb_strd.state_index_a) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) index = crb_entry->crb_strd.state_index_a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) addr = tmplt_hdr->saved_state_array[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) addr = crb_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) ha->isp_ops->rd_reg_indirect(ha, addr, &read_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) index = crb_entry->crb_ctrl.state_index_v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) tmplt_hdr->saved_state_array[index] = read_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) opcode &= ~QLA8XXX_DBG_OPCODE_RDSTATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) if (opcode & QLA8XXX_DBG_OPCODE_WRSTATE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) if (crb_entry->crb_strd.state_index_a) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) index = crb_entry->crb_strd.state_index_a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) addr = tmplt_hdr->saved_state_array[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) addr = crb_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) if (crb_entry->crb_ctrl.state_index_v) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) index = crb_entry->crb_ctrl.state_index_v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) read_value =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) tmplt_hdr->saved_state_array[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) read_value = crb_entry->value_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) ha->isp_ops->wr_reg_indirect(ha, addr, read_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) opcode &= ~QLA8XXX_DBG_OPCODE_WRSTATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) if (opcode & QLA8XXX_DBG_OPCODE_MDSTATE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) index = crb_entry->crb_ctrl.state_index_v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) read_value = tmplt_hdr->saved_state_array[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) read_value <<= crb_entry->crb_ctrl.shl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) read_value >>= crb_entry->crb_ctrl.shr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) if (crb_entry->value_2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) read_value &= crb_entry->value_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) read_value |= crb_entry->value_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) read_value += crb_entry->value_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) tmplt_hdr->saved_state_array[index] = read_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) opcode &= ~QLA8XXX_DBG_OPCODE_MDSTATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) crb_addr += crb_entry->crb_strd.addr_stride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) DEBUG2(ql4_printk(KERN_INFO, ha, "Leaving fn: %s\n", __func__));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) static void qla4_8xxx_minidump_process_rdocm(struct scsi_qla_host *ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) struct qla8xxx_minidump_entry_hdr *entry_hdr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) uint32_t **d_ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) uint32_t r_addr, r_stride, loop_cnt, i, r_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) struct qla8xxx_minidump_entry_rdocm *ocm_hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) uint32_t *data_ptr = *d_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) ocm_hdr = (struct qla8xxx_minidump_entry_rdocm *)entry_hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) r_addr = ocm_hdr->read_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) r_stride = ocm_hdr->read_addr_stride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) loop_cnt = ocm_hdr->op_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) DEBUG2(ql4_printk(KERN_INFO, ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) "[%s]: r_addr: 0x%x, r_stride: 0x%x, loop_cnt: 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) __func__, r_addr, r_stride, loop_cnt));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) for (i = 0; i < loop_cnt; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) r_value = readl((void __iomem *)(r_addr + ha->nx_pcibase));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) *data_ptr++ = cpu_to_le32(r_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) r_addr += r_stride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) DEBUG2(ql4_printk(KERN_INFO, ha, "Leaving fn: %s datacount: 0x%lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) __func__, (long unsigned int) (loop_cnt * sizeof(uint32_t))));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) *d_ptr = data_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) static void qla4_8xxx_minidump_process_rdmux(struct scsi_qla_host *ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) struct qla8xxx_minidump_entry_hdr *entry_hdr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) uint32_t **d_ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) uint32_t r_addr, s_stride, s_addr, s_value, loop_cnt, i, r_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) struct qla8xxx_minidump_entry_mux *mux_hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) uint32_t *data_ptr = *d_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) mux_hdr = (struct qla8xxx_minidump_entry_mux *)entry_hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) r_addr = mux_hdr->read_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) s_addr = mux_hdr->select_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) s_stride = mux_hdr->select_value_stride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) s_value = mux_hdr->select_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) loop_cnt = mux_hdr->op_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) for (i = 0; i < loop_cnt; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) ha->isp_ops->wr_reg_indirect(ha, s_addr, s_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) ha->isp_ops->rd_reg_indirect(ha, r_addr, &r_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) *data_ptr++ = cpu_to_le32(s_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) *data_ptr++ = cpu_to_le32(r_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) s_value += s_stride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) *d_ptr = data_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) static void qla4_8xxx_minidump_process_l1cache(struct scsi_qla_host *ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) struct qla8xxx_minidump_entry_hdr *entry_hdr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) uint32_t **d_ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) uint32_t addr, r_addr, c_addr, t_r_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) uint32_t i, k, loop_count, t_value, r_cnt, r_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) uint32_t c_value_w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) struct qla8xxx_minidump_entry_cache *cache_hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) uint32_t *data_ptr = *d_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) cache_hdr = (struct qla8xxx_minidump_entry_cache *)entry_hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) loop_count = cache_hdr->op_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) r_addr = cache_hdr->read_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) c_addr = cache_hdr->control_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) c_value_w = cache_hdr->cache_ctrl.write_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) t_r_addr = cache_hdr->tag_reg_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) t_value = cache_hdr->addr_ctrl.init_tag_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) r_cnt = cache_hdr->read_ctrl.read_addr_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) for (i = 0; i < loop_count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) ha->isp_ops->wr_reg_indirect(ha, t_r_addr, t_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) ha->isp_ops->wr_reg_indirect(ha, c_addr, c_value_w);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) addr = r_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) for (k = 0; k < r_cnt; k++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) ha->isp_ops->rd_reg_indirect(ha, addr, &r_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) *data_ptr++ = cpu_to_le32(r_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) addr += cache_hdr->read_ctrl.read_addr_stride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) t_value += cache_hdr->addr_ctrl.tag_value_stride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) *d_ptr = data_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) static void qla4_8xxx_minidump_process_queue(struct scsi_qla_host *ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) struct qla8xxx_minidump_entry_hdr *entry_hdr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) uint32_t **d_ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) uint32_t s_addr, r_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) uint32_t r_stride, r_value, r_cnt, qid = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) uint32_t i, k, loop_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) struct qla8xxx_minidump_entry_queue *q_hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) uint32_t *data_ptr = *d_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) q_hdr = (struct qla8xxx_minidump_entry_queue *)entry_hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) s_addr = q_hdr->select_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) r_cnt = q_hdr->rd_strd.read_addr_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) r_stride = q_hdr->rd_strd.read_addr_stride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) loop_cnt = q_hdr->op_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) for (i = 0; i < loop_cnt; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) ha->isp_ops->wr_reg_indirect(ha, s_addr, qid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) r_addr = q_hdr->read_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) for (k = 0; k < r_cnt; k++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) ha->isp_ops->rd_reg_indirect(ha, r_addr, &r_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) *data_ptr++ = cpu_to_le32(r_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) r_addr += r_stride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) qid += q_hdr->q_strd.queue_id_stride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) *d_ptr = data_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) #define MD_DIRECT_ROM_WINDOW 0x42110030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) #define MD_DIRECT_ROM_READ_BASE 0x42150000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) static void qla4_82xx_minidump_process_rdrom(struct scsi_qla_host *ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) struct qla8xxx_minidump_entry_hdr *entry_hdr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) uint32_t **d_ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) uint32_t r_addr, r_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) uint32_t i, loop_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) struct qla8xxx_minidump_entry_rdrom *rom_hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) uint32_t *data_ptr = *d_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) rom_hdr = (struct qla8xxx_minidump_entry_rdrom *)entry_hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) r_addr = rom_hdr->read_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) loop_cnt = rom_hdr->read_data_size/sizeof(uint32_t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) DEBUG2(ql4_printk(KERN_INFO, ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) "[%s]: flash_addr: 0x%x, read_data_size: 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) __func__, r_addr, loop_cnt));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) for (i = 0; i < loop_cnt; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) ha->isp_ops->wr_reg_indirect(ha, MD_DIRECT_ROM_WINDOW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) (r_addr & 0xFFFF0000));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) ha->isp_ops->rd_reg_indirect(ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) MD_DIRECT_ROM_READ_BASE + (r_addr & 0x0000FFFF),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) &r_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) *data_ptr++ = cpu_to_le32(r_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) r_addr += sizeof(uint32_t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) *d_ptr = data_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) #define MD_MIU_TEST_AGT_CTRL 0x41000090
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) #define MD_MIU_TEST_AGT_ADDR_LO 0x41000094
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) #define MD_MIU_TEST_AGT_ADDR_HI 0x41000098
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) static int __qla4_8xxx_minidump_process_rdmem(struct scsi_qla_host *ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) struct qla8xxx_minidump_entry_hdr *entry_hdr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) uint32_t **d_ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) uint32_t r_addr, r_value, r_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) uint32_t i, j, loop_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) struct qla8xxx_minidump_entry_rdmem *m_hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) uint32_t *data_ptr = *d_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) m_hdr = (struct qla8xxx_minidump_entry_rdmem *)entry_hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) r_addr = m_hdr->read_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) loop_cnt = m_hdr->read_data_size/16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) DEBUG2(ql4_printk(KERN_INFO, ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) "[%s]: Read addr: 0x%x, read_data_size: 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) __func__, r_addr, m_hdr->read_data_size));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) if (r_addr & 0xf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) DEBUG2(ql4_printk(KERN_INFO, ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) "[%s]: Read addr 0x%x not 16 bytes aligned\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) __func__, r_addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) return QLA_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) if (m_hdr->read_data_size % 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) DEBUG2(ql4_printk(KERN_INFO, ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) "[%s]: Read data[0x%x] not multiple of 16 bytes\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) __func__, m_hdr->read_data_size));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) return QLA_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) DEBUG2(ql4_printk(KERN_INFO, ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) "[%s]: rdmem_addr: 0x%x, read_data_size: 0x%x, loop_cnt: 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) __func__, r_addr, m_hdr->read_data_size, loop_cnt));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) write_lock_irqsave(&ha->hw_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) for (i = 0; i < loop_cnt; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) ha->isp_ops->wr_reg_indirect(ha, MD_MIU_TEST_AGT_ADDR_LO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) r_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) r_value = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) ha->isp_ops->wr_reg_indirect(ha, MD_MIU_TEST_AGT_ADDR_HI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) r_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) r_value = MIU_TA_CTL_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) ha->isp_ops->wr_reg_indirect(ha, MD_MIU_TEST_AGT_CTRL, r_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) r_value = MIU_TA_CTL_START_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) ha->isp_ops->wr_reg_indirect(ha, MD_MIU_TEST_AGT_CTRL, r_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) for (j = 0; j < MAX_CTL_CHECK; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) ha->isp_ops->rd_reg_indirect(ha, MD_MIU_TEST_AGT_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) &r_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528) if ((r_value & MIU_TA_CTL_BUSY) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) if (j >= MAX_CTL_CHECK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) printk_ratelimited(KERN_ERR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) "%s: failed to read through agent\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) write_unlock_irqrestore(&ha->hw_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) return QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) for (j = 0; j < 4; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) ha->isp_ops->rd_reg_indirect(ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) MD_MIU_TEST_AGT_RDDATA[j],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) &r_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) *data_ptr++ = cpu_to_le32(r_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) r_addr += 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) write_unlock_irqrestore(&ha->hw_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) DEBUG2(ql4_printk(KERN_INFO, ha, "Leaving fn: %s datacount: 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) __func__, (loop_cnt * 16)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) *d_ptr = data_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) return QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) static int qla4_8xxx_minidump_process_rdmem(struct scsi_qla_host *ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559) struct qla8xxx_minidump_entry_hdr *entry_hdr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) uint32_t **d_ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562) uint32_t *data_ptr = *d_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) int rval = QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) rval = qla4_8xxx_minidump_pex_dma_read(ha, entry_hdr, &data_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) if (rval != QLA_SUCCESS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567) rval = __qla4_8xxx_minidump_process_rdmem(ha, entry_hdr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) &data_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) *d_ptr = data_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) static void qla4_8xxx_mark_entry_skipped(struct scsi_qla_host *ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) struct qla8xxx_minidump_entry_hdr *entry_hdr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) int index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) entry_hdr->d_ctrl.driver_flags |= QLA8XXX_DBG_SKIPPED_FLAG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) DEBUG2(ql4_printk(KERN_INFO, ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579) "scsi(%ld): Skipping entry[%d]: ETYPE[0x%x]-ELEVEL[0x%x]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580) ha->host_no, index, entry_hdr->entry_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) entry_hdr->d_ctrl.entry_capture_mask));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) /* If driver encounters a new entry type that it cannot process,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583) * it should just skip the entry and adjust the total buffer size by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584) * from subtracting the skipped bytes from it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) ha->fw_dump_skip_size += entry_hdr->entry_capture_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589) /* ISP83xx functions to process new minidump entries... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) static uint32_t qla83xx_minidump_process_pollrd(struct scsi_qla_host *ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) struct qla8xxx_minidump_entry_hdr *entry_hdr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592) uint32_t **d_ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) uint32_t r_addr, s_addr, s_value, r_value, poll_wait, poll_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595) uint16_t s_stride, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596) uint32_t *data_ptr = *d_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) uint32_t rval = QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598) struct qla83xx_minidump_entry_pollrd *pollrd_hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) pollrd_hdr = (struct qla83xx_minidump_entry_pollrd *)entry_hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601) s_addr = le32_to_cpu(pollrd_hdr->select_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) r_addr = le32_to_cpu(pollrd_hdr->read_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603) s_value = le32_to_cpu(pollrd_hdr->select_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) s_stride = le32_to_cpu(pollrd_hdr->select_value_stride);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606) poll_wait = le32_to_cpu(pollrd_hdr->poll_wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607) poll_mask = le32_to_cpu(pollrd_hdr->poll_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609) for (i = 0; i < le32_to_cpu(pollrd_hdr->op_count); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) ha->isp_ops->wr_reg_indirect(ha, s_addr, s_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) poll_wait = le32_to_cpu(pollrd_hdr->poll_wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612) while (1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) ha->isp_ops->rd_reg_indirect(ha, s_addr, &r_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615) if ((r_value & poll_mask) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618) msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619) if (--poll_wait == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620) ql4_printk(KERN_ERR, ha, "%s: TIMEOUT\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622) rval = QLA_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623) goto exit_process_pollrd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) ha->isp_ops->rd_reg_indirect(ha, r_addr, &r_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628) *data_ptr++ = cpu_to_le32(s_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629) *data_ptr++ = cpu_to_le32(r_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630) s_value += s_stride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) *d_ptr = data_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635) exit_process_pollrd:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639) static uint32_t qla4_84xx_minidump_process_rddfe(struct scsi_qla_host *ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640) struct qla8xxx_minidump_entry_hdr *entry_hdr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641) uint32_t **d_ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643) int loop_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644) uint32_t addr1, addr2, value, data, temp, wrval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645) uint8_t stride, stride2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646) uint16_t count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647) uint32_t poll, mask, modify_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648) uint32_t wait_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649) uint32_t *data_ptr = *d_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650) struct qla8044_minidump_entry_rddfe *rddfe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651) uint32_t rval = QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653) rddfe = (struct qla8044_minidump_entry_rddfe *)entry_hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654) addr1 = le32_to_cpu(rddfe->addr_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655) value = le32_to_cpu(rddfe->value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656) stride = le32_to_cpu(rddfe->stride);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657) stride2 = le32_to_cpu(rddfe->stride2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658) count = le32_to_cpu(rddfe->count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660) poll = le32_to_cpu(rddfe->poll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661) mask = le32_to_cpu(rddfe->mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662) modify_mask = le32_to_cpu(rddfe->modify_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664) addr2 = addr1 + stride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666) for (loop_cnt = 0x0; loop_cnt < count; loop_cnt++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667) ha->isp_ops->wr_reg_indirect(ha, addr1, (0x40000000 | value));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669) wait_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670) while (wait_count < poll) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671) ha->isp_ops->rd_reg_indirect(ha, addr1, &temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672) if ((temp & mask) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674) wait_count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677) if (wait_count == poll) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678) ql4_printk(KERN_ERR, ha, "%s: TIMEOUT\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679) rval = QLA_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680) goto exit_process_rddfe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682) ha->isp_ops->rd_reg_indirect(ha, addr2, &temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683) temp = temp & modify_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684) temp = (temp | ((loop_cnt << 16) | loop_cnt));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685) wrval = ((temp << 16) | temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687) ha->isp_ops->wr_reg_indirect(ha, addr2, wrval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688) ha->isp_ops->wr_reg_indirect(ha, addr1, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690) wait_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691) while (wait_count < poll) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692) ha->isp_ops->rd_reg_indirect(ha, addr1, &temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693) if ((temp & mask) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695) wait_count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697) if (wait_count == poll) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698) ql4_printk(KERN_ERR, ha, "%s: TIMEOUT\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700) rval = QLA_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701) goto exit_process_rddfe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704) ha->isp_ops->wr_reg_indirect(ha, addr1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705) ((0x40000000 | value) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706) stride2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707) wait_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708) while (wait_count < poll) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709) ha->isp_ops->rd_reg_indirect(ha, addr1, &temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710) if ((temp & mask) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712) wait_count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715) if (wait_count == poll) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716) ql4_printk(KERN_ERR, ha, "%s: TIMEOUT\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718) rval = QLA_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2719) goto exit_process_rddfe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2720) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2722) ha->isp_ops->rd_reg_indirect(ha, addr2, &data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2724) *data_ptr++ = cpu_to_le32(wrval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2725) *data_ptr++ = cpu_to_le32(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2726) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2727) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2729) *d_ptr = data_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2730) exit_process_rddfe:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2731) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2732) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2734) static uint32_t qla4_84xx_minidump_process_rdmdio(struct scsi_qla_host *ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2735) struct qla8xxx_minidump_entry_hdr *entry_hdr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2736) uint32_t **d_ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2737) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2738) int rval = QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2739) uint32_t addr1, addr2, value1, value2, data, selval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2740) uint8_t stride1, stride2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2741) uint32_t addr3, addr4, addr5, addr6, addr7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2742) uint16_t count, loop_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2743) uint32_t mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2744) uint32_t *data_ptr = *d_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2745) struct qla8044_minidump_entry_rdmdio *rdmdio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2747) rdmdio = (struct qla8044_minidump_entry_rdmdio *)entry_hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2748) addr1 = le32_to_cpu(rdmdio->addr_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2749) addr2 = le32_to_cpu(rdmdio->addr_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2750) value1 = le32_to_cpu(rdmdio->value_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2751) stride1 = le32_to_cpu(rdmdio->stride_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2752) stride2 = le32_to_cpu(rdmdio->stride_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2753) count = le32_to_cpu(rdmdio->count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2755) mask = le32_to_cpu(rdmdio->mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2756) value2 = le32_to_cpu(rdmdio->value_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2758) addr3 = addr1 + stride1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2760) for (loop_cnt = 0; loop_cnt < count; loop_cnt++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2761) rval = ql4_84xx_poll_wait_ipmdio_bus_idle(ha, addr1, addr2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2762) addr3, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2763) if (rval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2764) goto exit_process_rdmdio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2766) addr4 = addr2 - stride1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2767) rval = ql4_84xx_ipmdio_wr_reg(ha, addr1, addr3, mask, addr4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2768) value2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2769) if (rval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2770) goto exit_process_rdmdio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2772) addr5 = addr2 - (2 * stride1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2773) rval = ql4_84xx_ipmdio_wr_reg(ha, addr1, addr3, mask, addr5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2774) value1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2775) if (rval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2776) goto exit_process_rdmdio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2778) addr6 = addr2 - (3 * stride1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2779) rval = ql4_84xx_ipmdio_wr_reg(ha, addr1, addr3, mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2780) addr6, 0x2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2781) if (rval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2782) goto exit_process_rdmdio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2784) rval = ql4_84xx_poll_wait_ipmdio_bus_idle(ha, addr1, addr2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2785) addr3, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2786) if (rval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2787) goto exit_process_rdmdio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2789) addr7 = addr2 - (4 * stride1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2790) rval = ql4_84xx_ipmdio_rd_reg(ha, addr1, addr3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2791) mask, addr7, &data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2792) if (rval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2793) goto exit_process_rdmdio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2795) selval = (value2 << 18) | (value1 << 2) | 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2797) stride2 = le32_to_cpu(rdmdio->stride_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2798) *data_ptr++ = cpu_to_le32(selval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2799) *data_ptr++ = cpu_to_le32(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2801) value1 = value1 + stride2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2802) *d_ptr = data_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2803) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2805) exit_process_rdmdio:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2806) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2807) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2809) static uint32_t qla4_84xx_minidump_process_pollwr(struct scsi_qla_host *ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2810) struct qla8xxx_minidump_entry_hdr *entry_hdr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2811) uint32_t **d_ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2812) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2813) uint32_t addr1, addr2, value1, value2, poll, r_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2814) struct qla8044_minidump_entry_pollwr *pollwr_hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2815) uint32_t wait_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2816) uint32_t rval = QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2818) pollwr_hdr = (struct qla8044_minidump_entry_pollwr *)entry_hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2819) addr1 = le32_to_cpu(pollwr_hdr->addr_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2820) addr2 = le32_to_cpu(pollwr_hdr->addr_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2821) value1 = le32_to_cpu(pollwr_hdr->value_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2822) value2 = le32_to_cpu(pollwr_hdr->value_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2824) poll = le32_to_cpu(pollwr_hdr->poll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2826) while (wait_count < poll) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2827) ha->isp_ops->rd_reg_indirect(ha, addr1, &r_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2829) if ((r_value & poll) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2830) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2832) wait_count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2833) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2835) if (wait_count == poll) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2836) ql4_printk(KERN_ERR, ha, "%s: TIMEOUT\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2837) rval = QLA_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2838) goto exit_process_pollwr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2839) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2841) ha->isp_ops->wr_reg_indirect(ha, addr2, value2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2842) ha->isp_ops->wr_reg_indirect(ha, addr1, value1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2844) wait_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2845) while (wait_count < poll) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2846) ha->isp_ops->rd_reg_indirect(ha, addr1, &r_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2848) if ((r_value & poll) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2849) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2850) wait_count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2851) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2853) exit_process_pollwr:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2854) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2855) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2857) static void qla83xx_minidump_process_rdmux2(struct scsi_qla_host *ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2858) struct qla8xxx_minidump_entry_hdr *entry_hdr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2859) uint32_t **d_ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2860) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2861) uint32_t sel_val1, sel_val2, t_sel_val, data, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2862) uint32_t sel_addr1, sel_addr2, sel_val_mask, read_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2863) struct qla83xx_minidump_entry_rdmux2 *rdmux2_hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2864) uint32_t *data_ptr = *d_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2866) rdmux2_hdr = (struct qla83xx_minidump_entry_rdmux2 *)entry_hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2867) sel_val1 = le32_to_cpu(rdmux2_hdr->select_value_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2868) sel_val2 = le32_to_cpu(rdmux2_hdr->select_value_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2869) sel_addr1 = le32_to_cpu(rdmux2_hdr->select_addr_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2870) sel_addr2 = le32_to_cpu(rdmux2_hdr->select_addr_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2871) sel_val_mask = le32_to_cpu(rdmux2_hdr->select_value_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2872) read_addr = le32_to_cpu(rdmux2_hdr->read_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2874) for (i = 0; i < rdmux2_hdr->op_count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2875) ha->isp_ops->wr_reg_indirect(ha, sel_addr1, sel_val1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2876) t_sel_val = sel_val1 & sel_val_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2877) *data_ptr++ = cpu_to_le32(t_sel_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2879) ha->isp_ops->wr_reg_indirect(ha, sel_addr2, t_sel_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2880) ha->isp_ops->rd_reg_indirect(ha, read_addr, &data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2882) *data_ptr++ = cpu_to_le32(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2884) ha->isp_ops->wr_reg_indirect(ha, sel_addr1, sel_val2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2885) t_sel_val = sel_val2 & sel_val_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2886) *data_ptr++ = cpu_to_le32(t_sel_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2888) ha->isp_ops->wr_reg_indirect(ha, sel_addr2, t_sel_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2889) ha->isp_ops->rd_reg_indirect(ha, read_addr, &data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2891) *data_ptr++ = cpu_to_le32(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2893) sel_val1 += rdmux2_hdr->select_value_stride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2894) sel_val2 += rdmux2_hdr->select_value_stride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2895) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2897) *d_ptr = data_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2898) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2900) static uint32_t qla83xx_minidump_process_pollrdmwr(struct scsi_qla_host *ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2901) struct qla8xxx_minidump_entry_hdr *entry_hdr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2902) uint32_t **d_ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2903) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2904) uint32_t poll_wait, poll_mask, r_value, data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2905) uint32_t addr_1, addr_2, value_1, value_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2906) uint32_t *data_ptr = *d_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2907) uint32_t rval = QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2908) struct qla83xx_minidump_entry_pollrdmwr *poll_hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2910) poll_hdr = (struct qla83xx_minidump_entry_pollrdmwr *)entry_hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2911) addr_1 = le32_to_cpu(poll_hdr->addr_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2912) addr_2 = le32_to_cpu(poll_hdr->addr_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2913) value_1 = le32_to_cpu(poll_hdr->value_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2914) value_2 = le32_to_cpu(poll_hdr->value_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2915) poll_mask = le32_to_cpu(poll_hdr->poll_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2917) ha->isp_ops->wr_reg_indirect(ha, addr_1, value_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2919) poll_wait = le32_to_cpu(poll_hdr->poll_wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2920) while (1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2921) ha->isp_ops->rd_reg_indirect(ha, addr_1, &r_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2923) if ((r_value & poll_mask) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2924) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2925) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2926) msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2927) if (--poll_wait == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2928) ql4_printk(KERN_ERR, ha, "%s: TIMEOUT_1\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2929) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2930) rval = QLA_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2931) goto exit_process_pollrdmwr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2932) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2933) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2934) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2936) ha->isp_ops->rd_reg_indirect(ha, addr_2, &data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2937) data &= le32_to_cpu(poll_hdr->modify_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2938) ha->isp_ops->wr_reg_indirect(ha, addr_2, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2939) ha->isp_ops->wr_reg_indirect(ha, addr_1, value_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2941) poll_wait = le32_to_cpu(poll_hdr->poll_wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2942) while (1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2943) ha->isp_ops->rd_reg_indirect(ha, addr_1, &r_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2945) if ((r_value & poll_mask) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2946) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2947) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2948) msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2949) if (--poll_wait == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2950) ql4_printk(KERN_ERR, ha, "%s: TIMEOUT_2\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2951) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2952) rval = QLA_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2953) goto exit_process_pollrdmwr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2954) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2955) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2956) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2958) *data_ptr++ = cpu_to_le32(addr_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2959) *data_ptr++ = cpu_to_le32(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2960) *d_ptr = data_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2962) exit_process_pollrdmwr:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2963) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2964) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2966) static uint32_t qla4_83xx_minidump_process_rdrom(struct scsi_qla_host *ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2967) struct qla8xxx_minidump_entry_hdr *entry_hdr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2968) uint32_t **d_ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2969) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2970) uint32_t fl_addr, u32_count, rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2971) struct qla8xxx_minidump_entry_rdrom *rom_hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2972) uint32_t *data_ptr = *d_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2974) rom_hdr = (struct qla8xxx_minidump_entry_rdrom *)entry_hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2975) fl_addr = le32_to_cpu(rom_hdr->read_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2976) u32_count = le32_to_cpu(rom_hdr->read_data_size)/sizeof(uint32_t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2978) DEBUG2(ql4_printk(KERN_INFO, ha, "[%s]: fl_addr: 0x%x, count: 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2979) __func__, fl_addr, u32_count));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2981) rval = qla4_83xx_lockless_flash_read_u32(ha, fl_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2982) (u8 *)(data_ptr), u32_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2984) if (rval == QLA_ERROR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2985) ql4_printk(KERN_ERR, ha, "%s: Flash Read Error,Count=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2986) __func__, u32_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2987) goto exit_process_rdrom;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2988) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2990) data_ptr += u32_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2991) *d_ptr = data_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2993) exit_process_rdrom:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2994) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2995) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2997) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2998) * qla4_8xxx_collect_md_data - Retrieve firmware minidump data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2999) * @ha: pointer to adapter structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3000) **/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3001) static int qla4_8xxx_collect_md_data(struct scsi_qla_host *ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3002) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3003) int num_entry_hdr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3004) struct qla8xxx_minidump_entry_hdr *entry_hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3005) struct qla4_8xxx_minidump_template_hdr *tmplt_hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3006) uint32_t *data_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3007) uint32_t data_collected = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3008) int i, rval = QLA_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3009) uint64_t now;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3010) uint32_t timestamp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3012) ha->fw_dump_skip_size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3013) if (!ha->fw_dump) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3014) ql4_printk(KERN_INFO, ha, "%s(%ld) No buffer to dump\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3015) __func__, ha->host_no);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3016) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3017) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3019) tmplt_hdr = (struct qla4_8xxx_minidump_template_hdr *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3020) ha->fw_dump_tmplt_hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3021) data_ptr = (uint32_t *)((uint8_t *)ha->fw_dump +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3022) ha->fw_dump_tmplt_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3023) data_collected += ha->fw_dump_tmplt_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3025) num_entry_hdr = tmplt_hdr->num_of_entries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3026) ql4_printk(KERN_INFO, ha, "[%s]: starting data ptr: %p\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3027) __func__, data_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3028) ql4_printk(KERN_INFO, ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3029) "[%s]: no of entry headers in Template: 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3030) __func__, num_entry_hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3031) ql4_printk(KERN_INFO, ha, "[%s]: Capture Mask obtained: 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3032) __func__, ha->fw_dump_capture_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3033) ql4_printk(KERN_INFO, ha, "[%s]: Total_data_size 0x%x, %d obtained\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3034) __func__, ha->fw_dump_size, ha->fw_dump_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3036) /* Update current timestamp before taking dump */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3037) now = get_jiffies_64();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3038) timestamp = (u32)(jiffies_to_msecs(now) / 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3039) tmplt_hdr->driver_timestamp = timestamp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3041) entry_hdr = (struct qla8xxx_minidump_entry_hdr *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3042) (((uint8_t *)ha->fw_dump_tmplt_hdr) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3043) tmplt_hdr->first_entry_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3045) if (is_qla8032(ha) || is_qla8042(ha))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3046) tmplt_hdr->saved_state_array[QLA83XX_SS_OCM_WNDREG_INDEX] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3047) tmplt_hdr->ocm_window_reg[ha->func_num];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3049) /* Walk through the entry headers - validate/perform required action */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3050) for (i = 0; i < num_entry_hdr; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3051) if (data_collected > ha->fw_dump_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3052) ql4_printk(KERN_INFO, ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3053) "Data collected: [0x%x], Total Dump size: [0x%x]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3054) data_collected, ha->fw_dump_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3055) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3056) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3058) if (!(entry_hdr->d_ctrl.entry_capture_mask &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3059) ha->fw_dump_capture_mask)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3060) entry_hdr->d_ctrl.driver_flags |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3061) QLA8XXX_DBG_SKIPPED_FLAG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3062) goto skip_nxt_entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3063) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3065) DEBUG2(ql4_printk(KERN_INFO, ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3066) "Data collected: [0x%x], Dump size left:[0x%x]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3067) data_collected,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3068) (ha->fw_dump_size - data_collected)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3070) /* Decode the entry type and take required action to capture
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3071) * debug data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3072) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3073) switch (entry_hdr->entry_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3074) case QLA8XXX_RDEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3075) qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3076) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3077) case QLA8XXX_CNTRL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3078) rval = qla4_8xxx_minidump_process_control(ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3079) entry_hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3080) if (rval != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3081) qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3082) goto md_failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3083) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3084) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3085) case QLA8XXX_RDCRB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3086) qla4_8xxx_minidump_process_rdcrb(ha, entry_hdr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3087) &data_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3088) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3089) case QLA8XXX_RDMEM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3090) rval = qla4_8xxx_minidump_process_rdmem(ha, entry_hdr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3091) &data_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3092) if (rval != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3093) qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3094) goto md_failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3095) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3096) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3097) case QLA8XXX_BOARD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3098) case QLA8XXX_RDROM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3099) if (is_qla8022(ha)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3100) qla4_82xx_minidump_process_rdrom(ha, entry_hdr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3101) &data_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3102) } else if (is_qla8032(ha) || is_qla8042(ha)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3103) rval = qla4_83xx_minidump_process_rdrom(ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3104) entry_hdr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3105) &data_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3106) if (rval != QLA_SUCCESS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3107) qla4_8xxx_mark_entry_skipped(ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3108) entry_hdr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3109) i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3111) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3112) case QLA8XXX_L2DTG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3113) case QLA8XXX_L2ITG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3114) case QLA8XXX_L2DAT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3115) case QLA8XXX_L2INS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3116) rval = qla4_8xxx_minidump_process_l2tag(ha, entry_hdr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3117) &data_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3118) if (rval != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3119) qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3120) goto md_failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3122) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3123) case QLA8XXX_L1DTG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3124) case QLA8XXX_L1ITG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3125) case QLA8XXX_L1DAT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3126) case QLA8XXX_L1INS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3127) qla4_8xxx_minidump_process_l1cache(ha, entry_hdr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3128) &data_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3129) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3130) case QLA8XXX_RDOCM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3131) qla4_8xxx_minidump_process_rdocm(ha, entry_hdr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3132) &data_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3133) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3134) case QLA8XXX_RDMUX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3135) qla4_8xxx_minidump_process_rdmux(ha, entry_hdr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3136) &data_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3137) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3138) case QLA8XXX_QUEUE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3139) qla4_8xxx_minidump_process_queue(ha, entry_hdr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3140) &data_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3141) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3142) case QLA83XX_POLLRD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3143) if (is_qla8022(ha)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3144) qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3145) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3147) rval = qla83xx_minidump_process_pollrd(ha, entry_hdr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3148) &data_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3149) if (rval != QLA_SUCCESS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3150) qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3151) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3152) case QLA83XX_RDMUX2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3153) if (is_qla8022(ha)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3154) qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3155) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3157) qla83xx_minidump_process_rdmux2(ha, entry_hdr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3158) &data_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3159) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3160) case QLA83XX_POLLRDMWR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3161) if (is_qla8022(ha)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3162) qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3163) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3165) rval = qla83xx_minidump_process_pollrdmwr(ha, entry_hdr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3166) &data_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3167) if (rval != QLA_SUCCESS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3168) qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3169) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3170) case QLA8044_RDDFE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3171) rval = qla4_84xx_minidump_process_rddfe(ha, entry_hdr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3172) &data_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3173) if (rval != QLA_SUCCESS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3174) qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3175) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3176) case QLA8044_RDMDIO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3177) rval = qla4_84xx_minidump_process_rdmdio(ha, entry_hdr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3178) &data_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3179) if (rval != QLA_SUCCESS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3180) qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3181) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3182) case QLA8044_POLLWR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3183) rval = qla4_84xx_minidump_process_pollwr(ha, entry_hdr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3184) &data_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3185) if (rval != QLA_SUCCESS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3186) qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3187) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3188) case QLA8XXX_RDNOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3189) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3190) qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3191) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3194) data_collected = (uint8_t *)data_ptr - (uint8_t *)ha->fw_dump;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3195) skip_nxt_entry:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3196) /* next entry in the template */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3197) entry_hdr = (struct qla8xxx_minidump_entry_hdr *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3198) (((uint8_t *)entry_hdr) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3199) entry_hdr->entry_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3202) if ((data_collected + ha->fw_dump_skip_size) != ha->fw_dump_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3203) ql4_printk(KERN_INFO, ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3204) "Dump data mismatch: Data collected: [0x%x], total_data_size:[0x%x]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3205) data_collected, ha->fw_dump_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3206) rval = QLA_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3207) goto md_failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3210) DEBUG2(ql4_printk(KERN_INFO, ha, "Leaving fn: %s Last entry: 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3211) __func__, i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3212) md_failed:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3213) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3216) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3217) * qla4_8xxx_uevent_emit - Send uevent when the firmware dump is ready.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3218) * @ha: pointer to adapter structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3219) * @code: uevent code to act upon
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3220) **/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3221) static void qla4_8xxx_uevent_emit(struct scsi_qla_host *ha, u32 code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3222) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3223) char event_string[40];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3224) char *envp[] = { event_string, NULL };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3226) switch (code) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3227) case QL4_UEVENT_CODE_FW_DUMP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3228) snprintf(event_string, sizeof(event_string), "FW_DUMP=%lu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3229) ha->host_no);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3230) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3231) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3232) /*do nothing*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3233) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3236) kobject_uevent_env(&(&ha->pdev->dev)->kobj, KOBJ_CHANGE, envp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3239) void qla4_8xxx_get_minidump(struct scsi_qla_host *ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3240) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3241) if (ql4xenablemd && test_bit(AF_FW_RECOVERY, &ha->flags) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3242) !test_bit(AF_82XX_FW_DUMPED, &ha->flags)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3243) if (!qla4_8xxx_collect_md_data(ha)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3244) qla4_8xxx_uevent_emit(ha, QL4_UEVENT_CODE_FW_DUMP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3245) set_bit(AF_82XX_FW_DUMPED, &ha->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3246) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3247) ql4_printk(KERN_INFO, ha, "%s: Unable to collect minidump\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3248) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3253) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3254) * qla4_8xxx_device_bootstrap - Initialize device, set DEV_READY, start fw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3255) * @ha: pointer to adapter structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3256) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3257) * Note: IDC lock must be held upon entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3258) **/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3259) int qla4_8xxx_device_bootstrap(struct scsi_qla_host *ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3260) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3261) int rval = QLA_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3262) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3263) uint32_t old_count, count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3264) int need_reset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3266) need_reset = ha->isp_ops->need_reset(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3268) if (need_reset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3269) /* We are trying to perform a recovery here. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3270) if (test_bit(AF_FW_RECOVERY, &ha->flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3271) ha->isp_ops->rom_lock_recovery(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3272) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3273) old_count = qla4_8xxx_rd_direct(ha, QLA8XXX_PEG_ALIVE_COUNTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3274) for (i = 0; i < 10; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3275) msleep(200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3276) count = qla4_8xxx_rd_direct(ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3277) QLA8XXX_PEG_ALIVE_COUNTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3278) if (count != old_count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3279) rval = QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3280) goto dev_ready;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3283) ha->isp_ops->rom_lock_recovery(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3286) /* set to DEV_INITIALIZING */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3287) ql4_printk(KERN_INFO, ha, "HW State: INITIALIZING\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3288) qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DEV_STATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3289) QLA8XXX_DEV_INITIALIZING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3291) ha->isp_ops->idc_unlock(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3293) if (is_qla8022(ha))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3294) qla4_8xxx_get_minidump(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3296) rval = ha->isp_ops->restart_firmware(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3297) ha->isp_ops->idc_lock(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3299) if (rval != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3300) ql4_printk(KERN_INFO, ha, "HW State: FAILED\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3301) qla4_8xxx_clear_drv_active(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3302) qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DEV_STATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3303) QLA8XXX_DEV_FAILED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3304) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3307) dev_ready:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3308) ql4_printk(KERN_INFO, ha, "HW State: READY\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3309) qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DEV_STATE, QLA8XXX_DEV_READY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3311) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3314) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3315) * qla4_82xx_need_reset_handler - Code to start reset sequence
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3316) * @ha: pointer to adapter structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3317) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3318) * Note: IDC lock must be held upon entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3319) **/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3320) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3321) qla4_82xx_need_reset_handler(struct scsi_qla_host *ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3322) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3323) uint32_t dev_state, drv_state, drv_active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3324) uint32_t active_mask = 0xFFFFFFFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3325) unsigned long reset_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3327) ql4_printk(KERN_INFO, ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3328) "Performing ISP error recovery\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3330) if (test_and_clear_bit(AF_ONLINE, &ha->flags)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3331) qla4_82xx_idc_unlock(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3332) ha->isp_ops->disable_intrs(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3333) qla4_82xx_idc_lock(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3336) if (!test_bit(AF_8XXX_RST_OWNER, &ha->flags)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3337) DEBUG2(ql4_printk(KERN_INFO, ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3338) "%s(%ld): reset acknowledged\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3339) __func__, ha->host_no));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3340) qla4_8xxx_set_rst_ready(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3341) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3342) active_mask = (~(1 << (ha->func_num * 4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3345) /* wait for 10 seconds for reset ack from all functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3346) reset_timeout = jiffies + (ha->nx_reset_timeout * HZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3348) drv_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3349) drv_active = qla4_82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3351) ql4_printk(KERN_INFO, ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3352) "%s(%ld): drv_state = 0x%x, drv_active = 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3353) __func__, ha->host_no, drv_state, drv_active);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3355) while (drv_state != (drv_active & active_mask)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3356) if (time_after_eq(jiffies, reset_timeout)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3357) ql4_printk(KERN_INFO, ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3358) "%s: RESET TIMEOUT! drv_state: 0x%08x, drv_active: 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3359) DRIVER_NAME, drv_state, drv_active);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3360) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3363) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3364) * When reset_owner times out, check which functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3365) * acked/did not ack
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3366) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3367) if (test_bit(AF_8XXX_RST_OWNER, &ha->flags)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3368) ql4_printk(KERN_INFO, ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3369) "%s(%ld): drv_state = 0x%x, drv_active = 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3370) __func__, ha->host_no, drv_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3371) drv_active);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3373) qla4_82xx_idc_unlock(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3374) msleep(1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3375) qla4_82xx_idc_lock(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3377) drv_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3378) drv_active = qla4_82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3381) /* Clear RESET OWNER as we are not going to use it any further */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3382) clear_bit(AF_8XXX_RST_OWNER, &ha->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3384) dev_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3385) ql4_printk(KERN_INFO, ha, "Device state is 0x%x = %s\n", dev_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3386) dev_state < MAX_STATES ? qdev_state[dev_state] : "Unknown");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3388) /* Force to DEV_COLD unless someone else is starting a reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3389) if (dev_state != QLA8XXX_DEV_INITIALIZING) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3390) ql4_printk(KERN_INFO, ha, "HW State: COLD/RE-INIT\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3391) qla4_82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_COLD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3392) qla4_8xxx_set_rst_ready(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3396) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3397) * qla4_8xxx_need_qsnt_handler - Code to start qsnt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3398) * @ha: pointer to adapter structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3399) **/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3400) void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3401) qla4_8xxx_need_qsnt_handler(struct scsi_qla_host *ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3402) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3403) ha->isp_ops->idc_lock(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3404) qla4_8xxx_set_qsnt_ready(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3405) ha->isp_ops->idc_unlock(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3408) static void qla4_82xx_set_idc_ver(struct scsi_qla_host *ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3409) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3410) int idc_ver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3411) uint32_t drv_active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3413) drv_active = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_ACTIVE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3414) if (drv_active == (1 << (ha->func_num * 4))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3415) qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_IDC_VERSION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3416) QLA82XX_IDC_VERSION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3417) ql4_printk(KERN_INFO, ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3418) "%s: IDC version updated to %d\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3419) QLA82XX_IDC_VERSION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3420) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3421) idc_ver = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_IDC_VERSION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3422) if (QLA82XX_IDC_VERSION != idc_ver) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3423) ql4_printk(KERN_INFO, ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3424) "%s: qla4xxx driver IDC version %d is not compatible with IDC version %d of other drivers!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3425) __func__, QLA82XX_IDC_VERSION, idc_ver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3428) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3430) static int qla4_83xx_set_idc_ver(struct scsi_qla_host *ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3431) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3432) int idc_ver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3433) uint32_t drv_active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3434) int rval = QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3436) drv_active = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_ACTIVE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3437) if (drv_active == (1 << ha->func_num)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3438) idc_ver = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_IDC_VERSION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3439) idc_ver &= (~0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3440) idc_ver |= QLA83XX_IDC_VER_MAJ_VALUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3441) qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_IDC_VERSION, idc_ver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3442) ql4_printk(KERN_INFO, ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3443) "%s: IDC version updated to %d\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3444) idc_ver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3445) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3446) idc_ver = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_IDC_VERSION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3447) idc_ver &= 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3448) if (QLA83XX_IDC_VER_MAJ_VALUE != idc_ver) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3449) ql4_printk(KERN_INFO, ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3450) "%s: qla4xxx driver IDC version %d is not compatible with IDC version %d of other drivers!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3451) __func__, QLA83XX_IDC_VER_MAJ_VALUE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3452) idc_ver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3453) rval = QLA_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3454) goto exit_set_idc_ver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3455) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3458) /* Update IDC_MINOR_VERSION */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3459) idc_ver = qla4_83xx_rd_reg(ha, QLA83XX_CRB_IDC_VER_MINOR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3460) idc_ver &= ~(0x03 << (ha->func_num * 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3461) idc_ver |= (QLA83XX_IDC_VER_MIN_VALUE << (ha->func_num * 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3462) qla4_83xx_wr_reg(ha, QLA83XX_CRB_IDC_VER_MINOR, idc_ver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3464) exit_set_idc_ver:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3465) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3466) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3468) int qla4_8xxx_update_idc_reg(struct scsi_qla_host *ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3469) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3470) uint32_t drv_active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3471) int rval = QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3473) if (test_bit(AF_INIT_DONE, &ha->flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3474) goto exit_update_idc_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3476) ha->isp_ops->idc_lock(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3477) qla4_8xxx_set_drv_active(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3479) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3480) * If we are the first driver to load and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3481) * ql4xdontresethba is not set, clear IDC_CTRL BIT0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3482) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3483) if (is_qla8032(ha) || is_qla8042(ha)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3484) drv_active = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_ACTIVE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3485) if ((drv_active == (1 << ha->func_num)) && !ql4xdontresethba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3486) qla4_83xx_clear_idc_dontreset(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3487) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3489) if (is_qla8022(ha)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3490) qla4_82xx_set_idc_ver(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3491) } else if (is_qla8032(ha) || is_qla8042(ha)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3492) rval = qla4_83xx_set_idc_ver(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3493) if (rval == QLA_ERROR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3494) qla4_8xxx_clear_drv_active(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3495) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3497) ha->isp_ops->idc_unlock(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3499) exit_update_idc_reg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3500) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3501) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3503) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3504) * qla4_8xxx_device_state_handler - Adapter state machine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3505) * @ha: pointer to host adapter structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3506) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3507) * Note: IDC lock must be UNLOCKED upon entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3508) **/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3509) int qla4_8xxx_device_state_handler(struct scsi_qla_host *ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3510) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3511) uint32_t dev_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3512) int rval = QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3513) unsigned long dev_init_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3515) rval = qla4_8xxx_update_idc_reg(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3516) if (rval == QLA_ERROR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3517) goto exit_state_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3519) dev_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DEV_STATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3520) DEBUG2(ql4_printk(KERN_INFO, ha, "Device state is 0x%x = %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3521) dev_state, dev_state < MAX_STATES ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3522) qdev_state[dev_state] : "Unknown"));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3524) /* wait for 30 seconds for device to go ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3525) dev_init_timeout = jiffies + (ha->nx_dev_init_timeout * HZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3527) ha->isp_ops->idc_lock(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3528) while (1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3530) if (time_after_eq(jiffies, dev_init_timeout)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3531) ql4_printk(KERN_WARNING, ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3532) "%s: Device Init Failed 0x%x = %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3533) DRIVER_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3534) dev_state, dev_state < MAX_STATES ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3535) qdev_state[dev_state] : "Unknown");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3536) qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DEV_STATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3537) QLA8XXX_DEV_FAILED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3538) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3540) dev_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DEV_STATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3541) ql4_printk(KERN_INFO, ha, "Device state is 0x%x = %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3542) dev_state, dev_state < MAX_STATES ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3543) qdev_state[dev_state] : "Unknown");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3545) /* NOTE: Make sure idc unlocked upon exit of switch statement */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3546) switch (dev_state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3547) case QLA8XXX_DEV_READY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3548) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3549) case QLA8XXX_DEV_COLD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3550) rval = qla4_8xxx_device_bootstrap(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3551) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3552) case QLA8XXX_DEV_INITIALIZING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3553) ha->isp_ops->idc_unlock(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3554) msleep(1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3555) ha->isp_ops->idc_lock(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3556) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3557) case QLA8XXX_DEV_NEED_RESET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3558) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3559) * For ISP8324 and ISP8042, if NEED_RESET is set by any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3560) * driver, it should be honored, irrespective of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3561) * IDC_CTRL DONTRESET_BIT0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3562) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3563) if (is_qla8032(ha) || is_qla8042(ha)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3564) qla4_83xx_need_reset_handler(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3565) } else if (is_qla8022(ha)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3566) if (!ql4xdontresethba) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3567) qla4_82xx_need_reset_handler(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3568) /* Update timeout value after need
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3569) * reset handler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3570) dev_init_timeout = jiffies +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3571) (ha->nx_dev_init_timeout * HZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3572) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3573) ha->isp_ops->idc_unlock(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3574) msleep(1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3575) ha->isp_ops->idc_lock(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3576) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3577) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3578) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3579) case QLA8XXX_DEV_NEED_QUIESCENT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3580) /* idc locked/unlocked in handler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3581) qla4_8xxx_need_qsnt_handler(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3582) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3583) case QLA8XXX_DEV_QUIESCENT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3584) ha->isp_ops->idc_unlock(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3585) msleep(1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3586) ha->isp_ops->idc_lock(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3587) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3588) case QLA8XXX_DEV_FAILED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3589) ha->isp_ops->idc_unlock(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3590) qla4xxx_dead_adapter_cleanup(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3591) rval = QLA_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3592) ha->isp_ops->idc_lock(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3593) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3594) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3595) ha->isp_ops->idc_unlock(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3596) qla4xxx_dead_adapter_cleanup(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3597) rval = QLA_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3598) ha->isp_ops->idc_lock(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3599) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3600) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3601) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3602) exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3603) ha->isp_ops->idc_unlock(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3604) exit_state_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3605) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3606) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3608) int qla4_8xxx_load_risc(struct scsi_qla_host *ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3609) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3610) int retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3612) /* clear the interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3613) if (is_qla8032(ha) || is_qla8042(ha)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3614) writel(0, &ha->qla4_83xx_reg->risc_intr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3615) readl(&ha->qla4_83xx_reg->risc_intr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3616) } else if (is_qla8022(ha)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3617) writel(0, &ha->qla4_82xx_reg->host_int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3618) readl(&ha->qla4_82xx_reg->host_int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3619) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3621) retval = qla4_8xxx_device_state_handler(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3623) /* Initialize request and response queues. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3624) if (retval == QLA_SUCCESS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3625) qla4xxx_init_rings(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3627) if (retval == QLA_SUCCESS && !test_bit(AF_IRQ_ATTACHED, &ha->flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3628) retval = qla4xxx_request_irqs(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3630) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3631) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3633) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3634) /* Flash Manipulation Routines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3635) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3637) #define OPTROM_BURST_SIZE 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3638) #define OPTROM_BURST_DWORDS (OPTROM_BURST_SIZE / 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3640) #define FARX_DATA_FLAG BIT_31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3641) #define FARX_ACCESS_FLASH_CONF 0x7FFD0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3642) #define FARX_ACCESS_FLASH_DATA 0x7FF00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3644) static inline uint32_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3645) flash_conf_addr(struct ql82xx_hw_data *hw, uint32_t faddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3646) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3647) return hw->flash_conf_off | faddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3648) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3650) static inline uint32_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3651) flash_data_addr(struct ql82xx_hw_data *hw, uint32_t faddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3652) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3653) return hw->flash_data_off | faddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3654) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3656) static uint32_t *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3657) qla4_82xx_read_flash_data(struct scsi_qla_host *ha, uint32_t *dwptr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3658) uint32_t faddr, uint32_t length)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3659) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3660) uint32_t i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3661) uint32_t val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3662) int loops = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3663) while ((qla4_82xx_rom_lock(ha) != 0) && (loops < 50000)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3664) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3665) cond_resched();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3666) loops++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3667) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3668) if (loops >= 50000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3669) ql4_printk(KERN_WARNING, ha, "ROM lock failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3670) return dwptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3671) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3673) /* Dword reads to flash. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3674) for (i = 0; i < length/4; i++, faddr += 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3675) if (qla4_82xx_do_rom_fast_read(ha, faddr, &val)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3676) ql4_printk(KERN_WARNING, ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3677) "Do ROM fast read failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3678) goto done_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3679) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3680) dwptr[i] = __constant_cpu_to_le32(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3681) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3683) done_read:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3684) qla4_82xx_rom_unlock(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3685) return dwptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3686) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3688) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3689) * Address and length are byte address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3690) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3691) static uint8_t *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3692) qla4_82xx_read_optrom_data(struct scsi_qla_host *ha, uint8_t *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3693) uint32_t offset, uint32_t length)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3694) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3695) qla4_82xx_read_flash_data(ha, (uint32_t *)buf, offset, length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3696) return buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3697) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3699) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3700) qla4_8xxx_find_flt_start(struct scsi_qla_host *ha, uint32_t *start)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3701) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3702) const char *loc, *locations[] = { "DEF", "PCI" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3704) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3705) * FLT-location structure resides after the last PCI region.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3706) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3708) /* Begin with sane defaults. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3709) loc = locations[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3710) *start = FA_FLASH_LAYOUT_ADDR_82;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3712) DEBUG2(ql4_printk(KERN_INFO, ha, "FLTL[%s] = 0x%x.\n", loc, *start));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3713) return QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3714) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3716) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3717) qla4_8xxx_get_flt_info(struct scsi_qla_host *ha, uint32_t flt_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3718) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3719) const char *loc, *locations[] = { "DEF", "FLT" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3720) uint16_t *wptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3721) uint16_t cnt, chksum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3722) uint32_t start, status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3723) struct qla_flt_header *flt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3724) struct qla_flt_region *region;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3725) struct ql82xx_hw_data *hw = &ha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3727) hw->flt_region_flt = flt_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3728) wptr = (uint16_t *)ha->request_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3729) flt = (struct qla_flt_header *)ha->request_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3730) region = (struct qla_flt_region *)&flt[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3732) if (is_qla8022(ha)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3733) qla4_82xx_read_optrom_data(ha, (uint8_t *)ha->request_ring,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3734) flt_addr << 2, OPTROM_BURST_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3735) } else if (is_qla8032(ha) || is_qla8042(ha)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3736) status = qla4_83xx_flash_read_u32(ha, flt_addr << 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3737) (uint8_t *)ha->request_ring,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3738) 0x400);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3739) if (status != QLA_SUCCESS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3740) goto no_flash_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3741) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3743) if (*wptr == __constant_cpu_to_le16(0xffff))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3744) goto no_flash_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3745) if (flt->version != __constant_cpu_to_le16(1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3746) DEBUG2(ql4_printk(KERN_INFO, ha, "Unsupported FLT detected: "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3747) "version=0x%x length=0x%x checksum=0x%x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3748) le16_to_cpu(flt->version), le16_to_cpu(flt->length),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3749) le16_to_cpu(flt->checksum)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3750) goto no_flash_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3751) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3753) cnt = (sizeof(struct qla_flt_header) + le16_to_cpu(flt->length)) >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3754) for (chksum = 0; cnt; cnt--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3755) chksum += le16_to_cpu(*wptr++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3756) if (chksum) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3757) DEBUG2(ql4_printk(KERN_INFO, ha, "Inconsistent FLT detected: "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3758) "version=0x%x length=0x%x checksum=0x%x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3759) le16_to_cpu(flt->version), le16_to_cpu(flt->length),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3760) chksum));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3761) goto no_flash_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3762) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3764) loc = locations[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3765) cnt = le16_to_cpu(flt->length) / sizeof(struct qla_flt_region);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3766) for ( ; cnt; cnt--, region++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3767) /* Store addresses as DWORD offsets. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3768) start = le32_to_cpu(region->start) >> 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3770) DEBUG3(ql4_printk(KERN_DEBUG, ha, "FLT[%02x]: start=0x%x "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3771) "end=0x%x size=0x%x.\n", le32_to_cpu(region->code), start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3772) le32_to_cpu(region->end) >> 2, le32_to_cpu(region->size)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3774) switch (le32_to_cpu(region->code) & 0xff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3775) case FLT_REG_FDT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3776) hw->flt_region_fdt = start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3777) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3778) case FLT_REG_BOOT_CODE_82:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3779) hw->flt_region_boot = start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3780) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3781) case FLT_REG_FW_82:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3782) case FLT_REG_FW_82_1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3783) hw->flt_region_fw = start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3784) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3785) case FLT_REG_BOOTLOAD_82:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3786) hw->flt_region_bootload = start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3787) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3788) case FLT_REG_ISCSI_PARAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3789) hw->flt_iscsi_param = start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3790) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3791) case FLT_REG_ISCSI_CHAP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3792) hw->flt_region_chap = start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3793) hw->flt_chap_size = le32_to_cpu(region->size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3794) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3795) case FLT_REG_ISCSI_DDB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3796) hw->flt_region_ddb = start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3797) hw->flt_ddb_size = le32_to_cpu(region->size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3798) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3799) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3800) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3801) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3803) no_flash_data:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3804) /* Use hardcoded defaults. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3805) loc = locations[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3807) hw->flt_region_fdt = FA_FLASH_DESCR_ADDR_82;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3808) hw->flt_region_boot = FA_BOOT_CODE_ADDR_82;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3809) hw->flt_region_bootload = FA_BOOT_LOAD_ADDR_82;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3810) hw->flt_region_fw = FA_RISC_CODE_ADDR_82;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3811) hw->flt_region_chap = FA_FLASH_ISCSI_CHAP >> 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3812) hw->flt_chap_size = FA_FLASH_CHAP_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3813) hw->flt_region_ddb = FA_FLASH_ISCSI_DDB >> 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3814) hw->flt_ddb_size = FA_FLASH_DDB_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3816) done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3817) DEBUG2(ql4_printk(KERN_INFO, ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3818) "FLT[%s]: flt=0x%x fdt=0x%x boot=0x%x bootload=0x%x fw=0x%x chap=0x%x chap_size=0x%x ddb=0x%x ddb_size=0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3819) loc, hw->flt_region_flt, hw->flt_region_fdt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3820) hw->flt_region_boot, hw->flt_region_bootload,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3821) hw->flt_region_fw, hw->flt_region_chap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3822) hw->flt_chap_size, hw->flt_region_ddb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3823) hw->flt_ddb_size));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3824) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3826) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3827) qla4_82xx_get_fdt_info(struct scsi_qla_host *ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3828) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3829) #define FLASH_BLK_SIZE_4K 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3830) #define FLASH_BLK_SIZE_32K 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3831) #define FLASH_BLK_SIZE_64K 0x10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3832) const char *loc, *locations[] = { "MID", "FDT" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3833) uint16_t cnt, chksum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3834) uint16_t *wptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3835) struct qla_fdt_layout *fdt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3836) uint16_t mid = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3837) uint16_t fid = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3838) struct ql82xx_hw_data *hw = &ha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3840) hw->flash_conf_off = FARX_ACCESS_FLASH_CONF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3841) hw->flash_data_off = FARX_ACCESS_FLASH_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3843) wptr = (uint16_t *)ha->request_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3844) fdt = (struct qla_fdt_layout *)ha->request_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3845) qla4_82xx_read_optrom_data(ha, (uint8_t *)ha->request_ring,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3846) hw->flt_region_fdt << 2, OPTROM_BURST_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3848) if (*wptr == __constant_cpu_to_le16(0xffff))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3849) goto no_flash_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3851) if (fdt->sig[0] != 'Q' || fdt->sig[1] != 'L' || fdt->sig[2] != 'I' ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3852) fdt->sig[3] != 'D')
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3853) goto no_flash_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3855) for (cnt = 0, chksum = 0; cnt < sizeof(struct qla_fdt_layout) >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3856) cnt++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3857) chksum += le16_to_cpu(*wptr++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3859) if (chksum) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3860) DEBUG2(ql4_printk(KERN_INFO, ha, "Inconsistent FDT detected: "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3861) "checksum=0x%x id=%c version=0x%x.\n", chksum, fdt->sig[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3862) le16_to_cpu(fdt->version)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3863) goto no_flash_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3864) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3866) loc = locations[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3867) mid = le16_to_cpu(fdt->man_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3868) fid = le16_to_cpu(fdt->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3869) hw->fdt_wrt_disable = fdt->wrt_disable_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3870) hw->fdt_erase_cmd = flash_conf_addr(hw, 0x0300 | fdt->erase_cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3871) hw->fdt_block_size = le32_to_cpu(fdt->block_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3873) if (fdt->unprotect_sec_cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3874) hw->fdt_unprotect_sec_cmd = flash_conf_addr(hw, 0x0300 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3875) fdt->unprotect_sec_cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3876) hw->fdt_protect_sec_cmd = fdt->protect_sec_cmd ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3877) flash_conf_addr(hw, 0x0300 | fdt->protect_sec_cmd) :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3878) flash_conf_addr(hw, 0x0336);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3879) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3880) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3882) no_flash_data:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3883) loc = locations[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3884) hw->fdt_block_size = FLASH_BLK_SIZE_64K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3885) done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3886) DEBUG2(ql4_printk(KERN_INFO, ha, "FDT[%s]: (0x%x/0x%x) erase=0x%x "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3887) "pro=%x upro=%x wrtd=0x%x blk=0x%x.\n", loc, mid, fid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3888) hw->fdt_erase_cmd, hw->fdt_protect_sec_cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3889) hw->fdt_unprotect_sec_cmd, hw->fdt_wrt_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3890) hw->fdt_block_size));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3891) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3893) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3894) qla4_82xx_get_idc_param(struct scsi_qla_host *ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3895) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3896) #define QLA82XX_IDC_PARAM_ADDR 0x003e885c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3897) uint32_t *wptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3899) if (!is_qla8022(ha))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3900) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3901) wptr = (uint32_t *)ha->request_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3902) qla4_82xx_read_optrom_data(ha, (uint8_t *)ha->request_ring,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3903) QLA82XX_IDC_PARAM_ADDR , 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3905) if (*wptr == __constant_cpu_to_le32(0xffffffff)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3906) ha->nx_dev_init_timeout = ROM_DEV_INIT_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3907) ha->nx_reset_timeout = ROM_DRV_RESET_ACK_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3908) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3909) ha->nx_dev_init_timeout = le32_to_cpu(*wptr++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3910) ha->nx_reset_timeout = le32_to_cpu(*wptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3911) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3913) DEBUG2(ql4_printk(KERN_DEBUG, ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3914) "ha->nx_dev_init_timeout = %d\n", ha->nx_dev_init_timeout));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3915) DEBUG2(ql4_printk(KERN_DEBUG, ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3916) "ha->nx_reset_timeout = %d\n", ha->nx_reset_timeout));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3917) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3918) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3920) void qla4_82xx_queue_mbox_cmd(struct scsi_qla_host *ha, uint32_t *mbx_cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3921) int in_count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3922) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3923) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3925) /* Load all mailbox registers, except mailbox 0. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3926) for (i = 1; i < in_count; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3927) writel(mbx_cmd[i], &ha->qla4_82xx_reg->mailbox_in[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3929) /* Wakeup firmware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3930) writel(mbx_cmd[0], &ha->qla4_82xx_reg->mailbox_in[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3931) readl(&ha->qla4_82xx_reg->mailbox_in[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3932) writel(HINT_MBX_INT_PENDING, &ha->qla4_82xx_reg->hint);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3933) readl(&ha->qla4_82xx_reg->hint);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3934) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3936) void qla4_82xx_process_mbox_intr(struct scsi_qla_host *ha, int out_count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3937) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3938) int intr_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3940) intr_status = readl(&ha->qla4_82xx_reg->host_int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3941) if (intr_status & ISRX_82XX_RISC_INT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3942) ha->mbox_status_count = out_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3943) intr_status = readl(&ha->qla4_82xx_reg->host_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3944) ha->isp_ops->interrupt_service_routine(ha, intr_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3946) if (test_bit(AF_INTERRUPTS_ON, &ha->flags) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3947) (!ha->pdev->msi_enabled && !ha->pdev->msix_enabled))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3948) qla4_82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3949) 0xfbff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3950) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3951) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3953) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3954) qla4_8xxx_get_flash_info(struct scsi_qla_host *ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3955) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3956) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3957) uint32_t flt_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3959) ret = qla4_8xxx_find_flt_start(ha, &flt_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3960) if (ret != QLA_SUCCESS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3961) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3963) qla4_8xxx_get_flt_info(ha, flt_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3964) if (is_qla8022(ha)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3965) qla4_82xx_get_fdt_info(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3966) qla4_82xx_get_idc_param(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3967) } else if (is_qla8032(ha) || is_qla8042(ha)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3968) qla4_83xx_get_idc_param(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3969) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3971) return QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3972) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3974) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3975) * qla4_8xxx_stop_firmware - stops firmware on specified adapter instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3976) * @ha: pointer to host adapter structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3977) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3978) * Remarks:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3979) * For iSCSI, throws away all I/O and AENs into bit bucket, so they will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3980) * not be available after successful return. Driver must cleanup potential
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3981) * outstanding I/O's after calling this funcion.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3982) **/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3983) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3984) qla4_8xxx_stop_firmware(struct scsi_qla_host *ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3985) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3986) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3987) uint32_t mbox_cmd[MBOX_REG_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3988) uint32_t mbox_sts[MBOX_REG_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3990) memset(&mbox_cmd, 0, sizeof(mbox_cmd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3991) memset(&mbox_sts, 0, sizeof(mbox_sts));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3993) mbox_cmd[0] = MBOX_CMD_STOP_FW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3994) status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3995) &mbox_cmd[0], &mbox_sts[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3997) DEBUG2(printk("scsi%ld: %s: status = %d\n", ha->host_no,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3998) __func__, status));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3999) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4000) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4002) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4003) * qla4_82xx_isp_reset - Resets ISP and aborts all outstanding commands.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4004) * @ha: pointer to host adapter structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4005) **/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4006) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4007) qla4_82xx_isp_reset(struct scsi_qla_host *ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4008) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4009) int rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4010) uint32_t dev_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4012) qla4_82xx_idc_lock(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4013) dev_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4015) if (dev_state == QLA8XXX_DEV_READY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4016) ql4_printk(KERN_INFO, ha, "HW State: NEED RESET\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4017) qla4_82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4018) QLA8XXX_DEV_NEED_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4019) set_bit(AF_8XXX_RST_OWNER, &ha->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4020) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4021) ql4_printk(KERN_INFO, ha, "HW State: DEVICE INITIALIZING\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4023) qla4_82xx_idc_unlock(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4025) rval = qla4_8xxx_device_state_handler(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4027) qla4_82xx_idc_lock(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4028) qla4_8xxx_clear_rst_ready(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4029) qla4_82xx_idc_unlock(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4031) if (rval == QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4032) ql4_printk(KERN_INFO, ha, "Clearing AF_RECOVERY in qla4_82xx_isp_reset\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4033) clear_bit(AF_FW_RECOVERY, &ha->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4034) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4036) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4037) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4039) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4040) * qla4_8xxx_get_sys_info - get adapter MAC address(es) and serial number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4041) * @ha: pointer to host adapter structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4042) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4043) **/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4044) int qla4_8xxx_get_sys_info(struct scsi_qla_host *ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4045) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4046) uint32_t mbox_cmd[MBOX_REG_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4047) uint32_t mbox_sts[MBOX_REG_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4048) struct mbx_sys_info *sys_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4049) dma_addr_t sys_info_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4050) int status = QLA_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4052) sys_info = dma_alloc_coherent(&ha->pdev->dev, sizeof(*sys_info),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4053) &sys_info_dma, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4054) if (sys_info == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4055) DEBUG2(printk("scsi%ld: %s: Unable to allocate dma buffer.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4056) ha->host_no, __func__));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4057) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4058) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4060) memset(&mbox_cmd, 0, sizeof(mbox_cmd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4061) memset(&mbox_sts, 0, sizeof(mbox_sts));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4063) mbox_cmd[0] = MBOX_CMD_GET_SYS_INFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4064) mbox_cmd[1] = LSDW(sys_info_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4065) mbox_cmd[2] = MSDW(sys_info_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4066) mbox_cmd[4] = sizeof(*sys_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4068) if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 6, &mbox_cmd[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4069) &mbox_sts[0]) != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4070) DEBUG2(printk("scsi%ld: %s: GET_SYS_INFO failed\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4071) ha->host_no, __func__));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4072) goto exit_validate_mac82;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4073) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4075) /* Make sure we receive the minimum required data to cache internally */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4076) if (((is_qla8032(ha) || is_qla8042(ha)) ? mbox_sts[3] : mbox_sts[4]) <
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4077) offsetof(struct mbx_sys_info, reserved)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4078) DEBUG2(printk("scsi%ld: %s: GET_SYS_INFO data receive"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4079) " error (%x)\n", ha->host_no, __func__, mbox_sts[4]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4080) goto exit_validate_mac82;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4081) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4083) /* Save M.A.C. address & serial_number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4084) ha->port_num = sys_info->port_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4085) memcpy(ha->my_mac, &sys_info->mac_addr[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4086) min(sizeof(ha->my_mac), sizeof(sys_info->mac_addr)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4087) memcpy(ha->serial_number, &sys_info->serial_number,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4088) min(sizeof(ha->serial_number), sizeof(sys_info->serial_number)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4089) memcpy(ha->model_name, &sys_info->board_id_str,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4090) min(sizeof(ha->model_name), sizeof(sys_info->board_id_str)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4091) ha->phy_port_cnt = sys_info->phys_port_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4092) ha->phy_port_num = sys_info->port_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4093) ha->iscsi_pci_func_cnt = sys_info->iscsi_pci_func_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4095) DEBUG2(printk("scsi%ld: %s: mac %pM serial %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4096) ha->host_no, __func__, ha->my_mac, ha->serial_number));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4098) status = QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4100) exit_validate_mac82:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4101) dma_free_coherent(&ha->pdev->dev, sizeof(*sys_info), sys_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4102) sys_info_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4103) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4106) /* Interrupt handling helpers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4108) int qla4_8xxx_intr_enable(struct scsi_qla_host *ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4110) uint32_t mbox_cmd[MBOX_REG_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4111) uint32_t mbox_sts[MBOX_REG_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4113) DEBUG2(ql4_printk(KERN_INFO, ha, "%s\n", __func__));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4115) memset(&mbox_cmd, 0, sizeof(mbox_cmd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4116) memset(&mbox_sts, 0, sizeof(mbox_sts));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4117) mbox_cmd[0] = MBOX_CMD_ENABLE_INTRS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4118) mbox_cmd[1] = INTR_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4119) if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4120) &mbox_sts[0]) != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4121) DEBUG2(ql4_printk(KERN_INFO, ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4122) "%s: MBOX_CMD_ENABLE_INTRS failed (0x%04x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4123) __func__, mbox_sts[0]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4124) return QLA_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4126) return QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4129) int qla4_8xxx_intr_disable(struct scsi_qla_host *ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4130) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4131) uint32_t mbox_cmd[MBOX_REG_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4132) uint32_t mbox_sts[MBOX_REG_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4134) DEBUG2(ql4_printk(KERN_INFO, ha, "%s\n", __func__));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4136) memset(&mbox_cmd, 0, sizeof(mbox_cmd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4137) memset(&mbox_sts, 0, sizeof(mbox_sts));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4138) mbox_cmd[0] = MBOX_CMD_ENABLE_INTRS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4139) mbox_cmd[1] = INTR_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4140) if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4141) &mbox_sts[0]) != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4142) DEBUG2(ql4_printk(KERN_INFO, ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4143) "%s: MBOX_CMD_ENABLE_INTRS failed (0x%04x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4144) __func__, mbox_sts[0]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4145) return QLA_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4148) return QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4151) void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4152) qla4_82xx_enable_intrs(struct scsi_qla_host *ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4153) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4154) qla4_8xxx_intr_enable(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4156) spin_lock_irq(&ha->hardware_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4157) /* BIT 10 - reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4158) qla4_82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4159) spin_unlock_irq(&ha->hardware_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4160) set_bit(AF_INTERRUPTS_ON, &ha->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4163) void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4164) qla4_82xx_disable_intrs(struct scsi_qla_host *ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4165) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4166) if (test_and_clear_bit(AF_INTERRUPTS_ON, &ha->flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4167) qla4_8xxx_intr_disable(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4169) spin_lock_irq(&ha->hardware_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4170) /* BIT 10 - set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4171) qla4_82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0x0400);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4172) spin_unlock_irq(&ha->hardware_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4175) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4176) qla4_8xxx_enable_msix(struct scsi_qla_host *ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4177) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4178) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4180) ret = pci_alloc_irq_vectors(ha->pdev, QLA_MSIX_ENTRIES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4181) QLA_MSIX_ENTRIES, PCI_IRQ_MSIX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4182) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4183) ql4_printk(KERN_WARNING, ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4184) "MSI-X: Failed to enable support -- %d/%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4185) QLA_MSIX_ENTRIES, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4186) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4189) ret = request_irq(pci_irq_vector(ha->pdev, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4190) qla4_8xxx_default_intr_handler, 0, "qla4xxx (default)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4191) ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4192) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4193) goto out_free_vectors;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4195) ret = request_irq(pci_irq_vector(ha->pdev, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4196) qla4_8xxx_msix_rsp_q, 0, "qla4xxx (rsp_q)", ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4197) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4198) goto out_free_default_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4200) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4202) out_free_default_irq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4203) free_irq(pci_irq_vector(ha->pdev, 0), ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4204) out_free_vectors:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4205) pci_free_irq_vectors(ha->pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4206) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4209) int qla4_8xxx_check_init_adapter_retry(struct scsi_qla_host *ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4210) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4211) int status = QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4213) /* Dont retry adapter initialization if IRQ allocation failed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4214) if (!test_bit(AF_IRQ_ATTACHED, &ha->flags)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4215) ql4_printk(KERN_WARNING, ha, "%s: Skipping retry of adapter initialization as IRQs are not attached\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4216) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4217) status = QLA_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4218) goto exit_init_adapter_failure;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4221) /* Since interrupts are registered in start_firmware for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4222) * 8xxx, release them here if initialize_adapter fails
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4223) * and retry adapter initialization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4224) qla4xxx_free_irqs(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4226) exit_init_adapter_failure:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4227) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4228) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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