Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * QLogic iSCSI HBA Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Copyright (c)  2003-2013 QLogic Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #ifndef _QL4XNVRM_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #define _QL4XNVRM_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  * AM29LV Flash definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  **/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #define FM93C56A_SIZE_8	 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #define FM93C56A_SIZE_16 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define FM93C66A_SIZE_8	 0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define FM93C66A_SIZE_16 0x100/* 4010 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define FM93C86A_SIZE_16 0x400/* 4022 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define	 FM93C56A_START	      0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) /* Commands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define	 FM93C56A_READ	      0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define	 FM93C56A_WEN	      0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define	 FM93C56A_WRITE	      0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define	 FM93C56A_WRITE_ALL   0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define	 FM93C56A_WDS	      0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define	 FM93C56A_ERASE	      0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define	 FM93C56A_ERASE_ALL   0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) /* Command Extensions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define	 FM93C56A_WEN_EXT	 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define	 FM93C56A_WRITE_ALL_EXT	 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define	 FM93C56A_WDS_EXT	 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define	 FM93C56A_ERASE_ALL_EXT	 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) /* Address Bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define	 FM93C56A_NO_ADDR_BITS_16   8	/* 4010 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define	 FM93C56A_NO_ADDR_BITS_8    9	/* 4010 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define	 FM93C86A_NO_ADDR_BITS_16   10	/* 4022 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) /* Data Bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define	 FM93C56A_DATA_BITS_16	 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define	 FM93C56A_DATA_BITS_8	 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) /* Special Bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define	 FM93C56A_READ_DUMMY_BITS   1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define	 FM93C56A_READY		    0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define	 FM93C56A_BUSY		    1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define	 FM93C56A_CMD_BITS	    2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) /* Auburn Bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define	 AUBURN_EEPROM_DI	    0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define	 AUBURN_EEPROM_DI_0	    0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define	 AUBURN_EEPROM_DI_1	    0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define	 AUBURN_EEPROM_DO	    0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define	 AUBURN_EEPROM_DO_0	    0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define	 AUBURN_EEPROM_DO_1	    0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define	 AUBURN_EEPROM_CS	    0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define	 AUBURN_EEPROM_CS_0	    0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define	 AUBURN_EEPROM_CS_1	    0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define	 AUBURN_EEPROM_CLK_RISE	    0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define	 AUBURN_EEPROM_CLK_FALL	    0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) /**/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) /* EEPROM format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) /**/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) struct bios_params {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	uint16_t SpinUpDelay:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	uint16_t BIOSDisable:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	uint16_t MMAPEnable:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	uint16_t BootEnable:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	uint16_t Reserved0:12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	uint8_t bootID0:7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	uint8_t bootID0Valid:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	uint8_t bootLUN0[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	uint8_t bootID1:7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	uint8_t bootID1Valid:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	uint8_t bootLUN1[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	uint16_t MaxLunsPerTarget;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	uint8_t Reserved1[10];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) struct eeprom_port_cfg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	/* MTU MAC 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	u16 etherMtu_mac;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	/* Flow Control MAC 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	u16 pauseThreshold_mac;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	u16 resumeThreshold_mac;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	u16 reserved[13];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) struct eeprom_function_cfg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	u8 reserved[30];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	/* MAC ADDR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	u8 macAddress[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	u8 macAddressSecondary[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	u16 subsysVendorId;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	u16 subsysDeviceId;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) struct eeprom_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 		struct {	/* isp4010 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 			u8 asic_id[4]; /* x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 			u8 version;	/* x04 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 			u8 reserved;	/* x05 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 			u16 board_id;	/* x06 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define	  EEPROM_BOARDID_ELDORADO    1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define	  EEPROM_BOARDID_PLACER	     2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define EEPROM_SERIAL_NUM_SIZE	     16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 			u8 serial_number[EEPROM_SERIAL_NUM_SIZE]; /* x08 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 			/* ExtHwConfig: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 			/* Offset = 24bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 			 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 			 * | SSRAM Size|     |ST|PD|SDRAM SZ| W| B| SP	|  |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 			 * |15|14|13|12|11|10| 9| 8| 7| 6| 5| 4| 3| 2| 1| 0|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 			 * +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 			 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 			u16 ext_hw_conf; /* x18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 			u8 mac0[6];	/* x1A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 			u8 mac1[6];	/* x20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 			u8 mac2[6];	/* x26 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 			u8 mac3[6];	/* x2C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 			u16 etherMtu;	/* x32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 			u16 macConfig;	/* x34 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define	 MAC_CONFIG_ENABLE_ANEG	    0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define	 MAC_CONFIG_ENABLE_PAUSE    0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 			u16 phyConfig;	/* x36 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define	 PHY_CONFIG_PHY_ADDR_MASK	      0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define	 PHY_CONFIG_ENABLE_FW_MANAGEMENT_MASK 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 			u16 reserved_56;	/* x38 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define EEPROM_UNUSED_1_SIZE   2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 			u8 unused_1[EEPROM_UNUSED_1_SIZE]; /* x3A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 			u16 bufletSize;	/* x3C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 			u16 bufletCount;	/* x3E */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 			u16 bufletPauseThreshold; /* x40 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 			u16 tcpWindowThreshold50; /* x42 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 			u16 tcpWindowThreshold25; /* x44 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 			u16 tcpWindowThreshold0; /* x46 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 			u16 ipHashTableBaseHi;	/* x48 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 			u16 ipHashTableBaseLo;	/* x4A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 			u16 ipHashTableSize;	/* x4C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 			u16 tcpHashTableBaseHi;	/* x4E */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 			u16 tcpHashTableBaseLo;	/* x50 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 			u16 tcpHashTableSize;	/* x52 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 			u16 ncbTableBaseHi;	/* x54 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 			u16 ncbTableBaseLo;	/* x56 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 			u16 ncbTableSize;	/* x58 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 			u16 drbTableBaseHi;	/* x5A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 			u16 drbTableBaseLo;	/* x5C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 			u16 drbTableSize;	/* x5E */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define EEPROM_UNUSED_2_SIZE   4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 			u8 unused_2[EEPROM_UNUSED_2_SIZE]; /* x60 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 			u16 ipReassemblyTimeout; /* x64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 			u16 tcpMaxWindowSizeHi;	/* x66 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 			u16 tcpMaxWindowSizeLo;	/* x68 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 			u32 net_ip_addr0;	/* x6A Added for TOE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 						 * functionality. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 			u32 net_ip_addr1;	/* x6E */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 			u32 scsi_ip_addr0;	/* x72 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 			u32 scsi_ip_addr1;	/* x76 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define EEPROM_UNUSED_3_SIZE   128	/* changed from 144 to account
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 					 * for ip addresses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 			u8 unused_3[EEPROM_UNUSED_3_SIZE]; /* x7A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 			u16 subsysVendorId_f0;	/* xFA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 			u16 subsysDeviceId_f0;	/* xFC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 			/* Address = 0x7F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define FM93C56A_SIGNATURE  0x9356
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define FM93C66A_SIGNATURE  0x9366
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 			u16 signature;	/* xFE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define EEPROM_UNUSED_4_SIZE   250
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 			u8 unused_4[EEPROM_UNUSED_4_SIZE]; /* x100 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 			u16 subsysVendorId_f1;	/* x1FA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 			u16 subsysDeviceId_f1;	/* x1FC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 			u16 checksum;	/* x1FE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 		} __attribute__ ((packed)) isp4010;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		struct {	/* isp4022 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 			u8 asicId[4];	/* x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 			u8 version;	/* x04 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 			u8 reserved_5;	/* x05 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 			u16 boardId;	/* x06 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 			u8 boardIdStr[16];	/* x08 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 			u8 serialNumber[16];	/* x18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 			/* External Hardware Configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 			u16 ext_hw_conf;	/* x28 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 			/* MAC 0 CONFIGURATION */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 			struct eeprom_port_cfg macCfg_port0; /* x2A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 			/* MAC 1 CONFIGURATION */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 			struct eeprom_port_cfg macCfg_port1; /* x4A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 			/* DDR SDRAM Configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 			u16 bufletSize;	/* x6A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 			u16 bufletCount;	/* x6C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 			u16 tcpWindowThreshold50; /* x6E */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 			u16 tcpWindowThreshold25; /* x70 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 			u16 tcpWindowThreshold0; /* x72 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 			u16 ipHashTableBaseHi;	/* x74 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 			u16 ipHashTableBaseLo;	/* x76 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 			u16 ipHashTableSize;	/* x78 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 			u16 tcpHashTableBaseHi;	/* x7A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 			u16 tcpHashTableBaseLo;	/* x7C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 			u16 tcpHashTableSize;	/* x7E */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 			u16 ncbTableBaseHi;	/* x80 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 			u16 ncbTableBaseLo;	/* x82 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 			u16 ncbTableSize;	/* x84 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 			u16 drbTableBaseHi;	/* x86 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 			u16 drbTableBaseLo;	/* x88 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 			u16 drbTableSize;	/* x8A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 			u16 reserved_142[4];	/* x8C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 			/* TCP/IP Parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 			u16 ipReassemblyTimeout; /* x94 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 			u16 tcpMaxWindowSize;	/* x96 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 			u16 ipSecurity;	/* x98 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 			u8 reserved_156[294]; /* x9A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 			u16 qDebug[8];	/* QLOGIC USE ONLY   x1C0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 			struct eeprom_function_cfg funcCfg_fn0;	/* x1D0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 			u16 reserved_510; /* x1FE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 			/* Address = 512 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 			u8 oemSpace[432]; /* x200 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 			struct bios_params sBIOSParams_fn1; /* x3B0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 			struct eeprom_function_cfg funcCfg_fn1;	/* x3D0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 			u16 reserved_1022; /* x3FE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 			/* Address = 1024 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 			u8 reserved_1024[464];	/* x400 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 			struct eeprom_function_cfg funcCfg_fn2;	/* x5D0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 			u16 reserved_1534; /* x5FE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 			/* Address = 1536 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 			u8 reserved_1536[432];	/* x600 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 			struct bios_params sBIOSParams_fn3; /* x7B0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 			struct eeprom_function_cfg funcCfg_fn3;	/* x7D0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 			u16 checksum;	/* x7FE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 		} __attribute__ ((packed)) isp4022;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #endif	/* _QL4XNVRM_H_ */