^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * QLogic iSCSI HBA Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (c) 2003-2013 QLogic Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/ctype.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include "ql4_def.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include "ql4_glbl.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include "ql4_dbg.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include "ql4_inline.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include "ql4_version.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) void qla4xxx_queue_mbox_cmd(struct scsi_qla_host *ha, uint32_t *mbx_cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) int in_count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) /* Load all mailbox registers, except mailbox 0. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) for (i = 1; i < in_count; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) writel(mbx_cmd[i], &ha->reg->mailbox[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /* Wakeup firmware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) writel(mbx_cmd[0], &ha->reg->mailbox[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) readl(&ha->reg->mailbox[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) writel(set_rmask(CSR_INTR_RISC), &ha->reg->ctrl_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) readl(&ha->reg->ctrl_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) void qla4xxx_process_mbox_intr(struct scsi_qla_host *ha, int out_count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) int intr_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) intr_status = readl(&ha->reg->ctrl_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) if (intr_status & INTR_PENDING) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * Service the interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * The ISR will save the mailbox status registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * to a temporary storage location in the adapter structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) ha->mbox_status_count = out_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) ha->isp_ops->interrupt_service_routine(ha, intr_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * qla4xxx_is_intr_poll_mode – Are we allowed to poll for interrupts?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * @ha: Pointer to host adapter structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * returns: 1=polling mode, 0=non-polling mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) **/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) static int qla4xxx_is_intr_poll_mode(struct scsi_qla_host *ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) int rval = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) if (is_qla8032(ha) || is_qla8042(ha)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) if (test_bit(AF_IRQ_ATTACHED, &ha->flags) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) test_bit(AF_83XX_MBOX_INTR_ON, &ha->flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) rval = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) if (test_bit(AF_IRQ_ATTACHED, &ha->flags) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) test_bit(AF_INTERRUPTS_ON, &ha->flags) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) test_bit(AF_ONLINE, &ha->flags) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) !test_bit(AF_HA_REMOVAL, &ha->flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) rval = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * qla4xxx_mailbox_command - issues mailbox commands
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * @ha: Pointer to host adapter structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * @inCount: number of mailbox registers to load.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * @outCount: number of mailbox registers to return.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * @mbx_cmd: data pointer for mailbox in registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * @mbx_sts: data pointer for mailbox out registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * This routine issue mailbox commands and waits for completion.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * If outCount is 0, this routine completes successfully WITHOUT waiting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * for the mailbox command to complete.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) **/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) int qla4xxx_mailbox_command(struct scsi_qla_host *ha, uint8_t inCount,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) uint8_t outCount, uint32_t *mbx_cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) uint32_t *mbx_sts)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) int status = QLA_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) uint8_t i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) u_long wait_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) unsigned long flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) uint32_t dev_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /* Make sure that pointers are valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) if (!mbx_cmd || !mbx_sts) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) DEBUG2(printk("scsi%ld: %s: Invalid mbx_cmd or mbx_sts "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) "pointer\n", ha->host_no, __func__));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) if (is_qla40XX(ha)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) if (test_bit(AF_HA_REMOVAL, &ha->flags)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) DEBUG2(ql4_printk(KERN_WARNING, ha, "scsi%ld: %s: "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) "prematurely completing mbx cmd as "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) "adapter removal detected\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) ha->host_no, __func__));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) if ((is_aer_supported(ha)) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) (test_bit(AF_PCI_CHANNEL_IO_PERM_FAILURE, &ha->flags))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) DEBUG2(printk(KERN_WARNING "scsi%ld: %s: Perm failure on EEH, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) "timeout MBX Exiting.\n", ha->host_no, __func__));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /* Mailbox code active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) wait_count = MBOX_TOV * 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) while (wait_count--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) mutex_lock(&ha->mbox_sem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) if (!test_bit(AF_MBOX_COMMAND, &ha->flags)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) set_bit(AF_MBOX_COMMAND, &ha->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) mutex_unlock(&ha->mbox_sem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) mutex_unlock(&ha->mbox_sem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) if (!wait_count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) DEBUG2(printk("scsi%ld: %s: mbox_sem failed\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) ha->host_no, __func__));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) msleep(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) if (is_qla80XX(ha)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) if (test_bit(AF_FW_RECOVERY, &ha->flags)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) DEBUG2(ql4_printk(KERN_WARNING, ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) "scsi%ld: %s: prematurely completing mbx cmd as firmware recovery detected\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) ha->host_no, __func__));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) goto mbox_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /* Do not send any mbx cmd if h/w is in failed state*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) ha->isp_ops->idc_lock(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) dev_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DEV_STATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) ha->isp_ops->idc_unlock(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) if (dev_state == QLA8XXX_DEV_FAILED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) ql4_printk(KERN_WARNING, ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) "scsi%ld: %s: H/W is in failed state, do not send any mailbox commands\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) ha->host_no, __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) goto mbox_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) spin_lock_irqsave(&ha->hardware_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) ha->mbox_status_count = outCount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) for (i = 0; i < outCount; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) ha->mbox_status[i] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /* Queue the mailbox command to the firmware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) ha->isp_ops->queue_mailbox_command(ha, mbx_cmd, inCount);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) spin_unlock_irqrestore(&ha->hardware_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /* Wait for completion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) * If we don't want status, don't wait for the mailbox command to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) * complete. For example, MBOX_CMD_RESET_FW doesn't return status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) * you must poll the inbound Interrupt Mask for completion.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) if (outCount == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) status = QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) goto mbox_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) * Wait for completion: Poll or completion queue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) if (qla4xxx_is_intr_poll_mode(ha)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) /* Poll for command to complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) wait_count = jiffies + MBOX_TOV * HZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) while (test_bit(AF_MBOX_COMMAND_DONE, &ha->flags) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) if (time_after_eq(jiffies, wait_count))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) * Service the interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) * The ISR will save the mailbox status registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) * to a temporary storage location in the adapter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) * structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) spin_lock_irqsave(&ha->hardware_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) ha->isp_ops->process_mailbox_interrupt(ha, outCount);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) spin_unlock_irqrestore(&ha->hardware_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) msleep(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /* Do not poll for completion. Use completion queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) set_bit(AF_MBOX_COMMAND_NOPOLL, &ha->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) wait_for_completion_timeout(&ha->mbx_intr_comp, MBOX_TOV * HZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) clear_bit(AF_MBOX_COMMAND_NOPOLL, &ha->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) /* Check for mailbox timeout. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) if (!test_bit(AF_MBOX_COMMAND_DONE, &ha->flags)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) if (is_qla80XX(ha) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) test_bit(AF_FW_RECOVERY, &ha->flags)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) DEBUG2(ql4_printk(KERN_INFO, ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) "scsi%ld: %s: prematurely completing mbx cmd as "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) "firmware recovery detected\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) ha->host_no, __func__));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) goto mbox_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) ql4_printk(KERN_WARNING, ha, "scsi%ld: Mailbox Cmd 0x%08X timed out, Scheduling Adapter Reset\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) ha->host_no, mbx_cmd[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) ha->mailbox_timeout_count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) mbx_sts[0] = (-1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) set_bit(DPC_RESET_HA, &ha->dpc_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) if (is_qla8022(ha)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) ql4_printk(KERN_INFO, ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) "disabling pause transmit on port 0 & 1.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x98,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) CRB_NIU_XG_PAUSE_CTL_P0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) CRB_NIU_XG_PAUSE_CTL_P1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) } else if (is_qla8032(ha) || is_qla8042(ha)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) ql4_printk(KERN_INFO, ha, " %s: disabling pause transmit on port 0 & 1.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) qla4_83xx_disable_pause(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) goto mbox_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) * Copy the mailbox out registers to the caller's mailbox in/out
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) * structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) spin_lock_irqsave(&ha->hardware_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) for (i = 0; i < outCount; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) mbx_sts[i] = ha->mbox_status[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) /* Set return status and error flags (if applicable). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) switch (ha->mbox_status[0]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) case MBOX_STS_COMMAND_COMPLETE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) status = QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) case MBOX_STS_INTERMEDIATE_COMPLETION:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) status = QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) case MBOX_STS_BUSY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) ql4_printk(KERN_WARNING, ha, "scsi%ld: %s: Cmd = %08X, ISP BUSY\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) ha->host_no, __func__, mbx_cmd[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) ha->mailbox_timeout_count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) ql4_printk(KERN_WARNING, ha, "scsi%ld: %s: FAILED, MBOX CMD = %08X, MBOX STS = %08X %08X %08X %08X %08X %08X %08X %08X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) ha->host_no, __func__, mbx_cmd[0], mbx_sts[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) mbx_sts[1], mbx_sts[2], mbx_sts[3], mbx_sts[4],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) mbx_sts[5], mbx_sts[6], mbx_sts[7]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) spin_unlock_irqrestore(&ha->hardware_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) mbox_exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) mutex_lock(&ha->mbox_sem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) clear_bit(AF_MBOX_COMMAND, &ha->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) mutex_unlock(&ha->mbox_sem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) clear_bit(AF_MBOX_COMMAND_DONE, &ha->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) * qla4xxx_get_minidump_template - Get the firmware template
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) * @ha: Pointer to host adapter structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) * @phys_addr: dma address for template
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) * Obtain the minidump template from firmware during initialization
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) * as it may not be available when minidump is desired.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) **/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) int qla4xxx_get_minidump_template(struct scsi_qla_host *ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) dma_addr_t phys_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) uint32_t mbox_cmd[MBOX_REG_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) uint32_t mbox_sts[MBOX_REG_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) memset(&mbox_cmd, 0, sizeof(mbox_cmd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) memset(&mbox_sts, 0, sizeof(mbox_sts));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) mbox_cmd[0] = MBOX_CMD_MINIDUMP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) mbox_cmd[1] = MINIDUMP_GET_TMPLT_SUBCOMMAND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) mbox_cmd[2] = LSDW(phys_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) mbox_cmd[3] = MSDW(phys_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) mbox_cmd[4] = ha->fw_dump_tmplt_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) mbox_cmd[5] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 2, &mbox_cmd[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) &mbox_sts[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) if (status != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) DEBUG2(ql4_printk(KERN_INFO, ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) "scsi%ld: %s: Cmd = %08X, mbx[0] = 0x%04x, mbx[1] = 0x%04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) ha->host_no, __func__, mbox_cmd[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) mbox_sts[0], mbox_sts[1]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) * qla4xxx_req_template_size - Get minidump template size from firmware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) * @ha: Pointer to host adapter structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) **/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) int qla4xxx_req_template_size(struct scsi_qla_host *ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) uint32_t mbox_cmd[MBOX_REG_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) uint32_t mbox_sts[MBOX_REG_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) memset(&mbox_cmd, 0, sizeof(mbox_cmd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) memset(&mbox_sts, 0, sizeof(mbox_sts));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) mbox_cmd[0] = MBOX_CMD_MINIDUMP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) mbox_cmd[1] = MINIDUMP_GET_SIZE_SUBCOMMAND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 8, &mbox_cmd[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) &mbox_sts[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) if (status == QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) ha->fw_dump_tmplt_size = mbox_sts[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) DEBUG2(ql4_printk(KERN_INFO, ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) "%s: sts[0]=0x%04x, template size=0x%04x, size_cm_02=0x%04x, size_cm_04=0x%04x, size_cm_08=0x%04x, size_cm_10=0x%04x, size_cm_FF=0x%04x, version=0x%04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) __func__, mbox_sts[0], mbox_sts[1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) mbox_sts[2], mbox_sts[3], mbox_sts[4],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) mbox_sts[5], mbox_sts[6], mbox_sts[7]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) if (ha->fw_dump_tmplt_size == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) status = QLA_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) ql4_printk(KERN_WARNING, ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) "%s: Error sts[0]=0x%04x, mbx[1]=0x%04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) __func__, mbox_sts[0], mbox_sts[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) status = QLA_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) void qla4xxx_mailbox_premature_completion(struct scsi_qla_host *ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) set_bit(AF_FW_RECOVERY, &ha->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) ql4_printk(KERN_INFO, ha, "scsi%ld: %s: set FW RECOVERY!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) ha->host_no, __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) if (test_bit(AF_MBOX_COMMAND, &ha->flags)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) if (test_bit(AF_MBOX_COMMAND_NOPOLL, &ha->flags)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) complete(&ha->mbx_intr_comp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) ql4_printk(KERN_INFO, ha, "scsi%ld: %s: Due to fw "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) "recovery, doing premature completion of "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) "mbx cmd\n", ha->host_no, __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) set_bit(AF_MBOX_COMMAND_DONE, &ha->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) ql4_printk(KERN_INFO, ha, "scsi%ld: %s: Due to fw "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) "recovery, doing premature completion of "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) "polling mbx cmd\n", ha->host_no, __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) static uint8_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) qla4xxx_set_ifcb(struct scsi_qla_host *ha, uint32_t *mbox_cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) uint32_t *mbox_sts, dma_addr_t init_fw_cb_dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) memset(mbox_cmd, 0, sizeof(mbox_cmd[0]) * MBOX_REG_COUNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) memset(mbox_sts, 0, sizeof(mbox_sts[0]) * MBOX_REG_COUNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) if (is_qla8022(ha))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) qla4_82xx_wr_32(ha, ha->nx_db_wr_ptr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) mbox_cmd[0] = MBOX_CMD_INITIALIZE_FIRMWARE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) mbox_cmd[1] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) mbox_cmd[2] = LSDW(init_fw_cb_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) mbox_cmd[3] = MSDW(init_fw_cb_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) mbox_cmd[4] = sizeof(struct addr_ctrl_blk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) if (qla4xxx_mailbox_command(ha, 6, 6, mbox_cmd, mbox_sts) !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) DEBUG2(printk(KERN_WARNING "scsi%ld: %s: "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) "MBOX_CMD_INITIALIZE_FIRMWARE"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) " failed w/ status %04X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) ha->host_no, __func__, mbox_sts[0]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) return QLA_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) return QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) uint8_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) qla4xxx_get_ifcb(struct scsi_qla_host *ha, uint32_t *mbox_cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) uint32_t *mbox_sts, dma_addr_t init_fw_cb_dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) memset(mbox_cmd, 0, sizeof(mbox_cmd[0]) * MBOX_REG_COUNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) memset(mbox_sts, 0, sizeof(mbox_sts[0]) * MBOX_REG_COUNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) mbox_cmd[0] = MBOX_CMD_GET_INIT_FW_CTRL_BLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) mbox_cmd[2] = LSDW(init_fw_cb_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) mbox_cmd[3] = MSDW(init_fw_cb_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) mbox_cmd[4] = sizeof(struct addr_ctrl_blk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) if (qla4xxx_mailbox_command(ha, 5, 5, mbox_cmd, mbox_sts) !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) DEBUG2(printk(KERN_WARNING "scsi%ld: %s: "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) "MBOX_CMD_GET_INIT_FW_CTRL_BLOCK"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) " failed w/ status %04X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) ha->host_no, __func__, mbox_sts[0]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) return QLA_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) return QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) uint8_t qla4xxx_set_ipaddr_state(uint8_t fw_ipaddr_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) uint8_t ipaddr_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) switch (fw_ipaddr_state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) case IP_ADDRSTATE_UNCONFIGURED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) ipaddr_state = ISCSI_IPDDRESS_STATE_UNCONFIGURED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) case IP_ADDRSTATE_INVALID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) ipaddr_state = ISCSI_IPDDRESS_STATE_INVALID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) case IP_ADDRSTATE_ACQUIRING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) ipaddr_state = ISCSI_IPDDRESS_STATE_ACQUIRING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) case IP_ADDRSTATE_TENTATIVE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) ipaddr_state = ISCSI_IPDDRESS_STATE_TENTATIVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) case IP_ADDRSTATE_DEPRICATED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) ipaddr_state = ISCSI_IPDDRESS_STATE_DEPRECATED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) case IP_ADDRSTATE_PREFERRED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) ipaddr_state = ISCSI_IPDDRESS_STATE_VALID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) case IP_ADDRSTATE_DISABLING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) ipaddr_state = ISCSI_IPDDRESS_STATE_DISABLING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) ipaddr_state = ISCSI_IPDDRESS_STATE_UNCONFIGURED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) return ipaddr_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) qla4xxx_update_local_ip(struct scsi_qla_host *ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) struct addr_ctrl_blk *init_fw_cb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) ha->ip_config.tcp_options = le16_to_cpu(init_fw_cb->ipv4_tcp_opts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) ha->ip_config.ipv4_options = le16_to_cpu(init_fw_cb->ipv4_ip_opts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) ha->ip_config.ipv4_addr_state =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) qla4xxx_set_ipaddr_state(init_fw_cb->ipv4_addr_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) ha->ip_config.eth_mtu_size =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) le16_to_cpu(init_fw_cb->eth_mtu_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) ha->ip_config.ipv4_port = le16_to_cpu(init_fw_cb->ipv4_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) if (ha->acb_version == ACB_SUPPORTED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) ha->ip_config.ipv6_options = le16_to_cpu(init_fw_cb->ipv6_opts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) ha->ip_config.ipv6_addl_options =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) le16_to_cpu(init_fw_cb->ipv6_addtl_opts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) ha->ip_config.ipv6_tcp_options =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) le16_to_cpu(init_fw_cb->ipv6_tcp_opts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) /* Save IPv4 Address Info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) memcpy(ha->ip_config.ip_address, init_fw_cb->ipv4_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) min(sizeof(ha->ip_config.ip_address),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) sizeof(init_fw_cb->ipv4_addr)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) memcpy(ha->ip_config.subnet_mask, init_fw_cb->ipv4_subnet,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) min(sizeof(ha->ip_config.subnet_mask),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) sizeof(init_fw_cb->ipv4_subnet)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) memcpy(ha->ip_config.gateway, init_fw_cb->ipv4_gw_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) min(sizeof(ha->ip_config.gateway),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) sizeof(init_fw_cb->ipv4_gw_addr)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) ha->ip_config.ipv4_vlan_tag = be16_to_cpu(init_fw_cb->ipv4_vlan_tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) ha->ip_config.control = init_fw_cb->control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) ha->ip_config.tcp_wsf = init_fw_cb->ipv4_tcp_wsf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) ha->ip_config.ipv4_tos = init_fw_cb->ipv4_tos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) ha->ip_config.ipv4_cache_id = init_fw_cb->ipv4_cacheid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) ha->ip_config.ipv4_alt_cid_len = init_fw_cb->ipv4_dhcp_alt_cid_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) memcpy(ha->ip_config.ipv4_alt_cid, init_fw_cb->ipv4_dhcp_alt_cid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) min(sizeof(ha->ip_config.ipv4_alt_cid),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) sizeof(init_fw_cb->ipv4_dhcp_alt_cid)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) ha->ip_config.ipv4_vid_len = init_fw_cb->ipv4_dhcp_vid_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) memcpy(ha->ip_config.ipv4_vid, init_fw_cb->ipv4_dhcp_vid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) min(sizeof(ha->ip_config.ipv4_vid),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) sizeof(init_fw_cb->ipv4_dhcp_vid)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) ha->ip_config.ipv4_ttl = init_fw_cb->ipv4_ttl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) ha->ip_config.def_timeout = le16_to_cpu(init_fw_cb->def_timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) ha->ip_config.abort_timer = init_fw_cb->abort_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) ha->ip_config.iscsi_options = le16_to_cpu(init_fw_cb->iscsi_opts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) ha->ip_config.iscsi_max_pdu_size =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) le16_to_cpu(init_fw_cb->iscsi_max_pdu_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) ha->ip_config.iscsi_first_burst_len =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) le16_to_cpu(init_fw_cb->iscsi_fburst_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) ha->ip_config.iscsi_max_outstnd_r2t =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) le16_to_cpu(init_fw_cb->iscsi_max_outstnd_r2t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) ha->ip_config.iscsi_max_burst_len =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) le16_to_cpu(init_fw_cb->iscsi_max_burst_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) memcpy(ha->ip_config.iscsi_name, init_fw_cb->iscsi_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) min(sizeof(ha->ip_config.iscsi_name),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) sizeof(init_fw_cb->iscsi_name)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) if (is_ipv6_enabled(ha)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) /* Save IPv6 Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) ha->ip_config.ipv6_link_local_state =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) qla4xxx_set_ipaddr_state(init_fw_cb->ipv6_lnk_lcl_addr_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) ha->ip_config.ipv6_addr0_state =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) qla4xxx_set_ipaddr_state(init_fw_cb->ipv6_addr0_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) ha->ip_config.ipv6_addr1_state =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) qla4xxx_set_ipaddr_state(init_fw_cb->ipv6_addr1_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) switch (le16_to_cpu(init_fw_cb->ipv6_dflt_rtr_state)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) case IPV6_RTRSTATE_UNKNOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) ha->ip_config.ipv6_default_router_state =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) ISCSI_ROUTER_STATE_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) case IPV6_RTRSTATE_MANUAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) ha->ip_config.ipv6_default_router_state =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) ISCSI_ROUTER_STATE_MANUAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) case IPV6_RTRSTATE_ADVERTISED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) ha->ip_config.ipv6_default_router_state =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) ISCSI_ROUTER_STATE_ADVERTISED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) case IPV6_RTRSTATE_STALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) ha->ip_config.ipv6_default_router_state =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) ISCSI_ROUTER_STATE_STALE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) ha->ip_config.ipv6_default_router_state =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) ISCSI_ROUTER_STATE_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) ha->ip_config.ipv6_link_local_addr.in6_u.u6_addr8[0] = 0xFE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) ha->ip_config.ipv6_link_local_addr.in6_u.u6_addr8[1] = 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) memcpy(&ha->ip_config.ipv6_link_local_addr.in6_u.u6_addr8[8],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) init_fw_cb->ipv6_if_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) min(sizeof(ha->ip_config.ipv6_link_local_addr)/2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) sizeof(init_fw_cb->ipv6_if_id)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) memcpy(&ha->ip_config.ipv6_addr0, init_fw_cb->ipv6_addr0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) min(sizeof(ha->ip_config.ipv6_addr0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) sizeof(init_fw_cb->ipv6_addr0)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) memcpy(&ha->ip_config.ipv6_addr1, init_fw_cb->ipv6_addr1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) min(sizeof(ha->ip_config.ipv6_addr1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) sizeof(init_fw_cb->ipv6_addr1)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) memcpy(&ha->ip_config.ipv6_default_router_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) init_fw_cb->ipv6_dflt_rtr_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) min(sizeof(ha->ip_config.ipv6_default_router_addr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) sizeof(init_fw_cb->ipv6_dflt_rtr_addr)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) ha->ip_config.ipv6_vlan_tag =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) be16_to_cpu(init_fw_cb->ipv6_vlan_tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) ha->ip_config.ipv6_port = le16_to_cpu(init_fw_cb->ipv6_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) ha->ip_config.ipv6_cache_id = init_fw_cb->ipv6_cache_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) ha->ip_config.ipv6_flow_lbl =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) le16_to_cpu(init_fw_cb->ipv6_flow_lbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) ha->ip_config.ipv6_traffic_class =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) init_fw_cb->ipv6_traffic_class;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) ha->ip_config.ipv6_hop_limit = init_fw_cb->ipv6_hop_limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) ha->ip_config.ipv6_nd_reach_time =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) le32_to_cpu(init_fw_cb->ipv6_nd_reach_time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) ha->ip_config.ipv6_nd_rexmit_timer =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) le32_to_cpu(init_fw_cb->ipv6_nd_rexmit_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) ha->ip_config.ipv6_nd_stale_timeout =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) le32_to_cpu(init_fw_cb->ipv6_nd_stale_timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) ha->ip_config.ipv6_dup_addr_detect_count =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) init_fw_cb->ipv6_dup_addr_detect_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) ha->ip_config.ipv6_gw_advrt_mtu =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) le32_to_cpu(init_fw_cb->ipv6_gw_advrt_mtu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) ha->ip_config.ipv6_tcp_wsf = init_fw_cb->ipv6_tcp_wsf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) uint8_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) qla4xxx_update_local_ifcb(struct scsi_qla_host *ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) uint32_t *mbox_cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) uint32_t *mbox_sts,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) struct addr_ctrl_blk *init_fw_cb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) dma_addr_t init_fw_cb_dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) if (qla4xxx_get_ifcb(ha, mbox_cmd, mbox_sts, init_fw_cb_dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) DEBUG2(printk(KERN_WARNING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) "scsi%ld: %s: Failed to get init_fw_ctrl_blk\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) ha->host_no, __func__));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) return QLA_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) DEBUG2(qla4xxx_dump_buffer(init_fw_cb, sizeof(struct addr_ctrl_blk)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) /* Save some info in adapter structure. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) ha->acb_version = init_fw_cb->acb_version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) ha->firmware_options = le16_to_cpu(init_fw_cb->fw_options);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) ha->heartbeat_interval = init_fw_cb->hb_interval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) memcpy(ha->name_string, init_fw_cb->iscsi_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) min(sizeof(ha->name_string),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) sizeof(init_fw_cb->iscsi_name)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) ha->def_timeout = le16_to_cpu(init_fw_cb->def_timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) /*memcpy(ha->alias, init_fw_cb->Alias,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) min(sizeof(ha->alias), sizeof(init_fw_cb->Alias)));*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) qla4xxx_update_local_ip(ha, init_fw_cb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) return QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) * qla4xxx_initialize_fw_cb - initializes firmware control block.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) * @ha: Pointer to host adapter structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) **/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) int qla4xxx_initialize_fw_cb(struct scsi_qla_host * ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) struct addr_ctrl_blk *init_fw_cb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) dma_addr_t init_fw_cb_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) uint32_t mbox_cmd[MBOX_REG_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) uint32_t mbox_sts[MBOX_REG_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) int status = QLA_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) init_fw_cb = dma_alloc_coherent(&ha->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) sizeof(struct addr_ctrl_blk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) &init_fw_cb_dma, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) if (init_fw_cb == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) DEBUG2(printk("scsi%ld: %s: Unable to alloc init_cb\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) ha->host_no, __func__));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) goto exit_init_fw_cb_no_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) /* Get Initialize Firmware Control Block. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) memset(&mbox_cmd, 0, sizeof(mbox_cmd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) memset(&mbox_sts, 0, sizeof(mbox_sts));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) if (qla4xxx_get_ifcb(ha, &mbox_cmd[0], &mbox_sts[0], init_fw_cb_dma) !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) goto exit_init_fw_cb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) /* Fill in the request and response queue information. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) init_fw_cb->rqq_consumer_idx = cpu_to_le16(ha->request_out);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) init_fw_cb->compq_producer_idx = cpu_to_le16(ha->response_in);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) init_fw_cb->rqq_len = __constant_cpu_to_le16(REQUEST_QUEUE_DEPTH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) init_fw_cb->compq_len = __constant_cpu_to_le16(RESPONSE_QUEUE_DEPTH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) init_fw_cb->rqq_addr_lo = cpu_to_le32(LSDW(ha->request_dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) init_fw_cb->rqq_addr_hi = cpu_to_le32(MSDW(ha->request_dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) init_fw_cb->compq_addr_lo = cpu_to_le32(LSDW(ha->response_dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) init_fw_cb->compq_addr_hi = cpu_to_le32(MSDW(ha->response_dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) init_fw_cb->shdwreg_addr_lo = cpu_to_le32(LSDW(ha->shadow_regs_dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) init_fw_cb->shdwreg_addr_hi = cpu_to_le32(MSDW(ha->shadow_regs_dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) /* Set up required options. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) init_fw_cb->fw_options |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) __constant_cpu_to_le16(FWOPT_SESSION_MODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) FWOPT_INITIATOR_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) if (is_qla80XX(ha))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) init_fw_cb->fw_options |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) __constant_cpu_to_le16(FWOPT_ENABLE_CRBDB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) init_fw_cb->fw_options &= __constant_cpu_to_le16(~FWOPT_TARGET_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) init_fw_cb->add_fw_options = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) init_fw_cb->add_fw_options |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) __constant_cpu_to_le16(ADFWOPT_SERIALIZE_TASK_MGMT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) init_fw_cb->add_fw_options |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) __constant_cpu_to_le16(ADFWOPT_AUTOCONN_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) if (qla4xxx_set_ifcb(ha, &mbox_cmd[0], &mbox_sts[0], init_fw_cb_dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) DEBUG2(printk(KERN_WARNING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) "scsi%ld: %s: Failed to set init_fw_ctrl_blk\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) ha->host_no, __func__));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) goto exit_init_fw_cb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) if (qla4xxx_update_local_ifcb(ha, &mbox_cmd[0], &mbox_sts[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) init_fw_cb, init_fw_cb_dma) != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) DEBUG2(printk("scsi%ld: %s: Failed to update local ifcb\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) ha->host_no, __func__));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) goto exit_init_fw_cb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) status = QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) exit_init_fw_cb:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) dma_free_coherent(&ha->pdev->dev, sizeof(struct addr_ctrl_blk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) init_fw_cb, init_fw_cb_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) exit_init_fw_cb_no_free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) * qla4xxx_get_dhcp_ip_address - gets HBA ip address via DHCP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) * @ha: Pointer to host adapter structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) **/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) int qla4xxx_get_dhcp_ip_address(struct scsi_qla_host * ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) struct addr_ctrl_blk *init_fw_cb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) dma_addr_t init_fw_cb_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) uint32_t mbox_cmd[MBOX_REG_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) uint32_t mbox_sts[MBOX_REG_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) init_fw_cb = dma_alloc_coherent(&ha->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) sizeof(struct addr_ctrl_blk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) &init_fw_cb_dma, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) if (init_fw_cb == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) printk("scsi%ld: %s: Unable to alloc init_cb\n", ha->host_no,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) return QLA_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) /* Get Initialize Firmware Control Block. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) if (qla4xxx_get_ifcb(ha, &mbox_cmd[0], &mbox_sts[0], init_fw_cb_dma) !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) DEBUG2(printk("scsi%ld: %s: Failed to get init_fw_ctrl_blk\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) ha->host_no, __func__));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) dma_free_coherent(&ha->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) sizeof(struct addr_ctrl_blk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) init_fw_cb, init_fw_cb_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) return QLA_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) /* Save IP Address. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) qla4xxx_update_local_ip(ha, init_fw_cb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) dma_free_coherent(&ha->pdev->dev, sizeof(struct addr_ctrl_blk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) init_fw_cb, init_fw_cb_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) return QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) * qla4xxx_get_firmware_state - gets firmware state of HBA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) * @ha: Pointer to host adapter structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) **/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) int qla4xxx_get_firmware_state(struct scsi_qla_host * ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) uint32_t mbox_cmd[MBOX_REG_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) uint32_t mbox_sts[MBOX_REG_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) /* Get firmware version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) memset(&mbox_cmd, 0, sizeof(mbox_cmd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) memset(&mbox_sts, 0, sizeof(mbox_sts));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) mbox_cmd[0] = MBOX_CMD_GET_FW_STATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 4, &mbox_cmd[0], &mbox_sts[0]) !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) DEBUG2(printk("scsi%ld: %s: MBOX_CMD_GET_FW_STATE failed w/ "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) "status %04X\n", ha->host_no, __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) mbox_sts[0]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) return QLA_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) ha->firmware_state = mbox_sts[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) ha->board_id = mbox_sts[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) ha->addl_fw_state = mbox_sts[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) DEBUG2(printk("scsi%ld: %s firmware_state=0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) ha->host_no, __func__, ha->firmware_state);)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) return QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) * qla4xxx_get_firmware_status - retrieves firmware status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) * @ha: Pointer to host adapter structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) **/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) int qla4xxx_get_firmware_status(struct scsi_qla_host * ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) uint32_t mbox_cmd[MBOX_REG_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) uint32_t mbox_sts[MBOX_REG_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) /* Get firmware version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) memset(&mbox_cmd, 0, sizeof(mbox_cmd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) memset(&mbox_sts, 0, sizeof(mbox_sts));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) mbox_cmd[0] = MBOX_CMD_GET_FW_STATUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 3, &mbox_cmd[0], &mbox_sts[0]) !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) DEBUG2(printk("scsi%ld: %s: MBOX_CMD_GET_FW_STATUS failed w/ "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) "status %04X\n", ha->host_no, __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) mbox_sts[0]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) return QLA_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) /* High-water mark of IOCBs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) ha->iocb_hiwat = mbox_sts[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) DEBUG2(ql4_printk(KERN_INFO, ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) "%s: firmware IOCBs available = %d\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) ha->iocb_hiwat));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) if (ha->iocb_hiwat > IOCB_HIWAT_CUSHION)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) ha->iocb_hiwat -= IOCB_HIWAT_CUSHION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) /* Ideally, we should not enter this code, as the # of firmware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) * IOCBs is hard-coded in the firmware. We set a default
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) * iocb_hiwat here just in case */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) if (ha->iocb_hiwat == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) ha->iocb_hiwat = REQUEST_QUEUE_DEPTH / 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) DEBUG2(ql4_printk(KERN_WARNING, ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) "%s: Setting IOCB's to = %d\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) ha->iocb_hiwat));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) return QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) * qla4xxx_get_fwddb_entry - retrieves firmware ddb entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) * @ha: Pointer to host adapter structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) * @fw_ddb_index: Firmware's device database index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) * @fw_ddb_entry: Pointer to firmware's device database entry structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) * @num_valid_ddb_entries: Pointer to number of valid ddb entries
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) * @next_ddb_index: Pointer to next valid device database index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) * @fw_ddb_device_state: Pointer to device state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) **/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) int qla4xxx_get_fwddb_entry(struct scsi_qla_host *ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) uint16_t fw_ddb_index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) struct dev_db_entry *fw_ddb_entry,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) dma_addr_t fw_ddb_entry_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) uint32_t *num_valid_ddb_entries,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) uint32_t *next_ddb_index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) uint32_t *fw_ddb_device_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) uint32_t *conn_err_detail,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) uint16_t *tcp_source_port_num,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) uint16_t *connection_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) int status = QLA_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) uint16_t options;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) uint32_t mbox_cmd[MBOX_REG_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) uint32_t mbox_sts[MBOX_REG_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) /* Make sure the device index is valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) if (fw_ddb_index >= MAX_DDB_ENTRIES) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) DEBUG2(printk("scsi%ld: %s: ddb [%d] out of range.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) ha->host_no, __func__, fw_ddb_index));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) goto exit_get_fwddb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) memset(&mbox_cmd, 0, sizeof(mbox_cmd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) memset(&mbox_sts, 0, sizeof(mbox_sts));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) if (fw_ddb_entry)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) memset(fw_ddb_entry, 0, sizeof(struct dev_db_entry));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) mbox_cmd[0] = MBOX_CMD_GET_DATABASE_ENTRY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) mbox_cmd[1] = (uint32_t) fw_ddb_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) mbox_cmd[2] = LSDW(fw_ddb_entry_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) mbox_cmd[3] = MSDW(fw_ddb_entry_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) mbox_cmd[4] = sizeof(struct dev_db_entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 7, &mbox_cmd[0], &mbox_sts[0]) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) QLA_ERROR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) DEBUG2(printk("scsi%ld: %s: MBOX_CMD_GET_DATABASE_ENTRY failed"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) " with status 0x%04X\n", ha->host_no, __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) mbox_sts[0]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) goto exit_get_fwddb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) if (fw_ddb_index != mbox_sts[1]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) DEBUG2(printk("scsi%ld: %s: ddb mismatch [%d] != [%d].\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) ha->host_no, __func__, fw_ddb_index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) mbox_sts[1]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) goto exit_get_fwddb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) if (fw_ddb_entry) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) options = le16_to_cpu(fw_ddb_entry->options);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) if (options & DDB_OPT_IPV6_DEVICE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) ql4_printk(KERN_INFO, ha, "%s: DDB[%d] MB0 %04x Tot %d "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) "Next %d State %04x ConnErr %08x %pI6 "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) ":%04d \"%s\"\n", __func__, fw_ddb_index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) mbox_sts[0], mbox_sts[2], mbox_sts[3],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) mbox_sts[4], mbox_sts[5],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) fw_ddb_entry->ip_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) le16_to_cpu(fw_ddb_entry->port),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) fw_ddb_entry->iscsi_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) ql4_printk(KERN_INFO, ha, "%s: DDB[%d] MB0 %04x Tot %d "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) "Next %d State %04x ConnErr %08x %pI4 "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) ":%04d \"%s\"\n", __func__, fw_ddb_index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) mbox_sts[0], mbox_sts[2], mbox_sts[3],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) mbox_sts[4], mbox_sts[5],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) fw_ddb_entry->ip_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) le16_to_cpu(fw_ddb_entry->port),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) fw_ddb_entry->iscsi_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) if (num_valid_ddb_entries)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) *num_valid_ddb_entries = mbox_sts[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) if (next_ddb_index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) *next_ddb_index = mbox_sts[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) if (fw_ddb_device_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) *fw_ddb_device_state = mbox_sts[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) * RA: This mailbox has been changed to pass connection error and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) * details. Its true for ISP4010 as per Version E - Not sure when it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) * was changed. Get the time2wait from the fw_dd_entry field :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) * default_time2wait which we call it as minTime2Wait DEV_DB_ENTRY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) * struct.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) if (conn_err_detail)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) *conn_err_detail = mbox_sts[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) if (tcp_source_port_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) *tcp_source_port_num = (uint16_t) (mbox_sts[6] >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) if (connection_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) *connection_id = (uint16_t) mbox_sts[6] & 0x00FF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) status = QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) exit_get_fwddb:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) int qla4xxx_conn_open(struct scsi_qla_host *ha, uint16_t fw_ddb_index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) uint32_t mbox_cmd[MBOX_REG_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) uint32_t mbox_sts[MBOX_REG_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) memset(&mbox_cmd, 0, sizeof(mbox_cmd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) memset(&mbox_sts, 0, sizeof(mbox_sts));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) mbox_cmd[0] = MBOX_CMD_CONN_OPEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) mbox_cmd[1] = fw_ddb_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 2, &mbox_cmd[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) &mbox_sts[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) DEBUG2(ql4_printk(KERN_INFO, ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) "%s: status = %d mbx0 = 0x%x mbx1 = 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) __func__, status, mbox_sts[0], mbox_sts[1]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) * qla4xxx_set_fwddb_entry - sets a ddb entry.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) * @ha: Pointer to host adapter structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) * @fw_ddb_index: Firmware's device database index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) * @fw_ddb_entry_dma: dma address of ddb entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) * @mbx_sts: mailbox 0 to be returned or NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) * This routine initializes or updates the adapter's device database
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) * entry for the specified device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) **/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) int qla4xxx_set_ddb_entry(struct scsi_qla_host * ha, uint16_t fw_ddb_index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) dma_addr_t fw_ddb_entry_dma, uint32_t *mbx_sts)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) uint32_t mbox_cmd[MBOX_REG_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) uint32_t mbox_sts[MBOX_REG_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) /* Do not wait for completion. The firmware will send us an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) * ASTS_DATABASE_CHANGED (0x8014) to notify us of the login status.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) memset(&mbox_cmd, 0, sizeof(mbox_cmd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) memset(&mbox_sts, 0, sizeof(mbox_sts));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) mbox_cmd[0] = MBOX_CMD_SET_DATABASE_ENTRY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) mbox_cmd[1] = (uint32_t) fw_ddb_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) mbox_cmd[2] = LSDW(fw_ddb_entry_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) mbox_cmd[3] = MSDW(fw_ddb_entry_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) mbox_cmd[4] = sizeof(struct dev_db_entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) &mbox_sts[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) if (mbx_sts)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) *mbx_sts = mbox_sts[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) DEBUG2(printk("scsi%ld: %s: status=%d mbx0=0x%x mbx4=0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) ha->host_no, __func__, status, mbox_sts[0], mbox_sts[4]);)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) int qla4xxx_session_logout_ddb(struct scsi_qla_host *ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) struct ddb_entry *ddb_entry, int options)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) uint32_t mbox_cmd[MBOX_REG_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) uint32_t mbox_sts[MBOX_REG_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) memset(&mbox_cmd, 0, sizeof(mbox_cmd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) memset(&mbox_sts, 0, sizeof(mbox_sts));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) mbox_cmd[0] = MBOX_CMD_CONN_CLOSE_SESS_LOGOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) mbox_cmd[1] = ddb_entry->fw_ddb_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) mbox_cmd[3] = options;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 2, &mbox_cmd[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) &mbox_sts[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) if (status != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) DEBUG2(ql4_printk(KERN_INFO, ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) "%s: MBOX_CMD_CONN_CLOSE_SESS_LOGOUT "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) "failed sts %04X %04X", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) mbox_sts[0], mbox_sts[1]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) if ((mbox_sts[0] == MBOX_STS_COMMAND_ERROR) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) (mbox_sts[1] == DDB_NOT_LOGGED_IN)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) set_bit(DDB_CONN_CLOSE_FAILURE, &ddb_entry->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) * qla4xxx_get_crash_record - retrieves crash record.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) * @ha: Pointer to host adapter structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) * This routine retrieves a crash record from the QLA4010 after an 8002h aen.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) **/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) void qla4xxx_get_crash_record(struct scsi_qla_host * ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) uint32_t mbox_cmd[MBOX_REG_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) uint32_t mbox_sts[MBOX_REG_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) struct crash_record *crash_record = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) dma_addr_t crash_record_dma = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) uint32_t crash_record_size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) memset(&mbox_cmd, 0, sizeof(mbox_cmd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) memset(&mbox_sts, 0, sizeof(mbox_cmd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) /* Get size of crash record. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) mbox_cmd[0] = MBOX_CMD_GET_CRASH_RECORD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0], &mbox_sts[0]) !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) DEBUG2(printk("scsi%ld: %s: ERROR: Unable to retrieve size!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) ha->host_no, __func__));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) goto exit_get_crash_record;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) crash_record_size = mbox_sts[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) if (crash_record_size == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) DEBUG2(printk("scsi%ld: %s: ERROR: Crash record size is 0!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) ha->host_no, __func__));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) goto exit_get_crash_record;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) /* Alloc Memory for Crash Record. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) crash_record = dma_alloc_coherent(&ha->pdev->dev, crash_record_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) &crash_record_dma, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) if (crash_record == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) goto exit_get_crash_record;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) /* Get Crash Record. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) memset(&mbox_cmd, 0, sizeof(mbox_cmd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) memset(&mbox_sts, 0, sizeof(mbox_cmd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) mbox_cmd[0] = MBOX_CMD_GET_CRASH_RECORD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) mbox_cmd[2] = LSDW(crash_record_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) mbox_cmd[3] = MSDW(crash_record_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) mbox_cmd[4] = crash_record_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0], &mbox_sts[0]) !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) QLA_SUCCESS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) goto exit_get_crash_record;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) /* Dump Crash Record. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) exit_get_crash_record:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) if (crash_record)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) dma_free_coherent(&ha->pdev->dev, crash_record_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) crash_record, crash_record_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) * qla4xxx_get_conn_event_log - retrieves connection event log
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) * @ha: Pointer to host adapter structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) **/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) void qla4xxx_get_conn_event_log(struct scsi_qla_host * ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) uint32_t mbox_cmd[MBOX_REG_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) uint32_t mbox_sts[MBOX_REG_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) struct conn_event_log_entry *event_log = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) dma_addr_t event_log_dma = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) uint32_t event_log_size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) uint32_t num_valid_entries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) uint32_t oldest_entry = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) uint32_t max_event_log_entries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) uint8_t i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) memset(&mbox_cmd, 0, sizeof(mbox_cmd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) memset(&mbox_sts, 0, sizeof(mbox_cmd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) /* Get size of crash record. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) mbox_cmd[0] = MBOX_CMD_GET_CONN_EVENT_LOG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0], &mbox_sts[0]) !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) QLA_SUCCESS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) goto exit_get_event_log;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) event_log_size = mbox_sts[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) if (event_log_size == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) goto exit_get_event_log;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) /* Alloc Memory for Crash Record. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) event_log = dma_alloc_coherent(&ha->pdev->dev, event_log_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) &event_log_dma, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) if (event_log == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) goto exit_get_event_log;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) /* Get Crash Record. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) memset(&mbox_cmd, 0, sizeof(mbox_cmd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) memset(&mbox_sts, 0, sizeof(mbox_cmd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) mbox_cmd[0] = MBOX_CMD_GET_CONN_EVENT_LOG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) mbox_cmd[2] = LSDW(event_log_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) mbox_cmd[3] = MSDW(event_log_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0], &mbox_sts[0]) !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) DEBUG2(printk("scsi%ld: %s: ERROR: Unable to retrieve event "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) "log!\n", ha->host_no, __func__));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) goto exit_get_event_log;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) /* Dump Event Log. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) num_valid_entries = mbox_sts[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) max_event_log_entries = event_log_size /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) sizeof(struct conn_event_log_entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) if (num_valid_entries > max_event_log_entries)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) oldest_entry = num_valid_entries % max_event_log_entries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) DEBUG3(printk("scsi%ld: Connection Event Log Dump (%d entries):\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) ha->host_no, num_valid_entries));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) if (ql4xextended_error_logging == 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) if (oldest_entry == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) /* Circular Buffer has not wrapped around */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) for (i=0; i < num_valid_entries; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) qla4xxx_dump_buffer((uint8_t *)event_log+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) (i*sizeof(*event_log)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) sizeof(*event_log));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) /* Circular Buffer has wrapped around -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) * display accordingly*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) for (i=oldest_entry; i < max_event_log_entries; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) qla4xxx_dump_buffer((uint8_t *)event_log+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) (i*sizeof(*event_log)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) sizeof(*event_log));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) for (i=0; i < oldest_entry; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) qla4xxx_dump_buffer((uint8_t *)event_log+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) (i*sizeof(*event_log)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) sizeof(*event_log));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) exit_get_event_log:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) if (event_log)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) dma_free_coherent(&ha->pdev->dev, event_log_size, event_log,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) event_log_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) * qla4xxx_abort_task - issues Abort Task
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) * @ha: Pointer to host adapter structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) * @srb: Pointer to srb entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) * This routine performs a LUN RESET on the specified target/lun.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) * The caller must ensure that the ddb_entry and lun_entry pointers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) * are valid before calling this routine.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) **/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) int qla4xxx_abort_task(struct scsi_qla_host *ha, struct srb *srb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) uint32_t mbox_cmd[MBOX_REG_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) uint32_t mbox_sts[MBOX_REG_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) struct scsi_cmnd *cmd = srb->cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) int status = QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) unsigned long flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) uint32_t index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) * Send abort task command to ISP, so that the ISP will return
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) * request with ABORT status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) memset(&mbox_cmd, 0, sizeof(mbox_cmd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) memset(&mbox_sts, 0, sizeof(mbox_sts));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) spin_lock_irqsave(&ha->hardware_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) index = (unsigned long)(unsigned char *)cmd->host_scribble;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) spin_unlock_irqrestore(&ha->hardware_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) /* Firmware already posted completion on response queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) if (index == MAX_SRBS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) mbox_cmd[0] = MBOX_CMD_ABORT_TASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) mbox_cmd[1] = srb->ddb->fw_ddb_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) mbox_cmd[2] = index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) /* Immediate Command Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) mbox_cmd[5] = 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) &mbox_sts[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) if (mbox_sts[0] != MBOX_STS_COMMAND_COMPLETE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) status = QLA_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) DEBUG2(printk(KERN_WARNING "scsi%ld:%d:%llu: abort task FAILED: "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) "mbx0=%04X, mb1=%04X, mb2=%04X, mb3=%04X, mb4=%04X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) ha->host_no, cmd->device->id, cmd->device->lun, mbox_sts[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) mbox_sts[1], mbox_sts[2], mbox_sts[3], mbox_sts[4]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) * qla4xxx_reset_lun - issues LUN Reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) * @ha: Pointer to host adapter structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) * @ddb_entry: Pointer to device database entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) * @lun: lun number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) * This routine performs a LUN RESET on the specified target/lun.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) * The caller must ensure that the ddb_entry and lun_entry pointers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) * are valid before calling this routine.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) **/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) int qla4xxx_reset_lun(struct scsi_qla_host * ha, struct ddb_entry * ddb_entry,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) uint64_t lun)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) uint32_t mbox_cmd[MBOX_REG_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) uint32_t mbox_sts[MBOX_REG_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) uint32_t scsi_lun[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) int status = QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) DEBUG2(printk("scsi%ld:%d:%llu: lun reset issued\n", ha->host_no,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) ddb_entry->fw_ddb_index, lun));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) * Send lun reset command to ISP, so that the ISP will return all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) * outstanding requests with RESET status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) memset(&mbox_cmd, 0, sizeof(mbox_cmd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) memset(&mbox_sts, 0, sizeof(mbox_sts));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) int_to_scsilun(lun, (struct scsi_lun *) scsi_lun);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) mbox_cmd[0] = MBOX_CMD_LUN_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) mbox_cmd[1] = ddb_entry->fw_ddb_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) /* FW expects LUN bytes 0-3 in Incoming Mailbox 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) * (LUN byte 0 is LSByte, byte 3 is MSByte) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) mbox_cmd[2] = cpu_to_le32(scsi_lun[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) /* FW expects LUN bytes 4-7 in Incoming Mailbox 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) * (LUN byte 4 is LSByte, byte 7 is MSByte) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) mbox_cmd[3] = cpu_to_le32(scsi_lun[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) mbox_cmd[5] = 0x01; /* Immediate Command Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0], &mbox_sts[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) if (mbox_sts[0] != MBOX_STS_COMMAND_COMPLETE &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) mbox_sts[0] != MBOX_STS_COMMAND_ERROR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) status = QLA_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) * qla4xxx_reset_target - issues target Reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) * @ha: Pointer to host adapter structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) * @ddb_entry: Pointer to device database entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) * This routine performs a TARGET RESET on the specified target.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) * The caller must ensure that the ddb_entry pointers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) * are valid before calling this routine.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) **/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) int qla4xxx_reset_target(struct scsi_qla_host *ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) struct ddb_entry *ddb_entry)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) uint32_t mbox_cmd[MBOX_REG_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) uint32_t mbox_sts[MBOX_REG_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) int status = QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) DEBUG2(printk("scsi%ld:%d: target reset issued\n", ha->host_no,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) ddb_entry->fw_ddb_index));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) * Send target reset command to ISP, so that the ISP will return all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) * outstanding requests with RESET status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) memset(&mbox_cmd, 0, sizeof(mbox_cmd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) memset(&mbox_sts, 0, sizeof(mbox_sts));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) mbox_cmd[0] = MBOX_CMD_TARGET_WARM_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) mbox_cmd[1] = ddb_entry->fw_ddb_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) mbox_cmd[5] = 0x01; /* Immediate Command Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) &mbox_sts[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) if (mbox_sts[0] != MBOX_STS_COMMAND_COMPLETE &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) mbox_sts[0] != MBOX_STS_COMMAND_ERROR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) status = QLA_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) int qla4xxx_get_flash(struct scsi_qla_host * ha, dma_addr_t dma_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) uint32_t offset, uint32_t len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) uint32_t mbox_cmd[MBOX_REG_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) uint32_t mbox_sts[MBOX_REG_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) memset(&mbox_cmd, 0, sizeof(mbox_cmd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) memset(&mbox_sts, 0, sizeof(mbox_sts));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) mbox_cmd[0] = MBOX_CMD_READ_FLASH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) mbox_cmd[1] = LSDW(dma_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) mbox_cmd[2] = MSDW(dma_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) mbox_cmd[3] = offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) mbox_cmd[4] = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 2, &mbox_cmd[0], &mbox_sts[0]) !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) DEBUG2(printk("scsi%ld: %s: MBOX_CMD_READ_FLASH, failed w/ "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) "status %04X %04X, offset %08x, len %08x\n", ha->host_no,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) __func__, mbox_sts[0], mbox_sts[1], offset, len));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) return QLA_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) return QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) * qla4xxx_about_firmware - gets FW, iscsi draft and boot loader version
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) * @ha: Pointer to host adapter structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) * Retrieves the FW version, iSCSI draft version & bootloader version of HBA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) * Mailboxes 2 & 3 may hold an address for data. Make sure that we write 0 to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) * those mailboxes, if unused.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) **/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) int qla4xxx_about_firmware(struct scsi_qla_host *ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) struct about_fw_info *about_fw = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) dma_addr_t about_fw_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) uint32_t mbox_cmd[MBOX_REG_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) uint32_t mbox_sts[MBOX_REG_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) int status = QLA_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) about_fw = dma_alloc_coherent(&ha->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) sizeof(struct about_fw_info),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) &about_fw_dma, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) if (!about_fw) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) DEBUG2(ql4_printk(KERN_ERR, ha, "%s: Unable to alloc memory "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) "for about_fw\n", __func__));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) memset(&mbox_cmd, 0, sizeof(mbox_cmd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) memset(&mbox_sts, 0, sizeof(mbox_sts));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) mbox_cmd[0] = MBOX_CMD_ABOUT_FW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) mbox_cmd[2] = LSDW(about_fw_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) mbox_cmd[3] = MSDW(about_fw_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) mbox_cmd[4] = sizeof(struct about_fw_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, MBOX_REG_COUNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) &mbox_cmd[0], &mbox_sts[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) if (status != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) DEBUG2(ql4_printk(KERN_WARNING, ha, "%s: MBOX_CMD_ABOUT_FW "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) "failed w/ status %04X\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) mbox_sts[0]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) goto exit_about_fw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) /* Save version information. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) ha->fw_info.fw_major = le16_to_cpu(about_fw->fw_major);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) ha->fw_info.fw_minor = le16_to_cpu(about_fw->fw_minor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) ha->fw_info.fw_patch = le16_to_cpu(about_fw->fw_patch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) ha->fw_info.fw_build = le16_to_cpu(about_fw->fw_build);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) memcpy(ha->fw_info.fw_build_date, about_fw->fw_build_date,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) sizeof(about_fw->fw_build_date));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) memcpy(ha->fw_info.fw_build_time, about_fw->fw_build_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) sizeof(about_fw->fw_build_time));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) strcpy((char *)ha->fw_info.fw_build_user,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) skip_spaces((char *)about_fw->fw_build_user));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) ha->fw_info.fw_load_source = le16_to_cpu(about_fw->fw_load_source);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) ha->fw_info.iscsi_major = le16_to_cpu(about_fw->iscsi_major);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) ha->fw_info.iscsi_minor = le16_to_cpu(about_fw->iscsi_minor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) ha->fw_info.bootload_major = le16_to_cpu(about_fw->bootload_major);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) ha->fw_info.bootload_minor = le16_to_cpu(about_fw->bootload_minor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) ha->fw_info.bootload_patch = le16_to_cpu(about_fw->bootload_patch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) ha->fw_info.bootload_build = le16_to_cpu(about_fw->bootload_build);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) strcpy((char *)ha->fw_info.extended_timestamp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) skip_spaces((char *)about_fw->extended_timestamp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) ha->fw_uptime_secs = le32_to_cpu(mbox_sts[5]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) ha->fw_uptime_msecs = le32_to_cpu(mbox_sts[6]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) status = QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) exit_about_fw:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) dma_free_coherent(&ha->pdev->dev, sizeof(struct about_fw_info),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) about_fw, about_fw_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) int qla4xxx_get_default_ddb(struct scsi_qla_host *ha, uint32_t options,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) dma_addr_t dma_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) uint32_t mbox_cmd[MBOX_REG_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) uint32_t mbox_sts[MBOX_REG_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) memset(&mbox_cmd, 0, sizeof(mbox_cmd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) memset(&mbox_sts, 0, sizeof(mbox_sts));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) mbox_cmd[0] = MBOX_CMD_GET_DATABASE_ENTRY_DEFAULTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) mbox_cmd[1] = options;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) mbox_cmd[2] = LSDW(dma_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) mbox_cmd[3] = MSDW(dma_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0], &mbox_sts[0]) !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) DEBUG2(printk("scsi%ld: %s: failed status %04X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) ha->host_no, __func__, mbox_sts[0]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) return QLA_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) return QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) int qla4xxx_req_ddb_entry(struct scsi_qla_host *ha, uint32_t ddb_index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) uint32_t *mbx_sts)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) uint32_t mbox_cmd[MBOX_REG_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) uint32_t mbox_sts[MBOX_REG_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) memset(&mbox_cmd, 0, sizeof(mbox_cmd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) memset(&mbox_sts, 0, sizeof(mbox_sts));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) mbox_cmd[0] = MBOX_CMD_REQUEST_DATABASE_ENTRY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) mbox_cmd[1] = ddb_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) &mbox_sts[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) if (status != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) DEBUG2(ql4_printk(KERN_ERR, ha, "%s: failed status %04X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) __func__, mbox_sts[0]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) *mbx_sts = mbox_sts[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) int qla4xxx_clear_ddb_entry(struct scsi_qla_host *ha, uint32_t ddb_index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) uint32_t mbox_cmd[MBOX_REG_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) uint32_t mbox_sts[MBOX_REG_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) memset(&mbox_cmd, 0, sizeof(mbox_cmd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) memset(&mbox_sts, 0, sizeof(mbox_sts));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) mbox_cmd[0] = MBOX_CMD_CLEAR_DATABASE_ENTRY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) mbox_cmd[1] = ddb_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) status = qla4xxx_mailbox_command(ha, 2, 1, &mbox_cmd[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) &mbox_sts[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) if (status != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) DEBUG2(ql4_printk(KERN_ERR, ha, "%s: failed status %04X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) __func__, mbox_sts[0]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) int qla4xxx_set_flash(struct scsi_qla_host *ha, dma_addr_t dma_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) uint32_t offset, uint32_t length, uint32_t options)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) uint32_t mbox_cmd[MBOX_REG_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) uint32_t mbox_sts[MBOX_REG_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) int status = QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) memset(&mbox_cmd, 0, sizeof(mbox_cmd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) memset(&mbox_sts, 0, sizeof(mbox_sts));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) mbox_cmd[0] = MBOX_CMD_WRITE_FLASH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) mbox_cmd[1] = LSDW(dma_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) mbox_cmd[2] = MSDW(dma_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) mbox_cmd[3] = offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) mbox_cmd[4] = length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) mbox_cmd[5] = options;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) status = qla4xxx_mailbox_command(ha, 6, 2, &mbox_cmd[0], &mbox_sts[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) if (status != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) DEBUG2(ql4_printk(KERN_WARNING, ha, "%s: MBOX_CMD_WRITE_FLASH "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) "failed w/ status %04X, mbx1 %04X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) __func__, mbox_sts[0], mbox_sts[1]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) int qla4xxx_bootdb_by_index(struct scsi_qla_host *ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) struct dev_db_entry *fw_ddb_entry,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) dma_addr_t fw_ddb_entry_dma, uint16_t ddb_index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) uint32_t dev_db_start_offset = FLASH_OFFSET_DB_INFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) uint32_t dev_db_end_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) int status = QLA_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) memset(fw_ddb_entry, 0, sizeof(*fw_ddb_entry));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) dev_db_start_offset += (ddb_index * sizeof(*fw_ddb_entry));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) dev_db_end_offset = FLASH_OFFSET_DB_END;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) if (dev_db_start_offset > dev_db_end_offset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) DEBUG2(ql4_printk(KERN_ERR, ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) "%s:Invalid DDB index %d", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) ddb_index));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) goto exit_bootdb_failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) if (qla4xxx_get_flash(ha, fw_ddb_entry_dma, dev_db_start_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) sizeof(*fw_ddb_entry)) != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) ql4_printk(KERN_ERR, ha, "scsi%ld: %s: Get Flash"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) "failed\n", ha->host_no, __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) goto exit_bootdb_failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) if (fw_ddb_entry->cookie == DDB_VALID_COOKIE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) status = QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) exit_bootdb_failed:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) int qla4xxx_flashdb_by_index(struct scsi_qla_host *ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) struct dev_db_entry *fw_ddb_entry,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) dma_addr_t fw_ddb_entry_dma, uint16_t ddb_index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) uint32_t dev_db_start_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) uint32_t dev_db_end_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) int status = QLA_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) memset(fw_ddb_entry, 0, sizeof(*fw_ddb_entry));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) if (is_qla40XX(ha)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) dev_db_start_offset = FLASH_OFFSET_DB_INFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) dev_db_end_offset = FLASH_OFFSET_DB_END;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) dev_db_start_offset = FLASH_RAW_ACCESS_ADDR +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) (ha->hw.flt_region_ddb << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) /* flt_ddb_size is DDB table size for both ports
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) * so divide it by 2 to calculate the offset for second port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) if (ha->port_num == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) dev_db_start_offset += (ha->hw.flt_ddb_size / 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) dev_db_end_offset = dev_db_start_offset +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) (ha->hw.flt_ddb_size / 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) dev_db_start_offset += (ddb_index * sizeof(*fw_ddb_entry));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) if (dev_db_start_offset > dev_db_end_offset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) DEBUG2(ql4_printk(KERN_ERR, ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) "%s:Invalid DDB index %d", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) ddb_index));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) goto exit_fdb_failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) if (qla4xxx_get_flash(ha, fw_ddb_entry_dma, dev_db_start_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) sizeof(*fw_ddb_entry)) != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) ql4_printk(KERN_ERR, ha, "scsi%ld: %s: Get Flash failed\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) ha->host_no, __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) goto exit_fdb_failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) if (fw_ddb_entry->cookie == DDB_VALID_COOKIE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) status = QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) exit_fdb_failed:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) int qla4xxx_get_chap(struct scsi_qla_host *ha, char *username, char *password,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) uint16_t idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) int rval = QLA_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) uint32_t offset = 0, chap_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) struct ql4_chap_table *chap_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) dma_addr_t chap_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) chap_table = dma_pool_zalloc(ha->chap_dma_pool, GFP_KERNEL, &chap_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) if (chap_table == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) chap_size = sizeof(struct ql4_chap_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) if (is_qla40XX(ha))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) offset = FLASH_CHAP_OFFSET | (idx * chap_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) offset = FLASH_RAW_ACCESS_ADDR + (ha->hw.flt_region_chap << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) /* flt_chap_size is CHAP table size for both ports
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) * so divide it by 2 to calculate the offset for second port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) if (ha->port_num == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) offset += (ha->hw.flt_chap_size / 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) offset += (idx * chap_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) rval = qla4xxx_get_flash(ha, chap_dma, offset, chap_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) if (rval != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) goto exit_get_chap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) DEBUG2(ql4_printk(KERN_INFO, ha, "Chap Cookie: x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) __le16_to_cpu(chap_table->cookie)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) if (__le16_to_cpu(chap_table->cookie) != CHAP_VALID_COOKIE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) ql4_printk(KERN_ERR, ha, "No valid chap entry found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) goto exit_get_chap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) strlcpy(password, chap_table->secret, QL4_CHAP_MAX_SECRET_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) strlcpy(username, chap_table->name, QL4_CHAP_MAX_NAME_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) chap_table->cookie = __constant_cpu_to_le16(CHAP_VALID_COOKIE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) exit_get_chap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) dma_pool_free(ha->chap_dma_pool, chap_table, chap_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) * qla4xxx_set_chap - Make a chap entry at the given index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) * @ha: pointer to adapter structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) * @username: CHAP username to set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) * @password: CHAP password to set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) * @idx: CHAP index at which to make the entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) * @bidi: type of chap entry (chap_in or chap_out)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) * Create chap entry at the given index with the information provided.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) * Note: Caller should acquire the chap lock before getting here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) **/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) int qla4xxx_set_chap(struct scsi_qla_host *ha, char *username, char *password,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) uint16_t idx, int bidi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) int rval = QLA_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) uint32_t offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) struct ql4_chap_table *chap_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) uint32_t chap_size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) dma_addr_t chap_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) chap_table = dma_pool_zalloc(ha->chap_dma_pool, GFP_KERNEL, &chap_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) if (chap_table == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) goto exit_set_chap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) if (bidi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) chap_table->flags |= BIT_6; /* peer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) chap_table->flags |= BIT_7; /* local */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) chap_table->secret_len = strlen(password);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) strncpy(chap_table->secret, password, MAX_CHAP_SECRET_LEN - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) strncpy(chap_table->name, username, MAX_CHAP_NAME_LEN - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) chap_table->cookie = __constant_cpu_to_le16(CHAP_VALID_COOKIE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) if (is_qla40XX(ha)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) chap_size = MAX_CHAP_ENTRIES_40XX * sizeof(*chap_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) offset = FLASH_CHAP_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) } else { /* Single region contains CHAP info for both ports which is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) * divided into half for each port.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) chap_size = ha->hw.flt_chap_size / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) offset = FLASH_RAW_ACCESS_ADDR + (ha->hw.flt_region_chap << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) if (ha->port_num == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) offset += chap_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) offset += (idx * sizeof(struct ql4_chap_table));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) rval = qla4xxx_set_flash(ha, chap_dma, offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) sizeof(struct ql4_chap_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) FLASH_OPT_RMW_COMMIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) if (rval == QLA_SUCCESS && ha->chap_list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) /* Update ha chap_list cache */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) memcpy((struct ql4_chap_table *)ha->chap_list + idx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) chap_table, sizeof(struct ql4_chap_table));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) dma_pool_free(ha->chap_dma_pool, chap_table, chap_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) if (rval != QLA_SUCCESS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) exit_set_chap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) int qla4xxx_get_uni_chap_at_index(struct scsi_qla_host *ha, char *username,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) char *password, uint16_t chap_index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) int rval = QLA_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) struct ql4_chap_table *chap_table = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) int max_chap_entries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) if (!ha->chap_list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) ql4_printk(KERN_ERR, ha, "Do not have CHAP table cache\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) rval = QLA_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) goto exit_uni_chap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) if (!username || !password) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) ql4_printk(KERN_ERR, ha, "No memory for username & secret\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) rval = QLA_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) goto exit_uni_chap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) if (is_qla80XX(ha))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) max_chap_entries = (ha->hw.flt_chap_size / 2) /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) sizeof(struct ql4_chap_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) max_chap_entries = MAX_CHAP_ENTRIES_40XX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) if (chap_index > max_chap_entries) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) ql4_printk(KERN_ERR, ha, "Invalid Chap index\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) rval = QLA_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) goto exit_uni_chap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) mutex_lock(&ha->chap_sem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) chap_table = (struct ql4_chap_table *)ha->chap_list + chap_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) if (chap_table->cookie != __constant_cpu_to_le16(CHAP_VALID_COOKIE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) rval = QLA_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) goto exit_unlock_uni_chap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) if (!(chap_table->flags & BIT_7)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) ql4_printk(KERN_ERR, ha, "Unidirectional entry not set\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) rval = QLA_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) goto exit_unlock_uni_chap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) strlcpy(password, chap_table->secret, MAX_CHAP_SECRET_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) strlcpy(username, chap_table->name, MAX_CHAP_NAME_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) rval = QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) exit_unlock_uni_chap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) mutex_unlock(&ha->chap_sem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) exit_uni_chap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) * qla4xxx_get_chap_index - Get chap index given username and secret
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) * @ha: pointer to adapter structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) * @username: CHAP username to be searched
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) * @password: CHAP password to be searched
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) * @bidi: Is this a BIDI CHAP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) * @chap_index: CHAP index to be returned
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) * Match the username and password in the chap_list, return the index if a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) * match is found. If a match is not found then add the entry in FLASH and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) * return the index at which entry is written in the FLASH.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) **/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) int qla4xxx_get_chap_index(struct scsi_qla_host *ha, char *username,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) char *password, int bidi, uint16_t *chap_index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) int i, rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) int free_index = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) int found_index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) int max_chap_entries = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) struct ql4_chap_table *chap_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) if (is_qla80XX(ha))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) max_chap_entries = (ha->hw.flt_chap_size / 2) /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) sizeof(struct ql4_chap_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) max_chap_entries = MAX_CHAP_ENTRIES_40XX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) if (!ha->chap_list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) ql4_printk(KERN_ERR, ha, "Do not have CHAP table cache\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) return QLA_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) if (!username || !password) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) ql4_printk(KERN_ERR, ha, "Do not have username and psw\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) return QLA_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) mutex_lock(&ha->chap_sem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) for (i = 0; i < max_chap_entries; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) chap_table = (struct ql4_chap_table *)ha->chap_list + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) if (chap_table->cookie !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) __constant_cpu_to_le16(CHAP_VALID_COOKIE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) if (i > MAX_RESRV_CHAP_IDX && free_index == -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) free_index = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) if (bidi) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) if (chap_table->flags & BIT_7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) if (chap_table->flags & BIT_6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) if (!strncmp(chap_table->secret, password,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) MAX_CHAP_SECRET_LEN) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) !strncmp(chap_table->name, username,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) MAX_CHAP_NAME_LEN)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) *chap_index = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) found_index = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) /* If chap entry is not present and a free index is available then
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) * write the entry in flash
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) if (!found_index && free_index != -1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) rval = qla4xxx_set_chap(ha, username, password,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) free_index, bidi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) if (!rval) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) *chap_index = free_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) found_index = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) mutex_unlock(&ha->chap_sem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) if (found_index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) return QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) return QLA_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) int qla4xxx_conn_close_sess_logout(struct scsi_qla_host *ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) uint16_t fw_ddb_index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) uint16_t connection_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) uint16_t option)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) uint32_t mbox_cmd[MBOX_REG_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) uint32_t mbox_sts[MBOX_REG_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) int status = QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) memset(&mbox_cmd, 0, sizeof(mbox_cmd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) memset(&mbox_sts, 0, sizeof(mbox_sts));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) mbox_cmd[0] = MBOX_CMD_CONN_CLOSE_SESS_LOGOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) mbox_cmd[1] = fw_ddb_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) mbox_cmd[2] = connection_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) mbox_cmd[3] = option;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) status = qla4xxx_mailbox_command(ha, 4, 2, &mbox_cmd[0], &mbox_sts[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) if (status != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) DEBUG2(ql4_printk(KERN_WARNING, ha, "%s: MBOX_CMD_CONN_CLOSE "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) "option %04x failed w/ status %04X %04X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) __func__, option, mbox_sts[0], mbox_sts[1]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) * qla4_84xx_extend_idc_tmo - Extend IDC Timeout.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) * @ha: Pointer to host adapter structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) * @ext_tmo: idc timeout value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) * Requests firmware to extend the idc timeout value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) **/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) static int qla4_84xx_extend_idc_tmo(struct scsi_qla_host *ha, uint32_t ext_tmo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) uint32_t mbox_cmd[MBOX_REG_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) uint32_t mbox_sts[MBOX_REG_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) memset(&mbox_cmd, 0, sizeof(mbox_cmd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) memset(&mbox_sts, 0, sizeof(mbox_sts));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) ext_tmo &= 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) mbox_cmd[0] = MBOX_CMD_IDC_TIME_EXTEND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) mbox_cmd[1] = ((ha->idc_info.request_desc & 0xfffff0ff) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) (ext_tmo << 8)); /* new timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) mbox_cmd[2] = ha->idc_info.info1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) mbox_cmd[3] = ha->idc_info.info2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) mbox_cmd[4] = ha->idc_info.info3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, MBOX_REG_COUNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) mbox_cmd, mbox_sts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) if (status != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) DEBUG2(ql4_printk(KERN_INFO, ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) "scsi%ld: %s: failed status %04X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) ha->host_no, __func__, mbox_sts[0]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) return QLA_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) ql4_printk(KERN_INFO, ha, "%s: IDC timeout extended by %d secs\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) __func__, ext_tmo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) return QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) int qla4xxx_disable_acb(struct scsi_qla_host *ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) uint32_t mbox_cmd[MBOX_REG_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) uint32_t mbox_sts[MBOX_REG_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) int status = QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) memset(&mbox_cmd, 0, sizeof(mbox_cmd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) memset(&mbox_sts, 0, sizeof(mbox_sts));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) mbox_cmd[0] = MBOX_CMD_DISABLE_ACB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) status = qla4xxx_mailbox_command(ha, 8, 5, &mbox_cmd[0], &mbox_sts[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) if (status != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) DEBUG2(ql4_printk(KERN_WARNING, ha, "%s: MBOX_CMD_DISABLE_ACB "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) "failed w/ status %04X %04X %04X", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) mbox_sts[0], mbox_sts[1], mbox_sts[2]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) if (is_qla8042(ha) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) test_bit(DPC_POST_IDC_ACK, &ha->dpc_flags) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) (mbox_sts[0] != MBOX_STS_COMMAND_COMPLETE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) * Disable ACB mailbox command takes time to complete
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) * based on the total number of targets connected.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) * For 512 targets, it took approximately 5 secs to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) * complete. Setting the timeout value to 8, with the 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) * secs buffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) qla4_84xx_extend_idc_tmo(ha, IDC_EXTEND_TOV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) if (!wait_for_completion_timeout(&ha->disable_acb_comp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) IDC_EXTEND_TOV * HZ)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) ql4_printk(KERN_WARNING, ha, "%s: Disable ACB Completion not received\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) int qla4xxx_get_acb(struct scsi_qla_host *ha, dma_addr_t acb_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) uint32_t acb_type, uint32_t len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) uint32_t mbox_cmd[MBOX_REG_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) uint32_t mbox_sts[MBOX_REG_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) int status = QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) memset(&mbox_cmd, 0, sizeof(mbox_cmd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) memset(&mbox_sts, 0, sizeof(mbox_sts));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) mbox_cmd[0] = MBOX_CMD_GET_ACB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) mbox_cmd[1] = acb_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) mbox_cmd[2] = LSDW(acb_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) mbox_cmd[3] = MSDW(acb_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) mbox_cmd[4] = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) status = qla4xxx_mailbox_command(ha, 5, 5, &mbox_cmd[0], &mbox_sts[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) if (status != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) DEBUG2(ql4_printk(KERN_WARNING, ha, "%s: MBOX_CMD_GET_ACB "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) "failed w/ status %04X\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) mbox_sts[0]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) int qla4xxx_set_acb(struct scsi_qla_host *ha, uint32_t *mbox_cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) uint32_t *mbox_sts, dma_addr_t acb_dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) int status = QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) memset(mbox_cmd, 0, sizeof(mbox_cmd[0]) * MBOX_REG_COUNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) memset(mbox_sts, 0, sizeof(mbox_sts[0]) * MBOX_REG_COUNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) mbox_cmd[0] = MBOX_CMD_SET_ACB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) mbox_cmd[1] = 0; /* Primary ACB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) mbox_cmd[2] = LSDW(acb_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) mbox_cmd[3] = MSDW(acb_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) mbox_cmd[4] = sizeof(struct addr_ctrl_blk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) status = qla4xxx_mailbox_command(ha, 5, 5, &mbox_cmd[0], &mbox_sts[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) if (status != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) DEBUG2(ql4_printk(KERN_WARNING, ha, "%s: MBOX_CMD_SET_ACB "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) "failed w/ status %04X\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) mbox_sts[0]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) int qla4xxx_set_param_ddbentry(struct scsi_qla_host *ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) struct ddb_entry *ddb_entry,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) struct iscsi_cls_conn *cls_conn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) uint32_t *mbx_sts)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) struct dev_db_entry *fw_ddb_entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) struct iscsi_conn *conn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) struct iscsi_session *sess;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) struct qla_conn *qla_conn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) struct sockaddr *dst_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) dma_addr_t fw_ddb_entry_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) int status = QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) int rval = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) struct sockaddr_in *addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) struct sockaddr_in6 *addr6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) char *ip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) uint16_t iscsi_opts = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) uint32_t options = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) uint16_t idx, *ptid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) fw_ddb_entry = dma_alloc_coherent(&ha->pdev->dev, sizeof(*fw_ddb_entry),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) &fw_ddb_entry_dma, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) if (!fw_ddb_entry) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) DEBUG2(ql4_printk(KERN_ERR, ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) "%s: Unable to allocate dma buffer.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) __func__));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) rval = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) goto exit_set_param_no_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) conn = cls_conn->dd_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) qla_conn = conn->dd_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) sess = conn->session;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) dst_addr = (struct sockaddr *)&qla_conn->qla_ep->dst_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) if (dst_addr->sa_family == AF_INET6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) options |= IPV6_DEFAULT_DDB_ENTRY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) status = qla4xxx_get_default_ddb(ha, options, fw_ddb_entry_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) if (status == QLA_ERROR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) rval = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) goto exit_set_param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) ptid = (uint16_t *)&fw_ddb_entry->isid[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) *ptid = cpu_to_le16((uint16_t)ddb_entry->sess->target_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) DEBUG2(ql4_printk(KERN_INFO, ha, "ISID [%pmR]\n", fw_ddb_entry->isid));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) iscsi_opts = le16_to_cpu(fw_ddb_entry->iscsi_options);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) memset(fw_ddb_entry->iscsi_alias, 0, sizeof(fw_ddb_entry->iscsi_alias));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) memset(fw_ddb_entry->iscsi_name, 0, sizeof(fw_ddb_entry->iscsi_name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) if (sess->targetname != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) memcpy(fw_ddb_entry->iscsi_name, sess->targetname,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) min(strlen(sess->targetname),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) sizeof(fw_ddb_entry->iscsi_name)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) memset(fw_ddb_entry->ip_addr, 0, sizeof(fw_ddb_entry->ip_addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) memset(fw_ddb_entry->tgt_addr, 0, sizeof(fw_ddb_entry->tgt_addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) fw_ddb_entry->options = DDB_OPT_TARGET | DDB_OPT_AUTO_SENDTGTS_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) if (dst_addr->sa_family == AF_INET) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) addr = (struct sockaddr_in *)dst_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) ip = (char *)&addr->sin_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) memcpy(fw_ddb_entry->ip_addr, ip, IP_ADDR_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) fw_ddb_entry->port = cpu_to_le16(ntohs(addr->sin_port));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) DEBUG2(ql4_printk(KERN_INFO, ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) "%s: Destination Address [%pI4]: index [%d]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) __func__, fw_ddb_entry->ip_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) ddb_entry->fw_ddb_index));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) } else if (dst_addr->sa_family == AF_INET6) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) addr6 = (struct sockaddr_in6 *)dst_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) ip = (char *)&addr6->sin6_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) memcpy(fw_ddb_entry->ip_addr, ip, IPv6_ADDR_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) fw_ddb_entry->port = cpu_to_le16(ntohs(addr6->sin6_port));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) fw_ddb_entry->options |= DDB_OPT_IPV6_DEVICE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) DEBUG2(ql4_printk(KERN_INFO, ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) "%s: Destination Address [%pI6]: index [%d]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) __func__, fw_ddb_entry->ip_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) ddb_entry->fw_ddb_index));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) ql4_printk(KERN_ERR, ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) "%s: Failed to get IP Address\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) rval = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) goto exit_set_param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) /* CHAP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) if (sess->username != NULL && sess->password != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) if (strlen(sess->username) && strlen(sess->password)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) iscsi_opts |= BIT_7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) rval = qla4xxx_get_chap_index(ha, sess->username,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) sess->password,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) LOCAL_CHAP, &idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) if (rval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) goto exit_set_param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) fw_ddb_entry->chap_tbl_idx = cpu_to_le16(idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) if (sess->username_in != NULL && sess->password_in != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) /* Check if BIDI CHAP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) if (strlen(sess->username_in) && strlen(sess->password_in)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) iscsi_opts |= BIT_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) rval = qla4xxx_get_chap_index(ha, sess->username_in,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) sess->password_in,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) BIDI_CHAP, &idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) if (rval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) goto exit_set_param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) if (sess->initial_r2t_en)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) iscsi_opts |= BIT_10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) if (sess->imm_data_en)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) iscsi_opts |= BIT_11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) fw_ddb_entry->iscsi_options = cpu_to_le16(iscsi_opts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) if (conn->max_recv_dlength)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) fw_ddb_entry->iscsi_max_rcv_data_seg_len =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) __constant_cpu_to_le16((conn->max_recv_dlength / BYTE_UNITS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) if (sess->max_r2t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) fw_ddb_entry->iscsi_max_outsnd_r2t = cpu_to_le16(sess->max_r2t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) if (sess->first_burst)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) fw_ddb_entry->iscsi_first_burst_len =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) __constant_cpu_to_le16((sess->first_burst / BYTE_UNITS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) if (sess->max_burst)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) fw_ddb_entry->iscsi_max_burst_len =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) __constant_cpu_to_le16((sess->max_burst / BYTE_UNITS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) if (sess->time2wait)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) fw_ddb_entry->iscsi_def_time2wait =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) cpu_to_le16(sess->time2wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) if (sess->time2retain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) fw_ddb_entry->iscsi_def_time2retain =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) cpu_to_le16(sess->time2retain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) status = qla4xxx_set_ddb_entry(ha, ddb_entry->fw_ddb_index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) fw_ddb_entry_dma, mbx_sts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) if (status != QLA_SUCCESS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) rval = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) exit_set_param:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) dma_free_coherent(&ha->pdev->dev, sizeof(*fw_ddb_entry),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) fw_ddb_entry, fw_ddb_entry_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) exit_set_param_no_free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) int qla4xxx_get_mgmt_data(struct scsi_qla_host *ha, uint16_t fw_ddb_index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) uint16_t stats_size, dma_addr_t stats_dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) int status = QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) uint32_t mbox_cmd[MBOX_REG_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) uint32_t mbox_sts[MBOX_REG_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) memset(mbox_cmd, 0, sizeof(mbox_cmd[0]) * MBOX_REG_COUNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) memset(mbox_sts, 0, sizeof(mbox_sts[0]) * MBOX_REG_COUNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) mbox_cmd[0] = MBOX_CMD_GET_MANAGEMENT_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) mbox_cmd[1] = fw_ddb_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) mbox_cmd[2] = LSDW(stats_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) mbox_cmd[3] = MSDW(stats_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) mbox_cmd[4] = stats_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) status = qla4xxx_mailbox_command(ha, 5, 1, &mbox_cmd[0], &mbox_sts[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) if (status != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) DEBUG2(ql4_printk(KERN_WARNING, ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) "%s: MBOX_CMD_GET_MANAGEMENT_DATA "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) "failed w/ status %04X\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) mbox_sts[0]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) int qla4xxx_get_ip_state(struct scsi_qla_host *ha, uint32_t acb_idx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) uint32_t ip_idx, uint32_t *sts)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) uint32_t mbox_cmd[MBOX_REG_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) uint32_t mbox_sts[MBOX_REG_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) int status = QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) memset(&mbox_cmd, 0, sizeof(mbox_cmd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) memset(&mbox_sts, 0, sizeof(mbox_sts));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) mbox_cmd[0] = MBOX_CMD_GET_IP_ADDR_STATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) mbox_cmd[1] = acb_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) mbox_cmd[2] = ip_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) status = qla4xxx_mailbox_command(ha, 3, 8, &mbox_cmd[0], &mbox_sts[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) if (status != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) DEBUG2(ql4_printk(KERN_WARNING, ha, "%s: "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) "MBOX_CMD_GET_IP_ADDR_STATE failed w/ "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) "status %04X\n", __func__, mbox_sts[0]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) memcpy(sts, mbox_sts, sizeof(mbox_sts));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) int qla4xxx_get_nvram(struct scsi_qla_host *ha, dma_addr_t nvram_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) uint32_t offset, uint32_t size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) int status = QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) uint32_t mbox_cmd[MBOX_REG_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) uint32_t mbox_sts[MBOX_REG_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) memset(&mbox_cmd, 0, sizeof(mbox_cmd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) memset(&mbox_sts, 0, sizeof(mbox_sts));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) mbox_cmd[0] = MBOX_CMD_GET_NVRAM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) mbox_cmd[1] = LSDW(nvram_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) mbox_cmd[2] = MSDW(nvram_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) mbox_cmd[3] = offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) mbox_cmd[4] = size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) &mbox_sts[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) if (status != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) DEBUG2(ql4_printk(KERN_ERR, ha, "scsi%ld: %s: failed "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) "status %04X\n", ha->host_no, __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) mbox_sts[0]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) int qla4xxx_set_nvram(struct scsi_qla_host *ha, dma_addr_t nvram_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) uint32_t offset, uint32_t size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) int status = QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) uint32_t mbox_cmd[MBOX_REG_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) uint32_t mbox_sts[MBOX_REG_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) memset(&mbox_cmd, 0, sizeof(mbox_cmd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) memset(&mbox_sts, 0, sizeof(mbox_sts));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) mbox_cmd[0] = MBOX_CMD_SET_NVRAM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) mbox_cmd[1] = LSDW(nvram_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) mbox_cmd[2] = MSDW(nvram_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) mbox_cmd[3] = offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) mbox_cmd[4] = size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) &mbox_sts[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) if (status != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) DEBUG2(ql4_printk(KERN_ERR, ha, "scsi%ld: %s: failed "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) "status %04X\n", ha->host_no, __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) mbox_sts[0]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) int qla4xxx_restore_factory_defaults(struct scsi_qla_host *ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) uint32_t region, uint32_t field0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) uint32_t field1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) int status = QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) uint32_t mbox_cmd[MBOX_REG_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) uint32_t mbox_sts[MBOX_REG_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) memset(&mbox_cmd, 0, sizeof(mbox_cmd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) memset(&mbox_sts, 0, sizeof(mbox_sts));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) mbox_cmd[0] = MBOX_CMD_RESTORE_FACTORY_DEFAULTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) mbox_cmd[3] = region;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) mbox_cmd[4] = field0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) mbox_cmd[5] = field1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 3, &mbox_cmd[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) &mbox_sts[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) if (status != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) DEBUG2(ql4_printk(KERN_ERR, ha, "scsi%ld: %s: failed "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) "status %04X\n", ha->host_no, __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) mbox_sts[0]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) * qla4_8xxx_set_param - set driver version in firmware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) * @ha: Pointer to host adapter structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) * @param: Parameter to set i.e driver version
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) **/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) int qla4_8xxx_set_param(struct scsi_qla_host *ha, int param)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) uint32_t mbox_cmd[MBOX_REG_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) uint32_t mbox_sts[MBOX_REG_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) uint32_t status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) memset(&mbox_cmd, 0, sizeof(mbox_cmd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) memset(&mbox_sts, 0, sizeof(mbox_sts));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) mbox_cmd[0] = MBOX_CMD_SET_PARAM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) if (param == SET_DRVR_VERSION) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) mbox_cmd[1] = SET_DRVR_VERSION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) strncpy((char *)&mbox_cmd[2], QLA4XXX_DRIVER_VERSION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) MAX_DRVR_VER_LEN - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) ql4_printk(KERN_ERR, ha, "%s: invalid parameter 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) __func__, param);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) status = QLA_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) goto exit_set_param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 2, mbox_cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) mbox_sts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) if (status == QLA_ERROR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) ql4_printk(KERN_ERR, ha, "%s: failed status %04X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) __func__, mbox_sts[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) exit_set_param:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) * qla4_83xx_post_idc_ack - post IDC ACK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) * @ha: Pointer to host adapter structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) * Posts IDC ACK for IDC Request Notification AEN.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) **/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) int qla4_83xx_post_idc_ack(struct scsi_qla_host *ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) uint32_t mbox_cmd[MBOX_REG_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) uint32_t mbox_sts[MBOX_REG_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) memset(&mbox_cmd, 0, sizeof(mbox_cmd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) memset(&mbox_sts, 0, sizeof(mbox_sts));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) mbox_cmd[0] = MBOX_CMD_IDC_ACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) mbox_cmd[1] = ha->idc_info.request_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) mbox_cmd[2] = ha->idc_info.info1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) mbox_cmd[3] = ha->idc_info.info2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) mbox_cmd[4] = ha->idc_info.info3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, MBOX_REG_COUNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) mbox_cmd, mbox_sts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) if (status == QLA_ERROR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) ql4_printk(KERN_ERR, ha, "%s: failed status %04X\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) mbox_sts[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) ql4_printk(KERN_INFO, ha, "%s: IDC ACK posted\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) int qla4_84xx_config_acb(struct scsi_qla_host *ha, int acb_config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) uint32_t mbox_cmd[MBOX_REG_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) uint32_t mbox_sts[MBOX_REG_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) struct addr_ctrl_blk *acb = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) uint32_t acb_len = sizeof(struct addr_ctrl_blk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) int rval = QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) dma_addr_t acb_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) acb = dma_alloc_coherent(&ha->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) sizeof(struct addr_ctrl_blk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) &acb_dma, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) if (!acb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) ql4_printk(KERN_ERR, ha, "%s: Unable to alloc acb\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) rval = QLA_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) goto exit_config_acb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) memset(acb, 0, acb_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) switch (acb_config) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) case ACB_CONFIG_DISABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) rval = qla4xxx_get_acb(ha, acb_dma, 0, acb_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) if (rval != QLA_SUCCESS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) goto exit_free_acb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) rval = qla4xxx_disable_acb(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) if (rval != QLA_SUCCESS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) goto exit_free_acb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) if (!ha->saved_acb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) ha->saved_acb = kzalloc(acb_len, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) if (!ha->saved_acb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) ql4_printk(KERN_ERR, ha, "%s: Unable to alloc acb\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) rval = QLA_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) goto exit_free_acb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) memcpy(ha->saved_acb, acb, acb_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) case ACB_CONFIG_SET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) if (!ha->saved_acb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) ql4_printk(KERN_ERR, ha, "%s: Can't set ACB, Saved ACB not available\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) rval = QLA_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) goto exit_free_acb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) memcpy(acb, ha->saved_acb, acb_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) rval = qla4xxx_set_acb(ha, &mbox_cmd[0], &mbox_sts[0], acb_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) if (rval != QLA_SUCCESS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) goto exit_free_acb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) ql4_printk(KERN_ERR, ha, "%s: Invalid ACB Configuration\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) exit_free_acb:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) dma_free_coherent(&ha->pdev->dev, sizeof(struct addr_ctrl_blk), acb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) acb_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) exit_config_acb:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) if ((acb_config == ACB_CONFIG_SET) && ha->saved_acb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) kfree(ha->saved_acb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) ha->saved_acb = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) DEBUG2(ql4_printk(KERN_INFO, ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) "%s %s\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) rval == QLA_SUCCESS ? "SUCCEEDED" : "FAILED"));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) int qla4_83xx_get_port_config(struct scsi_qla_host *ha, uint32_t *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) uint32_t mbox_cmd[MBOX_REG_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) uint32_t mbox_sts[MBOX_REG_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) memset(&mbox_cmd, 0, sizeof(mbox_cmd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) memset(&mbox_sts, 0, sizeof(mbox_sts));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) mbox_cmd[0] = MBOX_CMD_GET_PORT_CONFIG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, MBOX_REG_COUNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) mbox_cmd, mbox_sts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) if (status == QLA_SUCCESS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) *config = mbox_sts[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) ql4_printk(KERN_ERR, ha, "%s: failed status %04X\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) mbox_sts[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) int qla4_83xx_set_port_config(struct scsi_qla_host *ha, uint32_t *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) uint32_t mbox_cmd[MBOX_REG_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) uint32_t mbox_sts[MBOX_REG_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) memset(&mbox_cmd, 0, sizeof(mbox_cmd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) memset(&mbox_sts, 0, sizeof(mbox_sts));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) mbox_cmd[0] = MBOX_CMD_SET_PORT_CONFIG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) mbox_cmd[1] = *config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, MBOX_REG_COUNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) mbox_cmd, mbox_sts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) if (status != QLA_SUCCESS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) ql4_printk(KERN_ERR, ha, "%s: failed status %04X\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) mbox_sts[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags