^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * QLogic iSCSI HBA Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (c) 2003-2013 QLogic Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #ifndef _QLA4X_FW_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define _QLA4X_FW_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define MAX_PRST_DEV_DB_ENTRIES 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define MIN_DISC_DEV_DB_ENTRY MAX_PRST_DEV_DB_ENTRIES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define MAX_DEV_DB_ENTRIES 512
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define MAX_DEV_DB_ENTRIES_40XX 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) /*************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * ISP 4010 I/O Register Set Structure and Definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) *************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) struct port_ctrl_stat_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) __le32 ext_hw_conf; /* 0x50 R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) __le32 rsrvd0; /* 0x54 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) __le32 port_ctrl; /* 0x58 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) __le32 port_status; /* 0x5c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) __le32 rsrvd1[32]; /* 0x60-0xdf */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) __le32 gp_out; /* 0xe0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) __le32 gp_in; /* 0xe4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) __le32 rsrvd2[5]; /* 0xe8-0xfb */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) __le32 port_err_status; /* 0xfc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) struct host_mem_cfg_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) __le32 rsrvd0[12]; /* 0x50-0x79 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) __le32 req_q_out; /* 0x80 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) __le32 rsrvd1[31]; /* 0x84-0xFF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * ISP 82xx I/O Register Set structure definitions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) struct device_reg_82xx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) __le32 req_q_out; /* 0x0000 (R): Request Queue out-Pointer. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) __le32 reserve1[63]; /* Request Queue out-Pointer. (64 * 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) __le32 rsp_q_in; /* 0x0100 (R/W): Response Queue In-Pointer. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) __le32 reserve2[63]; /* Response Queue In-Pointer. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) __le32 rsp_q_out; /* 0x0200 (R/W): Response Queue Out-Pointer. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) __le32 reserve3[63]; /* Response Queue Out-Pointer. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) __le32 mailbox_in[8]; /* 0x0300 (R/W): Mail box In registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) __le32 reserve4[24];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) __le32 hint; /* 0x0380 (R/W): Host interrupt register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define HINT_MBX_INT_PENDING BIT_0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) __le32 reserve5[31];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) __le32 mailbox_out[8]; /* 0x0400 (R): Mail box Out registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) __le32 reserve6[56];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) __le32 host_status; /* Offset 0x500 (R): host status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define HSRX_RISC_MB_INT BIT_0 /* RISC to Host Mailbox interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define HSRX_RISC_IOCB_INT BIT_1 /* RISC to Host IOCB interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) __le32 host_int; /* Offset 0x0504 (R/W): Interrupt status. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define ISRX_82XX_RISC_INT BIT_0 /* RISC interrupt. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /* ISP 83xx I/O Register Set structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) struct device_reg_83xx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) __le32 mailbox_in[16]; /* 0x0000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) __le32 reserve1[496]; /* 0x0040 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) __le32 mailbox_out[16]; /* 0x0800 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) __le32 reserve2[496];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) __le32 mbox_int; /* 0x1000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) __le32 reserve3[63];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) __le32 req_q_out; /* 0x1100 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) __le32 reserve4[63];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) __le32 rsp_q_in; /* 0x1200 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) __le32 reserve5[1919];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) __le32 req_q_in; /* 0x3000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) __le32 reserve6[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) __le32 iocb_int_mask; /* 0x3010 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) __le32 reserve7[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) __le32 rsp_q_out; /* 0x3020 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) __le32 reserve8[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) __le32 anonymousbuff; /* 0x3030 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) __le32 mb_int_mask; /* 0x3034 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) __le32 host_intr; /* 0x3038 - Host Interrupt Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) __le32 risc_intr; /* 0x303C - RISC Interrupt Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) __le32 reserve9[544];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) __le32 leg_int_ptr; /* 0x38C0 - Legacy Interrupt Pointer Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) __le32 leg_int_trig; /* 0x38C4 - Legacy Interrupt Trigger Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) __le32 leg_int_mask; /* 0x38C8 - Legacy Interrupt Mask Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define INT_ENABLE_FW_MB (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define INT_MASK_FW_MB (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /* remote register set (access via PCI memory read/write) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) struct isp_reg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define MBOX_REG_COUNT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) __le32 mailbox[MBOX_REG_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) __le32 flash_address; /* 0x20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) __le32 flash_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) __le32 ctrl_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) __le32 nvram;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) __le32 reserved1[2]; /* 0x30 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) } __attribute__ ((packed)) isp4010;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) __le32 intr_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) __le32 nvram; /* 0x30 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) __le32 semaphore;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) } __attribute__ ((packed)) isp4022;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) } u1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) __le32 req_q_in; /* SCSI Request Queue Producer Index */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) __le32 rsp_q_out; /* SCSI Completion Queue Consumer Index */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) __le32 reserved2[4]; /* 0x40 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) __le32 ext_hw_conf; /* 0x50 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) __le32 flow_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) __le32 port_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) __le32 port_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) __le32 reserved3[8]; /* 0x60 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) __le32 req_q_out; /* 0x80 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) __le32 reserved4[23]; /* 0x84 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) __le32 gp_out; /* 0xe0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) __le32 gp_in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) __le32 reserved5[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) __le32 port_err_status; /* 0xfc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) } __attribute__ ((packed)) isp4010;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) struct port_ctrl_stat_regs p0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) struct host_mem_cfg_regs p1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) } __attribute__ ((packed)) isp4022;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) } u2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }; /* 256 x100 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /* Semaphore Defines for 4010 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define QL4010_DRVR_SEM_BITS 0x00000030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define QL4010_GPIO_SEM_BITS 0x000000c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define QL4010_SDRAM_SEM_BITS 0x00000300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define QL4010_PHY_SEM_BITS 0x00000c00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define QL4010_NVRAM_SEM_BITS 0x00003000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define QL4010_FLASH_SEM_BITS 0x0000c000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define QL4010_DRVR_SEM_MASK 0x00300000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define QL4010_GPIO_SEM_MASK 0x00c00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define QL4010_SDRAM_SEM_MASK 0x03000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define QL4010_PHY_SEM_MASK 0x0c000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define QL4010_NVRAM_SEM_MASK 0x30000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define QL4010_FLASH_SEM_MASK 0xc0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /* Semaphore Defines for 4022 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define QL4022_RESOURCE_MASK_BASE_CODE 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define QL4022_RESOURCE_BITS_BASE_CODE 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define QL4022_DRVR_SEM_MASK (QL4022_RESOURCE_MASK_BASE_CODE << (1+16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define QL4022_DDR_RAM_SEM_MASK (QL4022_RESOURCE_MASK_BASE_CODE << (4+16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define QL4022_PHY_GIO_SEM_MASK (QL4022_RESOURCE_MASK_BASE_CODE << (7+16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define QL4022_NVRAM_SEM_MASK (QL4022_RESOURCE_MASK_BASE_CODE << (10+16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define QL4022_FLASH_SEM_MASK (QL4022_RESOURCE_MASK_BASE_CODE << (13+16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /* nvram address for 4032 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define NVRAM_PORT0_BOOT_MODE 0x03b1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define NVRAM_PORT0_BOOT_PRI_TGT 0x03b2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define NVRAM_PORT0_BOOT_SEC_TGT 0x03bb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define NVRAM_PORT1_BOOT_MODE 0x07b1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define NVRAM_PORT1_BOOT_PRI_TGT 0x07b2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define NVRAM_PORT1_BOOT_SEC_TGT 0x07bb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /* Page # defines for 4022 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define PORT_CTRL_STAT_PAGE 0 /* 4022 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define HOST_MEM_CFG_PAGE 1 /* 4022 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define LOCAL_RAM_CFG_PAGE 2 /* 4022 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define PROT_STAT_PAGE 3 /* 4022 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /* Register Mask - sets corresponding mask bits in the upper word */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static inline uint32_t set_rmask(uint32_t val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) return (val & 0xffff) | (val << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static inline uint32_t clr_rmask(uint32_t val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) return 0 | (val << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) /* ctrl_status definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define CSR_SCSI_PAGE_SELECT 0x00000003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define CSR_SCSI_INTR_ENABLE 0x00000004 /* 4010 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define CSR_SCSI_RESET_INTR 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define CSR_SCSI_COMPLETION_INTR 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define CSR_SCSI_PROCESSOR_INTR 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define CSR_INTR_RISC 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define CSR_BOOT_ENABLE 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define CSR_NET_PAGE_SELECT 0x00000300 /* 4010 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define CSR_FUNC_NUM 0x00000700 /* 4022 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define CSR_NET_RESET_INTR 0x00000800 /* 4010 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define CSR_FORCE_SOFT_RESET 0x00002000 /* 4022 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define CSR_FATAL_ERROR 0x00004000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define CSR_SOFT_RESET 0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define ISP_CONTROL_FN_MASK CSR_FUNC_NUM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define ISP_CONTROL_FN0_SCSI 0x0500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define ISP_CONTROL_FN1_SCSI 0x0700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define INTR_PENDING (CSR_SCSI_COMPLETION_INTR |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) CSR_SCSI_PROCESSOR_INTR |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) CSR_SCSI_RESET_INTR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) /* ISP InterruptMask definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define IMR_SCSI_INTR_ENABLE 0x00000004 /* 4022 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) /* ISP 4022 nvram definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define NVR_WRITE_ENABLE 0x00000010 /* 4022 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define QL4010_NVRAM_SIZE 0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define QL40X2_NVRAM_SIZE 0x800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) /* ISP port_status definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) /* ISP Semaphore definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) /* ISP General Purpose Output definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define GPOR_TOPCAT_RESET 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) /* shadow registers (DMA'd from HA to system memory. read only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) struct shadow_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) /* SCSI Request Queue Consumer Index */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) __le32 req_q_out; /* 0 x0 R */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) /* SCSI Completion Queue Producer Index */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) __le32 rsp_q_in; /* 4 x4 R */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }; /* 8 x8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) /* External hardware configuration register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) union external_hw_config_reg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) /* FIXME: Do we even need this? All values are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) * referred to by 16 bit quantities. Platform and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) * endianess issues. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) __le32 bReserved0:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) __le32 bSDRAMProtectionMethod:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) __le32 bSDRAMBanks:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) __le32 bSDRAMChipWidth:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) __le32 bSDRAMChipSize:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) __le32 bParityDisable:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) __le32 bExternalMemoryType:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) __le32 bFlashBIOSWriteEnable:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) __le32 bFlashUpperBankSelect:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) __le32 bWriteBurst:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) __le32 bReserved1:3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) __le32 bMask:16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) uint32_t Asuint32_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) /* 82XX Support start */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) /* 82xx Default FLT Addresses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define FA_FLASH_LAYOUT_ADDR_82 0xFC400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define FA_FLASH_DESCR_ADDR_82 0xFC000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define FA_BOOT_LOAD_ADDR_82 0x04000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define FA_BOOT_CODE_ADDR_82 0x20000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define FA_RISC_CODE_ADDR_82 0x40000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define FA_GOLD_RISC_CODE_ADDR_82 0x80000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define FA_FLASH_ISCSI_CHAP 0x540000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define FA_FLASH_CHAP_SIZE 0xC0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define FA_FLASH_ISCSI_DDB 0x420000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define FA_FLASH_DDB_SIZE 0x080000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) /* Flash Description Table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) struct qla_fdt_layout {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) uint8_t sig[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) uint16_t version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) uint16_t len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) uint16_t checksum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) uint8_t unused1[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) uint8_t model[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) uint16_t man_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) uint16_t id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) uint8_t flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) uint8_t erase_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) uint8_t alt_erase_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) uint8_t wrt_enable_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) uint8_t wrt_enable_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) uint8_t wrt_sts_reg_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) uint8_t unprotect_sec_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) uint8_t read_man_id_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) uint32_t block_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) uint32_t alt_block_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) uint32_t flash_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) uint32_t wrt_enable_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) uint8_t read_id_addr_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) uint8_t wrt_disable_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) uint8_t read_dev_id_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) uint8_t chip_erase_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) uint16_t read_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) uint8_t protect_sec_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) uint8_t unused2[65];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) /* Flash Layout Table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) struct qla_flt_location {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) uint8_t sig[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) uint16_t start_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) uint16_t start_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) uint8_t version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) uint8_t unused[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) uint16_t checksum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) struct qla_flt_header {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) uint16_t version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) uint16_t length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) uint16_t checksum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) uint16_t unused;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) /* 82xx FLT Regions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define FLT_REG_FDT 0x1a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define FLT_REG_FLT 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define FLT_REG_BOOTLOAD_82 0x72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define FLT_REG_FW_82 0x74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define FLT_REG_FW_82_1 0x97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define FLT_REG_GOLD_FW_82 0x75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define FLT_REG_BOOT_CODE_82 0x78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define FLT_REG_ISCSI_PARAM 0x65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define FLT_REG_ISCSI_CHAP 0x63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define FLT_REG_ISCSI_DDB 0x6A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) struct qla_flt_region {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) uint32_t code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) uint32_t size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) uint32_t start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) uint32_t end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) /*************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) * Mailbox Commands Structures and Definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) *************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) /* Mailbox command definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define MBOX_CMD_ABOUT_FW 0x0009
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define MBOX_CMD_PING 0x000B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define PING_IPV6_PROTOCOL_ENABLE 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define PING_IPV6_LINKLOCAL_ADDR 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define PING_IPV6_ADDR0 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define PING_IPV6_ADDR1 0xC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define MBOX_CMD_ENABLE_INTRS 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define INTR_DISABLE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define INTR_ENABLE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define MBOX_CMD_STOP_FW 0x0014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define MBOX_CMD_ABORT_TASK 0x0015
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define MBOX_CMD_LUN_RESET 0x0016
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define MBOX_CMD_TARGET_WARM_RESET 0x0017
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define MBOX_CMD_GET_MANAGEMENT_DATA 0x001E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define MBOX_CMD_GET_FW_STATUS 0x001F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define MBOX_CMD_SET_ISNS_SERVICE 0x0021
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define ISNS_DISABLE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define ISNS_ENABLE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define MBOX_CMD_COPY_FLASH 0x0024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define MBOX_CMD_WRITE_FLASH 0x0025
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define MBOX_CMD_READ_FLASH 0x0026
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define MBOX_CMD_CLEAR_DATABASE_ENTRY 0x0031
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define MBOX_CMD_CONN_OPEN 0x0074
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define MBOX_CMD_CONN_CLOSE_SESS_LOGOUT 0x0056
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define DDB_NOT_LOGGED_IN 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define LOGOUT_OPTION_CLOSE_SESSION 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define LOGOUT_OPTION_RELOGIN 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define LOGOUT_OPTION_FREE_DDB 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define MBOX_CMD_SET_PARAM 0x0059
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define SET_DRVR_VERSION 0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define MAX_DRVR_VER_LEN 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define MBOX_CMD_EXECUTE_IOCB_A64 0x005A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define MBOX_CMD_INITIALIZE_FIRMWARE 0x0060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define MBOX_CMD_GET_INIT_FW_CTRL_BLOCK 0x0061
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define MBOX_CMD_REQUEST_DATABASE_ENTRY 0x0062
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define MBOX_CMD_SET_DATABASE_ENTRY 0x0063
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define MBOX_CMD_GET_DATABASE_ENTRY 0x0064
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #define DDB_DS_UNASSIGNED 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define DDB_DS_NO_CONNECTION_ACTIVE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #define DDB_DS_DISCOVERY 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #define DDB_DS_SESSION_ACTIVE 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define DDB_DS_SESSION_FAILED 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define DDB_DS_LOGIN_IN_PROCESS 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #define MBOX_CMD_GET_FW_STATE 0x0069
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #define MBOX_CMD_GET_INIT_FW_CTRL_BLOCK_DEFAULTS 0x006A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define MBOX_CMD_DIAG_TEST 0x0075
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #define MBOX_CMD_GET_SYS_INFO 0x0078
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #define MBOX_CMD_GET_NVRAM 0x0078 /* For 40xx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #define MBOX_CMD_SET_NVRAM 0x0079 /* For 40xx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #define MBOX_CMD_RESTORE_FACTORY_DEFAULTS 0x0087
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) #define MBOX_CMD_SET_ACB 0x0088
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) #define MBOX_CMD_GET_ACB 0x0089
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #define MBOX_CMD_DISABLE_ACB 0x008A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) #define MBOX_CMD_GET_IPV6_NEIGHBOR_CACHE 0x008B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #define MBOX_CMD_GET_IPV6_DEST_CACHE 0x008C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #define MBOX_CMD_GET_IPV6_DEF_ROUTER_LIST 0x008D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #define MBOX_CMD_GET_IPV6_LCL_PREFIX_LIST 0x008E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #define MBOX_CMD_SET_IPV6_NEIGHBOR_CACHE 0x0090
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #define MBOX_CMD_GET_IP_ADDR_STATE 0x0091
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) #define MBOX_CMD_SEND_IPV6_ROUTER_SOL 0x0092
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) #define MBOX_CMD_GET_DB_ENTRY_CURRENT_IP_ADDR 0x0093
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) #define MBOX_CMD_SET_PORT_CONFIG 0x0122
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #define MBOX_CMD_GET_PORT_CONFIG 0x0123
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) #define MBOX_CMD_SET_LED_CONFIG 0x0125
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) #define MBOX_CMD_GET_LED_CONFIG 0x0126
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) #define MBOX_CMD_MINIDUMP 0x0129
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) /* Port Config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) #define ENABLE_INTERNAL_LOOPBACK 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) #define ENABLE_EXTERNAL_LOOPBACK 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) #define ENABLE_DCBX 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) /* Minidump subcommand */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) #define MINIDUMP_GET_SIZE_SUBCOMMAND 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) #define MINIDUMP_GET_TMPLT_SUBCOMMAND 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) /* Mailbox 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) #define FW_STATE_READY 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) #define FW_STATE_CONFIG_WAIT 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) #define FW_STATE_WAIT_AUTOCONNECT 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) #define FW_STATE_ERROR 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) #define FW_STATE_CONFIGURING_IP 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) /* Mailbox 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) #define FW_ADDSTATE_OPTICAL_MEDIA 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) #define FW_ADDSTATE_DHCPv4_ENABLED 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) #define FW_ADDSTATE_DHCPv4_LEASE_ACQUIRED 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) #define FW_ADDSTATE_DHCPv4_LEASE_EXPIRED 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) #define FW_ADDSTATE_LINK_UP 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) #define FW_ADDSTATE_ISNS_SVC_ENABLED 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) #define FW_ADDSTATE_LINK_SPEED_10MBPS 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) #define FW_ADDSTATE_LINK_SPEED_100MBPS 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) #define FW_ADDSTATE_LINK_SPEED_1GBPS 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) #define FW_ADDSTATE_LINK_SPEED_10GBPS 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) #define MBOX_CMD_GET_DATABASE_ENTRY_DEFAULTS 0x006B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) #define IPV6_DEFAULT_DDB_ENTRY 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) #define MBOX_CMD_CONN_OPEN_SESS_LOGIN 0x0074
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) #define MBOX_CMD_GET_CRASH_RECORD 0x0076 /* 4010 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) #define MBOX_CMD_GET_CONN_EVENT_LOG 0x0077
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) #define MBOX_CMD_IDC_ACK 0x0101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) #define MBOX_CMD_IDC_TIME_EXTEND 0x0102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) #define MBOX_CMD_PORT_RESET 0x0120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) #define MBOX_CMD_SET_PORT_CONFIG 0x0122
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) /* Mailbox status definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) #define MBOX_COMPLETION_STATUS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) #define MBOX_STS_BUSY 0x0007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) #define MBOX_STS_INTERMEDIATE_COMPLETION 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) #define MBOX_STS_COMMAND_COMPLETE 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) #define MBOX_STS_COMMAND_ERROR 0x4005
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) #define MBOX_ASYNC_EVENT_STATUS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) #define MBOX_ASTS_SYSTEM_ERROR 0x8002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) #define MBOX_ASTS_REQUEST_TRANSFER_ERROR 0x8003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) #define MBOX_ASTS_RESPONSE_TRANSFER_ERROR 0x8004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) #define MBOX_ASTS_PROTOCOL_STATISTIC_ALARM 0x8005
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) #define MBOX_ASTS_SCSI_COMMAND_PDU_REJECTED 0x8006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) #define MBOX_ASTS_LINK_UP 0x8010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) #define MBOX_ASTS_LINK_DOWN 0x8011
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) #define MBOX_ASTS_DATABASE_CHANGED 0x8014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) #define MBOX_ASTS_UNSOLICITED_PDU_RECEIVED 0x8015
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) #define MBOX_ASTS_SELF_TEST_FAILED 0x8016
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) #define MBOX_ASTS_LOGIN_FAILED 0x8017
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) #define MBOX_ASTS_DNS 0x8018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) #define MBOX_ASTS_HEARTBEAT 0x8019
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) #define MBOX_ASTS_NVRAM_INVALID 0x801A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) #define MBOX_ASTS_MAC_ADDRESS_CHANGED 0x801B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) #define MBOX_ASTS_IP_ADDRESS_CHANGED 0x801C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) #define MBOX_ASTS_DHCP_LEASE_EXPIRED 0x801D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) #define MBOX_ASTS_DHCP_LEASE_ACQUIRED 0x801F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) #define MBOX_ASTS_ISNS_UNSOLICITED_PDU_RECEIVED 0x8021
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) #define MBOX_ASTS_DUPLICATE_IP 0x8025
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) #define MBOX_ASTS_ARP_COMPLETE 0x8026
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) #define MBOX_ASTS_SUBNET_STATE_CHANGE 0x8027
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) #define MBOX_ASTS_RESPONSE_QUEUE_FULL 0x8028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) #define MBOX_ASTS_IP_ADDR_STATE_CHANGED 0x8029
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) #define MBOX_ASTS_IPV6_DEFAULT_ROUTER_CHANGED 0x802A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) #define MBOX_ASTS_IPV6_LINK_MTU_CHANGE 0x802B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) #define MBOX_ASTS_IPV6_AUTO_PREFIX_IGNORED 0x802C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) #define MBOX_ASTS_IPV6_ND_LOCAL_PREFIX_IGNORED 0x802D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) #define MBOX_ASTS_ICMPV6_ERROR_MSG_RCVD 0x802E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) #define MBOX_ASTS_INITIALIZATION_FAILED 0x8031
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) #define MBOX_ASTS_SYSTEM_WARNING_EVENT 0x8036
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) #define MBOX_ASTS_IDC_COMPLETE 0x8100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) #define MBOX_ASTS_IDC_REQUEST_NOTIFICATION 0x8101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) #define MBOX_ASTS_IDC_TIME_EXTEND_NOTIFICATION 0x8102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) #define MBOX_ASTS_DCBX_CONF_CHANGE 0x8110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) #define MBOX_ASTS_TXSCVR_INSERTED 0x8130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) #define MBOX_ASTS_TXSCVR_REMOVED 0x8131
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) #define ISNS_EVENT_DATA_RECEIVED 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) #define ISNS_EVENT_CONNECTION_OPENED 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) #define ISNS_EVENT_CONNECTION_FAILED 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) #define MBOX_ASTS_IPSEC_SYSTEM_FATAL_ERROR 0x8022
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) #define MBOX_ASTS_SUBNET_STATE_CHANGE 0x8027
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) /* ACB Configuration Defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) #define ACB_CONFIG_DISABLE 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) #define ACB_CONFIG_SET 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) /* ACB/IP Address State Defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) #define IP_ADDRSTATE_UNCONFIGURED 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) #define IP_ADDRSTATE_INVALID 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) #define IP_ADDRSTATE_ACQUIRING 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) #define IP_ADDRSTATE_TENTATIVE 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) #define IP_ADDRSTATE_DEPRICATED 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) #define IP_ADDRSTATE_PREFERRED 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) #define IP_ADDRSTATE_DISABLING 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) /* FLASH offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) #define FLASH_SEGMENT_IFCB 0x04000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) #define FLASH_OPT_RMW_HOLD 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) #define FLASH_OPT_RMW_INIT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) #define FLASH_OPT_COMMIT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) #define FLASH_OPT_RMW_COMMIT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) /* generic defines to enable/disable params */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) #define QL4_PARAM_DISABLE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) #define QL4_PARAM_ENABLE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) /*************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) /* Host Adapter Initialization Control Block (from host) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) struct addr_ctrl_blk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) uint8_t version; /* 00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) #define IFCB_VER_MIN 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) #define IFCB_VER_MAX 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) uint8_t control; /* 01 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) #define CTRLOPT_NEW_CONN_DISABLE 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) uint16_t fw_options; /* 02-03 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) #define FWOPT_HEARTBEAT_ENABLE 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) #define FWOPT_SESSION_MODE 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) #define FWOPT_INITIATOR_MODE 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) #define FWOPT_TARGET_MODE 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) #define FWOPT_ENABLE_CRBDB 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) uint16_t exec_throttle; /* 04-05 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) uint8_t zio_count; /* 06 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) uint8_t res0; /* 07 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) uint16_t eth_mtu_size; /* 08-09 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) uint16_t add_fw_options; /* 0A-0B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) #define ADFWOPT_SERIALIZE_TASK_MGMT 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) #define ADFWOPT_AUTOCONN_DISABLE 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) uint8_t hb_interval; /* 0C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) uint8_t inst_num; /* 0D */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) uint16_t res1; /* 0E-0F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) uint16_t rqq_consumer_idx; /* 10-11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) uint16_t compq_producer_idx; /* 12-13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) uint16_t rqq_len; /* 14-15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) uint16_t compq_len; /* 16-17 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) uint32_t rqq_addr_lo; /* 18-1B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) uint32_t rqq_addr_hi; /* 1C-1F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) uint32_t compq_addr_lo; /* 20-23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) uint32_t compq_addr_hi; /* 24-27 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) uint32_t shdwreg_addr_lo; /* 28-2B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) uint32_t shdwreg_addr_hi; /* 2C-2F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) uint16_t iscsi_opts; /* 30-31 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) #define ISCSIOPTS_HEADER_DIGEST_EN 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) #define ISCSIOPTS_DATA_DIGEST_EN 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) #define ISCSIOPTS_IMMEDIATE_DATA_EN 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) #define ISCSIOPTS_INITIAL_R2T_EN 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) #define ISCSIOPTS_DATA_SEQ_INORDER_EN 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) #define ISCSIOPTS_DATA_PDU_INORDER_EN 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) #define ISCSIOPTS_CHAP_AUTH_EN 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) #define ISCSIOPTS_SNACK_EN 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) #define ISCSIOPTS_DISCOVERY_LOGOUT_EN 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) #define ISCSIOPTS_BIDI_CHAP_EN 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) #define ISCSIOPTS_DISCOVERY_AUTH_EN 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) #define ISCSIOPTS_STRICT_LOGIN_COMP_EN 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) #define ISCSIOPTS_ERL 0x0003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) uint16_t ipv4_tcp_opts; /* 32-33 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) #define TCPOPT_DELAYED_ACK_DISABLE 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) #define TCPOPT_DHCP_ENABLE 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) #define TCPOPT_DNS_SERVER_IP_EN 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) #define TCPOPT_SLP_DA_INFO_EN 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) #define TCPOPT_NAGLE_ALGO_DISABLE 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) #define TCPOPT_WINDOW_SCALE_DISABLE 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) #define TCPOPT_TIMER_SCALE 0x000E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) #define TCPOPT_TIMESTAMP_ENABLE 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) uint16_t ipv4_ip_opts; /* 34-35 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) #define IPOPT_IPV4_PROTOCOL_ENABLE 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) #define IPOPT_IPV4_TOS_EN 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) #define IPOPT_VLAN_TAGGING_ENABLE 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) #define IPOPT_GRAT_ARP_EN 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) #define IPOPT_ALT_CID_EN 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) #define IPOPT_REQ_VID_EN 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) #define IPOPT_USE_VID_EN 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) #define IPOPT_LEARN_IQN_EN 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) #define IPOPT_FRAGMENTATION_DISABLE 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) #define IPOPT_IN_FORWARD_EN 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) #define IPOPT_ARP_REDIRECT_EN 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) uint16_t iscsi_max_pdu_size; /* 36-37 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) uint8_t ipv4_tos; /* 38 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) uint8_t ipv4_ttl; /* 39 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) uint8_t acb_version; /* 3A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) #define ACB_NOT_SUPPORTED 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) #define ACB_SUPPORTED 0x02 /* Capable of ACB Version 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) Features */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) uint8_t res2; /* 3B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) uint16_t def_timeout; /* 3C-3D */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) uint16_t iscsi_fburst_len; /* 3E-3F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) uint16_t iscsi_def_time2wait; /* 40-41 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) uint16_t iscsi_def_time2retain; /* 42-43 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) uint16_t iscsi_max_outstnd_r2t; /* 44-45 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) uint16_t conn_ka_timeout; /* 46-47 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) uint16_t ipv4_port; /* 48-49 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) uint16_t iscsi_max_burst_len; /* 4A-4B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) uint32_t res5; /* 4C-4F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) uint8_t ipv4_addr[4]; /* 50-53 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) uint16_t ipv4_vlan_tag; /* 54-55 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) uint8_t ipv4_addr_state; /* 56 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) uint8_t ipv4_cacheid; /* 57 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) uint8_t res6[8]; /* 58-5F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) uint8_t ipv4_subnet[4]; /* 60-63 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) uint8_t res7[12]; /* 64-6F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) uint8_t ipv4_gw_addr[4]; /* 70-73 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) uint8_t res8[0xc]; /* 74-7F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) uint8_t pri_dns_srvr_ip[4];/* 80-83 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) uint8_t sec_dns_srvr_ip[4];/* 84-87 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) uint16_t min_eph_port; /* 88-89 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) uint16_t max_eph_port; /* 8A-8B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) uint8_t res9[4]; /* 8C-8F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) uint8_t iscsi_alias[32];/* 90-AF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) uint8_t res9_1[0x16]; /* B0-C5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) uint16_t tgt_portal_grp;/* C6-C7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) uint8_t abort_timer; /* C8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) uint8_t ipv4_tcp_wsf; /* C9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) uint8_t res10[6]; /* CA-CF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) uint8_t ipv4_sec_ip_addr[4]; /* D0-D3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) uint8_t ipv4_dhcp_vid_len; /* D4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) uint8_t ipv4_dhcp_vid[11]; /* D5-DF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) uint8_t res11[20]; /* E0-F3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) uint8_t ipv4_dhcp_alt_cid_len; /* F4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) uint8_t ipv4_dhcp_alt_cid[11]; /* F5-FF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) uint8_t iscsi_name[224]; /* 100-1DF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) uint8_t res12[32]; /* 1E0-1FF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) uint32_t cookie; /* 200-203 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) uint16_t ipv6_port; /* 204-205 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) uint16_t ipv6_opts; /* 206-207 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) #define IPV6_OPT_IPV6_PROTOCOL_ENABLE 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) #define IPV6_OPT_VLAN_TAGGING_ENABLE 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) #define IPV6_OPT_GRAT_NEIGHBOR_ADV_EN 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) #define IPV6_OPT_REDIRECT_EN 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) uint16_t ipv6_addtl_opts; /* 208-209 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) #define IPV6_ADDOPT_IGNORE_ICMP_ECHO_REQ 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) #define IPV6_ADDOPT_MLD_EN 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) #define IPV6_ADDOPT_NEIGHBOR_DISCOVERY_ADDR_ENABLE 0x0002 /* Pri ACB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) Only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) #define IPV6_ADDOPT_AUTOCONFIG_LINK_LOCAL_ADDR 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) uint16_t ipv6_tcp_opts; /* 20A-20B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) #define IPV6_TCPOPT_DELAYED_ACK_DISABLE 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) #define IPV6_TCPOPT_NAGLE_ALGO_DISABLE 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) #define IPV6_TCPOPT_WINDOW_SCALE_DISABLE 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) #define IPV6_TCPOPT_TIMER_SCALE 0x000E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) #define IPV6_TCPOPT_TIMESTAMP_EN 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) uint8_t ipv6_tcp_wsf; /* 20C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) uint16_t ipv6_flow_lbl; /* 20D-20F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) uint8_t ipv6_dflt_rtr_addr[16]; /* 210-21F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) uint16_t ipv6_vlan_tag; /* 220-221 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) uint8_t ipv6_lnk_lcl_addr_state;/* 222 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) uint8_t ipv6_addr0_state; /* 223 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) uint8_t ipv6_addr1_state; /* 224 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) uint8_t ipv6_dflt_rtr_state; /* 225 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) #define IPV6_RTRSTATE_UNKNOWN 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) #define IPV6_RTRSTATE_MANUAL 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) #define IPV6_RTRSTATE_ADVERTISED 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) #define IPV6_RTRSTATE_STALE 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) uint8_t ipv6_traffic_class; /* 226 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) uint8_t ipv6_hop_limit; /* 227 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) uint8_t ipv6_if_id[8]; /* 228-22F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) uint8_t ipv6_addr0[16]; /* 230-23F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) uint8_t ipv6_addr1[16]; /* 240-24F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) uint32_t ipv6_nd_reach_time; /* 250-253 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) uint32_t ipv6_nd_rexmit_timer; /* 254-257 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) uint32_t ipv6_nd_stale_timeout; /* 258-25B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) uint8_t ipv6_dup_addr_detect_count; /* 25C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) uint8_t ipv6_cache_id; /* 25D */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) uint8_t res13[18]; /* 25E-26F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) uint32_t ipv6_gw_advrt_mtu; /* 270-273 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) uint8_t res14[140]; /* 274-2FF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) #define IP_ADDR_COUNT 4 /* Total 4 IP address supported in one interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) * One IPv4, one IPv6 link local and 2 IPv6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) #define IP_STATE_MASK 0x0F000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) #define IP_STATE_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) struct init_fw_ctrl_blk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) struct addr_ctrl_blk pri;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) /* struct addr_ctrl_blk sec;*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) #define PRIMARI_ACB 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) #define SECONDARY_ACB 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) struct addr_ctrl_blk_def {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) uint8_t reserved1[1]; /* 00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) uint8_t control; /* 01 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) uint8_t reserved2[11]; /* 02-0C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) uint8_t inst_num; /* 0D */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) uint8_t reserved3[34]; /* 0E-2F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) uint16_t iscsi_opts; /* 30-31 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) uint16_t ipv4_tcp_opts; /* 32-33 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) uint16_t ipv4_ip_opts; /* 34-35 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) uint16_t iscsi_max_pdu_size; /* 36-37 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) uint8_t ipv4_tos; /* 38 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) uint8_t ipv4_ttl; /* 39 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) uint8_t reserved4[2]; /* 3A-3B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) uint16_t def_timeout; /* 3C-3D */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) uint16_t iscsi_fburst_len; /* 3E-3F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) uint8_t reserved5[4]; /* 40-43 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) uint16_t iscsi_max_outstnd_r2t; /* 44-45 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) uint8_t reserved6[2]; /* 46-47 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) uint16_t ipv4_port; /* 48-49 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) uint16_t iscsi_max_burst_len; /* 4A-4B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) uint8_t reserved7[4]; /* 4C-4F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) uint8_t ipv4_addr[4]; /* 50-53 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) uint16_t ipv4_vlan_tag; /* 54-55 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) uint8_t ipv4_addr_state; /* 56 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) uint8_t ipv4_cacheid; /* 57 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) uint8_t reserved8[8]; /* 58-5F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) uint8_t ipv4_subnet[4]; /* 60-63 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) uint8_t reserved9[12]; /* 64-6F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) uint8_t ipv4_gw_addr[4]; /* 70-73 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) uint8_t reserved10[84]; /* 74-C7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) uint8_t abort_timer; /* C8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) uint8_t ipv4_tcp_wsf; /* C9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) uint8_t reserved11[10]; /* CA-D3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) uint8_t ipv4_dhcp_vid_len; /* D4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) uint8_t ipv4_dhcp_vid[11]; /* D5-DF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) uint8_t reserved12[20]; /* E0-F3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) uint8_t ipv4_dhcp_alt_cid_len; /* F4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) uint8_t ipv4_dhcp_alt_cid[11]; /* F5-FF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) uint8_t iscsi_name[224]; /* 100-1DF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) uint8_t reserved13[32]; /* 1E0-1FF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) uint32_t cookie; /* 200-203 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) uint16_t ipv6_port; /* 204-205 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) uint16_t ipv6_opts; /* 206-207 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) uint16_t ipv6_addtl_opts; /* 208-209 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) uint16_t ipv6_tcp_opts; /* 20A-20B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) uint8_t ipv6_tcp_wsf; /* 20C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) uint16_t ipv6_flow_lbl; /* 20D-20F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) uint8_t ipv6_dflt_rtr_addr[16]; /* 210-21F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) uint16_t ipv6_vlan_tag; /* 220-221 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) uint8_t ipv6_lnk_lcl_addr_state; /* 222 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) uint8_t ipv6_addr0_state; /* 223 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) uint8_t ipv6_addr1_state; /* 224 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) uint8_t ipv6_dflt_rtr_state; /* 225 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) uint8_t ipv6_traffic_class; /* 226 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) uint8_t ipv6_hop_limit; /* 227 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) uint8_t ipv6_if_id[8]; /* 228-22F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) uint8_t ipv6_addr0[16]; /* 230-23F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) uint8_t ipv6_addr1[16]; /* 240-24F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) uint32_t ipv6_nd_reach_time; /* 250-253 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) uint32_t ipv6_nd_rexmit_timer; /* 254-257 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) uint32_t ipv6_nd_stale_timeout; /* 258-25B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) uint8_t ipv6_dup_addr_detect_count; /* 25C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) uint8_t ipv6_cache_id; /* 25D */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) uint8_t reserved14[18]; /* 25E-26F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) uint32_t ipv6_gw_advrt_mtu; /* 270-273 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) uint8_t reserved15[140]; /* 274-2FF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) /*************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) #define MAX_CHAP_ENTRIES_40XX 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) #define MAX_CHAP_ENTRIES_82XX 1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) #define MAX_RESRV_CHAP_IDX 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) #define FLASH_CHAP_OFFSET 0x06000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) struct ql4_chap_table {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) uint16_t link;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) uint8_t flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) uint8_t secret_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) #define MIN_CHAP_SECRET_LEN 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) #define MAX_CHAP_SECRET_LEN 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) uint8_t secret[MAX_CHAP_SECRET_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) #define MAX_CHAP_NAME_LEN 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) uint8_t name[MAX_CHAP_NAME_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) uint16_t reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) #define CHAP_VALID_COOKIE 0x4092
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) #define CHAP_INVALID_COOKIE 0xFFEE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) uint16_t cookie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) struct dev_db_entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) uint16_t options; /* 00-01 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) #define DDB_OPT_DISC_SESSION 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) #define DDB_OPT_TARGET 0x02 /* device is a target */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) #define DDB_OPT_IPV6_DEVICE 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) #define DDB_OPT_AUTO_SENDTGTS_DISABLE 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) #define DDB_OPT_IPV6_NULL_LINK_LOCAL 0x800 /* post connection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) #define DDB_OPT_IPV6_FW_DEFINED_LINK_LOCAL 0x800 /* pre connection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) #define OPT_IS_FW_ASSIGNED_IPV6 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) #define OPT_IPV6_DEVICE 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) #define OPT_AUTO_SENDTGTS_DISABLE 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) #define OPT_DISC_SESSION 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) #define OPT_ENTRY_STATE 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) uint16_t exec_throttle; /* 02-03 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) uint16_t exec_count; /* 04-05 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) uint16_t res0; /* 06-07 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) uint16_t iscsi_options; /* 08-09 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) #define ISCSIOPT_HEADER_DIGEST_EN 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) #define ISCSIOPT_DATA_DIGEST_EN 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) #define ISCSIOPT_IMMEDIATE_DATA_EN 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) #define ISCSIOPT_INITIAL_R2T_EN 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) #define ISCSIOPT_DATA_SEQ_IN_ORDER 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) #define ISCSIOPT_DATA_PDU_IN_ORDER 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) #define ISCSIOPT_CHAP_AUTH_EN 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) #define ISCSIOPT_SNACK_REQ_EN 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) #define ISCSIOPT_DISCOVERY_LOGOUT_EN 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) #define ISCSIOPT_BIDI_CHAP_EN 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) #define ISCSIOPT_DISCOVERY_AUTH_OPTIONAL 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) #define ISCSIOPT_ERL1 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) #define ISCSIOPT_ERL0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) uint16_t tcp_options; /* 0A-0B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) #define TCPOPT_TIMESTAMP_STAT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) #define TCPOPT_NAGLE_DISABLE 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) #define TCPOPT_WSF_DISABLE 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) #define TCPOPT_TIMER_SCALE3 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) #define TCPOPT_TIMER_SCALE2 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) #define TCPOPT_TIMER_SCALE1 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) #define TCPOPT_TIMESTAMP_EN 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) uint16_t ip_options; /* 0C-0D */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) #define IPOPT_FRAGMENT_DISABLE 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) uint16_t iscsi_max_rcv_data_seg_len; /* 0E-0F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) #define BYTE_UNITS 512
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) uint32_t res1; /* 10-13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) uint16_t iscsi_max_snd_data_seg_len; /* 14-15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) uint16_t iscsi_first_burst_len; /* 16-17 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) uint16_t iscsi_def_time2wait; /* 18-19 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) uint16_t iscsi_def_time2retain; /* 1A-1B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) uint16_t iscsi_max_outsnd_r2t; /* 1C-1D */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) uint16_t ka_timeout; /* 1E-1F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) uint8_t isid[6]; /* 20-25 big-endian, must be converted
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) * to little-endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) uint16_t tsid; /* 26-27 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) uint16_t port; /* 28-29 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) uint16_t iscsi_max_burst_len; /* 2A-2B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) uint16_t def_timeout; /* 2C-2D */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) uint16_t res2; /* 2E-2F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) uint8_t ip_addr[0x10]; /* 30-3F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) uint8_t iscsi_alias[0x20]; /* 40-5F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) uint8_t tgt_addr[0x20]; /* 60-7F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) uint16_t mss; /* 80-81 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) uint16_t res3; /* 82-83 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) uint16_t lcl_port; /* 84-85 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) uint8_t ipv4_tos; /* 86 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) uint16_t ipv6_flow_lbl; /* 87-89 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) uint8_t res4[0x36]; /* 8A-BF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) uint8_t iscsi_name[0xE0]; /* C0-19F : xxzzy Make this a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) * pointer to a string so we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) * don't have to reserve so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) * much RAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) uint8_t link_local_ipv6_addr[0x10]; /* 1A0-1AF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) uint8_t res5[0x10]; /* 1B0-1BF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) #define DDB_NO_LINK 0xFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) #define DDB_ISNS 0xFFFD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) uint16_t ddb_link; /* 1C0-1C1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) uint16_t chap_tbl_idx; /* 1C2-1C3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) uint16_t tgt_portal_grp; /* 1C4-1C5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) uint8_t tcp_xmt_wsf; /* 1C6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) uint8_t tcp_rcv_wsf; /* 1C7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) uint32_t stat_sn; /* 1C8-1CB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) uint32_t exp_stat_sn; /* 1CC-1CF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) uint8_t res6[0x2b]; /* 1D0-1FB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) #define DDB_VALID_COOKIE 0x9034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) uint16_t cookie; /* 1FC-1FD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) uint16_t len; /* 1FE-1FF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) /*************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) /* Flash definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) #define FLASH_OFFSET_SYS_INFO 0x02000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) #define FLASH_DEFAULTBLOCKSIZE 0x20000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) #define FLASH_EOF_OFFSET (FLASH_DEFAULTBLOCKSIZE-8) /* 4 bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) * for EOF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) * signature */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) #define FLASH_RAW_ACCESS_ADDR 0x8e000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) #define BOOT_PARAM_OFFSET_PORT0 0x3b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) #define BOOT_PARAM_OFFSET_PORT1 0x7b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) #define FLASH_OFFSET_DB_INFO 0x05000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) #define FLASH_OFFSET_DB_END (FLASH_OFFSET_DB_INFO + 0x7fff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) struct sys_info_phys_addr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) uint8_t address[6]; /* 00-05 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) uint8_t filler[2]; /* 06-07 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) struct flash_sys_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) uint32_t cookie; /* 00-03 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) uint32_t physAddrCount; /* 04-07 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) struct sys_info_phys_addr physAddr[4]; /* 08-27 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) uint8_t vendorId[128]; /* 28-A7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) uint8_t productId[128]; /* A8-127 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) uint32_t serialNumber; /* 128-12B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) /* PCI Configuration values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) uint32_t pciDeviceVendor; /* 12C-12F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) uint32_t pciDeviceId; /* 130-133 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) uint32_t pciSubsysVendor; /* 134-137 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) uint32_t pciSubsysId; /* 138-13B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) /* This validates version 1. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) uint32_t crumbs; /* 13C-13F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) uint32_t enterpriseNumber; /* 140-143 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) uint32_t mtu; /* 144-147 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) uint32_t reserved0; /* 148-14b */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) uint32_t crumbs2; /* 14c-14f */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) uint8_t acSerialNumber[16]; /* 150-15f */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) uint32_t crumbs3; /* 160-16f */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) /* Leave this last in the struct so it is declared invalid if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) * any new items are added.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) uint32_t reserved1[39]; /* 170-1ff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) }; /* 200 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) struct mbx_sys_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) uint8_t board_id_str[16]; /* 0-f Keep board ID string first */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) /* in this structure for GUI. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) uint16_t board_id; /* 10-11 board ID code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) uint16_t phys_port_cnt; /* 12-13 number of physical network ports */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) uint16_t port_num; /* 14-15 network port for this PCI function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) /* (port 0 is first port) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) uint8_t mac_addr[6]; /* 16-1b MAC address for this PCI function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) uint32_t iscsi_pci_func_cnt; /* 1c-1f number of iSCSI PCI functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) uint32_t pci_func; /* 20-23 this PCI function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) unsigned char serial_number[16]; /* 24-33 serial number string */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) uint8_t reserved[12]; /* 34-3f */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) struct about_fw_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) uint16_t fw_major; /* 00 - 01 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) uint16_t fw_minor; /* 02 - 03 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) uint16_t fw_patch; /* 04 - 05 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) uint16_t fw_build; /* 06 - 07 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) uint8_t fw_build_date[16]; /* 08 - 17 ASCII String */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) uint8_t fw_build_time[16]; /* 18 - 27 ASCII String */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) uint8_t fw_build_user[16]; /* 28 - 37 ASCII String */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) uint16_t fw_load_source; /* 38 - 39 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) /* 1 = Flash Primary,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) 2 = Flash Secondary,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) 3 = Host Download
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) uint8_t reserved1[6]; /* 3A - 3F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) uint16_t iscsi_major; /* 40 - 41 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) uint16_t iscsi_minor; /* 42 - 43 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) uint16_t bootload_major; /* 44 - 45 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) uint16_t bootload_minor; /* 46 - 47 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) uint16_t bootload_patch; /* 48 - 49 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) uint16_t bootload_build; /* 4A - 4B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) uint8_t extended_timestamp[180];/* 4C - FF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) struct crash_record {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) uint16_t fw_major_version; /* 00 - 01 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) uint16_t fw_minor_version; /* 02 - 03 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) uint16_t fw_patch_version; /* 04 - 05 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) uint16_t fw_build_version; /* 06 - 07 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) uint8_t build_date[16]; /* 08 - 17 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) uint8_t build_time[16]; /* 18 - 27 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) uint8_t build_user[16]; /* 28 - 37 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) uint8_t card_serial_num[16]; /* 38 - 47 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) uint32_t time_of_crash_in_secs; /* 48 - 4B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) uint32_t time_of_crash_in_ms; /* 4C - 4F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) uint16_t out_RISC_sd_num_frames; /* 50 - 51 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) uint16_t OAP_sd_num_words; /* 52 - 53 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) uint16_t IAP_sd_num_frames; /* 54 - 55 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) uint16_t in_RISC_sd_num_words; /* 56 - 57 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) uint8_t reserved1[28]; /* 58 - 7F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) uint8_t out_RISC_reg_dump[256]; /* 80 -17F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) uint8_t in_RISC_reg_dump[256]; /*180 -27F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) uint8_t in_out_RISC_stack_dump[0]; /*280 - ??? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) struct conn_event_log_entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) #define MAX_CONN_EVENT_LOG_ENTRIES 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) uint32_t timestamp_sec; /* 00 - 03 seconds since boot */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) uint32_t timestamp_ms; /* 04 - 07 milliseconds since boot */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) uint16_t device_index; /* 08 - 09 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) uint16_t fw_conn_state; /* 0A - 0B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) uint8_t event_type; /* 0C - 0C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) uint8_t error_code; /* 0D - 0D */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) uint16_t error_code_detail; /* 0E - 0F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) uint8_t num_consecutive_events; /* 10 - 10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) uint8_t rsvd[3]; /* 11 - 13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) /*************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) * IOCB Commands Structures and Definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) *************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) #define IOCB_MAX_CDB_LEN 16 /* Bytes in a CBD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) #define IOCB_MAX_SENSEDATA_LEN 32 /* Bytes of sense data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) #define IOCB_MAX_EXT_SENSEDATA_LEN 60 /* Bytes of extended sense data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) /* IOCB header structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) struct qla4_header {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) uint8_t entryType;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) #define ET_STATUS 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) #define ET_MARKER 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) #define ET_CONT_T1 0x0A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) #define ET_STATUS_CONTINUATION 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) #define ET_CMND_T3 0x19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) #define ET_PASSTHRU0 0x3A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) #define ET_PASSTHRU_STATUS 0x3C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) #define ET_MBOX_CMD 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) #define ET_MBOX_STATUS 0x39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) uint8_t entryStatus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) uint8_t systemDefined;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) #define SD_ISCSI_PDU 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) uint8_t entryCount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) /* SyetemDefined definition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) /* Generic queue entry structure*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) struct queue_entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) uint8_t data[60];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) uint32_t signature;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) /* 64 bit addressing segment counts*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) #define COMMAND_SEG_A64 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) #define CONTINUE_SEG_A64 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) /* 64 bit addressing segment definition*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) struct data_seg_a64 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) uint32_t addrLow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) uint32_t addrHigh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) } base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) uint32_t count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) /* Command Type 3 entry structure*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) struct command_t3_entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) struct qla4_header hdr; /* 00-03 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) uint32_t handle; /* 04-07 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) uint16_t target; /* 08-09 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) uint16_t connection_id; /* 0A-0B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) uint8_t control_flags; /* 0C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) /* data direction (bits 5-6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) #define CF_WRITE 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) #define CF_READ 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) #define CF_NO_DATA 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) /* task attributes (bits 2-0) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) #define CF_HEAD_TAG 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) #define CF_ORDERED_TAG 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) #define CF_SIMPLE_TAG 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) /* STATE FLAGS FIELD IS A PLACE HOLDER. THE FW WILL SET BITS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) * IN THIS FIELD AS THE COMMAND IS PROCESSED. WHEN THE IOCB IS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) * CHANGED TO AN IOSB THIS FIELD WILL HAVE THE STATE FLAGS SET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) * PROPERLY.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) uint8_t state_flags; /* 0D */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) uint8_t cmdRefNum; /* 0E */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) uint8_t reserved1; /* 0F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) uint8_t cdb[IOCB_MAX_CDB_LEN]; /* 10-1F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) struct scsi_lun lun; /* FCP LUN (BE). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) uint32_t cmdSeqNum; /* 28-2B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) uint16_t timeout; /* 2C-2D */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) uint16_t dataSegCnt; /* 2E-2F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) uint32_t ttlByteCnt; /* 30-33 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) struct data_seg_a64 dataseg[COMMAND_SEG_A64]; /* 34-3F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) /* Continuation Type 1 entry structure*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) struct continuation_t1_entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) struct qla4_header hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) struct data_seg_a64 dataseg[CONTINUE_SEG_A64];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) /* Parameterize for 64 or 32 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) #define COMMAND_SEG COMMAND_SEG_A64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) #define CONTINUE_SEG CONTINUE_SEG_A64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) #define ET_COMMAND ET_CMND_T3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) #define ET_CONTINUE ET_CONT_T1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) /* Marker entry structure*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) struct qla4_marker_entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) struct qla4_header hdr; /* 00-03 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) uint32_t system_defined; /* 04-07 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) uint16_t target; /* 08-09 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) uint16_t modifier; /* 0A-0B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) #define MM_LUN_RESET 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) #define MM_TGT_WARM_RESET 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) uint16_t flags; /* 0C-0D */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) uint16_t reserved1; /* 0E-0F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) struct scsi_lun lun; /* FCP LUN (BE). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) uint64_t reserved2; /* 18-1F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) uint64_t reserved3; /* 20-27 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) uint64_t reserved4; /* 28-2F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) uint64_t reserved5; /* 30-37 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) uint64_t reserved6; /* 38-3F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) /* Status entry structure*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) struct status_entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) struct qla4_header hdr; /* 00-03 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) uint32_t handle; /* 04-07 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) uint8_t scsiStatus; /* 08 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) #define SCSI_CHECK_CONDITION 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) uint8_t iscsiFlags; /* 09 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) #define ISCSI_FLAG_RESIDUAL_UNDER 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) #define ISCSI_FLAG_RESIDUAL_OVER 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) uint8_t iscsiResponse; /* 0A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) uint8_t completionStatus; /* 0B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) #define SCS_COMPLETE 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) #define SCS_INCOMPLETE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) #define SCS_RESET_OCCURRED 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) #define SCS_ABORTED 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) #define SCS_TIMEOUT 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) #define SCS_DATA_OVERRUN 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) #define SCS_DATA_UNDERRUN 0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) #define SCS_QUEUE_FULL 0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) #define SCS_DEVICE_UNAVAILABLE 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) #define SCS_DEVICE_LOGGED_OUT 0x29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) uint8_t reserved1; /* 0C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) /* state_flags MUST be at the same location as state_flags in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) * the Command_T3/4_Entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) uint8_t state_flags; /* 0D */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) uint16_t senseDataByteCnt; /* 0E-0F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) uint32_t residualByteCnt; /* 10-13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) uint32_t bidiResidualByteCnt; /* 14-17 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) uint32_t expSeqNum; /* 18-1B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) uint32_t maxCmdSeqNum; /* 1C-1F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) uint8_t senseData[IOCB_MAX_SENSEDATA_LEN]; /* 20-3F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) /* Status Continuation entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) struct status_cont_entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) struct qla4_header hdr; /* 00-03 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) uint8_t ext_sense_data[IOCB_MAX_EXT_SENSEDATA_LEN]; /* 04-63 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) struct passthru0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) struct qla4_header hdr; /* 00-03 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) uint32_t handle; /* 04-07 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) uint16_t target; /* 08-09 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) uint16_t connection_id; /* 0A-0B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) #define ISNS_DEFAULT_SERVER_CONN_ID ((uint16_t)0x8000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) uint16_t control_flags; /* 0C-0D */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) #define PT_FLAG_ETHERNET_FRAME 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) #define PT_FLAG_ISNS_PDU 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) #define PT_FLAG_SEND_BUFFER 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) #define PT_FLAG_WAIT_4_RESPONSE 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) #define PT_FLAG_ISCSI_PDU 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) uint16_t timeout; /* 0E-0F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) #define PT_DEFAULT_TIMEOUT 30 /* seconds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) struct data_seg_a64 out_dsd; /* 10-1B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) uint32_t res1; /* 1C-1F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) struct data_seg_a64 in_dsd; /* 20-2B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) uint8_t res2[20]; /* 2C-3F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) struct passthru_status {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) struct qla4_header hdr; /* 00-03 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) uint32_t handle; /* 04-07 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) uint16_t target; /* 08-09 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) uint16_t connectionID; /* 0A-0B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) uint8_t completionStatus; /* 0C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) #define PASSTHRU_STATUS_COMPLETE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) uint8_t residualFlags; /* 0D */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) uint16_t timeout; /* 0E-0F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) uint16_t portNumber; /* 10-11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) uint8_t res1[10]; /* 12-1B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) uint32_t outResidual; /* 1C-1F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) uint8_t res2[12]; /* 20-2B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) uint32_t inResidual; /* 2C-2F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) uint8_t res4[16]; /* 30-3F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) struct mbox_cmd_iocb {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) struct qla4_header hdr; /* 00-03 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) uint32_t handle; /* 04-07 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) uint32_t in_mbox[8]; /* 08-25 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) uint32_t res1[6]; /* 26-3F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) struct mbox_status_iocb {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) struct qla4_header hdr; /* 00-03 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) uint32_t handle; /* 04-07 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) uint32_t out_mbox[8]; /* 08-25 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) uint32_t res1[6]; /* 26-3F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) * ISP queue - response queue entry definition.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) struct response {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) uint8_t data[60];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) uint32_t signature;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) #define RESPONSE_PROCESSED 0xDEADDEAD /* Signature */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) struct ql_iscsi_stats {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) uint64_t mac_tx_frames; /* 0000–0007 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) uint64_t mac_tx_bytes; /* 0008–000F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) uint64_t mac_tx_multicast_frames; /* 0010–0017 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) uint64_t mac_tx_broadcast_frames; /* 0018–001F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) uint64_t mac_tx_pause_frames; /* 0020–0027 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) uint64_t mac_tx_control_frames; /* 0028–002F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) uint64_t mac_tx_deferral; /* 0030–0037 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) uint64_t mac_tx_excess_deferral; /* 0038–003F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) uint64_t mac_tx_late_collision; /* 0040–0047 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) uint64_t mac_tx_abort; /* 0048–004F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) uint64_t mac_tx_single_collision; /* 0050–0057 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) uint64_t mac_tx_multiple_collision; /* 0058–005F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) uint64_t mac_tx_collision; /* 0060–0067 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) uint64_t mac_tx_frames_dropped; /* 0068–006F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) uint64_t mac_tx_jumbo_frames; /* 0070–0077 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) uint64_t mac_rx_frames; /* 0078–007F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) uint64_t mac_rx_bytes; /* 0080–0087 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) uint64_t mac_rx_unknown_control_frames; /* 0088–008F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) uint64_t mac_rx_pause_frames; /* 0090–0097 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) uint64_t mac_rx_control_frames; /* 0098–009F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) uint64_t mac_rx_dribble; /* 00A0–00A7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) uint64_t mac_rx_frame_length_error; /* 00A8–00AF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) uint64_t mac_rx_jabber; /* 00B0–00B7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) uint64_t mac_rx_carrier_sense_error; /* 00B8–00BF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) uint64_t mac_rx_frame_discarded; /* 00C0–00C7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) uint64_t mac_rx_frames_dropped; /* 00C8–00CF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) uint64_t mac_crc_error; /* 00D0–00D7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) uint64_t mac_encoding_error; /* 00D8–00DF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) uint64_t mac_rx_length_error_large; /* 00E0–00E7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) uint64_t mac_rx_length_error_small; /* 00E8–00EF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) uint64_t mac_rx_multicast_frames; /* 00F0–00F7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) uint64_t mac_rx_broadcast_frames; /* 00F8–00FF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) uint64_t ip_tx_packets; /* 0100–0107 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) uint64_t ip_tx_bytes; /* 0108–010F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) uint64_t ip_tx_fragments; /* 0110–0117 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) uint64_t ip_rx_packets; /* 0118–011F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) uint64_t ip_rx_bytes; /* 0120–0127 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) uint64_t ip_rx_fragments; /* 0128–012F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) uint64_t ip_datagram_reassembly; /* 0130–0137 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) uint64_t ip_invalid_address_error; /* 0138–013F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) uint64_t ip_error_packets; /* 0140–0147 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) uint64_t ip_fragrx_overlap; /* 0148–014F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) uint64_t ip_fragrx_outoforder; /* 0150–0157 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) uint64_t ip_datagram_reassembly_timeout; /* 0158–015F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) uint64_t ipv6_tx_packets; /* 0160–0167 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) uint64_t ipv6_tx_bytes; /* 0168–016F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) uint64_t ipv6_tx_fragments; /* 0170–0177 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) uint64_t ipv6_rx_packets; /* 0178–017F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) uint64_t ipv6_rx_bytes; /* 0180–0187 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) uint64_t ipv6_rx_fragments; /* 0188–018F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) uint64_t ipv6_datagram_reassembly; /* 0190–0197 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) uint64_t ipv6_invalid_address_error; /* 0198–019F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) uint64_t ipv6_error_packets; /* 01A0–01A7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) uint64_t ipv6_fragrx_overlap; /* 01A8–01AF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) uint64_t ipv6_fragrx_outoforder; /* 01B0–01B7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) uint64_t ipv6_datagram_reassembly_timeout; /* 01B8–01BF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) uint64_t tcp_tx_segments; /* 01C0–01C7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) uint64_t tcp_tx_bytes; /* 01C8–01CF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) uint64_t tcp_rx_segments; /* 01D0–01D7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) uint64_t tcp_rx_byte; /* 01D8–01DF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) uint64_t tcp_duplicate_ack_retx; /* 01E0–01E7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) uint64_t tcp_retx_timer_expired; /* 01E8–01EF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) uint64_t tcp_rx_duplicate_ack; /* 01F0–01F7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) uint64_t tcp_rx_pure_ackr; /* 01F8–01FF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) uint64_t tcp_tx_delayed_ack; /* 0200–0207 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) uint64_t tcp_tx_pure_ack; /* 0208–020F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) uint64_t tcp_rx_segment_error; /* 0210–0217 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) uint64_t tcp_rx_segment_outoforder; /* 0218–021F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) uint64_t tcp_rx_window_probe; /* 0220–0227 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) uint64_t tcp_rx_window_update; /* 0228–022F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) uint64_t tcp_tx_window_probe_persist; /* 0230–0237 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) uint64_t ecc_error_correction; /* 0238–023F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) uint64_t iscsi_pdu_tx; /* 0240-0247 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) uint64_t iscsi_data_bytes_tx; /* 0248-024F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) uint64_t iscsi_pdu_rx; /* 0250-0257 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) uint64_t iscsi_data_bytes_rx; /* 0258-025F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) uint64_t iscsi_io_completed; /* 0260-0267 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) uint64_t iscsi_unexpected_io_rx; /* 0268-026F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) uint64_t iscsi_format_error; /* 0270-0277 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) uint64_t iscsi_hdr_digest_error; /* 0278-027F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) uint64_t iscsi_data_digest_error; /* 0280-0287 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) uint64_t iscsi_sequence_error; /* 0288-028F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) uint32_t tx_cmd_pdu; /* 0290-0293 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) uint32_t tx_resp_pdu; /* 0294-0297 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) uint32_t rx_cmd_pdu; /* 0298-029B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) uint32_t rx_resp_pdu; /* 029C-029F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) uint64_t tx_data_octets; /* 02A0-02A7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) uint64_t rx_data_octets; /* 02A8-02AF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) uint32_t hdr_digest_err; /* 02B0–02B3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) uint32_t data_digest_err; /* 02B4–02B7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) uint32_t conn_timeout_err; /* 02B8–02BB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) uint32_t framing_err; /* 02BC–02BF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) uint32_t tx_nopout_pdus; /* 02C0–02C3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) uint32_t tx_scsi_cmd_pdus; /* 02C4–02C7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) uint32_t tx_tmf_cmd_pdus; /* 02C8–02CB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) uint32_t tx_login_cmd_pdus; /* 02CC–02CF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) uint32_t tx_text_cmd_pdus; /* 02D0–02D3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) uint32_t tx_scsi_write_pdus; /* 02D4–02D7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) uint32_t tx_logout_cmd_pdus; /* 02D8–02DB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) uint32_t tx_snack_req_pdus; /* 02DC–02DF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) uint32_t rx_nopin_pdus; /* 02E0–02E3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) uint32_t rx_scsi_resp_pdus; /* 02E4–02E7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) uint32_t rx_tmf_resp_pdus; /* 02E8–02EB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) uint32_t rx_login_resp_pdus; /* 02EC–02EF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) uint32_t rx_text_resp_pdus; /* 02F0–02F3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) uint32_t rx_scsi_read_pdus; /* 02F4–02F7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) uint32_t rx_logout_resp_pdus; /* 02F8–02FB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) uint32_t rx_r2t_pdus; /* 02FC–02FF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) uint32_t rx_async_pdus; /* 0300–0303 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) uint32_t rx_reject_pdus; /* 0304–0307 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) uint8_t reserved2[264]; /* 0x0308 - 0x040F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) #define QLA8XXX_DBG_STATE_ARRAY_LEN 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) #define QLA8XXX_DBG_CAP_SIZE_ARRAY_LEN 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) #define QLA8XXX_DBG_RSVD_ARRAY_LEN 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) #define QLA83XX_DBG_OCM_WNDREG_ARRAY_LEN 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) #define QLA83XX_SS_OCM_WNDREG_INDEX 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) #define QLA83XX_SS_PCI_INDEX 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) #define QLA8022_TEMPLATE_CAP_OFFSET 172
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) #define QLA83XX_TEMPLATE_CAP_OFFSET 268
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) #define QLA80XX_TEMPLATE_RESERVED_BITS 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) struct qla4_8xxx_minidump_template_hdr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) uint32_t entry_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) uint32_t first_entry_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) uint32_t size_of_template;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) uint32_t capture_debug_level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) uint32_t num_of_entries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) uint32_t version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) uint32_t driver_timestamp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) uint32_t checksum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) uint32_t driver_capture_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) uint32_t driver_info_word2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) uint32_t driver_info_word3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) uint32_t driver_info_word4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) uint32_t saved_state_array[QLA8XXX_DBG_STATE_ARRAY_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) uint32_t capture_size_array[QLA8XXX_DBG_CAP_SIZE_ARRAY_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) uint32_t ocm_window_reg[QLA83XX_DBG_OCM_WNDREG_ARRAY_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) uint32_t capabilities[QLA80XX_TEMPLATE_RESERVED_BITS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) #endif /* _QLA4X_FW_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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