^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * QLogic iSCSI HBA Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (c) 2003-2013 QLogic Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #ifndef __QL4_DEF_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define __QL4_DEF_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/list.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/dmapool.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/mempool.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/workqueue.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/aer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/bsg-lib.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/vmalloc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <net/tcp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <scsi/scsi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <scsi/scsi_host.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <scsi/scsi_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <scsi/scsi_cmnd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <scsi/scsi_transport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <scsi/scsi_transport_iscsi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <scsi/scsi_bsg_iscsi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <scsi/scsi_netlink.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include <scsi/libiscsi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include "ql4_dbg.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #include "ql4_nx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #include "ql4_fw.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #include "ql4_nvram.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #include "ql4_83xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #ifndef PCI_DEVICE_ID_QLOGIC_ISP4010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define PCI_DEVICE_ID_QLOGIC_ISP4010 0x4010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #ifndef PCI_DEVICE_ID_QLOGIC_ISP4022
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define PCI_DEVICE_ID_QLOGIC_ISP4022 0x4022
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #ifndef PCI_DEVICE_ID_QLOGIC_ISP4032
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define PCI_DEVICE_ID_QLOGIC_ISP4032 0x4032
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #ifndef PCI_DEVICE_ID_QLOGIC_ISP8022
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define PCI_DEVICE_ID_QLOGIC_ISP8022 0x8022
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #ifndef PCI_DEVICE_ID_QLOGIC_ISP8324
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define PCI_DEVICE_ID_QLOGIC_ISP8324 0x8032
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #ifndef PCI_DEVICE_ID_QLOGIC_ISP8042
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define PCI_DEVICE_ID_QLOGIC_ISP8042 0x8042
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define ISP4XXX_PCI_FN_1 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define ISP4XXX_PCI_FN_2 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define QLA_SUCCESS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define QLA_ERROR 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define STATUS(status) status == QLA_ERROR ? "FAILED" : "SUCCEEDED"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * Data bit definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define BIT_0 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define BIT_1 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define BIT_2 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define BIT_3 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define BIT_4 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define BIT_5 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define BIT_6 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define BIT_7 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define BIT_8 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define BIT_9 0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define BIT_10 0x400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define BIT_11 0x800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define BIT_12 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define BIT_13 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define BIT_14 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define BIT_15 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define BIT_16 0x10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define BIT_17 0x20000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define BIT_18 0x40000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define BIT_19 0x80000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define BIT_20 0x100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define BIT_21 0x200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define BIT_22 0x400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define BIT_23 0x800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define BIT_24 0x1000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define BIT_25 0x2000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define BIT_26 0x4000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define BIT_27 0x8000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define BIT_28 0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define BIT_29 0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define BIT_30 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define BIT_31 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * Macros to help code, maintain, etc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) **/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define ql4_printk(level, ha, format, arg...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) dev_printk(level , &((ha)->pdev->dev) , format , ## arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * Host adapter default definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) ***********************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define MAX_HBAS 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define MAX_BUSES 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define MAX_TARGETS MAX_DEV_DB_ENTRIES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define MAX_LUNS 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define MAX_AEN_ENTRIES MAX_DEV_DB_ENTRIES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define MAX_DDB_ENTRIES MAX_DEV_DB_ENTRIES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define MAX_PDU_ENTRIES 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define INVALID_ENTRY 0xFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define MAX_CMDS_TO_RISC 1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define MAX_SRBS MAX_CMDS_TO_RISC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define MBOX_AEN_REG_COUNT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define MAX_INIT_RETRIES 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * Buffer sizes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define REQUEST_QUEUE_DEPTH MAX_CMDS_TO_RISC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define RESPONSE_QUEUE_DEPTH 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define QUEUE_SIZE 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define DMA_BUFFER_SIZE 512
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define IOCB_HIWAT_CUSHION 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * Misc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define MAC_ADDR_LEN 6 /* in bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define IP_ADDR_LEN 4 /* in bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define IPv6_ADDR_LEN 16 /* IPv6 address size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define DRIVER_NAME "qla4xxx"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define MAX_LINKED_CMDS_PER_LUN 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define MAX_REQS_SERVICED_PER_INTR 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define ISCSI_IPADDR_SIZE 4 /* IP address size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define ISCSI_ALIAS_SIZE 32 /* ISCSI Alias name size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define ISCSI_NAME_SIZE 0xE0 /* ISCSI Name size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define QL4_SESS_RECOVERY_TMO 120 /* iSCSI session */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /* recovery timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define LSDW(x) ((u32)((u64)(x)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define MSDW(x) ((u32)((((u64)(x)) >> 16) >> 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define DEV_DB_NON_PERSISTENT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define DEV_DB_PERSISTENT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define QL4_ISP_REG_DISCONNECT 0xffffffffU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define COPY_ISID(dst_isid, src_isid) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) int i, j; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) for (i = 0, j = ISID_SIZE - 1; i < ISID_SIZE;) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) dst_isid[i++] = src_isid[j--]; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define SET_BITVAL(o, n, v) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) if (o) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) n |= v; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) else \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) n &= ~v; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define OP_STATE(o, f, p) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) p = (o & f) ? "enable" : "disable"; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) * Retry & Timeout Values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define MBOX_TOV 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define SOFT_RESET_TOV 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define RESET_INTR_TOV 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define SEMAPHORE_TOV 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define ADAPTER_INIT_TOV 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define ADAPTER_RESET_TOV 180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define EXTEND_CMD_TOV 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define WAIT_CMD_TOV 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define EH_WAIT_CMD_TOV 120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define FIRMWARE_UP_TOV 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define RESET_FIRMWARE_TOV 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define LOGOUT_TOV 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define IOCB_TOV_MARGIN 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define RELOGIN_TOV 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define ISNS_DEREG_TOV 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define HBA_ONLINE_TOV 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define DISABLE_ACB_TOV 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define IP_CONFIG_TOV 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define LOGIN_TOV 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define BOOT_LOGIN_RESP_TOV 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define MAX_RESET_HA_RETRIES 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define FW_ALIVE_WAIT_TOV 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define IDC_EXTEND_TOV 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define IDC_COMP_TOV 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define LINK_UP_COMP_TOV 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define CMD_SP(Cmnd) ((Cmnd)->SCp.ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) * SCSI Request Block structure (srb) that is placed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) * on cmd->SCp location of every I/O [We have 22 bytes available]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) struct srb {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) struct list_head list; /* (8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) struct scsi_qla_host *ha; /* HA the SP is queued on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) struct ddb_entry *ddb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) uint16_t flags; /* (1) Status flags. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define SRB_DMA_VALID BIT_3 /* DMA Buffer mapped. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define SRB_GOT_SENSE BIT_4 /* sense data received. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) uint8_t state; /* (1) Status flags. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define SRB_NO_QUEUE_STATE 0 /* Request is in between states */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define SRB_FREE_STATE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define SRB_ACTIVE_STATE 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define SRB_ACTIVE_TIMEOUT_STATE 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define SRB_SUSPENDED_STATE 7 /* Request in suspended state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) struct scsi_cmnd *cmd; /* (4) SCSI command block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) dma_addr_t dma_handle; /* (4) for unmap of single transfers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) struct kref srb_ref; /* reference count for this srb */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) uint8_t err_id; /* error id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define SRB_ERR_PORT 1 /* Request failed because "port down" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define SRB_ERR_LOOP 2 /* Request failed because "loop down" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define SRB_ERR_DEVICE 3 /* Request failed because "device error" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define SRB_ERR_OTHER 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) uint16_t reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) uint16_t iocb_tov;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) uint16_t iocb_cnt; /* Number of used iocbs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) uint16_t cc_stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) /* Used for extended sense / status continuation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) uint8_t *req_sense_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) uint16_t req_sense_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) uint16_t reserved2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) /* Mailbox request block structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) struct mrb {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) struct scsi_qla_host *ha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) struct mbox_cmd_iocb *mbox;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) uint32_t mbox_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) uint16_t iocb_cnt; /* Number of used iocbs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) uint32_t pid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) * Asynchronous Event Queue structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) struct aen {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) uint32_t mbox_sts[MBOX_AEN_REG_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) struct ql4_aen_log {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) int count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) struct aen entry[MAX_AEN_ENTRIES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) * Device Database (DDB) structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) struct ddb_entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) struct scsi_qla_host *ha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) struct iscsi_cls_session *sess;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) struct iscsi_cls_conn *conn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) uint16_t fw_ddb_index; /* DDB firmware index */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) uint32_t fw_ddb_device_state; /* F/W Device State -- see ql4_fw.h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) uint16_t ddb_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define FLASH_DDB 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) struct dev_db_entry fw_ddb_entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) int (*unblock_sess)(struct iscsi_cls_session *cls_session);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) int (*ddb_change)(struct scsi_qla_host *ha, uint32_t fw_ddb_index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) struct ddb_entry *ddb_entry, uint32_t state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) /* Driver Re-login */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) unsigned long flags; /* DDB Flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define DDB_CONN_CLOSE_FAILURE 0 /* 0x00000001 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) uint16_t default_relogin_timeout; /* Max time to wait for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) * relogin to complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) atomic_t retry_relogin_timer; /* Min Time between relogins
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) * (4000 only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) atomic_t relogin_timer; /* Max Time to wait for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) * relogin to complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) atomic_t relogin_retry_count; /* Num of times relogin has been
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) * retried */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) uint32_t default_time2wait; /* Default Min time between
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) * relogins (+aens) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) uint16_t chap_tbl_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) struct qla_ddb_index {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) struct list_head list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) uint16_t fw_ddb_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) uint16_t flash_ddb_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) struct dev_db_entry fw_ddb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) uint8_t flash_isid[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define DDB_IPADDR_LEN 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) struct ql4_tuple_ddb {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) int port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) int tpgt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) char ip_addr[DDB_IPADDR_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) char iscsi_name[ISCSI_NAME_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) uint16_t options;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define DDB_OPT_IPV6 0x0e0e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define DDB_OPT_IPV4 0x0f0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) uint8_t isid[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) * DDB states.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define DDB_STATE_DEAD 0 /* We can no longer talk to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) * this device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define DDB_STATE_ONLINE 1 /* Device ready to accept
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) * commands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define DDB_STATE_MISSING 2 /* Device logged off, trying
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) * to re-login */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) * DDB flags.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define DF_RELOGIN 0 /* Relogin to device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define DF_BOOT_TGT 1 /* Boot target entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define DF_ISNS_DISCOVERED 2 /* Device was discovered via iSNS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define DF_FO_MASKED 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define DF_DISABLE_RELOGIN 4 /* Disable relogin to device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) enum qla4_work_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) QLA4_EVENT_AEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) QLA4_EVENT_PING_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) struct qla4_work_evt {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) struct list_head list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) enum qla4_work_type type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) enum iscsi_host_event_code code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) uint32_t data_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) uint8_t data[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) } aen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) uint32_t status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) uint32_t pid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) uint32_t data_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) uint8_t data[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) } ping;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) } u;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) struct ql82xx_hw_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) /* Offsets for flash/nvram access (set to ~0 if not used). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) uint32_t flash_conf_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) uint32_t flash_data_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) uint32_t fdt_wrt_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) uint32_t fdt_erase_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) uint32_t fdt_block_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) uint32_t fdt_unprotect_sec_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) uint32_t fdt_protect_sec_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) uint32_t flt_region_flt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) uint32_t flt_region_fdt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) uint32_t flt_region_boot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) uint32_t flt_region_bootload;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) uint32_t flt_region_fw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) uint32_t flt_iscsi_param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) uint32_t flt_region_chap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) uint32_t flt_chap_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) uint32_t flt_region_ddb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) uint32_t flt_ddb_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) struct qla4_8xxx_legacy_intr_set {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) uint32_t int_vec_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) uint32_t tgt_status_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) uint32_t tgt_mask_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) uint32_t pci_int_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) /* MSI-X Support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #define QLA_MSIX_ENTRIES 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) * ISP Operations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) struct isp_operations {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) int (*iospace_config) (struct scsi_qla_host *ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) void (*pci_config) (struct scsi_qla_host *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) void (*disable_intrs) (struct scsi_qla_host *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) void (*enable_intrs) (struct scsi_qla_host *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) int (*start_firmware) (struct scsi_qla_host *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) int (*restart_firmware) (struct scsi_qla_host *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) irqreturn_t (*intr_handler) (int , void *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) void (*interrupt_service_routine) (struct scsi_qla_host *, uint32_t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) int (*need_reset) (struct scsi_qla_host *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) int (*reset_chip) (struct scsi_qla_host *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) int (*reset_firmware) (struct scsi_qla_host *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) void (*queue_iocb) (struct scsi_qla_host *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) void (*complete_iocb) (struct scsi_qla_host *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) uint16_t (*rd_shdw_req_q_out) (struct scsi_qla_host *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) uint16_t (*rd_shdw_rsp_q_in) (struct scsi_qla_host *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) int (*get_sys_info) (struct scsi_qla_host *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) uint32_t (*rd_reg_direct) (struct scsi_qla_host *, ulong);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) void (*wr_reg_direct) (struct scsi_qla_host *, ulong, uint32_t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) int (*rd_reg_indirect) (struct scsi_qla_host *, uint32_t, uint32_t *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) int (*wr_reg_indirect) (struct scsi_qla_host *, uint32_t, uint32_t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) int (*idc_lock) (struct scsi_qla_host *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) void (*idc_unlock) (struct scsi_qla_host *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) void (*rom_lock_recovery) (struct scsi_qla_host *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) void (*queue_mailbox_command) (struct scsi_qla_host *, uint32_t *, int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) void (*process_mailbox_interrupt) (struct scsi_qla_host *, int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) struct ql4_mdump_size_table {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) uint32_t size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) uint32_t size_cmask_02;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) uint32_t size_cmask_04;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) uint32_t size_cmask_08;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) uint32_t size_cmask_10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) uint32_t size_cmask_FF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) uint32_t version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) /*qla4xxx ipaddress configuration details */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) struct ipaddress_config {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) uint16_t ipv4_options;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) uint16_t tcp_options;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) uint16_t ipv4_vlan_tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) uint8_t ipv4_addr_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) uint8_t ip_address[IP_ADDR_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) uint8_t subnet_mask[IP_ADDR_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) uint8_t gateway[IP_ADDR_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) uint32_t ipv6_options;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) uint32_t ipv6_addl_options;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) uint8_t ipv6_link_local_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) uint8_t ipv6_addr0_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) uint8_t ipv6_addr1_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) uint8_t ipv6_default_router_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) uint16_t ipv6_vlan_tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) struct in6_addr ipv6_link_local_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) struct in6_addr ipv6_addr0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) struct in6_addr ipv6_addr1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) struct in6_addr ipv6_default_router_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) uint16_t eth_mtu_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) uint16_t ipv4_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) uint16_t ipv6_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) uint8_t control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) uint16_t ipv6_tcp_options;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) uint8_t tcp_wsf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) uint8_t ipv6_tcp_wsf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) uint8_t ipv4_tos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) uint8_t ipv4_cache_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) uint8_t ipv6_cache_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) uint8_t ipv4_alt_cid_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) uint8_t ipv4_alt_cid[11];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) uint8_t ipv4_vid_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) uint8_t ipv4_vid[11];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) uint8_t ipv4_ttl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) uint16_t ipv6_flow_lbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) uint8_t ipv6_traffic_class;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) uint8_t ipv6_hop_limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) uint32_t ipv6_nd_reach_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) uint32_t ipv6_nd_rexmit_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) uint32_t ipv6_nd_stale_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) uint8_t ipv6_dup_addr_detect_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) uint32_t ipv6_gw_advrt_mtu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) uint16_t def_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) uint8_t abort_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) uint16_t iscsi_options;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) uint16_t iscsi_max_pdu_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) uint16_t iscsi_first_burst_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) uint16_t iscsi_max_outstnd_r2t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) uint16_t iscsi_max_burst_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) uint8_t iscsi_name[224];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) #define QL4_CHAP_MAX_NAME_LEN 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) #define QL4_CHAP_MAX_SECRET_LEN 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) #define LOCAL_CHAP 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) #define BIDI_CHAP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) struct ql4_chap_format {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) u8 intr_chap_name[QL4_CHAP_MAX_NAME_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) u8 intr_secret[QL4_CHAP_MAX_SECRET_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) u8 target_chap_name[QL4_CHAP_MAX_NAME_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) u8 target_secret[QL4_CHAP_MAX_SECRET_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) u16 intr_chap_name_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) u16 intr_secret_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) u16 target_chap_name_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) u16 target_secret_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) struct ip_address_format {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) u8 ip_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) u8 ip_address[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) struct ql4_conn_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) u16 dest_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) struct ip_address_format dest_ipaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) struct ql4_chap_format chap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) struct ql4_boot_session_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) u8 target_name[224];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) struct ql4_conn_info conn_list[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) struct ql4_boot_tgt_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) struct ql4_boot_session_info boot_pri_sess;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) struct ql4_boot_session_info boot_sec_sess;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) * Linux Host Adapter structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) struct scsi_qla_host {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) /* Linux adapter configuration data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) #define AF_ONLINE 0 /* 0x00000001 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) #define AF_INIT_DONE 1 /* 0x00000002 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) #define AF_MBOX_COMMAND 2 /* 0x00000004 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) #define AF_MBOX_COMMAND_DONE 3 /* 0x00000008 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) #define AF_ST_DISCOVERY_IN_PROGRESS 4 /* 0x00000010 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) #define AF_INTERRUPTS_ON 6 /* 0x00000040 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) #define AF_GET_CRASH_RECORD 7 /* 0x00000080 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) #define AF_LINK_UP 8 /* 0x00000100 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) #define AF_LOOPBACK 9 /* 0x00000200 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) #define AF_IRQ_ATTACHED 10 /* 0x00000400 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) #define AF_DISABLE_ACB_COMPLETE 11 /* 0x00000800 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) #define AF_HA_REMOVAL 12 /* 0x00001000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) #define AF_MBOX_COMMAND_NOPOLL 18 /* 0x00040000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) #define AF_FW_RECOVERY 19 /* 0x00080000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) #define AF_EEH_BUSY 20 /* 0x00100000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) #define AF_PCI_CHANNEL_IO_PERM_FAILURE 21 /* 0x00200000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) #define AF_BUILD_DDB_LIST 22 /* 0x00400000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) #define AF_82XX_FW_DUMPED 24 /* 0x01000000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) #define AF_8XXX_RST_OWNER 25 /* 0x02000000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) #define AF_82XX_DUMP_READING 26 /* 0x04000000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) #define AF_83XX_IOCB_INTR_ON 28 /* 0x10000000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) #define AF_83XX_MBOX_INTR_ON 29 /* 0x20000000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) unsigned long dpc_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) #define DPC_RESET_HA 1 /* 0x00000002 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) #define DPC_RETRY_RESET_HA 2 /* 0x00000004 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) #define DPC_RELOGIN_DEVICE 3 /* 0x00000008 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) #define DPC_RESET_HA_FW_CONTEXT 4 /* 0x00000010 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) #define DPC_RESET_HA_INTR 5 /* 0x00000020 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) #define DPC_ISNS_RESTART 7 /* 0x00000080 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) #define DPC_AEN 9 /* 0x00000200 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) #define DPC_GET_DHCP_IP_ADDR 15 /* 0x00008000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) #define DPC_LINK_CHANGED 18 /* 0x00040000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) #define DPC_RESET_ACTIVE 20 /* 0x00100000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) #define DPC_HA_UNRECOVERABLE 21 /* 0x00200000 ISP-82xx only*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) #define DPC_HA_NEED_QUIESCENT 22 /* 0x00400000 ISP-82xx only*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) #define DPC_POST_IDC_ACK 23 /* 0x00800000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) #define DPC_RESTORE_ACB 24 /* 0x01000000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) #define DPC_SYSFS_DDB_EXPORT 25 /* 0x02000000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) struct Scsi_Host *host; /* pointer to host data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) uint32_t tot_ddbs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) uint16_t iocb_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) uint16_t iocb_hiwat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) /* SRB cache. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) #define SRB_MIN_REQ 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) mempool_t *srb_mempool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) /* pci information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) struct pci_dev *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) struct isp_reg __iomem *reg; /* Base I/O address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) unsigned long pio_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) unsigned long pio_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) #define MIN_IOBASE_LEN 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) uint16_t req_q_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) unsigned long host_no;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) /* NVRAM registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) struct eeprom_data *nvram;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) spinlock_t hardware_lock ____cacheline_aligned;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) uint32_t eeprom_cmd_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) /* Counters for general statistics */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) uint64_t isr_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) uint64_t adapter_error_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) uint64_t device_error_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) uint64_t total_io_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) uint64_t total_mbytes_xferred;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) uint64_t link_failure_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) uint64_t invalid_crc_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) uint32_t bytes_xfered;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) uint32_t spurious_int_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) uint32_t aborted_io_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) uint32_t io_timeout_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) uint32_t mailbox_timeout_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) uint32_t seconds_since_last_intr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) uint32_t seconds_since_last_heartbeat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) uint32_t mac_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) /* Info Needed for Management App */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) /* --- From GetFwVersion --- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) uint32_t firmware_version[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) uint32_t patch_number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) uint32_t build_number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) uint32_t board_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) /* --- From Init_FW --- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) /* init_cb_t *init_cb; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) uint16_t firmware_options;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) uint8_t alias[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) uint8_t name_string[256];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) uint8_t heartbeat_interval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) /* --- From FlashSysInfo --- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) uint8_t my_mac[MAC_ADDR_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) uint8_t serial_number[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) uint16_t port_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) /* --- From GetFwState --- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) uint32_t firmware_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) uint32_t addl_fw_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) /* Linux kernel thread */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) struct workqueue_struct *dpc_thread;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) struct work_struct dpc_work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) /* Linux timer thread */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) struct timer_list timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) uint32_t timer_active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) /* Recovery Timers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) atomic_t check_relogin_timeouts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) uint32_t retry_reset_ha_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) uint32_t isp_reset_timer; /* reset test timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) uint32_t nic_reset_timer; /* simulated nic reset test timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) int eh_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) struct list_head free_srb_q;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) uint16_t free_srb_q_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) uint16_t num_srbs_allocated;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) /* DMA Memory Block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) void *queues;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) dma_addr_t queues_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) unsigned long queues_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) #define MEM_ALIGN_VALUE \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) ((max(REQUEST_QUEUE_DEPTH, RESPONSE_QUEUE_DEPTH)) * \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) sizeof(struct queue_entry))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) /* request and response queue variables */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) dma_addr_t request_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) struct queue_entry *request_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) struct queue_entry *request_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) dma_addr_t response_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) struct queue_entry *response_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) struct queue_entry *response_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) dma_addr_t shadow_regs_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) struct shadow_regs *shadow_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) uint16_t request_in; /* Current indexes. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) uint16_t request_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) uint16_t response_in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) uint16_t response_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) /* aen queue variables */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) uint16_t aen_q_count; /* Number of available aen_q entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) uint16_t aen_in; /* Current indexes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) uint16_t aen_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) struct aen aen_q[MAX_AEN_ENTRIES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) struct ql4_aen_log aen_log;/* tracks all aens */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) /* This mutex protects several threads to do mailbox commands
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) * concurrently.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) struct mutex mbox_sem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) /* temporary mailbox status registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) volatile uint8_t mbox_status_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) volatile uint32_t mbox_status[MBOX_REG_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) /* FW ddb index map */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) struct ddb_entry *fw_ddb_index_map[MAX_DDB_ENTRIES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) /* Saved srb for status continuation entry processing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) struct srb *status_srb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) uint8_t acb_version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) /* qla82xx specific fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) struct device_reg_82xx __iomem *qla4_82xx_reg; /* Base I/O address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) unsigned long nx_pcibase; /* Base I/O address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) uint8_t *nx_db_rd_ptr; /* Doorbell read pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) unsigned long nx_db_wr_ptr; /* Door bell write pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) unsigned long first_page_group_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) unsigned long first_page_group_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) uint32_t crb_win;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) uint32_t curr_window;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) uint32_t ddr_mn_window;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) unsigned long mn_win_crb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) unsigned long ms_win_crb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) int qdr_sn_window;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) rwlock_t hw_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) uint16_t func_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) int link_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) struct qla4_8xxx_legacy_intr_set nx_legacy_intr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) u32 nx_crb_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) uint8_t revision_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) uint32_t fw_heartbeat_counter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) struct isp_operations *isp_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) struct ql82xx_hw_data hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) uint32_t nx_dev_init_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) uint32_t nx_reset_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) void *fw_dump;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) uint32_t fw_dump_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) uint32_t fw_dump_capture_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) void *fw_dump_tmplt_hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) uint32_t fw_dump_tmplt_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) uint32_t fw_dump_skip_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) struct completion mbx_intr_comp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) struct ipaddress_config ip_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) struct iscsi_iface *iface_ipv4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) struct iscsi_iface *iface_ipv6_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) struct iscsi_iface *iface_ipv6_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) /* --- From About Firmware --- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) struct about_fw_info fw_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) uint32_t fw_uptime_secs; /* seconds elapsed since fw bootup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) uint32_t fw_uptime_msecs; /* milliseconds beyond elapsed seconds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) uint16_t def_timeout; /* Default login timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) uint32_t flash_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) #define QLFLASH_WAITING 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) #define QLFLASH_READING 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) #define QLFLASH_WRITING 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) struct dma_pool *chap_dma_pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) uint8_t *chap_list; /* CHAP table cache */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) struct mutex chap_sem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) #define CHAP_DMA_BLOCK_SIZE 512
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) struct workqueue_struct *task_wq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) unsigned long ddb_idx_map[MAX_DDB_ENTRIES / BITS_PER_LONG];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) #define SYSFS_FLAG_FW_SEL_BOOT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) struct iscsi_boot_kset *boot_kset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) struct ql4_boot_tgt_info boot_tgt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) uint16_t phy_port_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) uint16_t phy_port_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) uint16_t iscsi_pci_func_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) uint8_t model_name[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) struct completion disable_acb_comp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) struct dma_pool *fw_ddb_dma_pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) #define DDB_DMA_BLOCK_SIZE 512
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) uint16_t pri_ddb_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) uint16_t sec_ddb_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) int is_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) uint16_t temperature;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) /* event work list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) struct list_head work_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) spinlock_t work_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) /* mbox iocb */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) #define MAX_MRB 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) struct mrb *active_mrb_array[MAX_MRB];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) uint32_t mrb_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) uint32_t *reg_tbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) struct qla4_83xx_reset_template reset_tmplt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) struct device_reg_83xx __iomem *qla4_83xx_reg; /* Base I/O address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) for ISP8324 and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) and ISP8042 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) uint32_t pf_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) struct qla4_83xx_idc_information idc_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) struct addr_ctrl_blk *saved_acb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) int notify_idc_comp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) int notify_link_up_comp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) int idc_extend_tmo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) struct completion idc_comp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) struct completion link_up_comp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) struct ql4_task_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) struct scsi_qla_host *ha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) uint8_t iocb_req_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) dma_addr_t data_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) void *req_buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) dma_addr_t req_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) uint32_t req_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) void *resp_buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) dma_addr_t resp_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) uint32_t resp_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) struct iscsi_task *task;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) struct passthru_status sts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) struct work_struct task_work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) struct qla_endpoint {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) struct Scsi_Host *host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) struct sockaddr_storage dst_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) struct qla_conn {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) struct qla_endpoint *qla_ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) static inline int is_ipv4_enabled(struct scsi_qla_host *ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) return ((ha->ip_config.ipv4_options & IPOPT_IPV4_PROTOCOL_ENABLE) != 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) static inline int is_ipv6_enabled(struct scsi_qla_host *ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) return ((ha->ip_config.ipv6_options &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) IPV6_OPT_IPV6_PROTOCOL_ENABLE) != 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) static inline int is_qla4010(struct scsi_qla_host *ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP4010;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) static inline int is_qla4022(struct scsi_qla_host *ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP4022;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) static inline int is_qla4032(struct scsi_qla_host *ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP4032;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) static inline int is_qla40XX(struct scsi_qla_host *ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) return is_qla4032(ha) || is_qla4022(ha) || is_qla4010(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) static inline int is_qla8022(struct scsi_qla_host *ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8022;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) static inline int is_qla8032(struct scsi_qla_host *ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8324;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) static inline int is_qla8042(struct scsi_qla_host *ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8042;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) static inline int is_qla80XX(struct scsi_qla_host *ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) return is_qla8022(ha) || is_qla8032(ha) || is_qla8042(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) static inline int is_aer_supported(struct scsi_qla_host *ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) return ((ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8022) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) (ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8324) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) (ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8042));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) static inline int adapter_up(struct scsi_qla_host *ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) return (test_bit(AF_ONLINE, &ha->flags) != 0) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) (test_bit(AF_LINK_UP, &ha->flags) != 0) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) (!test_bit(AF_LOOPBACK, &ha->flags));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) static inline struct scsi_qla_host* to_qla_host(struct Scsi_Host *shost)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) return (struct scsi_qla_host *)iscsi_host_priv(shost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) static inline void __iomem* isp_semaphore(struct scsi_qla_host *ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) return (is_qla4010(ha) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) &ha->reg->u1.isp4010.nvram :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) &ha->reg->u1.isp4022.semaphore);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) static inline void __iomem* isp_nvram(struct scsi_qla_host *ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) return (is_qla4010(ha) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) &ha->reg->u1.isp4010.nvram :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) &ha->reg->u1.isp4022.nvram);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) static inline void __iomem* isp_ext_hw_conf(struct scsi_qla_host *ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) return (is_qla4010(ha) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) &ha->reg->u2.isp4010.ext_hw_conf :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) &ha->reg->u2.isp4022.p0.ext_hw_conf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) static inline void __iomem* isp_port_status(struct scsi_qla_host *ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) return (is_qla4010(ha) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) &ha->reg->u2.isp4010.port_status :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) &ha->reg->u2.isp4022.p0.port_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) static inline void __iomem* isp_port_ctrl(struct scsi_qla_host *ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) return (is_qla4010(ha) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) &ha->reg->u2.isp4010.port_ctrl :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) &ha->reg->u2.isp4022.p0.port_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) static inline void __iomem* isp_port_error_status(struct scsi_qla_host *ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) return (is_qla4010(ha) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) &ha->reg->u2.isp4010.port_err_status :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) &ha->reg->u2.isp4022.p0.port_err_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) static inline void __iomem * isp_gp_out(struct scsi_qla_host *ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) return (is_qla4010(ha) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) &ha->reg->u2.isp4010.gp_out :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) &ha->reg->u2.isp4022.p0.gp_out);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) static inline int eeprom_ext_hw_conf_offset(struct scsi_qla_host *ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) return (is_qla4010(ha) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) offsetof(struct eeprom_data, isp4010.ext_hw_conf) / 2 :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) offsetof(struct eeprom_data, isp4022.ext_hw_conf) / 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) int ql4xxx_sem_spinlock(struct scsi_qla_host * ha, u32 sem_mask, u32 sem_bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) void ql4xxx_sem_unlock(struct scsi_qla_host * ha, u32 sem_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) int ql4xxx_sem_lock(struct scsi_qla_host * ha, u32 sem_mask, u32 sem_bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) static inline int ql4xxx_lock_flash(struct scsi_qla_host *a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) if (is_qla4010(a))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) return ql4xxx_sem_spinlock(a, QL4010_FLASH_SEM_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) QL4010_FLASH_SEM_BITS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) return ql4xxx_sem_spinlock(a, QL4022_FLASH_SEM_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) (QL4022_RESOURCE_BITS_BASE_CODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) (a->mac_index)) << 13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) static inline void ql4xxx_unlock_flash(struct scsi_qla_host *a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) if (is_qla4010(a))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) ql4xxx_sem_unlock(a, QL4010_FLASH_SEM_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) ql4xxx_sem_unlock(a, QL4022_FLASH_SEM_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) static inline int ql4xxx_lock_nvram(struct scsi_qla_host *a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) if (is_qla4010(a))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) return ql4xxx_sem_spinlock(a, QL4010_NVRAM_SEM_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) QL4010_NVRAM_SEM_BITS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) return ql4xxx_sem_spinlock(a, QL4022_NVRAM_SEM_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) (QL4022_RESOURCE_BITS_BASE_CODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) (a->mac_index)) << 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) static inline void ql4xxx_unlock_nvram(struct scsi_qla_host *a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) if (is_qla4010(a))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) ql4xxx_sem_unlock(a, QL4010_NVRAM_SEM_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) ql4xxx_sem_unlock(a, QL4022_NVRAM_SEM_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) static inline int ql4xxx_lock_drvr(struct scsi_qla_host *a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) if (is_qla4010(a))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) return ql4xxx_sem_lock(a, QL4010_DRVR_SEM_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) QL4010_DRVR_SEM_BITS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) return ql4xxx_sem_lock(a, QL4022_DRVR_SEM_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) (QL4022_RESOURCE_BITS_BASE_CODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) (a->mac_index)) << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) static inline void ql4xxx_unlock_drvr(struct scsi_qla_host *a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) if (is_qla4010(a))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) ql4xxx_sem_unlock(a, QL4010_DRVR_SEM_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) ql4xxx_sem_unlock(a, QL4022_DRVR_SEM_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) static inline int ql4xxx_reset_active(struct scsi_qla_host *ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) return test_bit(DPC_RESET_ACTIVE, &ha->dpc_flags) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) test_bit(DPC_RESET_HA, &ha->dpc_flags) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) test_bit(DPC_RETRY_RESET_HA, &ha->dpc_flags) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) test_bit(DPC_RESET_HA_INTR, &ha->dpc_flags) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) test_bit(DPC_RESET_HA_FW_CONTEXT, &ha->dpc_flags) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) test_bit(DPC_HA_UNRECOVERABLE, &ha->dpc_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) static inline int qla4_8xxx_rd_direct(struct scsi_qla_host *ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) const uint32_t crb_reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) return ha->isp_ops->rd_reg_direct(ha, ha->reg_tbl[crb_reg]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) static inline void qla4_8xxx_wr_direct(struct scsi_qla_host *ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) const uint32_t crb_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) const uint32_t value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) ha->isp_ops->wr_reg_direct(ha, ha->reg_tbl[crb_reg], value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) /*---------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) /* Defines for qla4xxx_initialize_adapter() and qla4xxx_recover_adapter() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) #define INIT_ADAPTER 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) #define RESET_ADAPTER 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) #define PRESERVE_DDB_LIST 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) #define REBUILD_DDB_LIST 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) /* Defines for process_aen() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) #define PROCESS_ALL_AENS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) #define FLUSH_DDB_CHANGED_AENS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) /* Defines for udev events */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) #define QL4_UEVENT_CODE_FW_DUMP 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) #endif /*_QLA4XXX_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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