^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * QLogic iSCSI HBA Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (c) 2003-2012 QLogic Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include "ql4_def.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include "ql4_glbl.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include "ql4_dbg.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include "ql4_inline.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) void qla4xxx_dump_buffer(void *b, uint32_t size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) uint32_t cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) uint8_t *c = b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) printk(" 0 1 2 3 4 5 6 7 8 9 Ah Bh Ch Dh Eh "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) "Fh\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) printk("------------------------------------------------------------"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) "--\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) for (cnt = 0; cnt < size; c++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) printk("%02x", *c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) if (!(++cnt % 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) printk("\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) printk(" ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) printk(KERN_INFO "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) void qla4xxx_dump_registers(struct scsi_qla_host *ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) uint8_t i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) if (is_qla8022(ha)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) for (i = 1; i < MBOX_REG_COUNT; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) printk(KERN_INFO "mailbox[%d] = 0x%08X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) i, readl(&ha->qla4_82xx_reg->mailbox_in[i]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) for (i = 0; i < MBOX_REG_COUNT; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) printk(KERN_INFO "0x%02X mailbox[%d] = 0x%08X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) (uint8_t) offsetof(struct isp_reg, mailbox[i]), i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) readw(&ha->reg->mailbox[i]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) printk(KERN_INFO "0x%02X flash_address = 0x%08X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) (uint8_t) offsetof(struct isp_reg, flash_address),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) readw(&ha->reg->flash_address));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) printk(KERN_INFO "0x%02X flash_data = 0x%08X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) (uint8_t) offsetof(struct isp_reg, flash_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) readw(&ha->reg->flash_data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) printk(KERN_INFO "0x%02X ctrl_status = 0x%08X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) (uint8_t) offsetof(struct isp_reg, ctrl_status),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) readw(&ha->reg->ctrl_status));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) if (is_qla4010(ha)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) printk(KERN_INFO "0x%02X nvram = 0x%08X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) (uint8_t) offsetof(struct isp_reg, u1.isp4010.nvram),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) readw(&ha->reg->u1.isp4010.nvram));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) } else if (is_qla4022(ha) | is_qla4032(ha)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) printk(KERN_INFO "0x%02X intr_mask = 0x%08X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) (uint8_t) offsetof(struct isp_reg, u1.isp4022.intr_mask),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) readw(&ha->reg->u1.isp4022.intr_mask));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) printk(KERN_INFO "0x%02X nvram = 0x%08X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) (uint8_t) offsetof(struct isp_reg, u1.isp4022.nvram),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) readw(&ha->reg->u1.isp4022.nvram));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) printk(KERN_INFO "0x%02X semaphore = 0x%08X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) (uint8_t) offsetof(struct isp_reg, u1.isp4022.semaphore),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) readw(&ha->reg->u1.isp4022.semaphore));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) printk(KERN_INFO "0x%02X req_q_in = 0x%08X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) (uint8_t) offsetof(struct isp_reg, req_q_in),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) readw(&ha->reg->req_q_in));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) printk(KERN_INFO "0x%02X rsp_q_out = 0x%08X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) (uint8_t) offsetof(struct isp_reg, rsp_q_out),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) readw(&ha->reg->rsp_q_out));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) if (is_qla4010(ha)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) printk(KERN_INFO "0x%02X ext_hw_conf = 0x%08X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) (uint8_t) offsetof(struct isp_reg, u2.isp4010.ext_hw_conf),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) readw(&ha->reg->u2.isp4010.ext_hw_conf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) printk(KERN_INFO "0x%02X port_ctrl = 0x%08X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) (uint8_t) offsetof(struct isp_reg, u2.isp4010.port_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) readw(&ha->reg->u2.isp4010.port_ctrl));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) printk(KERN_INFO "0x%02X port_status = 0x%08X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) (uint8_t) offsetof(struct isp_reg, u2.isp4010.port_status),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) readw(&ha->reg->u2.isp4010.port_status));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) printk(KERN_INFO "0x%02X req_q_out = 0x%08X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) (uint8_t) offsetof(struct isp_reg, u2.isp4010.req_q_out),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) readw(&ha->reg->u2.isp4010.req_q_out));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) printk(KERN_INFO "0x%02X gp_out = 0x%08X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) (uint8_t) offsetof(struct isp_reg, u2.isp4010.gp_out),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) readw(&ha->reg->u2.isp4010.gp_out));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) printk(KERN_INFO "0x%02X gp_in = 0x%08X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) (uint8_t) offsetof(struct isp_reg, u2.isp4010.gp_in),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) readw(&ha->reg->u2.isp4010.gp_in));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) printk(KERN_INFO "0x%02X port_err_status = 0x%08X\n", (uint8_t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) offsetof(struct isp_reg, u2.isp4010.port_err_status),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) readw(&ha->reg->u2.isp4010.port_err_status));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) } else if (is_qla4022(ha) | is_qla4032(ha)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) printk(KERN_INFO "Page 0 Registers:\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) printk(KERN_INFO "0x%02X ext_hw_conf = 0x%08X\n", (uint8_t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) offsetof(struct isp_reg, u2.isp4022.p0.ext_hw_conf),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) readw(&ha->reg->u2.isp4022.p0.ext_hw_conf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) printk(KERN_INFO "0x%02X port_ctrl = 0x%08X\n", (uint8_t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) offsetof(struct isp_reg, u2.isp4022.p0.port_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) readw(&ha->reg->u2.isp4022.p0.port_ctrl));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) printk(KERN_INFO "0x%02X port_status = 0x%08X\n", (uint8_t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) offsetof(struct isp_reg, u2.isp4022.p0.port_status),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) readw(&ha->reg->u2.isp4022.p0.port_status));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) printk(KERN_INFO "0x%02X gp_out = 0x%08X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) (uint8_t) offsetof(struct isp_reg, u2.isp4022.p0.gp_out),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) readw(&ha->reg->u2.isp4022.p0.gp_out));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) printk(KERN_INFO "0x%02X gp_in = 0x%08X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) (uint8_t) offsetof(struct isp_reg, u2.isp4022.p0.gp_in),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) readw(&ha->reg->u2.isp4022.p0.gp_in));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) printk(KERN_INFO "0x%02X port_err_status = 0x%08X\n", (uint8_t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) offsetof(struct isp_reg, u2.isp4022.p0.port_err_status),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) readw(&ha->reg->u2.isp4022.p0.port_err_status));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) printk(KERN_INFO "Page 1 Registers:\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) writel(HOST_MEM_CFG_PAGE & set_rmask(CSR_SCSI_PAGE_SELECT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) &ha->reg->ctrl_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) printk(KERN_INFO "0x%02X req_q_out = 0x%08X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) (uint8_t) offsetof(struct isp_reg, u2.isp4022.p1.req_q_out),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) readw(&ha->reg->u2.isp4022.p1.req_q_out));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) writel(PORT_CTRL_STAT_PAGE & set_rmask(CSR_SCSI_PAGE_SELECT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) &ha->reg->ctrl_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) void qla4_8xxx_dump_peg_reg(struct scsi_qla_host *ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) uint32_t halt_status1, halt_status2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) halt_status1 = qla4_8xxx_rd_direct(ha, QLA8XXX_PEG_HALT_STATUS1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) halt_status2 = qla4_8xxx_rd_direct(ha, QLA8XXX_PEG_HALT_STATUS2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) if (is_qla8022(ha)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) ql4_printk(KERN_INFO, ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) "scsi(%ld): %s, ISP%04x Dumping hw/fw registers:\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) " PEG_HALT_STATUS1: 0x%x, PEG_HALT_STATUS2: 0x%x,\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) " PEG_NET_0_PC: 0x%x, PEG_NET_1_PC: 0x%x,\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) " PEG_NET_2_PC: 0x%x, PEG_NET_3_PC: 0x%x,\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) " PEG_NET_4_PC: 0x%x\n", ha->host_no, __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) ha->pdev->device, halt_status1, halt_status2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) qla4_82xx_rd_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x3c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) qla4_82xx_rd_32(ha, QLA82XX_CRB_PEG_NET_1 + 0x3c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) qla4_82xx_rd_32(ha, QLA82XX_CRB_PEG_NET_2 + 0x3c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) qla4_82xx_rd_32(ha, QLA82XX_CRB_PEG_NET_3 + 0x3c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) qla4_82xx_rd_32(ha, QLA82XX_CRB_PEG_NET_4 + 0x3c));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) } else if (is_qla8032(ha) || is_qla8042(ha)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) ql4_printk(KERN_INFO, ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) "scsi(%ld): %s, ISP%04x Dumping hw/fw registers:\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) " PEG_HALT_STATUS1: 0x%x, PEG_HALT_STATUS2: 0x%x,\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) ha->host_no, __func__, ha->pdev->device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) halt_status1, halt_status2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags