^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * QLogic iSCSI HBA Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (c) 2003-2013 QLogic Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #ifndef __QL483XX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define __QL483XX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) /* Indirectly Mapped Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define QLA83XX_FLASH_SPI_STATUS 0x2808E010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define QLA83XX_FLASH_SPI_CONTROL 0x2808E014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define QLA83XX_FLASH_STATUS 0x42100004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define QLA83XX_FLASH_CONTROL 0x42110004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define QLA83XX_FLASH_ADDR 0x42110008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define QLA83XX_FLASH_WRDATA 0x4211000C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define QLA83XX_FLASH_RDDATA 0x42110018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define QLA83XX_FLASH_DIRECT_WINDOW 0x42110030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define QLA83XX_FLASH_DIRECT_DATA(DATA) (0x42150000 | (0x0000FFFF&DATA))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /* Directly Mapped Registers in 83xx register table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /* Flash access regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define QLA83XX_FLASH_LOCK 0x3850
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define QLA83XX_FLASH_UNLOCK 0x3854
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define QLA83XX_FLASH_LOCK_ID 0x3500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /* Driver Lock regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define QLA83XX_DRV_LOCK 0x3868
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define QLA83XX_DRV_UNLOCK 0x386C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define QLA83XX_DRV_LOCK_ID 0x3504
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define QLA83XX_DRV_LOCKRECOVERY 0x379C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* IDC version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define QLA83XX_IDC_VER_MAJ_VALUE 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define QLA83XX_IDC_VER_MIN_VALUE 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* IDC Registers : Driver Coexistence Defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define QLA83XX_CRB_IDC_VER_MAJOR 0x3780
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define QLA83XX_CRB_IDC_VER_MINOR 0x3798
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define QLA83XX_IDC_DRV_CTRL 0x3790
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define QLA83XX_IDC_DRV_AUDIT 0x3794
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define QLA83XX_SRE_SHIM_CONTROL 0x0D200284
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define QLA83XX_PORT0_RXB_PAUSE_THRS 0x0B2003A4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define QLA83XX_PORT1_RXB_PAUSE_THRS 0x0B2013A4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define QLA83XX_PORT0_RXB_TC_MAX_CELL 0x0B200388
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define QLA83XX_PORT1_RXB_TC_MAX_CELL 0x0B201388
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define QLA83XX_PORT0_RXB_TC_STATS 0x0B20039C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define QLA83XX_PORT1_RXB_TC_STATS 0x0B20139C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define QLA83XX_PORT2_IFB_PAUSE_THRS 0x0B200704
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define QLA83XX_PORT3_IFB_PAUSE_THRS 0x0B201704
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /* set value to pause threshold value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define QLA83XX_SET_PAUSE_VAL 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define QLA83XX_SET_TC_MAX_CELL_VAL 0x03FF03FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define QLA83XX_RESET_CONTROL 0x28084E50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define QLA83XX_RESET_REG 0x28084E60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define QLA83XX_RESET_PORT0 0x28084E70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define QLA83XX_RESET_PORT1 0x28084E80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define QLA83XX_RESET_PORT2 0x28084E90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define QLA83XX_RESET_PORT3 0x28084EA0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define QLA83XX_RESET_SRE_SHIM 0x28084EB0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define QLA83XX_RESET_EPG_SHIM 0x28084EC0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define QLA83XX_RESET_ETHER_PCS 0x28084ED0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /* qla_83xx_reg_tbl registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define QLA83XX_PEG_HALT_STATUS1 0x34A8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define QLA83XX_PEG_HALT_STATUS2 0x34AC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define QLA83XX_PEG_ALIVE_COUNTER 0x34B0 /* FW_HEARTBEAT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define QLA83XX_FW_CAPABILITIES 0x3528
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define QLA83XX_CRB_DRV_ACTIVE 0x3788 /* IDC_DRV_PRESENCE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define QLA83XX_CRB_DEV_STATE 0x3784 /* IDC_DEV_STATE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define QLA83XX_CRB_DRV_STATE 0x378C /* IDC_DRV_ACK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define QLA83XX_CRB_DRV_SCRATCH 0x3548
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define QLA83XX_CRB_DEV_PART_INFO1 0x37E0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define QLA83XX_CRB_DEV_PART_INFO2 0x37E4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define QLA83XX_FW_VER_MAJOR 0x3550
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define QLA83XX_FW_VER_MINOR 0x3554
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define QLA83XX_FW_VER_SUB 0x3558
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define QLA83XX_NPAR_STATE 0x359C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define QLA83XX_FW_IMAGE_VALID 0x35FC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define QLA83XX_CMDPEG_STATE 0x3650
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define QLA83XX_ASIC_TEMP 0x37B4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define QLA83XX_FW_API 0x356C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define QLA83XX_DRV_OP_MODE 0x3570
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define QLA83XX_CRB_WIN_BASE 0x3800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define QLA83XX_CRB_WIN_FUNC(f) (QLA83XX_CRB_WIN_BASE+((f)*4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define QLA83XX_SEM_LOCK_BASE 0x3840
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define QLA83XX_SEM_UNLOCK_BASE 0x3844
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define QLA83XX_SEM_LOCK_FUNC(f) (QLA83XX_SEM_LOCK_BASE+((f)*8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define QLA83XX_SEM_UNLOCK_FUNC(f) (QLA83XX_SEM_UNLOCK_BASE+((f)*8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define QLA83XX_LINK_STATE(f) (0x3698+((f) > 7 ? 4 : 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define QLA83XX_LINK_SPEED(f) (0x36E0+(((f) >> 2) * 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define QLA83XX_MAX_LINK_SPEED(f) (0x36F0+(((f) / 4) * 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define QLA83XX_LINK_SPEED_FACTOR 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* FLASH API Defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define QLA83xx_FLASH_MAX_WAIT_USEC 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define QLA83XX_FLASH_LOCK_TIMEOUT 10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define QLA83XX_FLASH_SECTOR_SIZE 65536
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define QLA83XX_DRV_LOCK_TIMEOUT 2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define QLA83XX_FLASH_SECTOR_ERASE_CMD 0xdeadbeef
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define QLA83XX_FLASH_WRITE_CMD 0xdacdacda
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define QLA83XX_FLASH_BUFFER_WRITE_CMD 0xcadcadca
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define QLA83XX_FLASH_READ_RETRY_COUNT 2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define QLA83XX_FLASH_STATUS_READY 0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define QLA83XX_FLASH_BUFFER_WRITE_MIN 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define QLA83XX_FLASH_BUFFER_WRITE_MAX 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define QLA83XX_FLASH_STATUS_REG_POLL_DELAY 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define QLA83XX_ERASE_MODE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define QLA83XX_WRITE_MODE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define QLA83XX_DWORD_WRITE_MODE 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define QLA83XX_GLOBAL_RESET 0x38CC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define QLA83XX_WILDCARD 0x38F0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define QLA83XX_INFORMANT 0x38FC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define QLA83XX_HOST_MBX_CTRL 0x3038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define QLA83XX_FW_MBX_CTRL 0x303C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define QLA83XX_BOOTLOADER_ADDR 0x355C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define QLA83XX_BOOTLOADER_SIZE 0x3560
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define QLA83XX_FW_IMAGE_ADDR 0x3564
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define QLA83XX_MBX_INTR_ENABLE 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define QLA83XX_MBX_INTR_MASK 0x1200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /* IDC Control Register bit defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define DONTRESET_BIT0 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define GRACEFUL_RESET_BIT1 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define QLA83XX_HALT_STATUS_INFORMATIONAL (0x1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define QLA83XX_HALT_STATUS_FW_RESET (0x2 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define QLA83XX_HALT_STATUS_UNRECOVERABLE (0x4 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /* Firmware image definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define QLA83XX_BOOTLOADER_FLASH_ADDR 0x10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define QLA83XX_BOOT_FROM_FLASH 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define QLA83XX_IDC_PARAM_ADDR 0x3e8020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /* Reset template definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define QLA83XX_MAX_RESET_SEQ_ENTRIES 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define QLA83XX_RESTART_TEMPLATE_SIZE 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define QLA83XX_RESET_TEMPLATE_ADDR 0x4F0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define QLA83XX_RESET_SEQ_VERSION 0x0101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /* Reset template entry opcodes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define OPCODE_NOP 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define OPCODE_WRITE_LIST 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define OPCODE_READ_WRITE_LIST 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define OPCODE_POLL_LIST 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define OPCODE_POLL_WRITE_LIST 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define OPCODE_READ_MODIFY_WRITE 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define OPCODE_SEQ_PAUSE 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define OPCODE_SEQ_END 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define OPCODE_TMPL_END 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define OPCODE_POLL_READ_LIST 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /* Template Header */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define RESET_TMPLT_HDR_SIGNATURE 0xCAFE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) struct qla4_83xx_reset_template_hdr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) __le16 version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) __le16 signature;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) __le16 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) __le16 entries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) __le16 hdr_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) __le16 checksum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) __le16 init_seq_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) __le16 start_seq_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /* Common Entry Header. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) struct qla4_83xx_reset_entry_hdr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) __le16 cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) __le16 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) __le16 count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) __le16 delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) /* Generic poll entry type. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) struct qla4_83xx_poll {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) __le32 test_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) __le32 test_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /* Read modify write entry type. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) struct qla4_83xx_rmw {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) __le32 test_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) __le32 xor_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) __le32 or_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) uint8_t shl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) uint8_t shr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) uint8_t index_a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) uint8_t rsvd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) /* Generic Entry Item with 2 DWords. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) struct qla4_83xx_entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) __le32 arg1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) __le32 arg2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) /* Generic Entry Item with 4 DWords.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) struct qla4_83xx_quad_entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) __le32 dr_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) __le32 dr_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) __le32 ar_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) __le32 ar_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) struct qla4_83xx_reset_template {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) int seq_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) int seq_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) int array_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) uint32_t array[QLA83XX_MAX_RESET_SEQ_ENTRIES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) uint8_t *buff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) uint8_t *stop_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) uint8_t *start_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) uint8_t *init_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) struct qla4_83xx_reset_template_hdr *hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) uint8_t seq_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) uint8_t template_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) /* POLLRD Entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) struct qla83xx_minidump_entry_pollrd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) struct qla8xxx_minidump_entry_hdr h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) uint32_t select_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) uint32_t read_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) uint32_t select_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) uint16_t select_value_stride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) uint16_t op_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) uint32_t poll_wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) uint32_t poll_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) uint32_t data_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) uint32_t rsvd_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) struct qla8044_minidump_entry_rddfe {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) struct qla8xxx_minidump_entry_hdr h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) uint32_t addr_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) uint32_t value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) uint8_t stride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) uint8_t stride2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) uint16_t count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) uint32_t poll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) uint32_t mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) uint32_t modify_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) uint32_t data_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) uint32_t rsvd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) struct qla8044_minidump_entry_rdmdio {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) struct qla8xxx_minidump_entry_hdr h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) uint32_t addr_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) uint32_t addr_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) uint32_t value_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) uint8_t stride_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) uint8_t stride_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) uint16_t count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) uint32_t poll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) uint32_t mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) uint32_t value_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) uint32_t data_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) struct qla8044_minidump_entry_pollwr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) struct qla8xxx_minidump_entry_hdr h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) uint32_t addr_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) uint32_t addr_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) uint32_t value_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) uint32_t value_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) uint32_t poll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) uint32_t mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) uint32_t data_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) uint32_t rsvd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) /* RDMUX2 Entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) struct qla83xx_minidump_entry_rdmux2 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) struct qla8xxx_minidump_entry_hdr h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) uint32_t select_addr_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) uint32_t select_addr_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) uint32_t select_value_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) uint32_t select_value_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) uint32_t op_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) uint32_t select_value_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) uint32_t read_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) uint8_t select_value_stride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) uint8_t data_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) uint8_t rsvd[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) /* POLLRDMWR Entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) struct qla83xx_minidump_entry_pollrdmwr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) struct qla8xxx_minidump_entry_hdr h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) uint32_t addr_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) uint32_t addr_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) uint32_t value_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) uint32_t value_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) uint32_t poll_wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) uint32_t poll_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) uint32_t modify_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) uint32_t data_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) /* IDC additional information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) struct qla4_83xx_idc_information {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) uint32_t request_desc; /* IDC request descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) uint32_t info1; /* IDC additional info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) uint32_t info2; /* IDC additional info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) uint32_t info3; /* IDC additional info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define QLA83XX_PEX_DMA_ENGINE_INDEX 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define QLA83XX_PEX_DMA_BASE_ADDRESS 0x77320000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define QLA83XX_PEX_DMA_NUM_OFFSET 0x10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define QLA83XX_PEX_DMA_CMD_ADDR_LOW 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define QLA83XX_PEX_DMA_CMD_ADDR_HIGH 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define QLA83XX_PEX_DMA_CMD_STS_AND_CNTRL 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define QLA83XX_PEX_DMA_READ_SIZE (16 * 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define QLA83XX_PEX_DMA_MAX_WAIT (100 * 100) /* Max wait of 100 msecs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) /* Read Memory: For Pex-DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) struct qla4_83xx_minidump_entry_rdmem_pex_dma {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) struct qla8xxx_minidump_entry_hdr h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) uint32_t desc_card_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) uint16_t dma_desc_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) uint8_t rsvd[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) uint32_t start_dma_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) uint8_t rsvd2[12];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) uint32_t read_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) uint32_t read_data_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) struct qla4_83xx_pex_dma_descriptor {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) uint32_t read_data_size; /* 0-23: size, 24-31: rsvd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) uint8_t rsvd[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) uint16_t dma_desc_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) } cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) uint64_t src_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) uint64_t dma_bus_addr; /* 0-3: desc-cmd, 4-7: pci-func,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) * 8-15: desc-cmd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) uint8_t rsvd[24];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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