^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * QLogic Fibre Channel HBA Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (c) 2003-2014 QLogic Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #ifndef __QLA_DMP27_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define __QLA_DMP27_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define IOBASE_ADDR offsetof(struct device_reg_24xx, iobase_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) struct __packed qla27xx_fwdt_template {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) __le32 template_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) __le32 entry_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) __le32 template_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) uint32_t count; /* borrow field for running/residual count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) __le32 entry_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) uint32_t template_version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) __le32 capture_timestamp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) uint32_t template_checksum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) uint32_t reserved_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) __le32 driver_info[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) uint32_t saved_state[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) uint32_t reserved_3[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) __le32 firmware_version[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define TEMPLATE_TYPE_FWDUMP 99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define ENTRY_TYPE_NOP 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define ENTRY_TYPE_TMP_END 255
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define ENTRY_TYPE_RD_IOB_T1 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define ENTRY_TYPE_WR_IOB_T1 257
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define ENTRY_TYPE_RD_IOB_T2 258
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define ENTRY_TYPE_WR_IOB_T2 259
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define ENTRY_TYPE_RD_PCI 260
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define ENTRY_TYPE_WR_PCI 261
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define ENTRY_TYPE_RD_RAM 262
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define ENTRY_TYPE_GET_QUEUE 263
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define ENTRY_TYPE_GET_FCE 264
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define ENTRY_TYPE_PSE_RISC 265
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define ENTRY_TYPE_RST_RISC 266
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define ENTRY_TYPE_DIS_INTR 267
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define ENTRY_TYPE_GET_HBUF 268
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define ENTRY_TYPE_SCRATCH 269
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define ENTRY_TYPE_RDREMREG 270
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define ENTRY_TYPE_WRREMREG 271
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define ENTRY_TYPE_RDREMRAM 272
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define ENTRY_TYPE_PCICFG 273
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define ENTRY_TYPE_GET_SHADOW 274
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define ENTRY_TYPE_WRITE_BUF 275
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define ENTRY_TYPE_CONDITIONAL 276
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define ENTRY_TYPE_RDPEPREG 277
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define ENTRY_TYPE_WRPEPREG 278
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define CAPTURE_FLAG_PHYS_ONLY BIT_0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define CAPTURE_FLAG_PHYS_VIRT BIT_1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define DRIVER_FLAG_SKIP_ENTRY BIT_7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct __packed qla27xx_fwdt_entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct __packed {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) __le32 type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) __le32 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) uint32_t reserved_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) uint8_t capture_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) uint8_t reserved_2[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) uint8_t driver_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) } hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) union __packed {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct __packed {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) } t0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) struct __packed {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) } t255;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct __packed {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) __le32 base_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) uint8_t reg_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) __le16 reg_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) uint8_t pci_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) } t256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct __packed {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) __le32 base_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) __le32 write_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) uint8_t pci_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) uint8_t reserved[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) } t257;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) struct __packed {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) __le32 base_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) uint8_t reg_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) __le16 reg_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) uint8_t pci_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) uint8_t banksel_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) uint8_t reserved[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) __le32 bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) } t258;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) struct __packed {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) __le32 base_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) __le32 write_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) uint8_t reserved[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) uint8_t pci_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) uint8_t banksel_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) __le32 bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) } t259;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct __packed {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) uint8_t pci_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) uint8_t reserved[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) } t260;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct __packed {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) uint8_t pci_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) uint8_t reserved[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) __le32 write_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) } t261;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct __packed {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) uint8_t ram_area;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) uint8_t reserved[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) __le32 start_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) __le32 end_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) } t262;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct __packed {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) uint32_t num_queues;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) uint8_t queue_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) uint8_t reserved[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) } t263;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) struct __packed {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) uint32_t fce_trace_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) uint64_t write_pointer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) uint64_t base_pointer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) uint32_t fce_enable_mb0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) uint32_t fce_enable_mb2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) uint32_t fce_enable_mb3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) uint32_t fce_enable_mb4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) uint32_t fce_enable_mb5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) uint32_t fce_enable_mb6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) } t264;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) struct __packed {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) } t265;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) struct __packed {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) } t266;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) struct __packed {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) uint8_t pci_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) uint8_t reserved[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) __le32 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) } t267;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) struct __packed {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) uint8_t buf_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) uint8_t reserved[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) uint32_t buf_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) uint64_t start_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) } t268;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) struct __packed {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) uint32_t scratch_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) } t269;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) struct __packed {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) __le32 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) __le32 count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) } t270;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) struct __packed {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) __le32 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) __le32 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) } t271;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) struct __packed {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) __le32 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) __le32 count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) } t272;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) struct __packed {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) __le32 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) __le32 count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) } t273;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) struct __packed {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) uint32_t num_queues;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) uint8_t queue_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) uint8_t reserved[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) } t274;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) struct __packed {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) __le32 length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) uint8_t buffer[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) } t275;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) struct __packed {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) __le32 cond1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) __le32 cond2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) } t276;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) struct __packed {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) __le32 cmd_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) __le32 wr_cmd_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) __le32 data_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) } t277;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) struct __packed {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) __le32 cmd_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) __le32 wr_cmd_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) __le32 data_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) __le32 wr_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) } t278;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define T262_RAM_AREA_CRITICAL_RAM 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define T262_RAM_AREA_EXTERNAL_RAM 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define T262_RAM_AREA_SHARED_RAM 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define T262_RAM_AREA_DDR_RAM 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define T262_RAM_AREA_MISC 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define T263_QUEUE_TYPE_REQ 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define T263_QUEUE_TYPE_RSP 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define T263_QUEUE_TYPE_ATIO 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define T268_BUF_TYPE_EXTD_TRACE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define T268_BUF_TYPE_EXCH_BUFOFF 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define T268_BUF_TYPE_EXTD_LOGIN 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define T268_BUF_TYPE_REQ_MIRROR 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define T268_BUF_TYPE_RSP_MIRROR 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define T274_QUEUE_TYPE_REQ_SHAD 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define T274_QUEUE_TYPE_RSP_SHAD 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define T274_QUEUE_TYPE_ATIO_SHAD 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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