^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2004 - 2010 Vladislav Bolkhovitin <vst@vlnb.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2004 - 2005 Leonid Stoljar
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2006 Nathaniel Clark <nate@misrule.us>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2007 - 2010 ID7 Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Forward port and refactoring to modern qla2xxx and target/configfs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Copyright (C) 2010-2011 Nicholas A. Bellinger <nab@kernel.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Additional file for the target driver support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * This is the global def file that is useful for including from the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * target portion.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #ifndef __QLA_TARGET_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define __QLA_TARGET_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "qla_def.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include "qla_dsd.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * Must be changed on any change in any initiator visible interfaces or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * data in the target add-on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define QLA2XXX_TARGET_MAGIC 269
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * Must be changed on any change in any target visible interfaces or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * data in the initiator
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define QLA2XXX_INITIATOR_MAGIC 57222
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define QLA2XXX_INI_MODE_STR_EXCLUSIVE "exclusive"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define QLA2XXX_INI_MODE_STR_DISABLED "disabled"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define QLA2XXX_INI_MODE_STR_ENABLED "enabled"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define QLA2XXX_INI_MODE_STR_DUAL "dual"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define QLA2XXX_INI_MODE_EXCLUSIVE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define QLA2XXX_INI_MODE_DISABLED 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define QLA2XXX_INI_MODE_ENABLED 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define QLA2XXX_INI_MODE_DUAL 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define QLA2XXX_COMMAND_COUNT_INIT 250
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define QLA2XXX_IMMED_NOTIFY_COUNT_INIT 250
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * Used to mark which completion handles (for RIO Status's) are for CTIO's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * vs. regular (non-target) info. This is checked for in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * qla2x00_process_response_queue() to see if a handle coming back in a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * multi-complete should come to the tgt driver or be handled there by qla2xxx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define CTIO_COMPLETION_HANDLE_MARK BIT_29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #if (CTIO_COMPLETION_HANDLE_MARK <= DEFAULT_OUTSTANDING_COMMANDS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #error "CTIO_COMPLETION_HANDLE_MARK not larger than "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) "DEFAULT_OUTSTANDING_COMMANDS"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define HANDLE_IS_CTIO_COMP(h) (h & CTIO_COMPLETION_HANDLE_MARK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /* Used to mark CTIO as intermediate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define CTIO_INTERMEDIATE_HANDLE_MARK BIT_30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define QLA_TGT_NULL_HANDLE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define QLA_TGT_HANDLE_MASK 0xF0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define QLA_QPID_HANDLE_MASK 0x00FF0000 /* qpair id mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define QLA_CMD_HANDLE_MASK 0x0000FFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define QLA_TGT_SKIP_HANDLE (0xFFFFFFFF & ~QLA_TGT_HANDLE_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define QLA_QPID_HANDLE_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define GET_QID(_h) ((_h & QLA_QPID_HANDLE_MASK) >> QLA_QPID_HANDLE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #ifndef OF_SS_MODE_0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * ISP target entries - Flags bit definitions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define OF_SS_MODE_0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define OF_SS_MODE_1 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define OF_SS_MODE_2 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define OF_SS_MODE_3 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define OF_EXPL_CONF BIT_5 /* Explicit Confirmation Requested */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define OF_DATA_IN BIT_6 /* Data in to initiator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* (data from target to initiator) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define OF_DATA_OUT BIT_7 /* Data out from initiator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /* (data from initiator to target) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define OF_NO_DATA (BIT_7 | BIT_6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define OF_INC_RC BIT_8 /* Increment command resource count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define OF_FAST_POST BIT_9 /* Enable mailbox fast posting. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define OF_CONF_REQ BIT_13 /* Confirmation Requested */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define OF_TERM_EXCH BIT_14 /* Terminate exchange */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define OF_SSTS BIT_15 /* Send SCSI status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #ifndef QLA_TGT_DATASEGS_PER_CMD32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define QLA_TGT_DATASEGS_PER_CMD32 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define QLA_TGT_DATASEGS_PER_CONT32 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define QLA_TGT_MAX_SG32(ql) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) (((ql) > 0) ? (QLA_TGT_DATASEGS_PER_CMD32 + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) QLA_TGT_DATASEGS_PER_CONT32*((ql) - 1)) : 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define QLA_TGT_DATASEGS_PER_CMD64 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define QLA_TGT_DATASEGS_PER_CONT64 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define QLA_TGT_MAX_SG64(ql) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) (((ql) > 0) ? (QLA_TGT_DATASEGS_PER_CMD64 + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) QLA_TGT_DATASEGS_PER_CONT64*((ql) - 1)) : 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #ifndef QLA_TGT_DATASEGS_PER_CMD_24XX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define QLA_TGT_DATASEGS_PER_CMD_24XX 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define QLA_TGT_DATASEGS_PER_CONT_24XX 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define QLA_TGT_MAX_SG_24XX(ql) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) (min(1270, ((ql) > 0) ? (QLA_TGT_DATASEGS_PER_CMD_24XX + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) QLA_TGT_DATASEGS_PER_CONT_24XX*((ql) - 1)) : 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define GET_TARGET_ID(ha, iocb) ((HAS_EXTENDED_IDS(ha)) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) ? le16_to_cpu((iocb)->u.isp2x.target.extended) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) : (uint16_t)(iocb)->u.isp2x.target.id.standard)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #ifndef NOTIFY_ACK_TYPE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define NOTIFY_ACK_TYPE 0x0E /* Notify acknowledge entry. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * ISP queue - notify acknowledge entry structure definition.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * This is sent to the ISP from the target driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) struct nack_to_isp {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) uint8_t entry_type; /* Entry type. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) uint8_t entry_count; /* Entry count. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) uint8_t sys_define; /* System defined. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) uint8_t entry_status; /* Entry Status. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) __le32 sys_define_2; /* System defined. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) target_id_t target;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) uint8_t target_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) uint8_t reserved_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) __le16 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) __le16 resp_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) __le16 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) __le16 task_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) __le16 seq_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) __le16 srr_rx_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) __le32 srr_rel_offs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) __le16 srr_ui;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) __le16 srr_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) __le16 srr_reject_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) uint8_t srr_reject_vendor_uniq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) uint8_t srr_reject_code_expl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) uint8_t reserved_2[24];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) } isp2x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) uint32_t handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) __le16 nport_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) uint16_t reserved_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) __le16 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) __le16 srr_rx_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) __le16 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) uint8_t status_subcode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) uint8_t fw_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) __le32 exchange_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) __le32 srr_rel_offs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) __le16 srr_ui;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) __le16 srr_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) uint8_t reserved_4[19];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) uint8_t vp_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) uint8_t srr_reject_vendor_uniq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) uint8_t srr_reject_code_expl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) uint8_t srr_reject_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) uint8_t reserved_5[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) } isp24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) } u;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) uint8_t reserved[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) __le16 ox_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define NOTIFY_ACK_FLAGS_TERMINATE BIT_3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define NOTIFY_ACK_SRR_FLAGS_ACCEPT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define NOTIFY_ACK_SRR_FLAGS_REJECT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define NOTIFY_ACK_SRR_REJECT_REASON_UNABLE_TO_PERFORM 0x9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define NOTIFY_ACK_SRR_FLAGS_REJECT_EXPL_NO_EXPL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define NOTIFY_ACK_SRR_FLAGS_REJECT_EXPL_UNABLE_TO_SUPPLY_DATA 0x2a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define NOTIFY_ACK_SUCCESS 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #ifndef ACCEPT_TGT_IO_TYPE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define ACCEPT_TGT_IO_TYPE 0x16 /* Accept target I/O entry. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #ifndef CONTINUE_TGT_IO_TYPE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define CONTINUE_TGT_IO_TYPE 0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) * ISP queue - Continue Target I/O (CTIO) entry for status mode 0 structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) * This structure is sent to the ISP 2xxx from target driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) struct ctio_to_2xxx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) uint8_t entry_type; /* Entry type. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) uint8_t entry_count; /* Entry count. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) uint8_t sys_define; /* System defined. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) uint8_t entry_status; /* Entry Status. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) uint32_t handle; /* System defined handle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) target_id_t target;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) __le16 rx_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) __le16 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) __le16 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) __le16 timeout; /* 0 = 30 seconds, 0xFFFF = disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) __le16 dseg_count; /* Data segment count. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) __le32 relative_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) __le32 residual;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) __le16 reserved_1[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) __le16 scsi_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) __le32 transfer_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) struct dsd32 dsd[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define ATIO_PATH_INVALID 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define ATIO_CANT_PROV_CAP 0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define ATIO_CDB_VALID 0x3D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define ATIO_EXEC_READ BIT_1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define ATIO_EXEC_WRITE BIT_0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #ifndef CTIO_A64_TYPE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define CTIO_A64_TYPE 0x1F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define CTIO_SUCCESS 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define CTIO_ABORTED 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define CTIO_INVALID_RX_ID 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define CTIO_TIMEOUT 0x0B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define CTIO_DIF_ERROR 0x0C /* DIF error detected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define CTIO_LIP_RESET 0x0E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define CTIO_TARGET_RESET 0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define CTIO_PORT_UNAVAILABLE 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define CTIO_PORT_LOGGED_OUT 0x29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define CTIO_PORT_CONF_CHANGED 0x2A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define CTIO_SRR_RECEIVED 0x45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #ifndef CTIO_RET_TYPE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define CTIO_RET_TYPE 0x17 /* CTIO return entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define ATIO_TYPE7 0x06 /* Accept target I/O entry for 24xx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) struct fcp_hdr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) uint8_t r_ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) be_id_t d_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) uint8_t cs_ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) be_id_t s_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) uint8_t type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) uint8_t f_ctl[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) uint8_t seq_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) uint8_t df_ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) uint16_t seq_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) __be16 ox_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) uint16_t rx_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) __le32 parameter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) struct fcp_hdr_le {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) le_id_t d_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) uint8_t r_ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) le_id_t s_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) uint8_t cs_ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) uint8_t f_ctl[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) uint8_t type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) __le16 seq_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) uint8_t df_ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) uint8_t seq_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) __le16 rx_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) __le16 ox_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) __le32 parameter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define F_CTL_EXCH_CONTEXT_RESP BIT_23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define F_CTL_SEQ_CONTEXT_RESIP BIT_22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define F_CTL_LAST_SEQ BIT_20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define F_CTL_END_SEQ BIT_19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define F_CTL_SEQ_INITIATIVE BIT_16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define R_CTL_BASIC_LINK_SERV 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define R_CTL_B_ACC 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define R_CTL_B_RJT 0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) struct atio7_fcp_cmnd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) uint64_t lun;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) uint8_t cmnd_ref;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) uint8_t task_attr:3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) uint8_t reserved:5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) uint8_t task_mgmt_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define FCP_CMND_TASK_MGMT_CLEAR_ACA 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define FCP_CMND_TASK_MGMT_TARGET_RESET 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define FCP_CMND_TASK_MGMT_LU_RESET 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define FCP_CMND_TASK_MGMT_CLEAR_TASK_SET 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define FCP_CMND_TASK_MGMT_ABORT_TASK_SET 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) uint8_t wrdata:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) uint8_t rddata:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) uint8_t add_cdb_len:6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) uint8_t cdb[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) * add_cdb is optional and can absent from struct atio7_fcp_cmnd. Size 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) * only to make sizeof(struct atio7_fcp_cmnd) be as expected by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) * BUILD_BUG_ON in qlt_init().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) uint8_t add_cdb[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) /* __le32 data_length; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) * ISP queue - Accept Target I/O (ATIO) type entry IOCB structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) * This is sent from the ISP to the target driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) struct atio_from_isp {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) __le16 entry_hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) uint8_t sys_define; /* System defined. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) uint8_t entry_status; /* Entry Status. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) __le32 sys_define_2; /* System defined. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) target_id_t target;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) __le16 rx_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) __le16 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) __le16 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) uint8_t command_ref;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) uint8_t task_codes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) uint8_t task_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) uint8_t execution_codes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) uint8_t cdb[MAX_CMDSZ];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) __le32 data_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) __le16 lun;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) uint8_t initiator_port_name[WWN_SIZE]; /* on qla23xx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) __le16 reserved_32[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) __le16 ox_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) } isp2x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) __le16 entry_hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) uint8_t fcp_cmnd_len_low;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) uint8_t fcp_cmnd_len_high:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) uint8_t attr:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) __le32 exchange_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define ATIO_EXCHANGE_ADDRESS_UNKNOWN 0xFFFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) struct fcp_hdr fcp_hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) struct atio7_fcp_cmnd fcp_cmnd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) } isp24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) uint8_t entry_type; /* Entry type. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) uint8_t entry_count; /* Entry count. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) __le16 attr_n_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define FCP_CMD_LENGTH_MASK 0x0fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define FCP_CMD_LENGTH_MIN 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) uint8_t data[56];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) __le32 signature;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define ATIO_PROCESSED 0xDEADDEAD /* Signature */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) } raw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) } u;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) static inline int fcpcmd_is_corrupted(struct atio *atio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) if (atio->entry_type == ATIO_TYPE7 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) ((le16_to_cpu(atio->attr_n_length) & FCP_CMD_LENGTH_MASK) <
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) FCP_CMD_LENGTH_MIN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) /* adjust corrupted atio so we won't trip over the same entry again. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) static inline void adjust_corrupted_atio(struct atio_from_isp *atio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) atio->u.raw.attr_n_length = cpu_to_le16(FCP_CMD_LENGTH_MIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) atio->u.isp24.fcp_cmnd.add_cdb_len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) static inline int get_datalen_for_atio(struct atio_from_isp *atio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) int len = atio->u.isp24.fcp_cmnd.add_cdb_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) return get_unaligned_be32(&atio->u.isp24.fcp_cmnd.add_cdb[len * 4]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define CTIO_TYPE7 0x12 /* Continue target I/O entry (for 24xx) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) * ISP queue - Continue Target I/O (ATIO) type 7 entry (for 24xx) structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) * This structure is sent to the ISP 24xx from the target driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) struct ctio7_to_24xx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) uint8_t entry_type; /* Entry type. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) uint8_t entry_count; /* Entry count. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) uint8_t sys_define; /* System defined. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) uint8_t entry_status; /* Entry Status. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) uint32_t handle; /* System defined handle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) __le16 nport_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define CTIO7_NHANDLE_UNRECOGNIZED 0xFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) __le16 timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) __le16 dseg_count; /* Data segment count. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) uint8_t vp_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) uint8_t add_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) le_id_t initiator_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) uint8_t reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) __le32 exchange_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) __le16 reserved1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) __le16 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) __le32 residual;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) __le16 ox_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) __le16 scsi_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) __le32 relative_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) __le32 reserved2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) __le32 transfer_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) __le32 reserved3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) struct dsd64 dsd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) } status0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) __le16 sense_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) __le16 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) __le32 residual;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) __le16 ox_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) __le16 scsi_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) __le16 response_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) __le16 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) uint8_t sense_data[24];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) } status1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) } u;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) * ISP queue - CTIO type 7 from ISP 24xx to target driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) * returned entry structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) struct ctio7_from_24xx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) uint8_t entry_type; /* Entry type. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) uint8_t entry_count; /* Entry count. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) uint8_t sys_define; /* System defined. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) uint8_t entry_status; /* Entry Status. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) uint32_t handle; /* System defined handle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) __le16 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) __le16 timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) __le16 dseg_count; /* Data segment count. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) uint8_t vp_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) uint8_t reserved1[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) __le32 exchange_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) __le16 reserved2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) __le16 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) __le32 residual;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) __le16 ox_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) __le16 reserved3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) __le32 relative_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) uint8_t reserved4[24];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) /* CTIO7 flags values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) #define CTIO7_FLAGS_SEND_STATUS BIT_15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) #define CTIO7_FLAGS_TERMINATE BIT_14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) #define CTIO7_FLAGS_CONFORM_REQ BIT_13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) #define CTIO7_FLAGS_DONT_RET_CTIO BIT_8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) #define CTIO7_FLAGS_STATUS_MODE_0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) #define CTIO7_FLAGS_STATUS_MODE_1 BIT_6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) #define CTIO7_FLAGS_STATUS_MODE_2 BIT_7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) #define CTIO7_FLAGS_EXPLICIT_CONFORM BIT_5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) #define CTIO7_FLAGS_CONFIRM_SATISF BIT_4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) #define CTIO7_FLAGS_DSD_PTR BIT_2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) #define CTIO7_FLAGS_DATA_IN BIT_1 /* data to initiator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) #define CTIO7_FLAGS_DATA_OUT BIT_0 /* data from initiator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) #define ELS_PLOGI 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) #define ELS_FLOGI 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) #define ELS_LOGO 0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) #define ELS_PRLI 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) #define ELS_PRLO 0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) #define ELS_TPRLO 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) #define ELS_PDISC 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) #define ELS_ADISC 0x52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) *CTIO Type CRC_2 IOCB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) struct ctio_crc2_to_fw {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) uint8_t entry_type; /* Entry type. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) #define CTIO_CRC2 0x7A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) uint8_t entry_count; /* Entry count. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) uint8_t sys_define; /* System defined. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) uint8_t entry_status; /* Entry Status. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) uint32_t handle; /* System handle. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) __le16 nport_handle; /* N_PORT handle. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) __le16 timeout; /* Command timeout. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) __le16 dseg_count; /* Data segment count. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) uint8_t vp_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) uint8_t add_flags; /* additional flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) #define CTIO_CRC2_AF_DIF_DSD_ENA BIT_3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) le_id_t initiator_id; /* initiator ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) uint8_t reserved1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) __le32 exchange_addr; /* rcv exchange address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) __le16 reserved2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) __le16 flags; /* refer to CTIO7 flags values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) __le32 residual;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) __le16 ox_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) __le16 scsi_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) __le32 relative_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) __le32 reserved5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) __le32 transfer_length; /* total fc transfer length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) __le32 reserved6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) __le64 crc_context_address __packed; /* Data segment address. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) __le16 crc_context_len; /* Data segment length. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) __le16 reserved_1; /* MUST be set to 0. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) /* CTIO Type CRC_x Status IOCB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) struct ctio_crc_from_fw {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) uint8_t entry_type; /* Entry type. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) uint8_t entry_count; /* Entry count. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) uint8_t sys_define; /* System defined. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) uint8_t entry_status; /* Entry Status. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) uint32_t handle; /* System handle. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) __le16 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) __le16 timeout; /* Command timeout. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) __le16 dseg_count; /* Data segment count. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) __le32 reserved1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) __le16 state_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) #define CTIO_CRC_SF_DIF_CHOPPED BIT_4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) __le32 exchange_address; /* rcv exchange address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) __le16 reserved2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) __le16 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) __le32 resid_xfer_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) __le16 ox_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) uint8_t reserved3[12];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) __le16 runt_guard; /* reported runt blk guard */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) uint8_t actual_dif[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) uint8_t expected_dif[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) * ISP queue - ABTS received/response entries structure definition for 24xx.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) #define ABTS_RECV_24XX 0x54 /* ABTS received (for 24xx) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) #define ABTS_RESP_24XX 0x55 /* ABTS responce (for 24xx) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) * ISP queue - ABTS received IOCB entry structure definition for 24xx.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) * The ABTS BLS received from the wire is sent to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) * target driver by the ISP 24xx.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) * The IOCB is placed on the response queue.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) struct abts_recv_from_24xx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) uint8_t entry_type; /* Entry type. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) uint8_t entry_count; /* Entry count. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) uint8_t sys_define; /* System defined. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) uint8_t entry_status; /* Entry Status. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) uint8_t reserved_1[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) __le16 nport_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) uint8_t reserved_2[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) uint8_t vp_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) uint8_t reserved_3:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) uint8_t sof_type:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) __le32 exchange_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) struct fcp_hdr_le fcp_hdr_le;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) uint8_t reserved_4[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) __le32 exchange_addr_to_abort;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) #define ABTS_PARAM_ABORT_SEQ BIT_0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) struct ba_acc_le {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) __le16 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) uint8_t seq_id_last;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) uint8_t seq_id_valid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) #define SEQ_ID_VALID 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) #define SEQ_ID_INVALID 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) __le16 rx_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) __le16 ox_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) __le16 high_seq_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) __le16 low_seq_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) struct ba_rjt_le {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) uint8_t vendor_uniq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) uint8_t reason_expl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) uint8_t reason_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) #define BA_RJT_REASON_CODE_INVALID_COMMAND 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) #define BA_RJT_REASON_CODE_UNABLE_TO_PERFORM 0x9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) uint8_t reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) * ISP queue - ABTS Response IOCB entry structure definition for 24xx.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) * The ABTS response to the ABTS received is sent by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) * target driver to the ISP 24xx.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) * The IOCB is placed on the request queue.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) struct abts_resp_to_24xx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) uint8_t entry_type; /* Entry type. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) uint8_t entry_count; /* Entry count. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) uint8_t sys_define; /* System defined. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) uint8_t entry_status; /* Entry Status. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) uint32_t handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) __le16 reserved_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) __le16 nport_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) __le16 control_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) #define ABTS_CONTR_FLG_TERM_EXCHG BIT_0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) uint8_t vp_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) uint8_t reserved_3:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) uint8_t sof_type:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) __le32 exchange_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) struct fcp_hdr_le fcp_hdr_le;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) struct ba_acc_le ba_acct;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) struct ba_rjt_le ba_rjt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) } __packed payload;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) __le32 reserved_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) __le32 exchange_addr_to_abort;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) * ISP queue - ABTS Response IOCB from ISP24xx Firmware entry structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) * The ABTS response with completion status to the ABTS response
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) * (sent by the target driver to the ISP 24xx) is sent by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) * ISP24xx firmware to the target driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) * The IOCB is placed on the response queue.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) struct abts_resp_from_24xx_fw {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) uint8_t entry_type; /* Entry type. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) uint8_t entry_count; /* Entry count. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) uint8_t sys_define; /* System defined. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) uint8_t entry_status; /* Entry Status. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) uint32_t handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) __le16 compl_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) #define ABTS_RESP_COMPL_SUCCESS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) #define ABTS_RESP_COMPL_SUBCODE_ERROR 0x31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) __le16 nport_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) __le16 reserved_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) uint8_t reserved_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) uint8_t reserved_3:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) uint8_t sof_type:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) __le32 exchange_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) struct fcp_hdr_le fcp_hdr_le;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) uint8_t reserved_4[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) __le32 error_subcode1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) #define ABTS_RESP_SUBCODE_ERR_ABORTED_EXCH_NOT_TERM 0x1E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) __le32 error_subcode2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) __le32 exchange_addr_to_abort;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) /********************************************************************\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) * Type Definitions used by initiator & target halves
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) \********************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) struct qla_tgt_mgmt_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) struct fc_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) struct qla_tgt_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) * This structure provides a template of function calls that the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) * target driver (from within qla_target.c) can issue to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) * target module (tcm_qla2xxx).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) struct qla_tgt_func_tmpl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) struct qla_tgt_cmd *(*find_cmd_by_tag)(struct fc_port *, uint64_t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) int (*handle_cmd)(struct scsi_qla_host *, struct qla_tgt_cmd *,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) unsigned char *, uint32_t, int, int, int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) void (*handle_data)(struct qla_tgt_cmd *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) int (*handle_tmr)(struct qla_tgt_mgmt_cmd *, u64, uint16_t,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) uint32_t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) struct qla_tgt_cmd *(*get_cmd)(struct fc_port *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) void (*rel_cmd)(struct qla_tgt_cmd *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) void (*free_cmd)(struct qla_tgt_cmd *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) void (*free_mcmd)(struct qla_tgt_mgmt_cmd *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) void (*free_session)(struct fc_port *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) int (*check_initiator_node_acl)(struct scsi_qla_host *, unsigned char *,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) struct fc_port *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) void (*update_sess)(struct fc_port *, port_id_t, uint16_t, bool);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) struct fc_port *(*find_sess_by_loop_id)(struct scsi_qla_host *,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) const uint16_t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) struct fc_port *(*find_sess_by_s_id)(struct scsi_qla_host *,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) const be_id_t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) void (*clear_nacl_from_fcport_map)(struct fc_port *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) void (*put_sess)(struct fc_port *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) void (*shutdown_sess)(struct fc_port *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) int (*get_dif_tags)(struct qla_tgt_cmd *cmd, uint16_t *pfw_prot_opts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) int (*chk_dif_tags)(uint32_t tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) void (*add_target)(struct scsi_qla_host *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) void (*remove_target)(struct scsi_qla_host *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) int qla2x00_wait_for_hba_online(struct scsi_qla_host *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) #include <target/target_core_base.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) #define QLA_TGT_TIMEOUT 10 /* in seconds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) #define QLA_TGT_MAX_HW_PENDING_TIME 60 /* in seconds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) /* Immediate notify status constants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) #define IMM_NTFY_LIP_RESET 0x000E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) #define IMM_NTFY_LIP_LINK_REINIT 0x000F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) #define IMM_NTFY_IOCB_OVERFLOW 0x0016
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) #define IMM_NTFY_ABORT_TASK 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) #define IMM_NTFY_PORT_LOGOUT 0x0029
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) #define IMM_NTFY_PORT_CONFIG 0x002A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) #define IMM_NTFY_GLBL_TPRLO 0x002D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) #define IMM_NTFY_GLBL_LOGO 0x002E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) #define IMM_NTFY_RESOURCE 0x0034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) #define IMM_NTFY_MSG_RX 0x0036
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) #define IMM_NTFY_SRR 0x0045
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) #define IMM_NTFY_ELS 0x0046
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) /* Immediate notify task flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) #define IMM_NTFY_TASK_MGMT_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) #define QLA_TGT_CLEAR_ACA 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) #define QLA_TGT_TARGET_RESET 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) #define QLA_TGT_LUN_RESET 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) #define QLA_TGT_CLEAR_TS 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) #define QLA_TGT_ABORT_TS 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) #define QLA_TGT_ABORT_ALL_SESS 0xFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) #define QLA_TGT_ABORT_ALL 0xFFFE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) #define QLA_TGT_NEXUS_LOSS_SESS 0xFFFD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) #define QLA_TGT_NEXUS_LOSS 0xFFFC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) #define QLA_TGT_ABTS 0xFFFB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) #define QLA_TGT_2G_ABORT_TASK 0xFFFA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) /* Notify Acknowledge flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) #define NOTIFY_ACK_RES_COUNT BIT_8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) #define NOTIFY_ACK_CLEAR_LIP_RESET BIT_5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) #define NOTIFY_ACK_TM_RESP_CODE_VALID BIT_4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) /* Command's states */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) #define QLA_TGT_STATE_NEW 0 /* New command + target processing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) #define QLA_TGT_STATE_NEED_DATA 1 /* target needs data to continue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) #define QLA_TGT_STATE_DATA_IN 2 /* Data arrived + target processing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) #define QLA_TGT_STATE_PROCESSED 3 /* target done processing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) /* ATIO task_codes field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) #define ATIO_SIMPLE_QUEUE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) #define ATIO_HEAD_OF_QUEUE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) #define ATIO_ORDERED_QUEUE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) #define ATIO_ACA_QUEUE 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) #define ATIO_UNTAGGED 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) /* TM failed response codes, see FCP (9.4.11 FCP_RSP_INFO) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) #define FC_TM_SUCCESS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) #define FC_TM_BAD_FCP_DATA 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) #define FC_TM_BAD_CMD 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) #define FC_TM_FCP_DATA_MISMATCH 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) #define FC_TM_REJECT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) #define FC_TM_FAILED 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) #define QLA_TGT_SENSE_VALID(sense) ((sense != NULL) && \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) (((const uint8_t *)(sense))[0] & 0x70) == 0x70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) struct qla_port_24xx_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) uint8_t port_name[WWN_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) uint16_t loop_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) uint16_t reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) struct qla_qpair_hint {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) struct list_head hint_elem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) struct qla_qpair *qpair;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) u16 cpuid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) uint8_t cmd_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) struct qla_tgt {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) struct scsi_qla_host *vha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) struct qla_hw_data *ha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) struct btree_head64 lun_qpair_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) struct qla_qpair_hint *qphints;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) * To sync between IRQ handlers and qlt_target_release(). Needed,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) * because req_pkt() can drop/reaquire HW lock inside. Protected by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) * HW lock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) int atio_irq_cmd_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) int sg_tablesize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) /* Target's flags, serialized by pha->hardware_lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) unsigned int link_reinit_iocb_pending:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) * Protected by tgt_mutex AND hardware_lock for writing and tgt_mutex
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) * OR hardware_lock for reading.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) int tgt_stop; /* the target mode driver is being stopped */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) int tgt_stopped; /* the target mode driver has been stopped */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) /* Count of sessions refering qla_tgt. Protected by hardware_lock. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) int sess_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) /* Protected by hardware_lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) struct list_head del_sess_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) spinlock_t sess_work_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) struct list_head sess_works_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) struct work_struct sess_work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) struct imm_ntfy_from_isp link_reinit_iocb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) wait_queue_head_t waitQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) int notify_ack_expected;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) int abts_resp_expected;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) int modify_lun_expected;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) atomic_t tgt_global_resets_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) struct list_head tgt_list_entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) struct qla_tgt_sess_op {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) struct scsi_qla_host *vha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) uint32_t chip_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) struct atio_from_isp atio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) struct work_struct work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) struct list_head cmd_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) bool aborted;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) struct rsp_que *rsp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) enum trace_flags {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) TRC_NEW_CMD = BIT_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) TRC_DO_WORK = BIT_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) TRC_DO_WORK_ERR = BIT_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) TRC_XFR_RDY = BIT_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) TRC_XMIT_DATA = BIT_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) TRC_XMIT_STATUS = BIT_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) TRC_SRR_RSP = BIT_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) TRC_SRR_XRDY = BIT_7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) TRC_SRR_TERM = BIT_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) TRC_SRR_CTIO = BIT_9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) TRC_FLUSH = BIT_10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) TRC_CTIO_ERR = BIT_11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) TRC_CTIO_DONE = BIT_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) TRC_CTIO_ABORTED = BIT_13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) TRC_CTIO_STRANGE = BIT_14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) TRC_CMD_DONE = BIT_15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) TRC_CMD_CHK_STOP = BIT_16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) TRC_CMD_FREE = BIT_17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) TRC_DATA_IN = BIT_18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) TRC_ABORT = BIT_19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) TRC_DIF_ERR = BIT_20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) struct qla_tgt_cmd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) * Do not move cmd_type field. it needs to line up with srb->cmd_type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) uint8_t cmd_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) uint8_t pad[7];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) struct se_cmd se_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) struct fc_port *sess;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) struct qla_qpair *qpair;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) uint32_t reset_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) int state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) struct work_struct work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) /* Sense buffer that will be mapped into outgoing status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) unsigned char sense_buffer[TRANSPORT_SENSE_BUFFER];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) spinlock_t cmd_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) /* to save extra sess dereferences */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) unsigned int conf_compl_supported:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) unsigned int sg_mapped:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) unsigned int free_sg:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) unsigned int write_data_transferred:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) unsigned int q_full:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) unsigned int term_exchg:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) unsigned int cmd_sent_to_fw:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) unsigned int cmd_in_wq:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) * This variable may be set from outside the LIO and I/O completion
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) * callback functions. Do not declare this member variable as a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) * bitfield to avoid a read-modify-write operation when this variable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) * is set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) unsigned int aborted;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) struct scatterlist *sg; /* cmd data buffer SG vector */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) int sg_cnt; /* SG segments count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) int bufflen; /* cmd buffer length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) u64 unpacked_lun;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) enum dma_data_direction dma_data_direction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) uint16_t ctio_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) uint16_t vp_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) uint16_t loop_id; /* to save extra sess dereferences */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) struct qla_tgt *tgt; /* to save extra sess dereferences */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) struct scsi_qla_host *vha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) struct list_head cmd_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) struct atio_from_isp atio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) uint8_t ctx_dsd_alloced;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) /* T10-DIF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) #define DIF_ERR_NONE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) #define DIF_ERR_GRD 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) #define DIF_ERR_REF 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) #define DIF_ERR_APP 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) int8_t dif_err_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) struct scatterlist *prot_sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) uint32_t prot_sg_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) uint32_t blk_sz, num_blks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) uint8_t scsi_status, sense_key, asc, ascq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) struct crc_context *ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) const uint8_t *cdb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) uint64_t lba;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) uint16_t a_guard, e_guard, a_app_tag, e_app_tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) uint32_t a_ref_tag, e_ref_tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) #define DIF_BUNDL_DMA_VALID 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) uint16_t prot_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) uint64_t jiffies_at_alloc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) uint64_t jiffies_at_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) enum trace_flags trc_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) struct qla_tgt_sess_work_param {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) struct list_head sess_works_list_entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) #define QLA_TGT_SESS_WORK_ABORT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) #define QLA_TGT_SESS_WORK_TM 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) int type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) struct abts_recv_from_24xx abts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) struct imm_ntfy_from_isp tm_iocb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) struct atio_from_isp tm_iocb2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) struct qla_tgt_mgmt_cmd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) uint8_t cmd_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) uint8_t pad[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) uint16_t tmr_func;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) uint8_t fc_tm_rsp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) uint8_t abort_io_attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) struct fc_port *sess;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) struct qla_qpair *qpair;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) struct scsi_qla_host *vha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) struct se_cmd se_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) struct work_struct free_work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) unsigned int flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) #define QLA24XX_MGMT_SEND_NACK BIT_0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) #define QLA24XX_MGMT_ABORT_IO_ATTR_VALID BIT_1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) uint32_t reset_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) struct work_struct work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) uint64_t unpacked_lun;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) struct atio_from_isp atio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) struct imm_ntfy_from_isp imm_ntfy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) struct abts_recv_from_24xx abts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) } __packed orig_iocb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) struct qla_tgt_prm {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) struct qla_tgt_cmd *cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) struct qla_tgt *tgt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) void *pkt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) struct scatterlist *sg; /* cmd data buffer SG vector */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) unsigned char *sense_buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) int seg_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) int req_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) uint16_t rq_result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) int sense_buffer_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) int residual;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) int add_status_pkt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) /* dif */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) struct scatterlist *prot_sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) uint16_t prot_seg_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) uint16_t tot_dsds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) /* Check for Switch reserved address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) #define IS_SW_RESV_ADDR(_s_id) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) ((_s_id.b.domain == 0xff) && ((_s_id.b.area & 0xf0) == 0xf0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) #define QLA_TGT_XMIT_DATA 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) #define QLA_TGT_XMIT_STATUS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) #define QLA_TGT_XMIT_ALL (QLA_TGT_XMIT_STATUS|QLA_TGT_XMIT_DATA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) extern struct qla_tgt_data qla_target;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) * Function prototypes for qla_target.c logic used by qla2xxx LLD code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) extern int qlt_add_target(struct qla_hw_data *, struct scsi_qla_host *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) extern int qlt_remove_target(struct qla_hw_data *, struct scsi_qla_host *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) extern int qlt_lport_register(void *, u64, u64, u64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) int (*callback)(struct scsi_qla_host *, void *, u64, u64));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) extern void qlt_lport_deregister(struct scsi_qla_host *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) extern void qlt_unreg_sess(struct fc_port *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) extern void qlt_fc_port_added(struct scsi_qla_host *, fc_port_t *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) extern void qlt_fc_port_deleted(struct scsi_qla_host *, fc_port_t *, int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) extern int __init qlt_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) extern void qlt_exit(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) extern void qlt_update_vp_map(struct scsi_qla_host *, int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) extern void qlt_free_session_done(struct work_struct *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) * This macro is used during early initializations when host->active_mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) * is not set. Right now, ha value is ignored.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) #define QLA_TGT_MODE_ENABLED() (ql2x_ini_mode != QLA2XXX_INI_MODE_ENABLED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) extern int ql2x_ini_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) static inline bool qla_tgt_mode_enabled(struct scsi_qla_host *ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) return ha->host->active_mode == MODE_TARGET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) static inline bool qla_ini_mode_enabled(struct scsi_qla_host *ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) return ha->host->active_mode == MODE_INITIATOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) static inline bool qla_dual_mode_enabled(struct scsi_qla_host *ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) return (ha->host->active_mode == MODE_DUAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) static inline uint32_t sid_to_key(const be_id_t s_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) return s_id.domain << 16 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) s_id.area << 8 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) s_id.al_pa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) * Exported symbols from qla_target.c LLD logic used by qla2xxx code..
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) extern void qlt_response_pkt_all_vps(struct scsi_qla_host *, struct rsp_que *,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) response_t *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) extern int qlt_rdy_to_xfer(struct qla_tgt_cmd *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) extern int qlt_xmit_response(struct qla_tgt_cmd *, int, uint8_t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) extern int qlt_abort_cmd(struct qla_tgt_cmd *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) extern void qlt_xmit_tm_rsp(struct qla_tgt_mgmt_cmd *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) extern void qlt_free_mcmd(struct qla_tgt_mgmt_cmd *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) extern void qlt_free_cmd(struct qla_tgt_cmd *cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) extern void qlt_async_event(uint16_t, struct scsi_qla_host *, uint16_t *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) extern void qlt_enable_vha(struct scsi_qla_host *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) extern void qlt_vport_create(struct scsi_qla_host *, struct qla_hw_data *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) extern u8 qlt_rff_id(struct scsi_qla_host *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) extern void qlt_init_atio_q_entries(struct scsi_qla_host *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) extern void qlt_24xx_process_atio_queue(struct scsi_qla_host *, uint8_t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) extern void qlt_24xx_config_rings(struct scsi_qla_host *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) extern void qlt_24xx_config_nvram_stage1(struct scsi_qla_host *,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) struct nvram_24xx *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) extern void qlt_24xx_config_nvram_stage2(struct scsi_qla_host *,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) struct init_cb_24xx *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) extern void qlt_81xx_config_nvram_stage2(struct scsi_qla_host *,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) struct init_cb_81xx *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) extern void qlt_81xx_config_nvram_stage1(struct scsi_qla_host *,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) struct nvram_81xx *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) extern int qlt_24xx_process_response_error(struct scsi_qla_host *,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) struct sts_entry_24xx *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) extern void qlt_modify_vp_config(struct scsi_qla_host *,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) struct vp_config_entry_24xx *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) extern void qlt_probe_one_stage1(struct scsi_qla_host *, struct qla_hw_data *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) extern int qlt_mem_alloc(struct qla_hw_data *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) extern void qlt_mem_free(struct qla_hw_data *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) extern int qlt_stop_phase1(struct qla_tgt *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) extern void qlt_stop_phase2(struct qla_tgt *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) extern irqreturn_t qla83xx_msix_atio_q(int, void *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) extern void qlt_83xx_iospace_config(struct qla_hw_data *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) extern int qlt_free_qfull_cmds(struct qla_qpair *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) extern void qlt_logo_completion_handler(fc_port_t *, int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) extern void qlt_do_generation_tick(struct scsi_qla_host *, int *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) void qlt_send_resp_ctio(struct qla_qpair *, struct qla_tgt_cmd *, uint8_t,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) uint8_t, uint8_t, uint8_t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) #endif /* __QLA_TARGET_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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