^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * QLogic Fibre Channel HBA Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (c) 2003-2014 QLogic Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #ifndef __QLA_NX2_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define __QLA_NX2_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define QSNT_ACK_TOV 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define INTENT_TO_RECOVER 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define PROCEED_TO_RECOVER 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define IDC_LOCK_RECOVERY_OWNER_MASK 0x3C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define IDC_LOCK_RECOVERY_STATE_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define IDC_LOCK_RECOVERY_STATE_SHIFT_BITS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define QLA8044_DRV_LOCK_MSLEEP 200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define QLA8044_ADDR_DDR_NET (0x0000000000000000ULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define QLA8044_ADDR_DDR_NET_MAX (0x000000000fffffffULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define MD_MIU_TEST_AGT_WRDATA_LO 0x410000A0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define MD_MIU_TEST_AGT_WRDATA_HI 0x410000A4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define MD_MIU_TEST_AGT_WRDATA_ULO 0x410000B0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define MD_MIU_TEST_AGT_WRDATA_UHI 0x410000B4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* MIU_TEST_AGT_CTRL flags. work for SIU as well */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define MIU_TA_CTL_WRITE_ENABLE (MIU_TA_CTL_WRITE | MIU_TA_CTL_ENABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define MIU_TA_CTL_WRITE_START (MIU_TA_CTL_WRITE | MIU_TA_CTL_ENABLE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) MIU_TA_CTL_START)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define MIU_TA_CTL_START_ENABLE (MIU_TA_CTL_START | MIU_TA_CTL_ENABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* Imbus address bit used to indicate a host address. This bit is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * eliminated by the pcie bar and bar select before presentation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * over pcie. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /* host memory via IMBUS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define QLA8044_P2_ADDR_PCIE (0x0000000800000000ULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define QLA8044_P3_ADDR_PCIE (0x0000008000000000ULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define QLA8044_ADDR_PCIE_MAX (0x0000000FFFFFFFFFULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define QLA8044_ADDR_OCM0 (0x0000000200000000ULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define QLA8044_ADDR_OCM0_MAX (0x00000002000fffffULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define QLA8044_ADDR_OCM1 (0x0000000200400000ULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define QLA8044_ADDR_OCM1_MAX (0x00000002004fffffULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define QLA8044_ADDR_QDR_NET (0x0000000300000000ULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define QLA8044_P2_ADDR_QDR_NET_MAX (0x00000003001fffffULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define QLA8044_P3_ADDR_QDR_NET_MAX (0x0000000303ffffffULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define QLA8044_ADDR_QDR_NET_MAX (0x0000000307ffffffULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define QLA8044_PCI_CRBSPACE ((unsigned long)0x06000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define QLA8044_PCI_DIRECT_CRB ((unsigned long)0x04400000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define QLA8044_PCI_CAMQM ((unsigned long)0x04800000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define QLA8044_PCI_CAMQM_MAX ((unsigned long)0x04ffffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define QLA8044_PCI_DDR_NET ((unsigned long)0x00000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define QLA8044_PCI_QDR_NET ((unsigned long)0x04000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define QLA8044_PCI_QDR_NET_MAX ((unsigned long)0x043fffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /* PCI Windowing for DDR regions. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static inline bool addr_in_range(u64 addr, u64 low, u64 high)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) return addr <= high && addr >= low;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /* Indirectly Mapped Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define QLA8044_FLASH_SPI_STATUS 0x2808E010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define QLA8044_FLASH_SPI_CONTROL 0x2808E014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define QLA8044_FLASH_STATUS 0x42100004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define QLA8044_FLASH_CONTROL 0x42110004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define QLA8044_FLASH_ADDR 0x42110008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define QLA8044_FLASH_WRDATA 0x4211000C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define QLA8044_FLASH_RDDATA 0x42110018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define QLA8044_FLASH_DIRECT_WINDOW 0x42110030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define QLA8044_FLASH_DIRECT_DATA(DATA) (0x42150000 | (0x0000FFFF&DATA))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* Flash access regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define QLA8044_FLASH_LOCK 0x3850
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define QLA8044_FLASH_UNLOCK 0x3854
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define QLA8044_FLASH_LOCK_ID 0x3500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* Driver Lock regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define QLA8044_DRV_LOCK 0x3868
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define QLA8044_DRV_UNLOCK 0x386C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define QLA8044_DRV_LOCK_ID 0x3504
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define QLA8044_DRV_LOCKRECOVERY 0x379C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /* IDC version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define QLA8044_IDC_VER_MAJ_VALUE 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define QLA8044_IDC_VER_MIN_VALUE 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* IDC Registers : Driver Coexistence Defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define QLA8044_CRB_IDC_VER_MAJOR 0x3780
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define QLA8044_CRB_IDC_VER_MINOR 0x3798
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define QLA8044_IDC_DRV_AUDIT 0x3794
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define QLA8044_SRE_SHIM_CONTROL 0x0D200284
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define QLA8044_PORT0_RXB_PAUSE_THRS 0x0B2003A4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define QLA8044_PORT1_RXB_PAUSE_THRS 0x0B2013A4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define QLA8044_PORT0_RXB_TC_MAX_CELL 0x0B200388
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define QLA8044_PORT1_RXB_TC_MAX_CELL 0x0B201388
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define QLA8044_PORT0_RXB_TC_STATS 0x0B20039C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define QLA8044_PORT1_RXB_TC_STATS 0x0B20139C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define QLA8044_PORT2_IFB_PAUSE_THRS 0x0B200704
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define QLA8044_PORT3_IFB_PAUSE_THRS 0x0B201704
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /* set value to pause threshold value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define QLA8044_SET_PAUSE_VAL 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define QLA8044_SET_TC_MAX_CELL_VAL 0x03FF03FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define QLA8044_PEG_HALT_STATUS1 0x34A8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define QLA8044_PEG_HALT_STATUS2 0x34AC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define QLA8044_PEG_ALIVE_COUNTER 0x34B0 /* FW_HEARTBEAT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define QLA8044_FW_CAPABILITIES 0x3528
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define QLA8044_CRB_DRV_ACTIVE 0x3788 /* IDC_DRV_PRESENCE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define QLA8044_CRB_DEV_STATE 0x3784 /* IDC_DEV_STATE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define QLA8044_CRB_DRV_STATE 0x378C /* IDC_DRV_ACK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define QLA8044_CRB_DRV_SCRATCH 0x3548
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define QLA8044_CRB_DEV_PART_INFO1 0x37E0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define QLA8044_CRB_DEV_PART_INFO2 0x37E4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define QLA8044_FW_VER_MAJOR 0x3550
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define QLA8044_FW_VER_MINOR 0x3554
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define QLA8044_FW_VER_SUB 0x3558
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define QLA8044_NPAR_STATE 0x359C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define QLA8044_FW_IMAGE_VALID 0x35FC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define QLA8044_CMDPEG_STATE 0x3650
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define QLA8044_ASIC_TEMP 0x37B4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define QLA8044_FW_API 0x356C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define QLA8044_DRV_OP_MODE 0x3570
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define QLA8044_CRB_WIN_BASE 0x3800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define QLA8044_CRB_WIN_FUNC(f) (QLA8044_CRB_WIN_BASE+((f)*4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define QLA8044_SEM_LOCK_BASE 0x3840
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define QLA8044_SEM_UNLOCK_BASE 0x3844
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define QLA8044_SEM_LOCK_FUNC(f) (QLA8044_SEM_LOCK_BASE+((f)*8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define QLA8044_SEM_UNLOCK_FUNC(f) (QLA8044_SEM_UNLOCK_BASE+((f)*8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define QLA8044_LINK_STATE(f) (0x3698+((f) > 7 ? 4 : 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define QLA8044_LINK_SPEED(f) (0x36E0+(((f) >> 2) * 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define QLA8044_MAX_LINK_SPEED(f) (0x36F0+(((f) / 4) * 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define QLA8044_LINK_SPEED_FACTOR 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define QLA8044_FUN7_ACTIVE_INDEX 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /* FLASH API Defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define QLA8044_FLASH_MAX_WAIT_USEC 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define QLA8044_FLASH_LOCK_TIMEOUT 10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define QLA8044_FLASH_SECTOR_SIZE 65536
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define QLA8044_DRV_LOCK_TIMEOUT 2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define QLA8044_FLASH_SECTOR_ERASE_CMD 0xdeadbeef
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define QLA8044_FLASH_WRITE_CMD 0xdacdacda
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define QLA8044_FLASH_BUFFER_WRITE_CMD 0xcadcadca
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define QLA8044_FLASH_READ_RETRY_COUNT 2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define QLA8044_FLASH_STATUS_READY 0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define QLA8044_FLASH_BUFFER_WRITE_MIN 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define QLA8044_FLASH_BUFFER_WRITE_MAX 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define QLA8044_FLASH_STATUS_REG_POLL_DELAY 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define QLA8044_ERASE_MODE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define QLA8044_WRITE_MODE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define QLA8044_DWORD_WRITE_MODE 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define QLA8044_GLOBAL_RESET 0x38CC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define QLA8044_WILDCARD 0x38F0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define QLA8044_INFORMANT 0x38FC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define QLA8044_HOST_MBX_CTRL 0x3038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define QLA8044_FW_MBX_CTRL 0x303C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define QLA8044_BOOTLOADER_ADDR 0x355C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define QLA8044_BOOTLOADER_SIZE 0x3560
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define QLA8044_FW_IMAGE_ADDR 0x3564
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define QLA8044_MBX_INTR_ENABLE 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define QLA8044_MBX_INTR_MASK 0x1200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /* IDC Control Register bit defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define DONTRESET_BIT0 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define GRACEFUL_RESET_BIT1 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) /* ISP8044 PEG_HALT_STATUS1 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define QLA8044_HALT_STATUS_INFORMATIONAL (0x1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define QLA8044_HALT_STATUS_FW_RESET (0x2 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define QLA8044_HALT_STATUS_UNRECOVERABLE (0x4 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /* Firmware image definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define QLA8044_BOOTLOADER_FLASH_ADDR 0x10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define QLA8044_BOOT_FROM_FLASH 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define QLA8044_IDC_PARAM_ADDR 0x3e8020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /* FLASH related definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define QLA8044_OPTROM_BURST_SIZE 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define QLA8044_MAX_OPTROM_BURST_DWORDS (QLA8044_OPTROM_BURST_SIZE / 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define QLA8044_MIN_OPTROM_BURST_DWORDS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define QLA8044_SECTOR_SIZE (64 * 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define QLA8044_FLASH_SPI_CTL 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define QLA8044_FLASH_FIRST_TEMP_VAL 0x00800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define QLA8044_FLASH_SECOND_TEMP_VAL 0x00800001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define QLA8044_FLASH_FIRST_MS_PATTERN 0x43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define QLA8044_FLASH_SECOND_MS_PATTERN 0x7F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define QLA8044_FLASH_LAST_MS_PATTERN 0x7D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define QLA8044_FLASH_STATUS_WRITE_DEF_SIG 0xFD0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define QLA8044_FLASH_SECOND_ERASE_MS_VAL 0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define QLA8044_FLASH_ERASE_SIG 0xFD0300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define QLA8044_FLASH_LAST_ERASE_MS_VAL 0x3D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) /* Reset template definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define QLA8044_MAX_RESET_SEQ_ENTRIES 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define QLA8044_RESTART_TEMPLATE_SIZE 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define QLA8044_RESET_TEMPLATE_ADDR 0x4F0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define QLA8044_RESET_SEQ_VERSION 0x0101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /* Reset template entry opcodes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define OPCODE_NOP 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define OPCODE_WRITE_LIST 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define OPCODE_READ_WRITE_LIST 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define OPCODE_POLL_LIST 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define OPCODE_POLL_WRITE_LIST 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define OPCODE_READ_MODIFY_WRITE 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define OPCODE_SEQ_PAUSE 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define OPCODE_SEQ_END 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define OPCODE_TMPL_END 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define OPCODE_POLL_READ_LIST 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /* Template Header */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define RESET_TMPLT_HDR_SIGNATURE 0xCAFE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define QLA8044_IDC_DRV_CTRL 0x3790
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define AF_8044_NO_FW_DUMP 27 /* 0x08000000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define MINIDUMP_SIZE_36K 36864
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) struct qla8044_reset_template_hdr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) uint16_t version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) uint16_t signature;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) uint16_t size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) uint16_t entries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) uint16_t hdr_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) uint16_t checksum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) uint16_t init_seq_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) uint16_t start_seq_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) /* Common Entry Header. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) struct qla8044_reset_entry_hdr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) uint16_t cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) uint16_t size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) uint16_t count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) uint16_t delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /* Generic poll entry type. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) struct qla8044_poll {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) uint32_t test_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) uint32_t test_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) /* Read modify write entry type. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) struct qla8044_rmw {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) uint32_t test_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) uint32_t xor_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) uint32_t or_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) uint8_t shl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) uint8_t shr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) uint8_t index_a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) uint8_t rsvd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) /* Generic Entry Item with 2 DWords. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) struct qla8044_entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) uint32_t arg1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) uint32_t arg2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) /* Generic Entry Item with 4 DWords.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) struct qla8044_quad_entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) uint32_t dr_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) uint32_t dr_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) uint32_t ar_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) uint32_t ar_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) struct qla8044_reset_template {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) int seq_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) int seq_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) int array_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) uint32_t array[QLA8044_MAX_RESET_SEQ_ENTRIES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) uint8_t *buff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) uint8_t *stop_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) uint8_t *start_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) uint8_t *init_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) struct qla8044_reset_template_hdr *hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) uint8_t seq_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) uint8_t template_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) /* Driver_code is for driver to write some info about the entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) * currently not used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) struct qla8044_minidump_entry_hdr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) uint32_t entry_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) uint32_t entry_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) uint32_t entry_capture_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) uint8_t entry_capture_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) uint8_t entry_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) uint8_t driver_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) uint8_t driver_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) } d_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) /* Read CRB entry header */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) struct qla8044_minidump_entry_crb {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) struct qla8044_minidump_entry_hdr h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) uint32_t addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) uint8_t addr_stride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) uint8_t state_index_a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) uint16_t poll_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) } crb_strd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) uint32_t data_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) uint32_t op_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) uint8_t opcode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) uint8_t state_index_v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) uint8_t shl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) uint8_t shr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) } crb_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) uint32_t value_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) uint32_t value_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) uint32_t value_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) struct qla8044_minidump_entry_cache {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) struct qla8044_minidump_entry_hdr h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) uint32_t tag_reg_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) uint16_t tag_value_stride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) uint16_t init_tag_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) } addr_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) uint32_t data_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) uint32_t op_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) uint32_t control_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) uint16_t write_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) uint8_t poll_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) uint8_t poll_wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) } cache_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) uint32_t read_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) uint8_t read_addr_stride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) uint8_t read_addr_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) uint16_t rsvd_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) } read_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) /* Read OCM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) struct qla8044_minidump_entry_rdocm {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) struct qla8044_minidump_entry_hdr h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) uint32_t rsvd_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) uint32_t rsvd_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) uint32_t data_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) uint32_t op_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) uint32_t rsvd_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) uint32_t rsvd_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) uint32_t read_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) uint32_t read_addr_stride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) /* Read Memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) struct qla8044_minidump_entry_rdmem {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) struct qla8044_minidump_entry_hdr h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) uint32_t rsvd[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) uint32_t read_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) uint32_t read_data_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) /* Read Memory: For Pex-DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) struct qla8044_minidump_entry_rdmem_pex_dma {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) struct qla8044_minidump_entry_hdr h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) uint32_t desc_card_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) uint16_t dma_desc_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) uint8_t rsvd[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) uint32_t start_dma_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) uint8_t rsvd2[12];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) uint32_t read_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) uint32_t read_data_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) /* Read ROM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) struct qla8044_minidump_entry_rdrom {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) struct qla8044_minidump_entry_hdr h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) uint32_t rsvd[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) uint32_t read_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) uint32_t read_data_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) /* Mux entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) struct qla8044_minidump_entry_mux {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) struct qla8044_minidump_entry_hdr h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) uint32_t select_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) uint32_t rsvd_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) uint32_t data_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) uint32_t op_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) uint32_t select_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) uint32_t select_value_stride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) uint32_t read_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) uint32_t rsvd_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) /* Queue entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) struct qla8044_minidump_entry_queue {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) struct qla8044_minidump_entry_hdr h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) uint32_t select_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) uint16_t queue_id_stride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) uint16_t rsvd_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) } q_strd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) uint32_t data_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) uint32_t op_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) uint32_t rsvd_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) uint32_t rsvd_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) uint32_t read_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) uint8_t read_addr_stride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) uint8_t read_addr_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) uint16_t rsvd_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) } rd_strd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) /* POLLRD Entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) struct qla8044_minidump_entry_pollrd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) struct qla8044_minidump_entry_hdr h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) uint32_t select_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) uint32_t read_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) uint32_t select_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) uint16_t select_value_stride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) uint16_t op_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) uint32_t poll_wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) uint32_t poll_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) uint32_t data_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) uint32_t rsvd_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) struct qla8044_minidump_entry_rddfe {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) struct qla8044_minidump_entry_hdr h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) uint32_t addr_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) uint32_t value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) uint8_t stride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) uint8_t stride2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) uint16_t count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) uint32_t poll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) uint32_t mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) uint32_t modify_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) uint32_t data_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) uint32_t rsvd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) struct qla8044_minidump_entry_rdmdio {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) struct qla8044_minidump_entry_hdr h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) uint32_t addr_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) uint32_t addr_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) uint32_t value_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) uint8_t stride_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) uint8_t stride_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) uint16_t count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) uint32_t poll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) uint32_t mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) uint32_t value_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) uint32_t data_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) struct qla8044_minidump_entry_pollwr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) struct qla8044_minidump_entry_hdr h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) uint32_t addr_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) uint32_t addr_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) uint32_t value_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) uint32_t value_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) uint32_t poll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) uint32_t mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) uint32_t data_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) uint32_t rsvd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) /* RDMUX2 Entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) struct qla8044_minidump_entry_rdmux2 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) struct qla8044_minidump_entry_hdr h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) uint32_t select_addr_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) uint32_t select_addr_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) uint32_t select_value_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) uint32_t select_value_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) uint32_t op_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) uint32_t select_value_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) uint32_t read_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) uint8_t select_value_stride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) uint8_t data_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) uint8_t rsvd[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) /* POLLRDMWR Entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) struct qla8044_minidump_entry_pollrdmwr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) struct qla8044_minidump_entry_hdr h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) uint32_t addr_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) uint32_t addr_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) uint32_t value_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) uint32_t value_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) uint32_t poll_wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) uint32_t poll_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) uint32_t modify_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) uint32_t data_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) /* IDC additional information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) struct qla8044_idc_information {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) uint32_t request_desc; /* IDC request descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) uint32_t info1; /* IDC additional info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) uint32_t info2; /* IDC additional info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) uint32_t info3; /* IDC additional info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) enum qla_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) QLA8044_PEG_HALT_STATUS1_INDEX = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) QLA8044_PEG_HALT_STATUS2_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) QLA8044_PEG_ALIVE_COUNTER_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) QLA8044_CRB_DRV_ACTIVE_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) QLA8044_CRB_DEV_STATE_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) QLA8044_CRB_DRV_STATE_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) QLA8044_CRB_DRV_SCRATCH_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) QLA8044_CRB_DEV_PART_INFO_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) QLA8044_CRB_DRV_IDC_VERSION_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) QLA8044_FW_VERSION_MAJOR_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) QLA8044_FW_VERSION_MINOR_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) QLA8044_FW_VERSION_SUB_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) QLA8044_CRB_CMDPEG_STATE_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) QLA8044_CRB_TEMP_STATE_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) #define CRB_REG_INDEX_MAX 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) #define CRB_CMDPEG_CHECK_RETRY_COUNT 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) #define CRB_CMDPEG_CHECK_DELAY 500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) /* MiniDump Structures */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) /* Driver_code is for driver to write some info about the entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) * currently not used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) #define QLA8044_SS_OCM_WNDREG_INDEX 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) #define QLA8044_DBG_STATE_ARRAY_LEN 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) #define QLA8044_DBG_CAP_SIZE_ARRAY_LEN 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) #define QLA8044_DBG_RSVD_ARRAY_LEN 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) #define QLA8044_DBG_OCM_WNDREG_ARRAY_LEN 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) #define QLA8044_SS_PCI_INDEX 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) #define QLA8044_RDDFE 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) #define QLA8044_RDMDIO 39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) #define QLA8044_POLLWR 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) struct qla8044_minidump_template_hdr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) uint32_t entry_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) uint32_t first_entry_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) uint32_t size_of_template;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) uint32_t capture_debug_level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) uint32_t num_of_entries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) uint32_t version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) uint32_t driver_timestamp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) uint32_t checksum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) uint32_t driver_capture_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) uint32_t driver_info_word2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) uint32_t driver_info_word3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) uint32_t driver_info_word4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) uint32_t saved_state_array[QLA8044_DBG_STATE_ARRAY_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) uint32_t capture_size_array[QLA8044_DBG_CAP_SIZE_ARRAY_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) uint32_t ocm_window_reg[QLA8044_DBG_OCM_WNDREG_ARRAY_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) struct qla8044_pex_dma_descriptor {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) uint32_t read_data_size; /* 0-23: size, 24-31: rsvd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) uint8_t rsvd[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) uint16_t dma_desc_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) } cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) uint64_t src_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) uint64_t dma_bus_addr; /*0-3: desc-cmd, 4-7: pci-func, 8-15: desc-cmd*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) uint8_t rsvd[24];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags