^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * QLogic Fibre Channel HBA Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (c) 2003-2014 QLogic Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/vmalloc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include "qla_def.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include "qla_gbl.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define TIMEOUT_100_MS 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) static const uint32_t qla8044_reg_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) QLA8044_PEG_HALT_STATUS1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) QLA8044_PEG_HALT_STATUS2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) QLA8044_PEG_ALIVE_COUNTER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) QLA8044_CRB_DRV_ACTIVE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) QLA8044_CRB_DEV_STATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) QLA8044_CRB_DRV_STATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) QLA8044_CRB_DRV_SCRATCH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) QLA8044_CRB_DEV_PART_INFO1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) QLA8044_CRB_IDC_VER_MAJOR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) QLA8044_FW_VER_MAJOR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) QLA8044_FW_VER_MINOR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) QLA8044_FW_VER_SUB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) QLA8044_CMDPEG_STATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) QLA8044_ASIC_TEMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* 8044 Flash Read/Write functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) uint32_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) qla8044_rd_reg(struct qla_hw_data *ha, ulong addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) return readl((void __iomem *) (ha->nx_pcibase + addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) qla8044_wr_reg(struct qla_hw_data *ha, ulong addr, uint32_t val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) writel(val, (void __iomem *)((ha)->nx_pcibase + addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) qla8044_rd_direct(struct scsi_qla_host *vha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) const uint32_t crb_reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) if (crb_reg < CRB_REG_INDEX_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) return qla8044_rd_reg(ha, qla8044_reg_tbl[crb_reg]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) return QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) qla8044_wr_direct(struct scsi_qla_host *vha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) const uint32_t crb_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) const uint32_t value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) if (crb_reg < CRB_REG_INDEX_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) qla8044_wr_reg(ha, qla8044_reg_tbl[crb_reg], value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) qla8044_set_win_base(scsi_qla_host_t *vha, uint32_t addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) uint32_t val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) int ret_val = QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) qla8044_wr_reg(ha, QLA8044_CRB_WIN_FUNC(ha->portnum), addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) val = qla8044_rd_reg(ha, QLA8044_CRB_WIN_FUNC(ha->portnum));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) if (val != addr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) ql_log(ql_log_warn, vha, 0xb087,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) "%s: Failed to set register window : "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) "addr written 0x%x, read 0x%x!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) __func__, addr, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) ret_val = QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) return ret_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) qla8044_rd_reg_indirect(scsi_qla_host_t *vha, uint32_t addr, uint32_t *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) int ret_val = QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) ret_val = qla8044_set_win_base(vha, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) if (!ret_val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) *data = qla8044_rd_reg(ha, QLA8044_WILDCARD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) ql_log(ql_log_warn, vha, 0xb088,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) "%s: failed read of addr 0x%x!\n", __func__, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) return ret_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) qla8044_wr_reg_indirect(scsi_qla_host_t *vha, uint32_t addr, uint32_t data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) int ret_val = QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) ret_val = qla8044_set_win_base(vha, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) if (!ret_val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) qla8044_wr_reg(ha, QLA8044_WILDCARD, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) ql_log(ql_log_warn, vha, 0xb089,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) "%s: failed wrt to addr 0x%x, data 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) __func__, addr, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) return ret_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * qla8044_read_write_crb_reg - Read from raddr and write value to waddr.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * @ha : Pointer to adapter structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) * @raddr : CRB address to read from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * @waddr : CRB address to write to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) qla8044_read_write_crb_reg(struct scsi_qla_host *vha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) uint32_t raddr, uint32_t waddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) uint32_t value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) qla8044_rd_reg_indirect(vha, raddr, &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) qla8044_wr_reg_indirect(vha, waddr, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) qla8044_poll_wait_for_ready(struct scsi_qla_host *vha, uint32_t addr1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) uint32_t mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) unsigned long timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) uint32_t temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /* jiffies after 100ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) timeout = jiffies + msecs_to_jiffies(TIMEOUT_100_MS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) qla8044_rd_reg_indirect(vha, addr1, &temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) if ((temp & mask) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) if (time_after_eq(jiffies, timeout)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) ql_log(ql_log_warn, vha, 0xb151,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) "Error in processing rdmdio entry\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) } while (1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static uint32_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) qla8044_ipmdio_rd_reg(struct scsi_qla_host *vha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) uint32_t addr1, uint32_t addr3, uint32_t mask, uint32_t addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) uint32_t temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) ret = qla8044_poll_wait_for_ready(vha, addr1, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) if (ret == -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) temp = (0x40000000 | addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) qla8044_wr_reg_indirect(vha, addr1, temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) ret = qla8044_poll_wait_for_ready(vha, addr1, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) if (ret == -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) qla8044_rd_reg_indirect(vha, addr3, &ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) qla8044_poll_wait_ipmdio_bus_idle(struct scsi_qla_host *vha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) uint32_t addr1, uint32_t addr2, uint32_t addr3, uint32_t mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) unsigned long timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) uint32_t temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) /* jiffies after 100 msecs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) timeout = jiffies + msecs_to_jiffies(TIMEOUT_100_MS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) temp = qla8044_ipmdio_rd_reg(vha, addr1, addr3, mask, addr2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) if ((temp & 0x1) != 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) if (time_after_eq(jiffies, timeout)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) ql_log(ql_log_warn, vha, 0xb152,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) "Error in processing mdiobus idle\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) } while (1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) qla8044_ipmdio_wr_reg(struct scsi_qla_host *vha, uint32_t addr1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) uint32_t addr3, uint32_t mask, uint32_t addr, uint32_t value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) ret = qla8044_poll_wait_for_ready(vha, addr1, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) if (ret == -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) qla8044_wr_reg_indirect(vha, addr3, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) qla8044_wr_reg_indirect(vha, addr1, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) ret = qla8044_poll_wait_for_ready(vha, addr1, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) if (ret == -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) * qla8044_rmw_crb_reg - Read value from raddr, AND with test_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) * Shift Left,Right/OR/XOR with values RMW header and write value to waddr.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) * @vha : Pointer to adapter structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) * @raddr : CRB address to read from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) * @waddr : CRB address to write to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) * @p_rmw_hdr : header with shift/or/xor values.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) qla8044_rmw_crb_reg(struct scsi_qla_host *vha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) uint32_t raddr, uint32_t waddr, struct qla8044_rmw *p_rmw_hdr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) uint32_t value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) if (p_rmw_hdr->index_a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) value = vha->reset_tmplt.array[p_rmw_hdr->index_a];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) qla8044_rd_reg_indirect(vha, raddr, &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) value &= p_rmw_hdr->test_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) value <<= p_rmw_hdr->shl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) value >>= p_rmw_hdr->shr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) value |= p_rmw_hdr->or_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) value ^= p_rmw_hdr->xor_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) qla8044_wr_reg_indirect(vha, waddr, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) qla8044_set_qsnt_ready(struct scsi_qla_host *vha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) uint32_t qsnt_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) qsnt_state = qla8044_rd_direct(vha, QLA8044_CRB_DRV_STATE_INDEX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) qsnt_state |= (1 << ha->portnum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) qla8044_wr_direct(vha, QLA8044_CRB_DRV_STATE_INDEX, qsnt_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) ql_log(ql_log_info, vha, 0xb08e, "%s(%ld): qsnt_state: 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) __func__, vha->host_no, qsnt_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) qla8044_clear_qsnt_ready(struct scsi_qla_host *vha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) uint32_t qsnt_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) qsnt_state = qla8044_rd_direct(vha, QLA8044_CRB_DRV_STATE_INDEX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) qsnt_state &= ~(1 << ha->portnum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) qla8044_wr_direct(vha, QLA8044_CRB_DRV_STATE_INDEX, qsnt_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) ql_log(ql_log_info, vha, 0xb08f, "%s(%ld): qsnt_state: 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) __func__, vha->host_no, qsnt_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) * qla8044_lock_recovery - Recovers the idc_lock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) * @vha : Pointer to adapter structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) * Lock Recovery Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) * 5-2 Lock recovery owner: Function ID of driver doing lock recovery,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) * valid if bits 1..0 are set by driver doing lock recovery.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) * 1-0 1 - Driver intends to force unlock the IDC lock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) * 2 - Driver is moving forward to unlock the IDC lock. Driver clears
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) * this field after force unlocking the IDC lock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) * Lock Recovery process
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) * a. Read the IDC_LOCK_RECOVERY register. If the value in bits 1..0 is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) * greater than 0, then wait for the other driver to unlock otherwise
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) * move to the next step.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) * b. Indicate intent to force-unlock by writing 1h to the IDC_LOCK_RECOVERY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) * register bits 1..0 and also set the function# in bits 5..2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) * c. Read the IDC_LOCK_RECOVERY register again after a delay of 200ms.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) * Wait for the other driver to perform lock recovery if the function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) * number in bits 5..2 has changed, otherwise move to the next step.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) * d. Write a value of 2h to the IDC_LOCK_RECOVERY register bits 1..0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) * leaving your function# in bits 5..2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) * e. Force unlock using the DRIVER_UNLOCK register and immediately clear
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) * the IDC_LOCK_RECOVERY bits 5..0 by writing 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) **/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) qla8044_lock_recovery(struct scsi_qla_host *vha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) uint32_t lock = 0, lockid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) lockid = qla8044_rd_reg(ha, QLA8044_DRV_LOCKRECOVERY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) /* Check for other Recovery in progress, go wait */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) if ((lockid & IDC_LOCK_RECOVERY_STATE_MASK) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) return QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) /* Intent to Recover */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) qla8044_wr_reg(ha, QLA8044_DRV_LOCKRECOVERY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) (ha->portnum <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) IDC_LOCK_RECOVERY_STATE_SHIFT_BITS) | INTENT_TO_RECOVER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) msleep(200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) /* Check Intent to Recover is advertised */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) lockid = qla8044_rd_reg(ha, QLA8044_DRV_LOCKRECOVERY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) if ((lockid & IDC_LOCK_RECOVERY_OWNER_MASK) != (ha->portnum <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) IDC_LOCK_RECOVERY_STATE_SHIFT_BITS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) return QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) ql_dbg(ql_dbg_p3p, vha, 0xb08B, "%s:%d: IDC Lock recovery initiated\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) , __func__, ha->portnum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) /* Proceed to Recover */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) qla8044_wr_reg(ha, QLA8044_DRV_LOCKRECOVERY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) (ha->portnum << IDC_LOCK_RECOVERY_STATE_SHIFT_BITS) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) PROCEED_TO_RECOVER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) /* Force Unlock() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) qla8044_wr_reg(ha, QLA8044_DRV_LOCK_ID, 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) qla8044_rd_reg(ha, QLA8044_DRV_UNLOCK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) /* Clear bits 0-5 in IDC_RECOVERY register*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) qla8044_wr_reg(ha, QLA8044_DRV_LOCKRECOVERY, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) /* Get lock() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) lock = qla8044_rd_reg(ha, QLA8044_DRV_LOCK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) if (lock) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) lockid = qla8044_rd_reg(ha, QLA8044_DRV_LOCK_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) lockid = ((lockid + (1 << 8)) & ~0xFF) | ha->portnum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) qla8044_wr_reg(ha, QLA8044_DRV_LOCK_ID, lockid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) return QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) return QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) qla8044_idc_lock(struct qla_hw_data *ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) uint32_t ret_val = QLA_SUCCESS, timeout = 0, status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) uint32_t lock_id, lock_cnt, func_num, tmo_owner = 0, first_owner = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) while (status == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) /* acquire semaphore5 from PCI HW block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) status = qla8044_rd_reg(ha, QLA8044_DRV_LOCK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) if (status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) /* Increment Counter (8-31) and update func_num (0-7) on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) * getting a successful lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) lock_id = qla8044_rd_reg(ha, QLA8044_DRV_LOCK_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) lock_id = ((lock_id + (1 << 8)) & ~0xFF) | ha->portnum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) qla8044_wr_reg(ha, QLA8044_DRV_LOCK_ID, lock_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) if (timeout == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) first_owner = qla8044_rd_reg(ha, QLA8044_DRV_LOCK_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) if (++timeout >=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) (QLA8044_DRV_LOCK_TIMEOUT / QLA8044_DRV_LOCK_MSLEEP)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) tmo_owner = qla8044_rd_reg(ha, QLA8044_DRV_LOCK_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) func_num = tmo_owner & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) lock_cnt = tmo_owner >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) ql_log(ql_log_warn, vha, 0xb114,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) "%s: Lock by func %d failed after 2s, lock held "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) "by func %d, lock count %d, first_owner %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) __func__, ha->portnum, func_num, lock_cnt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) (first_owner & 0xFF));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) if (first_owner != tmo_owner) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) /* Some other driver got lock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) * OR same driver got lock again (counter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) * value changed), when we were waiting for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) * lock. Retry for another 2 sec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) ql_dbg(ql_dbg_p3p, vha, 0xb115,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) "%s: %d: IDC lock failed\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) __func__, ha->portnum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) timeout = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) /* Same driver holding lock > 2sec.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) * Force Recovery */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) if (qla8044_lock_recovery(vha) == QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) /* Recovered and got lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) ret_val = QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) ql_dbg(ql_dbg_p3p, vha, 0xb116,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) "%s:IDC lock Recovery by %d"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) "successful...\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) ha->portnum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) /* Recovery Failed, some other function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) * has the lock, wait for 2secs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) * and retry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) ql_dbg(ql_dbg_p3p, vha, 0xb08a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) "%s: IDC lock Recovery by %d "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) "failed, Retrying timeout\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) ha->portnum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) timeout = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) msleep(QLA8044_DRV_LOCK_MSLEEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) return ret_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) qla8044_idc_unlock(struct qla_hw_data *ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) int id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) id = qla8044_rd_reg(ha, QLA8044_DRV_LOCK_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) if ((id & 0xFF) != ha->portnum) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) ql_log(ql_log_warn, vha, 0xb118,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) "%s: IDC Unlock by %d failed, lock owner is %d!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) __func__, ha->portnum, (id & 0xFF));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) /* Keep lock counter value, update the ha->func_num to 0xFF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) qla8044_wr_reg(ha, QLA8044_DRV_LOCK_ID, (id | 0xFF));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) qla8044_rd_reg(ha, QLA8044_DRV_UNLOCK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) /* 8044 Flash Lock/Unlock functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) qla8044_flash_lock(scsi_qla_host_t *vha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) int lock_owner;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) int timeout = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) uint32_t lock_status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) int ret_val = QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) while (lock_status == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) lock_status = qla8044_rd_reg(ha, QLA8044_FLASH_LOCK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) if (lock_status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) if (++timeout >= QLA8044_FLASH_LOCK_TIMEOUT / 20) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) lock_owner = qla8044_rd_reg(ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) QLA8044_FLASH_LOCK_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) ql_log(ql_log_warn, vha, 0xb113,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) "%s: Simultaneous flash access by following ports, active port = %d: accessing port = %d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) __func__, ha->portnum, lock_owner);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) ret_val = QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) msleep(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) qla8044_wr_reg(ha, QLA8044_FLASH_LOCK_ID, ha->portnum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) return ret_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) qla8044_flash_unlock(scsi_qla_host_t *vha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) /* Reading FLASH_UNLOCK register unlocks the Flash */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) qla8044_wr_reg(ha, QLA8044_FLASH_LOCK_ID, 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) qla8044_rd_reg(ha, QLA8044_FLASH_UNLOCK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) static
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) void qla8044_flash_lock_recovery(struct scsi_qla_host *vha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) if (qla8044_flash_lock(vha)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) /* Someone else is holding the lock. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) ql_log(ql_log_warn, vha, 0xb120, "Resetting flash_lock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) * Either we got the lock, or someone
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) * else died while holding it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) * In either case, unlock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) qla8044_flash_unlock(vha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) * Address and length are byte address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) qla8044_read_flash_data(scsi_qla_host_t *vha, uint8_t *p_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) uint32_t flash_addr, int u32_word_count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) int i, ret_val = QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) uint32_t u32_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) if (qla8044_flash_lock(vha) != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) ret_val = QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) goto exit_lock_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) if (flash_addr & 0x03) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) ql_log(ql_log_warn, vha, 0xb117,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) "%s: Illegal addr = 0x%x\n", __func__, flash_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) ret_val = QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) goto exit_flash_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) for (i = 0; i < u32_word_count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) if (qla8044_wr_reg_indirect(vha, QLA8044_FLASH_DIRECT_WINDOW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) (flash_addr & 0xFFFF0000))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) ql_log(ql_log_warn, vha, 0xb119,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) "%s: failed to write addr 0x%x to "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) "FLASH_DIRECT_WINDOW\n! ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) __func__, flash_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) ret_val = QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) goto exit_flash_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) ret_val = qla8044_rd_reg_indirect(vha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) QLA8044_FLASH_DIRECT_DATA(flash_addr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) &u32_word);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) if (ret_val != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) ql_log(ql_log_warn, vha, 0xb08c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) "%s: failed to read addr 0x%x!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) __func__, flash_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) goto exit_flash_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) *(uint32_t *)p_data = u32_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) p_data = p_data + 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) flash_addr = flash_addr + 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) exit_flash_read:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) qla8044_flash_unlock(vha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) exit_lock_error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) return ret_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) * Address and length are byte address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) void *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) qla8044_read_optrom_data(struct scsi_qla_host *vha, void *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) uint32_t offset, uint32_t length)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) scsi_block_requests(vha->host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) if (qla8044_read_flash_data(vha, buf, offset, length / 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) ql_log(ql_log_warn, vha, 0xb08d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) "%s: Failed to read from flash\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) scsi_unblock_requests(vha->host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) return buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) static inline int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) qla8044_need_reset(struct scsi_qla_host *vha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) uint32_t drv_state, drv_active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) int rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) drv_active = qla8044_rd_direct(vha, QLA8044_CRB_DRV_ACTIVE_INDEX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) drv_state = qla8044_rd_direct(vha, QLA8044_CRB_DRV_STATE_INDEX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) rval = drv_state & (1 << ha->portnum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) if (ha->flags.eeh_busy && drv_active)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) rval = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) * qla8044_write_list - Write the value (p_entry->arg2) to address specified
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) * by p_entry->arg1 for all entries in header with delay of p_hdr->delay between
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) * entries.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) * @vha : Pointer to adapter structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) * @p_hdr : reset_entry header for WRITE_LIST opcode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) qla8044_write_list(struct scsi_qla_host *vha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) struct qla8044_reset_entry_hdr *p_hdr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) struct qla8044_entry *p_entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) uint32_t i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) p_entry = (struct qla8044_entry *)((char *)p_hdr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) sizeof(struct qla8044_reset_entry_hdr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) for (i = 0; i < p_hdr->count; i++, p_entry++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) qla8044_wr_reg_indirect(vha, p_entry->arg1, p_entry->arg2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) if (p_hdr->delay)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) udelay((uint32_t)(p_hdr->delay));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) * qla8044_read_write_list - Read from address specified by p_entry->arg1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) * write value read to address specified by p_entry->arg2, for all entries in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) * header with delay of p_hdr->delay between entries.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) * @vha : Pointer to adapter structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) * @p_hdr : reset_entry header for READ_WRITE_LIST opcode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) qla8044_read_write_list(struct scsi_qla_host *vha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) struct qla8044_reset_entry_hdr *p_hdr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) struct qla8044_entry *p_entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) uint32_t i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) p_entry = (struct qla8044_entry *)((char *)p_hdr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) sizeof(struct qla8044_reset_entry_hdr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) for (i = 0; i < p_hdr->count; i++, p_entry++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) qla8044_read_write_crb_reg(vha, p_entry->arg1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) p_entry->arg2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) if (p_hdr->delay)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) udelay((uint32_t)(p_hdr->delay));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) * qla8044_poll_reg - Poll the given CRB addr for duration msecs till
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) * value read ANDed with test_mask is equal to test_result.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) * @ha : Pointer to adapter structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) * @addr : CRB register address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) * @duration : Poll for total of "duration" msecs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) * @test_mask : Mask value read with "test_mask"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) * @test_result : Compare (value&test_mask) with test_result.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) * Return Value - QLA_SUCCESS/QLA_FUNCTION_FAILED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) qla8044_poll_reg(struct scsi_qla_host *vha, uint32_t addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) int duration, uint32_t test_mask, uint32_t test_result)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) uint32_t value = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) int timeout_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) uint8_t retries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) int ret_val = QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) ret_val = qla8044_rd_reg_indirect(vha, addr, &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) if (ret_val == QLA_FUNCTION_FAILED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) timeout_error = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) goto exit_poll_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) /* poll every 1/10 of the total duration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) retries = duration/10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) if ((value & test_mask) != test_result) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) timeout_error = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) msleep(duration/10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) ret_val = qla8044_rd_reg_indirect(vha, addr, &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) if (ret_val == QLA_FUNCTION_FAILED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) timeout_error = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) goto exit_poll_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) timeout_error = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) } while (retries--);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) exit_poll_reg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) if (timeout_error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) vha->reset_tmplt.seq_error++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) ql_log(ql_log_fatal, vha, 0xb090,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) "%s: Poll Failed: 0x%08x 0x%08x 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) __func__, value, test_mask, test_result);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) return timeout_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) * qla8044_poll_list - For all entries in the POLL_LIST header, poll read CRB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) * register specified by p_entry->arg1 and compare (value AND test_mask) with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) * test_result to validate it. Wait for p_hdr->delay between processing entries.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) * @ha : Pointer to adapter structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) * @p_hdr : reset_entry header for POLL_LIST opcode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) qla8044_poll_list(struct scsi_qla_host *vha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) struct qla8044_reset_entry_hdr *p_hdr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) long delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) struct qla8044_entry *p_entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) struct qla8044_poll *p_poll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) uint32_t i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) uint32_t value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) p_poll = (struct qla8044_poll *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) ((char *)p_hdr + sizeof(struct qla8044_reset_entry_hdr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) /* Entries start after 8 byte qla8044_poll, poll header contains
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) * the test_mask, test_value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) p_entry = (struct qla8044_entry *)((char *)p_poll +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) sizeof(struct qla8044_poll));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) delay = (long)p_hdr->delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) if (!delay) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) for (i = 0; i < p_hdr->count; i++, p_entry++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) qla8044_poll_reg(vha, p_entry->arg1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) delay, p_poll->test_mask, p_poll->test_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) for (i = 0; i < p_hdr->count; i++, p_entry++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) if (delay) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) if (qla8044_poll_reg(vha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) p_entry->arg1, delay,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) p_poll->test_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) p_poll->test_value)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) /*If
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) * (data_read&test_mask != test_value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) * read TIMEOUT_ADDR (arg1) and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) * ADDR (arg2) registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) qla8044_rd_reg_indirect(vha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) p_entry->arg1, &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) qla8044_rd_reg_indirect(vha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) p_entry->arg2, &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) * qla8044_poll_write_list - Write dr_value, ar_value to dr_addr/ar_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) * read ar_addr, if (value& test_mask != test_mask) re-read till timeout
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) * expires.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) * @vha : Pointer to adapter structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) * @p_hdr : reset entry header for POLL_WRITE_LIST opcode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) qla8044_poll_write_list(struct scsi_qla_host *vha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) struct qla8044_reset_entry_hdr *p_hdr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) long delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) struct qla8044_quad_entry *p_entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) struct qla8044_poll *p_poll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) uint32_t i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) p_poll = (struct qla8044_poll *)((char *)p_hdr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) sizeof(struct qla8044_reset_entry_hdr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) p_entry = (struct qla8044_quad_entry *)((char *)p_poll +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) sizeof(struct qla8044_poll));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) delay = (long)p_hdr->delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) for (i = 0; i < p_hdr->count; i++, p_entry++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) qla8044_wr_reg_indirect(vha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) p_entry->dr_addr, p_entry->dr_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) qla8044_wr_reg_indirect(vha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) p_entry->ar_addr, p_entry->ar_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) if (delay) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) if (qla8044_poll_reg(vha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) p_entry->ar_addr, delay,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) p_poll->test_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) p_poll->test_value)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) ql_dbg(ql_dbg_p3p, vha, 0xb091,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) "%s: Timeout Error: poll list, ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) ql_dbg(ql_dbg_p3p, vha, 0xb092,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) "item_num %d, entry_num %d\n", i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) vha->reset_tmplt.seq_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) * qla8044_read_modify_write - Read value from p_entry->arg1, modify the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) * value, write value to p_entry->arg2. Process entries with p_hdr->delay
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) * between entries.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) * @vha : Pointer to adapter structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) * @p_hdr : header with shift/or/xor values.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) qla8044_read_modify_write(struct scsi_qla_host *vha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) struct qla8044_reset_entry_hdr *p_hdr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) struct qla8044_entry *p_entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) struct qla8044_rmw *p_rmw_hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) uint32_t i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) p_rmw_hdr = (struct qla8044_rmw *)((char *)p_hdr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) sizeof(struct qla8044_reset_entry_hdr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) p_entry = (struct qla8044_entry *)((char *)p_rmw_hdr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) sizeof(struct qla8044_rmw));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) for (i = 0; i < p_hdr->count; i++, p_entry++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) qla8044_rmw_crb_reg(vha, p_entry->arg1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) p_entry->arg2, p_rmw_hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) if (p_hdr->delay)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) udelay((uint32_t)(p_hdr->delay));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) * qla8044_pause - Wait for p_hdr->delay msecs, called between processing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) * two entries of a sequence.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) * @vha : Pointer to adapter structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) * @p_hdr : Common reset entry header.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) static
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) void qla8044_pause(struct scsi_qla_host *vha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) struct qla8044_reset_entry_hdr *p_hdr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) if (p_hdr->delay)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) mdelay((uint32_t)((long)p_hdr->delay));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) * qla8044_template_end - Indicates end of reset sequence processing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) * @vha : Pointer to adapter structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) * @p_hdr : Common reset entry header.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) qla8044_template_end(struct scsi_qla_host *vha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) struct qla8044_reset_entry_hdr *p_hdr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) vha->reset_tmplt.template_end = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) if (vha->reset_tmplt.seq_error == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) ql_dbg(ql_dbg_p3p, vha, 0xb093,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) "%s: Reset sequence completed SUCCESSFULLY.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) ql_log(ql_log_fatal, vha, 0xb094,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) "%s: Reset sequence completed with some timeout "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) "errors.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) * qla8044_poll_read_list - Write ar_value to ar_addr register, read ar_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) * if (value & test_mask != test_value) re-read till timeout value expires,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) * read dr_addr register and assign to reset_tmplt.array.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) * @vha : Pointer to adapter structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) * @p_hdr : Common reset entry header.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) qla8044_poll_read_list(struct scsi_qla_host *vha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) struct qla8044_reset_entry_hdr *p_hdr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) long delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) int index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) struct qla8044_quad_entry *p_entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) struct qla8044_poll *p_poll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) uint32_t i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) uint32_t value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) p_poll = (struct qla8044_poll *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) ((char *)p_hdr + sizeof(struct qla8044_reset_entry_hdr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) p_entry = (struct qla8044_quad_entry *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) ((char *)p_poll + sizeof(struct qla8044_poll));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) delay = (long)p_hdr->delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) for (i = 0; i < p_hdr->count; i++, p_entry++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) qla8044_wr_reg_indirect(vha, p_entry->ar_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) p_entry->ar_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) if (delay) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) if (qla8044_poll_reg(vha, p_entry->ar_addr, delay,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) p_poll->test_mask, p_poll->test_value)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) ql_dbg(ql_dbg_p3p, vha, 0xb095,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) "%s: Timeout Error: poll "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) "list, ", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) ql_dbg(ql_dbg_p3p, vha, 0xb096,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) "Item_num %d, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) "entry_num %d\n", i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) vha->reset_tmplt.seq_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) index = vha->reset_tmplt.array_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) qla8044_rd_reg_indirect(vha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) p_entry->dr_addr, &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) vha->reset_tmplt.array[index++] = value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) if (index == QLA8044_MAX_RESET_SEQ_ENTRIES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) vha->reset_tmplt.array_index = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) * qla8031_process_reset_template - Process all entries in reset template
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) * till entry with SEQ_END opcode, which indicates end of the reset template
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) * processing. Each entry has a Reset Entry header, entry opcode/command, with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) * size of the entry, number of entries in sub-sequence and delay in microsecs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) * or timeout in millisecs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) * @ha : Pointer to adapter structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) * @p_buff : Common reset entry header.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) qla8044_process_reset_template(struct scsi_qla_host *vha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) char *p_buff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) int index, entries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) struct qla8044_reset_entry_hdr *p_hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) char *p_entry = p_buff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) vha->reset_tmplt.seq_end = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) vha->reset_tmplt.template_end = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) entries = vha->reset_tmplt.hdr->entries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) index = vha->reset_tmplt.seq_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) for (; (!vha->reset_tmplt.seq_end) && (index < entries); index++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) p_hdr = (struct qla8044_reset_entry_hdr *)p_entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) switch (p_hdr->cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) case OPCODE_NOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) case OPCODE_WRITE_LIST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) qla8044_write_list(vha, p_hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) case OPCODE_READ_WRITE_LIST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) qla8044_read_write_list(vha, p_hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) case OPCODE_POLL_LIST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) qla8044_poll_list(vha, p_hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) case OPCODE_POLL_WRITE_LIST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) qla8044_poll_write_list(vha, p_hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) case OPCODE_READ_MODIFY_WRITE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) qla8044_read_modify_write(vha, p_hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) case OPCODE_SEQ_PAUSE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) qla8044_pause(vha, p_hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) case OPCODE_SEQ_END:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) vha->reset_tmplt.seq_end = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) case OPCODE_TMPL_END:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) qla8044_template_end(vha, p_hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) case OPCODE_POLL_READ_LIST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) qla8044_poll_read_list(vha, p_hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) ql_log(ql_log_fatal, vha, 0xb097,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) "%s: Unknown command ==> 0x%04x on "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) "entry = %d\n", __func__, p_hdr->cmd, index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) *Set pointer to next entry in the sequence.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) p_entry += p_hdr->size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) vha->reset_tmplt.seq_index = index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) qla8044_process_init_seq(struct scsi_qla_host *vha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) qla8044_process_reset_template(vha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) vha->reset_tmplt.init_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) if (vha->reset_tmplt.seq_end != 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) ql_log(ql_log_fatal, vha, 0xb098,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) "%s: Abrupt INIT Sub-Sequence end.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) qla8044_process_stop_seq(struct scsi_qla_host *vha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) vha->reset_tmplt.seq_index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) qla8044_process_reset_template(vha, vha->reset_tmplt.stop_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) if (vha->reset_tmplt.seq_end != 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) ql_log(ql_log_fatal, vha, 0xb099,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) "%s: Abrupt STOP Sub-Sequence end.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) qla8044_process_start_seq(struct scsi_qla_host *vha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) qla8044_process_reset_template(vha, vha->reset_tmplt.start_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) if (vha->reset_tmplt.template_end != 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) ql_log(ql_log_fatal, vha, 0xb09a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) "%s: Abrupt START Sub-Sequence end.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) qla8044_lockless_flash_read_u32(struct scsi_qla_host *vha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) uint32_t flash_addr, uint8_t *p_data, int u32_word_count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) uint32_t i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) uint32_t u32_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) uint32_t flash_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) uint32_t addr = flash_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) int ret_val = QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) flash_offset = addr & (QLA8044_FLASH_SECTOR_SIZE - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) if (addr & 0x3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) ql_log(ql_log_fatal, vha, 0xb09b, "%s: Illegal addr = 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) __func__, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) ret_val = QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) goto exit_lockless_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) ret_val = qla8044_wr_reg_indirect(vha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) QLA8044_FLASH_DIRECT_WINDOW, (addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) if (ret_val != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) ql_log(ql_log_fatal, vha, 0xb09c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) "%s: failed to write addr 0x%x to FLASH_DIRECT_WINDOW!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) __func__, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) goto exit_lockless_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) /* Check if data is spread across multiple sectors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) if ((flash_offset + (u32_word_count * sizeof(uint32_t))) >
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) (QLA8044_FLASH_SECTOR_SIZE - 1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) /* Multi sector read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) for (i = 0; i < u32_word_count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) ret_val = qla8044_rd_reg_indirect(vha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) QLA8044_FLASH_DIRECT_DATA(addr), &u32_word);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) if (ret_val != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) ql_log(ql_log_fatal, vha, 0xb09d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) "%s: failed to read addr 0x%x!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) __func__, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) goto exit_lockless_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) *(uint32_t *)p_data = u32_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) p_data = p_data + 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) addr = addr + 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) flash_offset = flash_offset + 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) if (flash_offset > (QLA8044_FLASH_SECTOR_SIZE - 1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) /* This write is needed once for each sector */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) ret_val = qla8044_wr_reg_indirect(vha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) QLA8044_FLASH_DIRECT_WINDOW, (addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) if (ret_val != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) ql_log(ql_log_fatal, vha, 0xb09f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) "%s: failed to write addr "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) "0x%x to FLASH_DIRECT_WINDOW!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) __func__, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) goto exit_lockless_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) flash_offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) /* Single sector read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) for (i = 0; i < u32_word_count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) ret_val = qla8044_rd_reg_indirect(vha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) QLA8044_FLASH_DIRECT_DATA(addr), &u32_word);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) if (ret_val != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) ql_log(ql_log_fatal, vha, 0xb0a0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) "%s: failed to read addr 0x%x!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) __func__, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) goto exit_lockless_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) *(uint32_t *)p_data = u32_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) p_data = p_data + 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) addr = addr + 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) exit_lockless_read:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) return ret_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) * qla8044_ms_mem_write_128b - Writes data to MS/off-chip memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) * @vha : Pointer to adapter structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) * addr : Flash address to write to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) * data : Data to be written
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) * count : word_count to be written
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) * Return Value - QLA_SUCCESS/QLA_FUNCTION_FAILED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) qla8044_ms_mem_write_128b(struct scsi_qla_host *vha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) uint64_t addr, uint32_t *data, uint32_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) int i, j, ret_val = QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) uint32_t agt_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) /* Only 128-bit aligned access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) if (addr & 0xF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) ret_val = QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) goto exit_ms_mem_write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) write_lock_irqsave(&ha->hw_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) /* Write address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) ret_val = qla8044_wr_reg_indirect(vha, MD_MIU_TEST_AGT_ADDR_HI, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) if (ret_val == QLA_FUNCTION_FAILED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) ql_log(ql_log_fatal, vha, 0xb0a1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) "%s: write to AGT_ADDR_HI failed!\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) goto exit_ms_mem_write_unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) for (i = 0; i < count; i++, addr += 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) if (!((addr_in_range(addr, QLA8044_ADDR_QDR_NET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) QLA8044_ADDR_QDR_NET_MAX)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) (addr_in_range(addr, QLA8044_ADDR_DDR_NET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) QLA8044_ADDR_DDR_NET_MAX)))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) ret_val = QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) goto exit_ms_mem_write_unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) ret_val = qla8044_wr_reg_indirect(vha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) MD_MIU_TEST_AGT_ADDR_LO, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) /* Write data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) ret_val += qla8044_wr_reg_indirect(vha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) MD_MIU_TEST_AGT_WRDATA_LO, *data++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) ret_val += qla8044_wr_reg_indirect(vha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) MD_MIU_TEST_AGT_WRDATA_HI, *data++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) ret_val += qla8044_wr_reg_indirect(vha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) MD_MIU_TEST_AGT_WRDATA_ULO, *data++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) ret_val += qla8044_wr_reg_indirect(vha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) MD_MIU_TEST_AGT_WRDATA_UHI, *data++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) if (ret_val == QLA_FUNCTION_FAILED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) ql_log(ql_log_fatal, vha, 0xb0a2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) "%s: write to AGT_WRDATA failed!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) goto exit_ms_mem_write_unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) /* Check write status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) ret_val = qla8044_wr_reg_indirect(vha, MD_MIU_TEST_AGT_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) MIU_TA_CTL_WRITE_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) ret_val += qla8044_wr_reg_indirect(vha, MD_MIU_TEST_AGT_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) MIU_TA_CTL_WRITE_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) if (ret_val == QLA_FUNCTION_FAILED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) ql_log(ql_log_fatal, vha, 0xb0a3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) "%s: write to AGT_CTRL failed!\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) goto exit_ms_mem_write_unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) for (j = 0; j < MAX_CTL_CHECK; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) ret_val = qla8044_rd_reg_indirect(vha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) MD_MIU_TEST_AGT_CTRL, &agt_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) if (ret_val == QLA_FUNCTION_FAILED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) ql_log(ql_log_fatal, vha, 0xb0a4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) "%s: failed to read "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) "MD_MIU_TEST_AGT_CTRL!\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) goto exit_ms_mem_write_unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) if ((agt_ctrl & MIU_TA_CTL_BUSY) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) /* Status check failed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) if (j >= MAX_CTL_CHECK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) ql_log(ql_log_fatal, vha, 0xb0a5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) "%s: MS memory write failed!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) ret_val = QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) goto exit_ms_mem_write_unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) exit_ms_mem_write_unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) write_unlock_irqrestore(&ha->hw_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) exit_ms_mem_write:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) return ret_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) qla8044_copy_bootloader(struct scsi_qla_host *vha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) uint8_t *p_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) uint32_t src, count, size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) uint64_t dest;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) int ret_val = QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) src = QLA8044_BOOTLOADER_FLASH_ADDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) dest = qla8044_rd_reg(ha, QLA8044_BOOTLOADER_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) size = qla8044_rd_reg(ha, QLA8044_BOOTLOADER_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) /* 128 bit alignment check */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) if (size & 0xF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) size = (size + 16) & ~0xF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) /* 16 byte count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) count = size/16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) p_cache = vmalloc(size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) if (p_cache == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) ql_log(ql_log_fatal, vha, 0xb0a6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) "%s: Failed to allocate memory for "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) "boot loader cache\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) ret_val = QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) goto exit_copy_bootloader;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) ret_val = qla8044_lockless_flash_read_u32(vha, src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) p_cache, size/sizeof(uint32_t));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) if (ret_val == QLA_FUNCTION_FAILED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) ql_log(ql_log_fatal, vha, 0xb0a7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) "%s: Error reading F/W from flash!!!\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) goto exit_copy_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) ql_dbg(ql_dbg_p3p, vha, 0xb0a8, "%s: Read F/W from flash!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) /* 128 bit/16 byte write to MS memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) ret_val = qla8044_ms_mem_write_128b(vha, dest,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) (uint32_t *)p_cache, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) if (ret_val == QLA_FUNCTION_FAILED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) ql_log(ql_log_fatal, vha, 0xb0a9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) "%s: Error writing F/W to MS !!!\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) goto exit_copy_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) ql_dbg(ql_dbg_p3p, vha, 0xb0aa,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) "%s: Wrote F/W (size %d) to MS !!!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) __func__, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) exit_copy_error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) vfree(p_cache);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) exit_copy_bootloader:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) return ret_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) qla8044_restart(struct scsi_qla_host *vha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) int ret_val = QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) qla8044_process_stop_seq(vha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) /* Collect minidump */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) if (ql2xmdenable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) qla8044_get_minidump(vha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) ql_log(ql_log_fatal, vha, 0xb14c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) "Minidump disabled.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) qla8044_process_init_seq(vha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) if (qla8044_copy_bootloader(vha)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) ql_log(ql_log_fatal, vha, 0xb0ab,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) "%s: Copy bootloader, firmware restart failed!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) ret_val = QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) goto exit_restart;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) * Loads F/W from flash
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) qla8044_wr_reg(ha, QLA8044_FW_IMAGE_VALID, QLA8044_BOOT_FROM_FLASH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) qla8044_process_start_seq(vha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) exit_restart:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) return ret_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) * qla8044_check_cmd_peg_status - Check peg status to see if Peg is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) * initialized.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) * @ha : Pointer to adapter structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) * Return Value - QLA_SUCCESS/QLA_FUNCTION_FAILED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) qla8044_check_cmd_peg_status(struct scsi_qla_host *vha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) uint32_t val, ret_val = QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) int retries = CRB_CMDPEG_CHECK_RETRY_COUNT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) val = qla8044_rd_reg(ha, QLA8044_CMDPEG_STATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) if (val == PHAN_INITIALIZE_COMPLETE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) ql_dbg(ql_dbg_p3p, vha, 0xb0ac,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) "%s: Command Peg initialization "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) "complete! state=0x%x\n", __func__, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) ret_val = QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) msleep(CRB_CMDPEG_CHECK_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) } while (--retries);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) return ret_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) qla8044_start_firmware(struct scsi_qla_host *vha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) int ret_val = QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) if (qla8044_restart(vha)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) ql_log(ql_log_fatal, vha, 0xb0ad,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) "%s: Restart Error!!!, Need Reset!!!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) ret_val = QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) goto exit_start_fw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) ql_dbg(ql_dbg_p3p, vha, 0xb0af,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) "%s: Restart done!\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) ret_val = qla8044_check_cmd_peg_status(vha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) if (ret_val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) ql_log(ql_log_fatal, vha, 0xb0b0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) "%s: Peg not initialized!\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) ret_val = QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) exit_start_fw:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) return ret_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) qla8044_clear_drv_active(struct qla_hw_data *ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) uint32_t drv_active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) struct scsi_qla_host *vha = pci_get_drvdata(ha->pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) drv_active = qla8044_rd_direct(vha, QLA8044_CRB_DRV_ACTIVE_INDEX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) drv_active &= ~(1 << (ha->portnum));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) ql_log(ql_log_info, vha, 0xb0b1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) "%s(%ld): drv_active: 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) __func__, vha->host_no, drv_active);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) qla8044_wr_direct(vha, QLA8044_CRB_DRV_ACTIVE_INDEX, drv_active);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) * qla8044_device_bootstrap - Initialize device, set DEV_READY, start fw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) * @ha: pointer to adapter structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) * Note: IDC lock must be held upon entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) **/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) qla8044_device_bootstrap(struct scsi_qla_host *vha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) int rval = QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) uint32_t old_count = 0, count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) int need_reset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) uint32_t idc_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) need_reset = qla8044_need_reset(vha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) if (!need_reset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) old_count = qla8044_rd_direct(vha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) QLA8044_PEG_ALIVE_COUNTER_INDEX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) for (i = 0; i < 10; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) msleep(200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) count = qla8044_rd_direct(vha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) QLA8044_PEG_ALIVE_COUNTER_INDEX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) if (count != old_count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) rval = QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) goto dev_ready;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) qla8044_flash_lock_recovery(vha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) /* We are trying to perform a recovery here. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) if (ha->flags.isp82xx_fw_hung)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) qla8044_flash_lock_recovery(vha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) /* set to DEV_INITIALIZING */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) ql_log(ql_log_info, vha, 0xb0b2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) "%s: HW State: INITIALIZING\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) qla8044_wr_direct(vha, QLA8044_CRB_DEV_STATE_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) QLA8XXX_DEV_INITIALIZING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) qla8044_idc_unlock(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) rval = qla8044_start_firmware(vha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) qla8044_idc_lock(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) if (rval != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) ql_log(ql_log_info, vha, 0xb0b3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) "%s: HW State: FAILED\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) qla8044_clear_drv_active(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) qla8044_wr_direct(vha, QLA8044_CRB_DEV_STATE_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) QLA8XXX_DEV_FAILED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) /* For ISP8044, If IDC_CTRL GRACEFUL_RESET_BIT1 is set , reset it after
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) * device goes to INIT state. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) idc_ctrl = qla8044_rd_reg(ha, QLA8044_IDC_DRV_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) if (idc_ctrl & GRACEFUL_RESET_BIT1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) qla8044_wr_reg(ha, QLA8044_IDC_DRV_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) (idc_ctrl & ~GRACEFUL_RESET_BIT1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) ha->fw_dumped = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) dev_ready:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) ql_log(ql_log_info, vha, 0xb0b4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) "%s: HW State: READY\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) qla8044_wr_direct(vha, QLA8044_CRB_DEV_STATE_INDEX, QLA8XXX_DEV_READY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) /*-------------------------Reset Sequence Functions-----------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) qla8044_dump_reset_seq_hdr(struct scsi_qla_host *vha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) u8 *phdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) if (!vha->reset_tmplt.buff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) ql_log(ql_log_fatal, vha, 0xb0b5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) "%s: Error Invalid reset_seq_template\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) phdr = vha->reset_tmplt.buff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) ql_dbg(ql_dbg_p3p, vha, 0xb0b6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) "Reset Template :\n\t0x%X 0x%X 0x%X 0x%X"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) "0x%X 0x%X 0x%X 0x%X 0x%X 0x%X\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) "\t0x%X 0x%X 0x%X 0x%X 0x%X 0x%X\n\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) *phdr, *(phdr+1), *(phdr+2), *(phdr+3), *(phdr+4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) *(phdr+5), *(phdr+6), *(phdr+7), *(phdr + 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) *(phdr+9), *(phdr+10), *(phdr+11), *(phdr+12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) *(phdr+13), *(phdr+14), *(phdr+15));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) * qla8044_reset_seq_checksum_test - Validate Reset Sequence template.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) * @ha : Pointer to adapter structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) * Return Value - QLA_SUCCESS/QLA_FUNCTION_FAILED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) qla8044_reset_seq_checksum_test(struct scsi_qla_host *vha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) uint32_t sum = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) uint16_t *buff = (uint16_t *)vha->reset_tmplt.buff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) int u16_count = vha->reset_tmplt.hdr->size / sizeof(uint16_t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) while (u16_count-- > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) sum += *buff++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) while (sum >> 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) sum = (sum & 0xFFFF) + (sum >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) /* checksum of 0 indicates a valid template */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) if (~sum) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) return QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) ql_log(ql_log_fatal, vha, 0xb0b7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) "%s: Reset seq checksum failed\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) return QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) * qla8044_read_reset_template - Read Reset Template from Flash, validate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) * the template and store offsets of stop/start/init offsets in ha->reset_tmplt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) * @ha : Pointer to adapter structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) qla8044_read_reset_template(struct scsi_qla_host *vha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) uint8_t *p_buff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) uint32_t addr, tmplt_hdr_def_size, tmplt_hdr_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) vha->reset_tmplt.seq_error = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) vha->reset_tmplt.buff = vmalloc(QLA8044_RESTART_TEMPLATE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) if (vha->reset_tmplt.buff == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) ql_log(ql_log_fatal, vha, 0xb0b8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) "%s: Failed to allocate reset template resources\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) goto exit_read_reset_template;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) p_buff = vha->reset_tmplt.buff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) addr = QLA8044_RESET_TEMPLATE_ADDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) tmplt_hdr_def_size =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) sizeof(struct qla8044_reset_template_hdr) / sizeof(uint32_t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) ql_dbg(ql_dbg_p3p, vha, 0xb0b9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) "%s: Read template hdr size %d from Flash\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) __func__, tmplt_hdr_def_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) /* Copy template header from flash */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) if (qla8044_read_flash_data(vha, p_buff, addr, tmplt_hdr_def_size)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) ql_log(ql_log_fatal, vha, 0xb0ba,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) "%s: Failed to read reset template\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) goto exit_read_template_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) vha->reset_tmplt.hdr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) (struct qla8044_reset_template_hdr *) vha->reset_tmplt.buff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) /* Validate the template header size and signature */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) tmplt_hdr_size = vha->reset_tmplt.hdr->hdr_size/sizeof(uint32_t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) if ((tmplt_hdr_size != tmplt_hdr_def_size) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) (vha->reset_tmplt.hdr->signature != RESET_TMPLT_HDR_SIGNATURE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) ql_log(ql_log_fatal, vha, 0xb0bb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) "%s: Template Header size invalid %d "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) "tmplt_hdr_def_size %d!!!\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) tmplt_hdr_size, tmplt_hdr_def_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) goto exit_read_template_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) addr = QLA8044_RESET_TEMPLATE_ADDR + vha->reset_tmplt.hdr->hdr_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) p_buff = vha->reset_tmplt.buff + vha->reset_tmplt.hdr->hdr_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) tmplt_hdr_def_size = (vha->reset_tmplt.hdr->size -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) vha->reset_tmplt.hdr->hdr_size)/sizeof(uint32_t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) ql_dbg(ql_dbg_p3p, vha, 0xb0bc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) "%s: Read rest of the template size %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) __func__, vha->reset_tmplt.hdr->size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) /* Copy rest of the template */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) if (qla8044_read_flash_data(vha, p_buff, addr, tmplt_hdr_def_size)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) ql_log(ql_log_fatal, vha, 0xb0bd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) "%s: Failed to read reset template\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) goto exit_read_template_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) /* Integrity check */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) if (qla8044_reset_seq_checksum_test(vha)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) ql_log(ql_log_fatal, vha, 0xb0be,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) "%s: Reset Seq checksum failed!\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) goto exit_read_template_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) ql_dbg(ql_dbg_p3p, vha, 0xb0bf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) "%s: Reset Seq checksum passed! Get stop, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) "start and init seq offsets\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) /* Get STOP, START, INIT sequence offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) vha->reset_tmplt.init_offset = vha->reset_tmplt.buff +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) vha->reset_tmplt.hdr->init_seq_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) vha->reset_tmplt.start_offset = vha->reset_tmplt.buff +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) vha->reset_tmplt.hdr->start_seq_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) vha->reset_tmplt.stop_offset = vha->reset_tmplt.buff +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) vha->reset_tmplt.hdr->hdr_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) qla8044_dump_reset_seq_hdr(vha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) goto exit_read_reset_template;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) exit_read_template_error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) vfree(vha->reset_tmplt.buff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) exit_read_reset_template:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) qla8044_set_idc_dontreset(struct scsi_qla_host *vha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) uint32_t idc_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) idc_ctrl = qla8044_rd_reg(ha, QLA8044_IDC_DRV_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) idc_ctrl |= DONTRESET_BIT0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) ql_dbg(ql_dbg_p3p, vha, 0xb0c0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) "%s: idc_ctrl = %d\n", __func__, idc_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) qla8044_wr_reg(ha, QLA8044_IDC_DRV_CTRL, idc_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) qla8044_set_rst_ready(struct scsi_qla_host *vha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) uint32_t drv_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) drv_state = qla8044_rd_direct(vha, QLA8044_CRB_DRV_STATE_INDEX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) /* For ISP8044, drv_active register has 1 bit per function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) * shift 1 by func_num to set a bit for the function.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) drv_state |= (1 << ha->portnum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) ql_log(ql_log_info, vha, 0xb0c1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) "%s(%ld): drv_state: 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) __func__, vha->host_no, drv_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) qla8044_wr_direct(vha, QLA8044_CRB_DRV_STATE_INDEX, drv_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) * qla8044_need_reset_handler - Code to start reset sequence
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) * @vha: pointer to adapter structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) * Note: IDC lock must be held upon entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) qla8044_need_reset_handler(struct scsi_qla_host *vha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) uint32_t dev_state = 0, drv_state, drv_active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) unsigned long reset_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) ql_log(ql_log_fatal, vha, 0xb0c2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) "%s: Performing ISP error recovery\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) if (vha->flags.online) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) qla8044_idc_unlock(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) qla2x00_abort_isp_cleanup(vha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) ha->isp_ops->get_flash_version(vha, vha->req->ring);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) ha->isp_ops->nvram_config(vha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) qla8044_idc_lock(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) dev_state = qla8044_rd_direct(vha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) QLA8044_CRB_DEV_STATE_INDEX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) drv_state = qla8044_rd_direct(vha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) QLA8044_CRB_DRV_STATE_INDEX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) drv_active = qla8044_rd_direct(vha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) QLA8044_CRB_DRV_ACTIVE_INDEX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) ql_log(ql_log_info, vha, 0xb0c5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) "%s(%ld): drv_state = 0x%x, drv_active = 0x%x dev_state = 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) __func__, vha->host_no, drv_state, drv_active, dev_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) qla8044_set_rst_ready(vha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) /* wait for 10 seconds for reset ack from all functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) reset_timeout = jiffies + (ha->fcoe_reset_timeout * HZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) if (time_after_eq(jiffies, reset_timeout)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) ql_log(ql_log_info, vha, 0xb0c4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) "%s: Function %d: Reset Ack Timeout!, drv_state: 0x%08x, drv_active: 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) __func__, ha->portnum, drv_state, drv_active);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) qla8044_idc_unlock(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) msleep(1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) qla8044_idc_lock(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) dev_state = qla8044_rd_direct(vha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) QLA8044_CRB_DEV_STATE_INDEX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) drv_state = qla8044_rd_direct(vha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) QLA8044_CRB_DRV_STATE_INDEX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) drv_active = qla8044_rd_direct(vha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) QLA8044_CRB_DRV_ACTIVE_INDEX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) } while (((drv_state & drv_active) != drv_active) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) (dev_state == QLA8XXX_DEV_NEED_RESET));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) /* Remove IDC participation of functions not acknowledging */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) if (drv_state != drv_active) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) ql_log(ql_log_info, vha, 0xb0c7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) "%s(%ld): Function %d turning off drv_active of non-acking function 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) __func__, vha->host_no, ha->portnum,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) (drv_active ^ drv_state));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) drv_active = drv_active & drv_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) qla8044_wr_direct(vha, QLA8044_CRB_DRV_ACTIVE_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) drv_active);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) * Reset owner should execute reset recovery,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) * if all functions acknowledged
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) if ((ha->flags.nic_core_reset_owner) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) (dev_state == QLA8XXX_DEV_NEED_RESET)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) ha->flags.nic_core_reset_owner = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) qla8044_device_bootstrap(vha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) /* Exit if non active function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) if (!(drv_active & (1 << ha->portnum))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) ha->flags.nic_core_reset_owner = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) * Execute Reset Recovery if Reset Owner or Function 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) * is the only active function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) if (ha->flags.nic_core_reset_owner ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) ((drv_state & drv_active) == QLA8044_FUN7_ACTIVE_INDEX)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) ha->flags.nic_core_reset_owner = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) qla8044_device_bootstrap(vha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) qla8044_set_drv_active(struct scsi_qla_host *vha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) uint32_t drv_active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) drv_active = qla8044_rd_direct(vha, QLA8044_CRB_DRV_ACTIVE_INDEX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) /* For ISP8044, drv_active register has 1 bit per function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) * shift 1 by func_num to set a bit for the function.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) drv_active |= (1 << ha->portnum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) ql_log(ql_log_info, vha, 0xb0c8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) "%s(%ld): drv_active: 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) __func__, vha->host_no, drv_active);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) qla8044_wr_direct(vha, QLA8044_CRB_DRV_ACTIVE_INDEX, drv_active);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) qla8044_check_drv_active(struct scsi_qla_host *vha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) uint32_t drv_active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) drv_active = qla8044_rd_direct(vha, QLA8044_CRB_DRV_ACTIVE_INDEX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) if (drv_active & (1 << ha->portnum))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) return QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) return QLA_TEST_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) qla8044_clear_idc_dontreset(struct scsi_qla_host *vha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) uint32_t idc_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) idc_ctrl = qla8044_rd_reg(ha, QLA8044_IDC_DRV_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) idc_ctrl &= ~DONTRESET_BIT0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) ql_log(ql_log_info, vha, 0xb0c9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) "%s: idc_ctrl = %d\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) idc_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) qla8044_wr_reg(ha, QLA8044_IDC_DRV_CTRL, idc_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) qla8044_set_idc_ver(struct scsi_qla_host *vha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) int idc_ver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) uint32_t drv_active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) int rval = QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) drv_active = qla8044_rd_direct(vha, QLA8044_CRB_DRV_ACTIVE_INDEX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) if (drv_active == (1 << ha->portnum)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) idc_ver = qla8044_rd_direct(vha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) QLA8044_CRB_DRV_IDC_VERSION_INDEX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) idc_ver &= (~0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) idc_ver |= QLA8044_IDC_VER_MAJ_VALUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) qla8044_wr_direct(vha, QLA8044_CRB_DRV_IDC_VERSION_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) idc_ver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) ql_log(ql_log_info, vha, 0xb0ca,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) "%s: IDC version updated to %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) __func__, idc_ver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) idc_ver = qla8044_rd_direct(vha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) QLA8044_CRB_DRV_IDC_VERSION_INDEX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) idc_ver &= 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) if (QLA8044_IDC_VER_MAJ_VALUE != idc_ver) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) ql_log(ql_log_info, vha, 0xb0cb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) "%s: qla4xxx driver IDC version %d "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) "is not compatible with IDC version %d "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) "of other drivers!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) __func__, QLA8044_IDC_VER_MAJ_VALUE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) idc_ver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) rval = QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) goto exit_set_idc_ver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) /* Update IDC_MINOR_VERSION */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) idc_ver = qla8044_rd_reg(ha, QLA8044_CRB_IDC_VER_MINOR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) idc_ver &= ~(0x03 << (ha->portnum * 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) idc_ver |= (QLA8044_IDC_VER_MIN_VALUE << (ha->portnum * 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) qla8044_wr_reg(ha, QLA8044_CRB_IDC_VER_MINOR, idc_ver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) exit_set_idc_ver:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) qla8044_update_idc_reg(struct scsi_qla_host *vha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) uint32_t drv_active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) int rval = QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) if (vha->flags.init_done)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) goto exit_update_idc_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) qla8044_idc_lock(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) qla8044_set_drv_active(vha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) drv_active = qla8044_rd_direct(vha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) QLA8044_CRB_DRV_ACTIVE_INDEX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) /* If we are the first driver to load and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) * ql2xdontresethba is not set, clear IDC_CTRL BIT0. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) if ((drv_active == (1 << ha->portnum)) && !ql2xdontresethba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) qla8044_clear_idc_dontreset(vha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) rval = qla8044_set_idc_ver(vha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) if (rval == QLA_FUNCTION_FAILED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) qla8044_clear_drv_active(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) qla8044_idc_unlock(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) exit_update_idc_reg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) * qla8044_need_qsnt_handler - Code to start qsnt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) * @vha: pointer to adapter structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) qla8044_need_qsnt_handler(struct scsi_qla_host *vha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) unsigned long qsnt_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) uint32_t drv_state, drv_active, dev_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) if (vha->flags.online)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) qla2x00_quiesce_io(vha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) qla8044_set_qsnt_ready(vha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) /* Wait for 30 secs for all functions to ack qsnt mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) qsnt_timeout = jiffies + (QSNT_ACK_TOV * HZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) drv_state = qla8044_rd_direct(vha, QLA8044_CRB_DRV_STATE_INDEX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) drv_active = qla8044_rd_direct(vha, QLA8044_CRB_DRV_ACTIVE_INDEX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) /* Shift drv_active by 1 to match drv_state. As quiescent ready bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) position is at bit 1 and drv active is at bit 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) drv_active = drv_active << 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) while (drv_state != drv_active) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) if (time_after_eq(jiffies, qsnt_timeout)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) /* Other functions did not ack, changing state to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) * DEV_READY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) clear_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) qla8044_wr_direct(vha, QLA8044_CRB_DEV_STATE_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) QLA8XXX_DEV_READY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) qla8044_clear_qsnt_ready(vha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) ql_log(ql_log_info, vha, 0xb0cc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) "Timeout waiting for quiescent ack!!!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) qla8044_idc_unlock(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) msleep(1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) qla8044_idc_lock(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) drv_state = qla8044_rd_direct(vha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) QLA8044_CRB_DRV_STATE_INDEX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) drv_active = qla8044_rd_direct(vha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) QLA8044_CRB_DRV_ACTIVE_INDEX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) drv_active = drv_active << 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) /* All functions have Acked. Set quiescent state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) dev_state = qla8044_rd_direct(vha, QLA8044_CRB_DEV_STATE_INDEX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) if (dev_state == QLA8XXX_DEV_NEED_QUIESCENT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) qla8044_wr_direct(vha, QLA8044_CRB_DEV_STATE_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) QLA8XXX_DEV_QUIESCENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) ql_log(ql_log_info, vha, 0xb0cd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) "%s: HW State: QUIESCENT\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) * qla8044_device_state_handler - Adapter state machine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) * @ha: pointer to host adapter structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) * Note: IDC lock must be UNLOCKED upon entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) **/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) qla8044_device_state_handler(struct scsi_qla_host *vha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) uint32_t dev_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) int rval = QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) unsigned long dev_init_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) rval = qla8044_update_idc_reg(vha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) if (rval == QLA_FUNCTION_FAILED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) goto exit_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) dev_state = qla8044_rd_direct(vha, QLA8044_CRB_DEV_STATE_INDEX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) ql_dbg(ql_dbg_p3p, vha, 0xb0ce,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) "Device state is 0x%x = %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) dev_state, dev_state < MAX_STATES ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) qdev_state(dev_state) : "Unknown");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) /* wait for 30 seconds for device to go ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) qla8044_idc_lock(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) while (1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) if (time_after_eq(jiffies, dev_init_timeout)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) if (qla8044_check_drv_active(vha) == QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) ql_log(ql_log_warn, vha, 0xb0cf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) "%s: Device Init Failed 0x%x = %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) QLA2XXX_DRIVER_NAME, dev_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) dev_state < MAX_STATES ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) qdev_state(dev_state) : "Unknown");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) qla8044_wr_direct(vha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) QLA8044_CRB_DEV_STATE_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) QLA8XXX_DEV_FAILED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) dev_state = qla8044_rd_direct(vha, QLA8044_CRB_DEV_STATE_INDEX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) ql_log(ql_log_info, vha, 0xb0d0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) "Device state is 0x%x = %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) dev_state, dev_state < MAX_STATES ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) qdev_state(dev_state) : "Unknown");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) /* NOTE: Make sure idc unlocked upon exit of switch statement */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) switch (dev_state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) case QLA8XXX_DEV_READY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) ha->flags.nic_core_reset_owner = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) case QLA8XXX_DEV_COLD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) rval = qla8044_device_bootstrap(vha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) case QLA8XXX_DEV_INITIALIZING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) qla8044_idc_unlock(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) msleep(1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) qla8044_idc_lock(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) case QLA8XXX_DEV_NEED_RESET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) /* For ISP8044, if NEED_RESET is set by any driver,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) * it should be honored, irrespective of IDC_CTRL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) * DONTRESET_BIT0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) qla8044_need_reset_handler(vha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) case QLA8XXX_DEV_NEED_QUIESCENT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) /* idc locked/unlocked in handler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) qla8044_need_qsnt_handler(vha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) /* Reset the init timeout after qsnt handler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) dev_init_timeout = jiffies +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) (ha->fcoe_reset_timeout * HZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) case QLA8XXX_DEV_QUIESCENT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) ql_log(ql_log_info, vha, 0xb0d1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) "HW State: QUIESCENT\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) qla8044_idc_unlock(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) msleep(1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) qla8044_idc_lock(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) /* Reset the init timeout after qsnt handler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) dev_init_timeout = jiffies +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) (ha->fcoe_reset_timeout * HZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) case QLA8XXX_DEV_FAILED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) ha->flags.nic_core_reset_owner = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) qla8044_idc_unlock(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) qla8xxx_dev_failed_handler(vha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) rval = QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) qla8044_idc_lock(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) qla8044_idc_unlock(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) qla8xxx_dev_failed_handler(vha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) rval = QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) qla8044_idc_lock(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) qla8044_idc_unlock(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) exit_error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) * qla4_8xxx_check_temp - Check the ISP82XX temperature.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) * @vha: adapter block pointer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) * Note: The caller should not hold the idc lock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) qla8044_check_temp(struct scsi_qla_host *vha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) uint32_t temp, temp_state, temp_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) int status = QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) temp = qla8044_rd_direct(vha, QLA8044_CRB_TEMP_STATE_INDEX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) temp_state = qla82xx_get_temp_state(temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) temp_val = qla82xx_get_temp_val(temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) if (temp_state == QLA82XX_TEMP_PANIC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) ql_log(ql_log_warn, vha, 0xb0d2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) "Device temperature %d degrees C"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) " exceeds maximum allowed. Hardware has been shut"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) " down\n", temp_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) status = QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) } else if (temp_state == QLA82XX_TEMP_WARN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) ql_log(ql_log_warn, vha, 0xb0d3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) "Device temperature %d"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) " degrees C exceeds operating range."
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) " Immediate action needed.\n", temp_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) int qla8044_read_temperature(scsi_qla_host_t *vha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) uint32_t temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) temp = qla8044_rd_direct(vha, QLA8044_CRB_TEMP_STATE_INDEX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) return qla82xx_get_temp_val(temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) * qla8044_check_fw_alive - Check firmware health
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) * @vha: Pointer to host adapter structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) * Context: Interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) qla8044_check_fw_alive(struct scsi_qla_host *vha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) uint32_t fw_heartbeat_counter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) uint32_t halt_status1, halt_status2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) int status = QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) fw_heartbeat_counter = qla8044_rd_direct(vha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) QLA8044_PEG_ALIVE_COUNTER_INDEX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) /* If PEG_ALIVE_COUNTER is 0xffffffff, AER/EEH is in progress, ignore */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) if (fw_heartbeat_counter == 0xffffffff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) ql_dbg(ql_dbg_p3p, vha, 0xb0d4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) "scsi%ld: %s: Device in frozen "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) "state, QLA82XX_PEG_ALIVE_COUNTER is 0xffffffff\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) vha->host_no, __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) if (vha->fw_heartbeat_counter == fw_heartbeat_counter) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) vha->seconds_since_last_heartbeat++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) /* FW not alive after 2 seconds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) if (vha->seconds_since_last_heartbeat == 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) vha->seconds_since_last_heartbeat = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) halt_status1 = qla8044_rd_direct(vha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) QLA8044_PEG_HALT_STATUS1_INDEX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) halt_status2 = qla8044_rd_direct(vha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) QLA8044_PEG_HALT_STATUS2_INDEX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) ql_log(ql_log_info, vha, 0xb0d5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) "scsi(%ld): %s, ISP8044 "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) "Dumping hw/fw registers:\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) " PEG_HALT_STATUS1: 0x%x, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) "PEG_HALT_STATUS2: 0x%x,\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) vha->host_no, __func__, halt_status1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) halt_status2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) status = QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) vha->seconds_since_last_heartbeat = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) vha->fw_heartbeat_counter = fw_heartbeat_counter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) qla8044_watchdog(struct scsi_qla_host *vha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) uint32_t dev_state, halt_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) int halt_status_unrecoverable = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) /* don't poll if reset is going on or FW hang in quiescent state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) if (!(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) dev_state = qla8044_rd_direct(vha, QLA8044_CRB_DEV_STATE_INDEX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) if (qla8044_check_fw_alive(vha)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) ha->flags.isp82xx_fw_hung = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) ql_log(ql_log_warn, vha, 0xb10a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) "Firmware hung.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) qla82xx_clear_pending_mbx(vha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) if (qla8044_check_temp(vha)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) set_bit(ISP_UNRECOVERABLE, &vha->dpc_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) ha->flags.isp82xx_fw_hung = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) qla2xxx_wake_dpc(vha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) } else if (dev_state == QLA8XXX_DEV_NEED_RESET &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) !test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) ql_log(ql_log_info, vha, 0xb0d6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) "%s: HW State: NEED RESET!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) qla2xxx_wake_dpc(vha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) } else if (dev_state == QLA8XXX_DEV_NEED_QUIESCENT &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) !test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) ql_log(ql_log_info, vha, 0xb0d7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) "%s: HW State: NEED QUIES detected!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) set_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) qla2xxx_wake_dpc(vha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) /* Check firmware health */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) if (ha->flags.isp82xx_fw_hung) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) halt_status = qla8044_rd_direct(vha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) QLA8044_PEG_HALT_STATUS1_INDEX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) if (halt_status &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) QLA8044_HALT_STATUS_FW_RESET) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) ql_log(ql_log_fatal, vha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) 0xb0d8, "%s: Firmware "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) "error detected device "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) "is being reset\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) } else if (halt_status &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) QLA8044_HALT_STATUS_UNRECOVERABLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) halt_status_unrecoverable = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) /* Since we cannot change dev_state in interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) * context, set appropriate DPC flag then wakeup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) * DPC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) if (halt_status_unrecoverable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) set_bit(ISP_UNRECOVERABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) &vha->dpc_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) if (dev_state ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) QLA8XXX_DEV_QUIESCENT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) set_bit(FCOE_CTX_RESET_NEEDED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) &vha->dpc_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) ql_log(ql_log_info, vha, 0xb0d9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) "%s: FW CONTEXT Reset "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) "needed!\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) ql_log(ql_log_info, vha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) 0xb0da, "%s: "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) "detect abort needed\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) set_bit(ISP_ABORT_NEEDED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) &vha->dpc_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) qla2xxx_wake_dpc(vha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) qla8044_minidump_process_control(struct scsi_qla_host *vha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) struct qla8044_minidump_entry_hdr *entry_hdr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) struct qla8044_minidump_entry_crb *crb_entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) uint32_t read_value, opcode, poll_time, addr, index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) uint32_t crb_addr, rval = QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) unsigned long wtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) struct qla8044_minidump_template_hdr *tmplt_hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) ql_dbg(ql_dbg_p3p, vha, 0xb0dd, "Entering fn: %s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) tmplt_hdr = (struct qla8044_minidump_template_hdr *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) ha->md_tmplt_hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) crb_entry = (struct qla8044_minidump_entry_crb *)entry_hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) crb_addr = crb_entry->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) for (i = 0; i < crb_entry->op_count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) opcode = crb_entry->crb_ctrl.opcode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) if (opcode & QLA82XX_DBG_OPCODE_WR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) qla8044_wr_reg_indirect(vha, crb_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) crb_entry->value_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) opcode &= ~QLA82XX_DBG_OPCODE_WR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) if (opcode & QLA82XX_DBG_OPCODE_RW) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) qla8044_rd_reg_indirect(vha, crb_addr, &read_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) qla8044_wr_reg_indirect(vha, crb_addr, read_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) opcode &= ~QLA82XX_DBG_OPCODE_RW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) if (opcode & QLA82XX_DBG_OPCODE_AND) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) qla8044_rd_reg_indirect(vha, crb_addr, &read_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) read_value &= crb_entry->value_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) opcode &= ~QLA82XX_DBG_OPCODE_AND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) if (opcode & QLA82XX_DBG_OPCODE_OR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) read_value |= crb_entry->value_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) opcode &= ~QLA82XX_DBG_OPCODE_OR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) qla8044_wr_reg_indirect(vha, crb_addr, read_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) if (opcode & QLA82XX_DBG_OPCODE_OR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) qla8044_rd_reg_indirect(vha, crb_addr, &read_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) read_value |= crb_entry->value_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) qla8044_wr_reg_indirect(vha, crb_addr, read_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) opcode &= ~QLA82XX_DBG_OPCODE_OR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) if (opcode & QLA82XX_DBG_OPCODE_POLL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) poll_time = crb_entry->crb_strd.poll_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) wtime = jiffies + poll_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) qla8044_rd_reg_indirect(vha, crb_addr, &read_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) if ((read_value & crb_entry->value_2) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) crb_entry->value_1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) } else if (time_after_eq(jiffies, wtime)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) /* capturing dump failed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) rval = QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) qla8044_rd_reg_indirect(vha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) crb_addr, &read_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) } while (1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) opcode &= ~QLA82XX_DBG_OPCODE_POLL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) if (opcode & QLA82XX_DBG_OPCODE_RDSTATE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) if (crb_entry->crb_strd.state_index_a) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) index = crb_entry->crb_strd.state_index_a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) addr = tmplt_hdr->saved_state_array[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) addr = crb_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) qla8044_rd_reg_indirect(vha, addr, &read_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) index = crb_entry->crb_ctrl.state_index_v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) tmplt_hdr->saved_state_array[index] = read_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) opcode &= ~QLA82XX_DBG_OPCODE_RDSTATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) if (opcode & QLA82XX_DBG_OPCODE_WRSTATE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) if (crb_entry->crb_strd.state_index_a) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) index = crb_entry->crb_strd.state_index_a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) addr = tmplt_hdr->saved_state_array[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) addr = crb_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) if (crb_entry->crb_ctrl.state_index_v) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) index = crb_entry->crb_ctrl.state_index_v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) read_value =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) tmplt_hdr->saved_state_array[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) read_value = crb_entry->value_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) qla8044_wr_reg_indirect(vha, addr, read_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) opcode &= ~QLA82XX_DBG_OPCODE_WRSTATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) if (opcode & QLA82XX_DBG_OPCODE_MDSTATE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) index = crb_entry->crb_ctrl.state_index_v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) read_value = tmplt_hdr->saved_state_array[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) read_value <<= crb_entry->crb_ctrl.shl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) read_value >>= crb_entry->crb_ctrl.shr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) if (crb_entry->value_2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) read_value &= crb_entry->value_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) read_value |= crb_entry->value_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) read_value += crb_entry->value_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) tmplt_hdr->saved_state_array[index] = read_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) opcode &= ~QLA82XX_DBG_OPCODE_MDSTATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) crb_addr += crb_entry->crb_strd.addr_stride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) qla8044_minidump_process_rdcrb(struct scsi_qla_host *vha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) struct qla8044_minidump_entry_hdr *entry_hdr, uint32_t **d_ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) uint32_t r_addr, r_stride, loop_cnt, i, r_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) struct qla8044_minidump_entry_crb *crb_hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) uint32_t *data_ptr = *d_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) ql_dbg(ql_dbg_p3p, vha, 0xb0de, "Entering fn: %s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) crb_hdr = (struct qla8044_minidump_entry_crb *)entry_hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) r_addr = crb_hdr->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) r_stride = crb_hdr->crb_strd.addr_stride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) loop_cnt = crb_hdr->op_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) for (i = 0; i < loop_cnt; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) qla8044_rd_reg_indirect(vha, r_addr, &r_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) *data_ptr++ = r_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) *data_ptr++ = r_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) r_addr += r_stride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) *d_ptr = data_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) qla8044_minidump_process_rdmem(struct scsi_qla_host *vha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) struct qla8044_minidump_entry_hdr *entry_hdr, uint32_t **d_ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) uint32_t r_addr, r_value, r_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) uint32_t i, j, loop_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) struct qla8044_minidump_entry_rdmem *m_hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) uint32_t *data_ptr = *d_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) ql_dbg(ql_dbg_p3p, vha, 0xb0df, "Entering fn: %s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) m_hdr = (struct qla8044_minidump_entry_rdmem *)entry_hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) r_addr = m_hdr->read_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) loop_cnt = m_hdr->read_data_size/16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) ql_dbg(ql_dbg_p3p, vha, 0xb0f0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) "[%s]: Read addr: 0x%x, read_data_size: 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) __func__, r_addr, m_hdr->read_data_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) if (r_addr & 0xf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) ql_dbg(ql_dbg_p3p, vha, 0xb0f1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) "[%s]: Read addr 0x%x not 16 bytes aligned\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) __func__, r_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) return QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) if (m_hdr->read_data_size % 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) ql_dbg(ql_dbg_p3p, vha, 0xb0f2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) "[%s]: Read data[0x%x] not multiple of 16 bytes\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) __func__, m_hdr->read_data_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) return QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) ql_dbg(ql_dbg_p3p, vha, 0xb0f3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) "[%s]: rdmem_addr: 0x%x, read_data_size: 0x%x, loop_cnt: 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) __func__, r_addr, m_hdr->read_data_size, loop_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) write_lock_irqsave(&ha->hw_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) for (i = 0; i < loop_cnt; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) qla8044_wr_reg_indirect(vha, MD_MIU_TEST_AGT_ADDR_LO, r_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) r_value = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) qla8044_wr_reg_indirect(vha, MD_MIU_TEST_AGT_ADDR_HI, r_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) r_value = MIU_TA_CTL_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) qla8044_wr_reg_indirect(vha, MD_MIU_TEST_AGT_CTRL, r_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) r_value = MIU_TA_CTL_START_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) qla8044_wr_reg_indirect(vha, MD_MIU_TEST_AGT_CTRL, r_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) for (j = 0; j < MAX_CTL_CHECK; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) qla8044_rd_reg_indirect(vha, MD_MIU_TEST_AGT_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) &r_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) if ((r_value & MIU_TA_CTL_BUSY) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) if (j >= MAX_CTL_CHECK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) write_unlock_irqrestore(&ha->hw_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) return QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) for (j = 0; j < 4; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) qla8044_rd_reg_indirect(vha, MD_MIU_TEST_AGT_RDDATA[j],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) &r_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) *data_ptr++ = r_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) r_addr += 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) write_unlock_irqrestore(&ha->hw_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) ql_dbg(ql_dbg_p3p, vha, 0xb0f4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) "Leaving fn: %s datacount: 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) __func__, (loop_cnt * 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) *d_ptr = data_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) return QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) /* ISP83xx flash read for _RDROM _BOARD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) static uint32_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) qla8044_minidump_process_rdrom(struct scsi_qla_host *vha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) struct qla8044_minidump_entry_hdr *entry_hdr, uint32_t **d_ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) uint32_t fl_addr, u32_count, rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) struct qla8044_minidump_entry_rdrom *rom_hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) uint32_t *data_ptr = *d_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) rom_hdr = (struct qla8044_minidump_entry_rdrom *)entry_hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) fl_addr = rom_hdr->read_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) u32_count = (rom_hdr->read_data_size)/sizeof(uint32_t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) ql_dbg(ql_dbg_p3p, vha, 0xb0f5, "[%s]: fl_addr: 0x%x, count: 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) __func__, fl_addr, u32_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) rval = qla8044_lockless_flash_read_u32(vha, fl_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) (u8 *)(data_ptr), u32_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) if (rval != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) ql_log(ql_log_fatal, vha, 0xb0f6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) "%s: Flash Read Error,Count=%d\n", __func__, u32_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) return QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) data_ptr += u32_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) *d_ptr = data_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) return QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) qla8044_mark_entry_skipped(struct scsi_qla_host *vha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) struct qla8044_minidump_entry_hdr *entry_hdr, int index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) entry_hdr->d_ctrl.driver_flags |= QLA82XX_DBG_SKIPPED_FLAG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) ql_log(ql_log_info, vha, 0xb0f7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) "scsi(%ld): Skipping entry[%d]: ETYPE[0x%x]-ELEVEL[0x%x]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) vha->host_no, index, entry_hdr->entry_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) entry_hdr->d_ctrl.entry_capture_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) qla8044_minidump_process_l2tag(struct scsi_qla_host *vha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) struct qla8044_minidump_entry_hdr *entry_hdr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) uint32_t **d_ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) uint32_t addr, r_addr, c_addr, t_r_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) uint32_t i, k, loop_count, t_value, r_cnt, r_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) unsigned long p_wait, w_time, p_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) uint32_t c_value_w, c_value_r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) struct qla8044_minidump_entry_cache *cache_hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) int rval = QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) uint32_t *data_ptr = *d_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) ql_dbg(ql_dbg_p3p, vha, 0xb0f8, "Entering fn: %s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) cache_hdr = (struct qla8044_minidump_entry_cache *)entry_hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) loop_count = cache_hdr->op_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) r_addr = cache_hdr->read_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) c_addr = cache_hdr->control_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) c_value_w = cache_hdr->cache_ctrl.write_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) t_r_addr = cache_hdr->tag_reg_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) t_value = cache_hdr->addr_ctrl.init_tag_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) r_cnt = cache_hdr->read_ctrl.read_addr_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) p_wait = cache_hdr->cache_ctrl.poll_wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) p_mask = cache_hdr->cache_ctrl.poll_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) for (i = 0; i < loop_count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) qla8044_wr_reg_indirect(vha, t_r_addr, t_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) if (c_value_w)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) qla8044_wr_reg_indirect(vha, c_addr, c_value_w);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) if (p_mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) w_time = jiffies + p_wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) qla8044_rd_reg_indirect(vha, c_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) &c_value_r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) if ((c_value_r & p_mask) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) } else if (time_after_eq(jiffies, w_time)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) /* capturing dump failed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) } while (1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) addr = r_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) for (k = 0; k < r_cnt; k++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) qla8044_rd_reg_indirect(vha, addr, &r_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) *data_ptr++ = r_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) addr += cache_hdr->read_ctrl.read_addr_stride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) t_value += cache_hdr->addr_ctrl.tag_value_stride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) *d_ptr = data_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) return QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528) qla8044_minidump_process_l1cache(struct scsi_qla_host *vha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) struct qla8044_minidump_entry_hdr *entry_hdr, uint32_t **d_ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) uint32_t addr, r_addr, c_addr, t_r_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) uint32_t i, k, loop_count, t_value, r_cnt, r_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) uint32_t c_value_w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) struct qla8044_minidump_entry_cache *cache_hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) uint32_t *data_ptr = *d_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) cache_hdr = (struct qla8044_minidump_entry_cache *)entry_hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) loop_count = cache_hdr->op_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) r_addr = cache_hdr->read_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) c_addr = cache_hdr->control_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) c_value_w = cache_hdr->cache_ctrl.write_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) t_r_addr = cache_hdr->tag_reg_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) t_value = cache_hdr->addr_ctrl.init_tag_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) r_cnt = cache_hdr->read_ctrl.read_addr_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) for (i = 0; i < loop_count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) qla8044_wr_reg_indirect(vha, t_r_addr, t_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) qla8044_wr_reg_indirect(vha, c_addr, c_value_w);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) addr = r_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) for (k = 0; k < r_cnt; k++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) qla8044_rd_reg_indirect(vha, addr, &r_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) *data_ptr++ = r_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) addr += cache_hdr->read_ctrl.read_addr_stride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) t_value += cache_hdr->addr_ctrl.tag_value_stride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) *d_ptr = data_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562) qla8044_minidump_process_rdocm(struct scsi_qla_host *vha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) struct qla8044_minidump_entry_hdr *entry_hdr, uint32_t **d_ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) uint32_t r_addr, r_stride, loop_cnt, i, r_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) struct qla8044_minidump_entry_rdocm *ocm_hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567) uint32_t *data_ptr = *d_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) ql_dbg(ql_dbg_p3p, vha, 0xb0f9, "Entering fn: %s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) ocm_hdr = (struct qla8044_minidump_entry_rdocm *)entry_hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) r_addr = ocm_hdr->read_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) r_stride = ocm_hdr->read_addr_stride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) loop_cnt = ocm_hdr->op_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) ql_dbg(ql_dbg_p3p, vha, 0xb0fa,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) "[%s]: r_addr: 0x%x, r_stride: 0x%x, loop_cnt: 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579) __func__, r_addr, r_stride, loop_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) for (i = 0; i < loop_cnt; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) r_value = readl((void __iomem *)(r_addr + ha->nx_pcibase));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583) *data_ptr++ = r_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584) r_addr += r_stride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) ql_dbg(ql_dbg_p3p, vha, 0xb0fb, "Leaving fn: %s datacount: 0x%lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) __func__, (long unsigned int) (loop_cnt * sizeof(uint32_t)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589) *d_ptr = data_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) qla8044_minidump_process_rdmux(struct scsi_qla_host *vha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) struct qla8044_minidump_entry_hdr *entry_hdr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595) uint32_t **d_ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) uint32_t r_addr, s_stride, s_addr, s_value, loop_cnt, i, r_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598) struct qla8044_minidump_entry_mux *mux_hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) uint32_t *data_ptr = *d_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601) ql_dbg(ql_dbg_p3p, vha, 0xb0fc, "Entering fn: %s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603) mux_hdr = (struct qla8044_minidump_entry_mux *)entry_hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) r_addr = mux_hdr->read_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605) s_addr = mux_hdr->select_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606) s_stride = mux_hdr->select_value_stride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607) s_value = mux_hdr->select_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608) loop_cnt = mux_hdr->op_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) for (i = 0; i < loop_cnt; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) qla8044_wr_reg_indirect(vha, s_addr, s_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612) qla8044_rd_reg_indirect(vha, r_addr, &r_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) *data_ptr++ = s_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614) *data_ptr++ = r_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615) s_value += s_stride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617) *d_ptr = data_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621) qla8044_minidump_process_queue(struct scsi_qla_host *vha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622) struct qla8044_minidump_entry_hdr *entry_hdr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623) uint32_t **d_ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625) uint32_t s_addr, r_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626) uint32_t r_stride, r_value, r_cnt, qid = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) uint32_t i, k, loop_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628) struct qla8044_minidump_entry_queue *q_hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629) uint32_t *data_ptr = *d_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631) ql_dbg(ql_dbg_p3p, vha, 0xb0fd, "Entering fn: %s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632) q_hdr = (struct qla8044_minidump_entry_queue *)entry_hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) s_addr = q_hdr->select_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634) r_cnt = q_hdr->rd_strd.read_addr_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635) r_stride = q_hdr->rd_strd.read_addr_stride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636) loop_cnt = q_hdr->op_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638) for (i = 0; i < loop_cnt; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639) qla8044_wr_reg_indirect(vha, s_addr, qid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640) r_addr = q_hdr->read_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641) for (k = 0; k < r_cnt; k++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642) qla8044_rd_reg_indirect(vha, r_addr, &r_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643) *data_ptr++ = r_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644) r_addr += r_stride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646) qid += q_hdr->q_strd.queue_id_stride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648) *d_ptr = data_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651) /* ISP83xx functions to process new minidump entries... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652) static uint32_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653) qla8044_minidump_process_pollrd(struct scsi_qla_host *vha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654) struct qla8044_minidump_entry_hdr *entry_hdr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655) uint32_t **d_ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657) uint32_t r_addr, s_addr, s_value, r_value, poll_wait, poll_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658) uint16_t s_stride, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659) struct qla8044_minidump_entry_pollrd *pollrd_hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660) uint32_t *data_ptr = *d_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662) pollrd_hdr = (struct qla8044_minidump_entry_pollrd *) entry_hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663) s_addr = pollrd_hdr->select_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664) r_addr = pollrd_hdr->read_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665) s_value = pollrd_hdr->select_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666) s_stride = pollrd_hdr->select_value_stride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668) poll_wait = pollrd_hdr->poll_wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669) poll_mask = pollrd_hdr->poll_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671) for (i = 0; i < pollrd_hdr->op_count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672) qla8044_wr_reg_indirect(vha, s_addr, s_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673) poll_wait = pollrd_hdr->poll_wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674) while (1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675) qla8044_rd_reg_indirect(vha, s_addr, &r_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676) if ((r_value & poll_mask) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679) usleep_range(1000, 1100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680) if (--poll_wait == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681) ql_log(ql_log_fatal, vha, 0xb0fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682) "%s: TIMEOUT\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687) qla8044_rd_reg_indirect(vha, r_addr, &r_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688) *data_ptr++ = s_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689) *data_ptr++ = r_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691) s_value += s_stride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693) *d_ptr = data_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694) return QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697) return QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701) qla8044_minidump_process_rdmux2(struct scsi_qla_host *vha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702) struct qla8044_minidump_entry_hdr *entry_hdr, uint32_t **d_ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704) uint32_t sel_val1, sel_val2, t_sel_val, data, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705) uint32_t sel_addr1, sel_addr2, sel_val_mask, read_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706) struct qla8044_minidump_entry_rdmux2 *rdmux2_hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707) uint32_t *data_ptr = *d_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709) rdmux2_hdr = (struct qla8044_minidump_entry_rdmux2 *) entry_hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710) sel_val1 = rdmux2_hdr->select_value_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711) sel_val2 = rdmux2_hdr->select_value_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712) sel_addr1 = rdmux2_hdr->select_addr_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713) sel_addr2 = rdmux2_hdr->select_addr_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714) sel_val_mask = rdmux2_hdr->select_value_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715) read_addr = rdmux2_hdr->read_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717) for (i = 0; i < rdmux2_hdr->op_count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718) qla8044_wr_reg_indirect(vha, sel_addr1, sel_val1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2719) t_sel_val = sel_val1 & sel_val_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2720) *data_ptr++ = t_sel_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2722) qla8044_wr_reg_indirect(vha, sel_addr2, t_sel_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2723) qla8044_rd_reg_indirect(vha, read_addr, &data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2725) *data_ptr++ = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2727) qla8044_wr_reg_indirect(vha, sel_addr1, sel_val2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2728) t_sel_val = sel_val2 & sel_val_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2729) *data_ptr++ = t_sel_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2731) qla8044_wr_reg_indirect(vha, sel_addr2, t_sel_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2732) qla8044_rd_reg_indirect(vha, read_addr, &data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2734) *data_ptr++ = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2736) sel_val1 += rdmux2_hdr->select_value_stride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2737) sel_val2 += rdmux2_hdr->select_value_stride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2738) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2740) *d_ptr = data_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2741) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2743) static uint32_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2744) qla8044_minidump_process_pollrdmwr(struct scsi_qla_host *vha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2745) struct qla8044_minidump_entry_hdr *entry_hdr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2746) uint32_t **d_ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2747) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2748) uint32_t poll_wait, poll_mask, r_value, data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2749) uint32_t addr_1, addr_2, value_1, value_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2750) struct qla8044_minidump_entry_pollrdmwr *poll_hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2751) uint32_t *data_ptr = *d_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2753) poll_hdr = (struct qla8044_minidump_entry_pollrdmwr *) entry_hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2754) addr_1 = poll_hdr->addr_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2755) addr_2 = poll_hdr->addr_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2756) value_1 = poll_hdr->value_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2757) value_2 = poll_hdr->value_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2758) poll_mask = poll_hdr->poll_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2760) qla8044_wr_reg_indirect(vha, addr_1, value_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2762) poll_wait = poll_hdr->poll_wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2763) while (1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2764) qla8044_rd_reg_indirect(vha, addr_1, &r_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2766) if ((r_value & poll_mask) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2767) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2768) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2769) usleep_range(1000, 1100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2770) if (--poll_wait == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2771) ql_log(ql_log_fatal, vha, 0xb0ff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2772) "%s: TIMEOUT\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2773) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2774) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2775) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2776) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2778) qla8044_rd_reg_indirect(vha, addr_2, &data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2779) data &= poll_hdr->modify_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2780) qla8044_wr_reg_indirect(vha, addr_2, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2781) qla8044_wr_reg_indirect(vha, addr_1, value_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2783) poll_wait = poll_hdr->poll_wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2784) while (1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2785) qla8044_rd_reg_indirect(vha, addr_1, &r_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2787) if ((r_value & poll_mask) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2788) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2789) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2790) usleep_range(1000, 1100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2791) if (--poll_wait == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2792) ql_log(ql_log_fatal, vha, 0xb100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2793) "%s: TIMEOUT2\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2794) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2795) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2796) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2797) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2799) *data_ptr++ = addr_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2800) *data_ptr++ = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2802) *d_ptr = data_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2804) return QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2806) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2807) return QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2808) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2810) #define ISP8044_PEX_DMA_ENGINE_INDEX 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2811) #define ISP8044_PEX_DMA_BASE_ADDRESS 0x77320000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2812) #define ISP8044_PEX_DMA_NUM_OFFSET 0x10000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2813) #define ISP8044_PEX_DMA_CMD_ADDR_LOW 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2814) #define ISP8044_PEX_DMA_CMD_ADDR_HIGH 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2815) #define ISP8044_PEX_DMA_CMD_STS_AND_CNTRL 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2817) #define ISP8044_PEX_DMA_READ_SIZE (16 * 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2818) #define ISP8044_PEX_DMA_MAX_WAIT (100 * 100) /* Max wait of 100 msecs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2820) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2821) qla8044_check_dma_engine_state(struct scsi_qla_host *vha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2822) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2823) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2824) int rval = QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2825) uint32_t dma_eng_num = 0, cmd_sts_and_cntrl = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2826) uint64_t dma_base_addr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2827) struct qla8044_minidump_template_hdr *tmplt_hdr = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2829) tmplt_hdr = ha->md_tmplt_hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2830) dma_eng_num =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2831) tmplt_hdr->saved_state_array[ISP8044_PEX_DMA_ENGINE_INDEX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2832) dma_base_addr = ISP8044_PEX_DMA_BASE_ADDRESS +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2833) (dma_eng_num * ISP8044_PEX_DMA_NUM_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2835) /* Read the pex-dma's command-status-and-control register. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2836) rval = qla8044_rd_reg_indirect(vha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2837) (dma_base_addr + ISP8044_PEX_DMA_CMD_STS_AND_CNTRL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2838) &cmd_sts_and_cntrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2839) if (rval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2840) return QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2842) /* Check if requested pex-dma engine is available. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2843) if (cmd_sts_and_cntrl & BIT_31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2844) return QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2846) return QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2847) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2849) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2850) qla8044_start_pex_dma(struct scsi_qla_host *vha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2851) struct qla8044_minidump_entry_rdmem_pex_dma *m_hdr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2852) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2853) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2854) int rval = QLA_SUCCESS, wait = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2855) uint32_t dma_eng_num = 0, cmd_sts_and_cntrl = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2856) uint64_t dma_base_addr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2857) struct qla8044_minidump_template_hdr *tmplt_hdr = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2859) tmplt_hdr = ha->md_tmplt_hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2860) dma_eng_num =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2861) tmplt_hdr->saved_state_array[ISP8044_PEX_DMA_ENGINE_INDEX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2862) dma_base_addr = ISP8044_PEX_DMA_BASE_ADDRESS +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2863) (dma_eng_num * ISP8044_PEX_DMA_NUM_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2865) rval = qla8044_wr_reg_indirect(vha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2866) dma_base_addr + ISP8044_PEX_DMA_CMD_ADDR_LOW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2867) m_hdr->desc_card_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2868) if (rval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2869) goto error_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2871) rval = qla8044_wr_reg_indirect(vha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2872) dma_base_addr + ISP8044_PEX_DMA_CMD_ADDR_HIGH, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2873) if (rval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2874) goto error_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2876) rval = qla8044_wr_reg_indirect(vha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2877) dma_base_addr + ISP8044_PEX_DMA_CMD_STS_AND_CNTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2878) m_hdr->start_dma_cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2879) if (rval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2880) goto error_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2882) /* Wait for dma operation to complete. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2883) for (wait = 0; wait < ISP8044_PEX_DMA_MAX_WAIT; wait++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2884) rval = qla8044_rd_reg_indirect(vha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2885) (dma_base_addr + ISP8044_PEX_DMA_CMD_STS_AND_CNTRL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2886) &cmd_sts_and_cntrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2887) if (rval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2888) goto error_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2890) if ((cmd_sts_and_cntrl & BIT_1) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2891) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2893) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2894) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2896) /* Wait a max of 100 ms, otherwise fallback to rdmem entry read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2897) if (wait >= ISP8044_PEX_DMA_MAX_WAIT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2898) rval = QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2899) goto error_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2900) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2902) error_exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2903) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2904) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2906) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2907) qla8044_minidump_pex_dma_read(struct scsi_qla_host *vha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2908) struct qla8044_minidump_entry_hdr *entry_hdr, uint32_t **d_ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2909) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2910) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2911) int rval = QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2912) struct qla8044_minidump_entry_rdmem_pex_dma *m_hdr = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2913) uint32_t chunk_size, read_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2914) uint8_t *data_ptr = (uint8_t *)*d_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2915) void *rdmem_buffer = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2916) dma_addr_t rdmem_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2917) struct qla8044_pex_dma_descriptor dma_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2919) rval = qla8044_check_dma_engine_state(vha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2920) if (rval != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2921) ql_dbg(ql_dbg_p3p, vha, 0xb147,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2922) "DMA engine not available. Fallback to rdmem-read.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2923) return QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2924) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2926) m_hdr = (void *)entry_hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2928) rdmem_buffer = dma_alloc_coherent(&ha->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2929) ISP8044_PEX_DMA_READ_SIZE, &rdmem_dma, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2930) if (!rdmem_buffer) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2931) ql_dbg(ql_dbg_p3p, vha, 0xb148,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2932) "Unable to allocate rdmem dma buffer\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2933) return QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2934) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2936) /* Prepare pex-dma descriptor to be written to MS memory. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2937) /* dma-desc-cmd layout:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2938) * 0-3: dma-desc-cmd 0-3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2939) * 4-7: pcid function number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2940) * 8-15: dma-desc-cmd 8-15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2941) * dma_bus_addr: dma buffer address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2942) * cmd.read_data_size: amount of data-chunk to be read.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2943) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2944) dma_desc.cmd.dma_desc_cmd = (m_hdr->dma_desc_cmd & 0xff0f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2945) dma_desc.cmd.dma_desc_cmd |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2946) ((PCI_FUNC(ha->pdev->devfn) & 0xf) << 0x4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2948) dma_desc.dma_bus_addr = rdmem_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2949) dma_desc.cmd.read_data_size = chunk_size = ISP8044_PEX_DMA_READ_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2950) read_size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2952) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2953) * Perform rdmem operation using pex-dma.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2954) * Prepare dma in chunks of ISP8044_PEX_DMA_READ_SIZE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2955) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2956) while (read_size < m_hdr->read_data_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2957) if (m_hdr->read_data_size - read_size <
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2958) ISP8044_PEX_DMA_READ_SIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2959) chunk_size = (m_hdr->read_data_size - read_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2960) dma_desc.cmd.read_data_size = chunk_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2961) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2963) dma_desc.src_addr = m_hdr->read_addr + read_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2965) /* Prepare: Write pex-dma descriptor to MS memory. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2966) rval = qla8044_ms_mem_write_128b(vha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2967) m_hdr->desc_card_addr, (uint32_t *)&dma_desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2968) (sizeof(struct qla8044_pex_dma_descriptor)/16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2969) if (rval) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2970) ql_log(ql_log_warn, vha, 0xb14a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2971) "%s: Error writing rdmem-dma-init to MS !!!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2972) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2973) goto error_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2974) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2975) ql_dbg(ql_dbg_p3p, vha, 0xb14b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2976) "%s: Dma-descriptor: Instruct for rdmem dma "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2977) "(chunk_size 0x%x).\n", __func__, chunk_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2979) /* Execute: Start pex-dma operation. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2980) rval = qla8044_start_pex_dma(vha, m_hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2981) if (rval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2982) goto error_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2984) memcpy(data_ptr, rdmem_buffer, chunk_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2985) data_ptr += chunk_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2986) read_size += chunk_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2987) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2989) *d_ptr = (uint32_t *)data_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2991) error_exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2992) if (rdmem_buffer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2993) dma_free_coherent(&ha->pdev->dev, ISP8044_PEX_DMA_READ_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2994) rdmem_buffer, rdmem_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2996) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2997) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2999) static uint32_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3000) qla8044_minidump_process_rddfe(struct scsi_qla_host *vha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3001) struct qla8044_minidump_entry_hdr *entry_hdr, uint32_t **d_ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3002) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3003) int loop_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3004) uint32_t addr1, addr2, value, data, temp, wrVal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3005) uint8_t stride, stride2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3006) uint16_t count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3007) uint32_t poll, mask, modify_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3008) uint32_t wait_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3009) uint32_t *data_ptr = *d_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3010) struct qla8044_minidump_entry_rddfe *rddfe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3012) rddfe = (struct qla8044_minidump_entry_rddfe *) entry_hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3014) addr1 = rddfe->addr_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3015) value = rddfe->value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3016) stride = rddfe->stride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3017) stride2 = rddfe->stride2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3018) count = rddfe->count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3020) poll = rddfe->poll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3021) mask = rddfe->mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3022) modify_mask = rddfe->modify_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3024) addr2 = addr1 + stride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3026) for (loop_cnt = 0x0; loop_cnt < count; loop_cnt++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3027) qla8044_wr_reg_indirect(vha, addr1, (0x40000000 | value));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3029) wait_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3030) while (wait_count < poll) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3031) qla8044_rd_reg_indirect(vha, addr1, &temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3032) if ((temp & mask) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3033) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3034) wait_count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3035) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3037) if (wait_count == poll) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3038) ql_log(ql_log_warn, vha, 0xb153,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3039) "%s: TIMEOUT\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3040) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3041) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3042) qla8044_rd_reg_indirect(vha, addr2, &temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3043) temp = temp & modify_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3044) temp = (temp | ((loop_cnt << 16) | loop_cnt));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3045) wrVal = ((temp << 16) | temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3047) qla8044_wr_reg_indirect(vha, addr2, wrVal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3048) qla8044_wr_reg_indirect(vha, addr1, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3050) wait_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3051) while (wait_count < poll) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3052) qla8044_rd_reg_indirect(vha, addr1, &temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3053) if ((temp & mask) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3054) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3055) wait_count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3056) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3057) if (wait_count == poll) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3058) ql_log(ql_log_warn, vha, 0xb154,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3059) "%s: TIMEOUT\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3060) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3061) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3063) qla8044_wr_reg_indirect(vha, addr1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3064) ((0x40000000 | value) + stride2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3065) wait_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3066) while (wait_count < poll) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3067) qla8044_rd_reg_indirect(vha, addr1, &temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3068) if ((temp & mask) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3069) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3070) wait_count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3071) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3073) if (wait_count == poll) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3074) ql_log(ql_log_warn, vha, 0xb155,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3075) "%s: TIMEOUT\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3076) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3077) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3079) qla8044_rd_reg_indirect(vha, addr2, &data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3081) *data_ptr++ = wrVal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3082) *data_ptr++ = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3083) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3085) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3087) *d_ptr = data_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3088) return QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3090) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3091) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3093) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3095) static uint32_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3096) qla8044_minidump_process_rdmdio(struct scsi_qla_host *vha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3097) struct qla8044_minidump_entry_hdr *entry_hdr, uint32_t **d_ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3098) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3099) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3100) uint32_t addr1, addr2, value1, value2, data, selVal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3101) uint8_t stride1, stride2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3102) uint32_t addr3, addr4, addr5, addr6, addr7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3103) uint16_t count, loop_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3104) uint32_t mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3105) uint32_t *data_ptr = *d_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3107) struct qla8044_minidump_entry_rdmdio *rdmdio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3109) rdmdio = (struct qla8044_minidump_entry_rdmdio *) entry_hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3111) addr1 = rdmdio->addr_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3112) addr2 = rdmdio->addr_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3113) value1 = rdmdio->value_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3114) stride1 = rdmdio->stride_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3115) stride2 = rdmdio->stride_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3116) count = rdmdio->count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3118) mask = rdmdio->mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3119) value2 = rdmdio->value_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3121) addr3 = addr1 + stride1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3123) for (loop_cnt = 0; loop_cnt < count; loop_cnt++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3124) ret = qla8044_poll_wait_ipmdio_bus_idle(vha, addr1, addr2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3125) addr3, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3126) if (ret == -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3127) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3129) addr4 = addr2 - stride1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3130) ret = qla8044_ipmdio_wr_reg(vha, addr1, addr3, mask, addr4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3131) value2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3132) if (ret == -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3133) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3135) addr5 = addr2 - (2 * stride1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3136) ret = qla8044_ipmdio_wr_reg(vha, addr1, addr3, mask, addr5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3137) value1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3138) if (ret == -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3139) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3141) addr6 = addr2 - (3 * stride1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3142) ret = qla8044_ipmdio_wr_reg(vha, addr1, addr3, mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3143) addr6, 0x2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3144) if (ret == -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3145) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3147) ret = qla8044_poll_wait_ipmdio_bus_idle(vha, addr1, addr2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3148) addr3, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3149) if (ret == -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3150) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3152) addr7 = addr2 - (4 * stride1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3153) data = qla8044_ipmdio_rd_reg(vha, addr1, addr3, mask, addr7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3154) if (data == -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3155) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3157) selVal = (value2 << 18) | (value1 << 2) | 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3159) stride2 = rdmdio->stride_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3160) *data_ptr++ = selVal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3161) *data_ptr++ = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3163) value1 = value1 + stride2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3164) *d_ptr = data_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3167) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3169) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3170) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3173) static uint32_t qla8044_minidump_process_pollwr(struct scsi_qla_host *vha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3174) struct qla8044_minidump_entry_hdr *entry_hdr, uint32_t **d_ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3175) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3176) uint32_t addr1, addr2, value1, value2, poll, r_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3177) uint32_t wait_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3178) struct qla8044_minidump_entry_pollwr *pollwr_hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3180) pollwr_hdr = (struct qla8044_minidump_entry_pollwr *)entry_hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3181) addr1 = pollwr_hdr->addr_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3182) addr2 = pollwr_hdr->addr_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3183) value1 = pollwr_hdr->value_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3184) value2 = pollwr_hdr->value_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3186) poll = pollwr_hdr->poll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3188) while (wait_count < poll) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3189) qla8044_rd_reg_indirect(vha, addr1, &r_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3191) if ((r_value & poll) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3192) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3193) wait_count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3196) if (wait_count == poll) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3197) ql_log(ql_log_warn, vha, 0xb156, "%s: TIMEOUT\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3198) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3201) qla8044_wr_reg_indirect(vha, addr2, value2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3202) qla8044_wr_reg_indirect(vha, addr1, value1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3204) wait_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3205) while (wait_count < poll) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3206) qla8044_rd_reg_indirect(vha, addr1, &r_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3208) if ((r_value & poll) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3209) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3210) wait_count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3213) return QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3215) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3216) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3219) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3220) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3221) * qla8044_collect_md_data - Retrieve firmware minidump data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3222) * @ha: pointer to adapter structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3223) **/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3224) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3225) qla8044_collect_md_data(struct scsi_qla_host *vha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3226) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3227) int num_entry_hdr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3228) struct qla8044_minidump_entry_hdr *entry_hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3229) struct qla8044_minidump_template_hdr *tmplt_hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3230) uint32_t *data_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3231) uint32_t data_collected = 0, f_capture_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3232) int i, rval = QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3233) uint64_t now;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3234) uint32_t timestamp, idc_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3235) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3237) if (!ha->md_dump) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3238) ql_log(ql_log_info, vha, 0xb101,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3239) "%s(%ld) No buffer to dump\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3240) __func__, vha->host_no);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3241) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3244) if (ha->fw_dumped) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3245) ql_log(ql_log_warn, vha, 0xb10d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3246) "Firmware has been previously dumped (%p) "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3247) "-- ignoring request.\n", ha->fw_dump);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3248) goto md_failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3251) ha->fw_dumped = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3253) if (!ha->md_tmplt_hdr || !ha->md_dump) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3254) ql_log(ql_log_warn, vha, 0xb10e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3255) "Memory not allocated for minidump capture\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3256) goto md_failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3259) qla8044_idc_lock(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3260) idc_control = qla8044_rd_reg(ha, QLA8044_IDC_DRV_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3261) if (idc_control & GRACEFUL_RESET_BIT1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3262) ql_log(ql_log_warn, vha, 0xb112,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3263) "Forced reset from application, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3264) "ignore minidump capture\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3265) qla8044_wr_reg(ha, QLA8044_IDC_DRV_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3266) (idc_control & ~GRACEFUL_RESET_BIT1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3267) qla8044_idc_unlock(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3269) goto md_failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3271) qla8044_idc_unlock(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3273) if (qla82xx_validate_template_chksum(vha)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3274) ql_log(ql_log_info, vha, 0xb109,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3275) "Template checksum validation error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3276) goto md_failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3279) tmplt_hdr = (struct qla8044_minidump_template_hdr *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3280) ha->md_tmplt_hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3281) data_ptr = (uint32_t *)((uint8_t *)ha->md_dump);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3282) num_entry_hdr = tmplt_hdr->num_of_entries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3284) ql_dbg(ql_dbg_p3p, vha, 0xb11a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3285) "Capture Mask obtained: 0x%x\n", tmplt_hdr->capture_debug_level);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3287) f_capture_mask = tmplt_hdr->capture_debug_level & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3289) /* Validate whether required debug level is set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3290) if ((f_capture_mask & 0x3) != 0x3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3291) ql_log(ql_log_warn, vha, 0xb10f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3292) "Minimum required capture mask[0x%x] level not set\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3293) f_capture_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3296) tmplt_hdr->driver_capture_mask = ql2xmdcapmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3297) ql_log(ql_log_info, vha, 0xb102,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3298) "[%s]: starting data ptr: %p\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3299) __func__, data_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3300) ql_log(ql_log_info, vha, 0xb10b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3301) "[%s]: no of entry headers in Template: 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3302) __func__, num_entry_hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3303) ql_log(ql_log_info, vha, 0xb10c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3304) "[%s]: Total_data_size 0x%x, %d obtained\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3305) __func__, ha->md_dump_size, ha->md_dump_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3307) /* Update current timestamp before taking dump */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3308) now = get_jiffies_64();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3309) timestamp = (u32)(jiffies_to_msecs(now) / 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3310) tmplt_hdr->driver_timestamp = timestamp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3312) entry_hdr = (struct qla8044_minidump_entry_hdr *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3313) (((uint8_t *)ha->md_tmplt_hdr) + tmplt_hdr->first_entry_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3314) tmplt_hdr->saved_state_array[QLA8044_SS_OCM_WNDREG_INDEX] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3315) tmplt_hdr->ocm_window_reg[ha->portnum];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3317) /* Walk through the entry headers - validate/perform required action */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3318) for (i = 0; i < num_entry_hdr; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3319) if (data_collected > ha->md_dump_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3320) ql_log(ql_log_info, vha, 0xb103,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3321) "Data collected: [0x%x], "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3322) "Total Dump size: [0x%x]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3323) data_collected, ha->md_dump_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3324) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3327) if (!(entry_hdr->d_ctrl.entry_capture_mask &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3328) ql2xmdcapmask)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3329) entry_hdr->d_ctrl.driver_flags |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3330) QLA82XX_DBG_SKIPPED_FLAG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3331) goto skip_nxt_entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3334) ql_dbg(ql_dbg_p3p, vha, 0xb104,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3335) "Data collected: [0x%x], Dump size left:[0x%x]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3336) data_collected,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3337) (ha->md_dump_size - data_collected));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3339) /* Decode the entry type and take required action to capture
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3340) * debug data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3341) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3342) switch (entry_hdr->entry_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3343) case QLA82XX_RDEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3344) qla8044_mark_entry_skipped(vha, entry_hdr, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3345) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3346) case QLA82XX_CNTRL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3347) rval = qla8044_minidump_process_control(vha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3348) entry_hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3349) if (rval != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3350) qla8044_mark_entry_skipped(vha, entry_hdr, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3351) goto md_failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3353) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3354) case QLA82XX_RDCRB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3355) qla8044_minidump_process_rdcrb(vha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3356) entry_hdr, &data_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3357) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3358) case QLA82XX_RDMEM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3359) rval = qla8044_minidump_pex_dma_read(vha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3360) entry_hdr, &data_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3361) if (rval != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3362) rval = qla8044_minidump_process_rdmem(vha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3363) entry_hdr, &data_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3364) if (rval != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3365) qla8044_mark_entry_skipped(vha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3366) entry_hdr, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3367) goto md_failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3369) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3370) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3371) case QLA82XX_BOARD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3372) case QLA82XX_RDROM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3373) rval = qla8044_minidump_process_rdrom(vha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3374) entry_hdr, &data_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3375) if (rval != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3376) qla8044_mark_entry_skipped(vha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3377) entry_hdr, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3379) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3380) case QLA82XX_L2DTG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3381) case QLA82XX_L2ITG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3382) case QLA82XX_L2DAT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3383) case QLA82XX_L2INS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3384) rval = qla8044_minidump_process_l2tag(vha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3385) entry_hdr, &data_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3386) if (rval != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3387) qla8044_mark_entry_skipped(vha, entry_hdr, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3388) goto md_failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3389) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3390) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3391) case QLA8044_L1DTG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3392) case QLA8044_L1ITG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3393) case QLA82XX_L1DAT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3394) case QLA82XX_L1INS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3395) qla8044_minidump_process_l1cache(vha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3396) entry_hdr, &data_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3397) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3398) case QLA82XX_RDOCM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3399) qla8044_minidump_process_rdocm(vha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3400) entry_hdr, &data_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3401) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3402) case QLA82XX_RDMUX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3403) qla8044_minidump_process_rdmux(vha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3404) entry_hdr, &data_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3405) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3406) case QLA82XX_QUEUE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3407) qla8044_minidump_process_queue(vha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3408) entry_hdr, &data_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3409) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3410) case QLA8044_POLLRD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3411) rval = qla8044_minidump_process_pollrd(vha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3412) entry_hdr, &data_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3413) if (rval != QLA_SUCCESS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3414) qla8044_mark_entry_skipped(vha, entry_hdr, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3415) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3416) case QLA8044_RDMUX2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3417) qla8044_minidump_process_rdmux2(vha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3418) entry_hdr, &data_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3419) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3420) case QLA8044_POLLRDMWR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3421) rval = qla8044_minidump_process_pollrdmwr(vha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3422) entry_hdr, &data_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3423) if (rval != QLA_SUCCESS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3424) qla8044_mark_entry_skipped(vha, entry_hdr, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3425) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3426) case QLA8044_RDDFE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3427) rval = qla8044_minidump_process_rddfe(vha, entry_hdr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3428) &data_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3429) if (rval != QLA_SUCCESS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3430) qla8044_mark_entry_skipped(vha, entry_hdr, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3431) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3432) case QLA8044_RDMDIO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3433) rval = qla8044_minidump_process_rdmdio(vha, entry_hdr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3434) &data_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3435) if (rval != QLA_SUCCESS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3436) qla8044_mark_entry_skipped(vha, entry_hdr, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3437) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3438) case QLA8044_POLLWR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3439) rval = qla8044_minidump_process_pollwr(vha, entry_hdr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3440) &data_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3441) if (rval != QLA_SUCCESS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3442) qla8044_mark_entry_skipped(vha, entry_hdr, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3443) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3444) case QLA82XX_RDNOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3445) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3446) qla8044_mark_entry_skipped(vha, entry_hdr, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3447) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3450) data_collected = (uint8_t *)data_ptr -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3451) (uint8_t *)((uint8_t *)ha->md_dump);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3452) skip_nxt_entry:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3453) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3454) * next entry in the template
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3455) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3456) entry_hdr = (struct qla8044_minidump_entry_hdr *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3457) (((uint8_t *)entry_hdr) + entry_hdr->entry_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3458) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3460) if (data_collected != ha->md_dump_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3461) ql_log(ql_log_info, vha, 0xb105,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3462) "Dump data mismatch: Data collected: "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3463) "[0x%x], total_data_size:[0x%x]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3464) data_collected, ha->md_dump_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3465) rval = QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3466) goto md_failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3469) ql_log(ql_log_info, vha, 0xb110,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3470) "Firmware dump saved to temp buffer (%ld/%p %ld/%p).\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3471) vha->host_no, ha->md_tmplt_hdr, vha->host_no, ha->md_dump);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3472) ha->fw_dumped = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3473) qla2x00_post_uevent_work(vha, QLA_UEVENT_CODE_FW_DUMP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3476) ql_log(ql_log_info, vha, 0xb106,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3477) "Leaving fn: %s Last entry: 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3478) __func__, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3479) md_failed:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3480) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3481) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3483) void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3484) qla8044_get_minidump(struct scsi_qla_host *vha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3485) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3486) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3488) if (!qla8044_collect_md_data(vha)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3489) ha->fw_dumped = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3490) ha->prev_minidump_failed = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3491) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3492) ql_log(ql_log_fatal, vha, 0xb0db,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3493) "%s: Unable to collect minidump\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3494) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3495) ha->prev_minidump_failed = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3496) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3497) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3499) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3500) qla8044_poll_flash_status_reg(struct scsi_qla_host *vha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3501) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3502) uint32_t flash_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3503) int retries = QLA8044_FLASH_READ_RETRY_COUNT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3504) int ret_val = QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3506) while (retries--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3507) ret_val = qla8044_rd_reg_indirect(vha, QLA8044_FLASH_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3508) &flash_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3509) if (ret_val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3510) ql_log(ql_log_warn, vha, 0xb13c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3511) "%s: Failed to read FLASH_STATUS reg.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3512) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3513) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3514) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3515) if ((flash_status & QLA8044_FLASH_STATUS_READY) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3516) QLA8044_FLASH_STATUS_READY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3517) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3518) msleep(QLA8044_FLASH_STATUS_REG_POLL_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3519) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3521) if (!retries)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3522) ret_val = QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3524) return ret_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3525) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3527) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3528) qla8044_write_flash_status_reg(struct scsi_qla_host *vha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3529) uint32_t data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3530) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3531) int ret_val = QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3532) uint32_t cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3534) cmd = vha->hw->fdt_wrt_sts_reg_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3536) ret_val = qla8044_wr_reg_indirect(vha, QLA8044_FLASH_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3537) QLA8044_FLASH_STATUS_WRITE_DEF_SIG | cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3538) if (ret_val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3539) ql_log(ql_log_warn, vha, 0xb125,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3540) "%s: Failed to write to FLASH_ADDR.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3541) goto exit_func;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3542) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3544) ret_val = qla8044_wr_reg_indirect(vha, QLA8044_FLASH_WRDATA, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3545) if (ret_val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3546) ql_log(ql_log_warn, vha, 0xb126,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3547) "%s: Failed to write to FLASH_WRDATA.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3548) goto exit_func;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3549) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3551) ret_val = qla8044_wr_reg_indirect(vha, QLA8044_FLASH_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3552) QLA8044_FLASH_SECOND_ERASE_MS_VAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3553) if (ret_val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3554) ql_log(ql_log_warn, vha, 0xb127,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3555) "%s: Failed to write to FLASH_CONTROL.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3556) goto exit_func;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3557) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3559) ret_val = qla8044_poll_flash_status_reg(vha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3560) if (ret_val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3561) ql_log(ql_log_warn, vha, 0xb128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3562) "%s: Error polling flash status reg.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3564) exit_func:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3565) return ret_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3566) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3568) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3569) * This function assumes that the flash lock is held.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3570) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3571) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3572) qla8044_unprotect_flash(scsi_qla_host_t *vha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3573) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3574) int ret_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3575) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3577) ret_val = qla8044_write_flash_status_reg(vha, ha->fdt_wrt_enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3578) if (ret_val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3579) ql_log(ql_log_warn, vha, 0xb139,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3580) "%s: Write flash status failed.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3582) return ret_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3583) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3585) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3586) * This function assumes that the flash lock is held.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3587) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3588) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3589) qla8044_protect_flash(scsi_qla_host_t *vha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3590) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3591) int ret_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3592) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3594) ret_val = qla8044_write_flash_status_reg(vha, ha->fdt_wrt_disable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3595) if (ret_val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3596) ql_log(ql_log_warn, vha, 0xb13b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3597) "%s: Write flash status failed.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3599) return ret_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3600) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3603) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3604) qla8044_erase_flash_sector(struct scsi_qla_host *vha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3605) uint32_t sector_start_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3606) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3607) uint32_t reversed_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3608) int ret_val = QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3610) ret_val = qla8044_poll_flash_status_reg(vha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3611) if (ret_val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3612) ql_log(ql_log_warn, vha, 0xb12e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3613) "%s: Poll flash status after erase failed..\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3614) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3616) reversed_addr = (((sector_start_addr & 0xFF) << 16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3617) (sector_start_addr & 0xFF00) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3618) ((sector_start_addr & 0xFF0000) >> 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3620) ret_val = qla8044_wr_reg_indirect(vha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3621) QLA8044_FLASH_WRDATA, reversed_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3622) if (ret_val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3623) ql_log(ql_log_warn, vha, 0xb12f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3624) "%s: Failed to write to FLASH_WRDATA.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3625) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3626) ret_val = qla8044_wr_reg_indirect(vha, QLA8044_FLASH_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3627) QLA8044_FLASH_ERASE_SIG | vha->hw->fdt_erase_cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3628) if (ret_val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3629) ql_log(ql_log_warn, vha, 0xb130,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3630) "%s: Failed to write to FLASH_ADDR.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3631) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3632) ret_val = qla8044_wr_reg_indirect(vha, QLA8044_FLASH_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3633) QLA8044_FLASH_LAST_ERASE_MS_VAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3634) if (ret_val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3635) ql_log(ql_log_warn, vha, 0xb131,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3636) "%s: Failed write to FLASH_CONTROL.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3637) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3638) ret_val = qla8044_poll_flash_status_reg(vha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3639) if (ret_val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3640) ql_log(ql_log_warn, vha, 0xb132,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3641) "%s: Poll flash status failed.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3642) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3645) return ret_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3646) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3648) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3649) * qla8044_flash_write_u32 - Write data to flash
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3650) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3651) * @ha : Pointer to adapter structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3652) * addr : Flash address to write to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3653) * p_data : Data to be written
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3654) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3655) * Return Value - QLA_SUCCESS/QLA_FUNCTION_FAILED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3656) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3657) * NOTE: Lock should be held on entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3658) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3659) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3660) qla8044_flash_write_u32(struct scsi_qla_host *vha, uint32_t addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3661) uint32_t *p_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3662) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3663) int ret_val = QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3665) ret_val = qla8044_wr_reg_indirect(vha, QLA8044_FLASH_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3666) 0x00800000 | (addr >> 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3667) if (ret_val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3668) ql_log(ql_log_warn, vha, 0xb134,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3669) "%s: Failed write to FLASH_ADDR.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3670) goto exit_func;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3671) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3672) ret_val = qla8044_wr_reg_indirect(vha, QLA8044_FLASH_WRDATA, *p_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3673) if (ret_val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3674) ql_log(ql_log_warn, vha, 0xb135,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3675) "%s: Failed write to FLASH_WRDATA.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3676) goto exit_func;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3677) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3678) ret_val = qla8044_wr_reg_indirect(vha, QLA8044_FLASH_CONTROL, 0x3D);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3679) if (ret_val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3680) ql_log(ql_log_warn, vha, 0xb136,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3681) "%s: Failed write to FLASH_CONTROL.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3682) goto exit_func;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3683) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3684) ret_val = qla8044_poll_flash_status_reg(vha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3685) if (ret_val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3686) ql_log(ql_log_warn, vha, 0xb137,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3687) "%s: Poll flash status failed.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3688) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3690) exit_func:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3691) return ret_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3692) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3694) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3695) qla8044_write_flash_buffer_mode(scsi_qla_host_t *vha, uint32_t *dwptr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3696) uint32_t faddr, uint32_t dwords)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3697) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3698) int ret = QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3699) uint32_t spi_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3701) if (dwords < QLA8044_MIN_OPTROM_BURST_DWORDS ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3702) dwords > QLA8044_MAX_OPTROM_BURST_DWORDS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3703) ql_dbg(ql_dbg_user, vha, 0xb123,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3704) "Got unsupported dwords = 0x%x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3705) dwords);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3706) return QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3707) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3709) qla8044_rd_reg_indirect(vha, QLA8044_FLASH_SPI_CONTROL, &spi_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3710) qla8044_wr_reg_indirect(vha, QLA8044_FLASH_SPI_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3711) spi_val | QLA8044_FLASH_SPI_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3712) qla8044_wr_reg_indirect(vha, QLA8044_FLASH_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3713) QLA8044_FLASH_FIRST_TEMP_VAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3715) /* First DWORD write to FLASH_WRDATA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3716) ret = qla8044_wr_reg_indirect(vha, QLA8044_FLASH_WRDATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3717) *dwptr++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3718) qla8044_wr_reg_indirect(vha, QLA8044_FLASH_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3719) QLA8044_FLASH_FIRST_MS_PATTERN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3721) ret = qla8044_poll_flash_status_reg(vha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3722) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3723) ql_log(ql_log_warn, vha, 0xb124,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3724) "%s: Failed.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3725) goto exit_func;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3726) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3728) dwords--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3730) qla8044_wr_reg_indirect(vha, QLA8044_FLASH_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3731) QLA8044_FLASH_SECOND_TEMP_VAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3734) /* Second to N-1 DWORDS writes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3735) while (dwords != 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3736) qla8044_wr_reg_indirect(vha, QLA8044_FLASH_WRDATA, *dwptr++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3737) qla8044_wr_reg_indirect(vha, QLA8044_FLASH_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3738) QLA8044_FLASH_SECOND_MS_PATTERN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3739) ret = qla8044_poll_flash_status_reg(vha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3740) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3741) ql_log(ql_log_warn, vha, 0xb129,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3742) "%s: Failed.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3743) goto exit_func;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3744) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3745) dwords--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3746) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3748) qla8044_wr_reg_indirect(vha, QLA8044_FLASH_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3749) QLA8044_FLASH_FIRST_TEMP_VAL | (faddr >> 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3751) /* Last DWORD write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3752) qla8044_wr_reg_indirect(vha, QLA8044_FLASH_WRDATA, *dwptr++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3753) qla8044_wr_reg_indirect(vha, QLA8044_FLASH_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3754) QLA8044_FLASH_LAST_MS_PATTERN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3755) ret = qla8044_poll_flash_status_reg(vha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3756) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3757) ql_log(ql_log_warn, vha, 0xb12a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3758) "%s: Failed.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3759) goto exit_func;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3760) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3761) qla8044_rd_reg_indirect(vha, QLA8044_FLASH_SPI_STATUS, &spi_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3763) if ((spi_val & QLA8044_FLASH_SPI_CTL) == QLA8044_FLASH_SPI_CTL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3764) ql_log(ql_log_warn, vha, 0xb12b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3765) "%s: Failed.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3766) spi_val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3767) /* Operation failed, clear error bit. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3768) qla8044_rd_reg_indirect(vha, QLA8044_FLASH_SPI_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3769) &spi_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3770) qla8044_wr_reg_indirect(vha, QLA8044_FLASH_SPI_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3771) spi_val | QLA8044_FLASH_SPI_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3772) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3773) exit_func:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3774) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3775) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3777) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3778) qla8044_write_flash_dword_mode(scsi_qla_host_t *vha, uint32_t *dwptr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3779) uint32_t faddr, uint32_t dwords)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3780) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3781) int ret = QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3782) uint32_t liter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3784) for (liter = 0; liter < dwords; liter++, faddr += 4, dwptr++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3785) ret = qla8044_flash_write_u32(vha, faddr, dwptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3786) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3787) ql_dbg(ql_dbg_p3p, vha, 0xb141,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3788) "%s: flash address=%x data=%x.\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3789) faddr, *dwptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3790) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3791) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3792) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3794) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3795) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3797) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3798) qla8044_write_optrom_data(struct scsi_qla_host *vha, void *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3799) uint32_t offset, uint32_t length)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3800) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3801) int rval = QLA_FUNCTION_FAILED, i, burst_iter_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3802) int dword_count, erase_sec_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3803) uint32_t erase_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3804) uint8_t *p_cache, *p_src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3806) erase_offset = offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3808) p_cache = kcalloc(length, sizeof(uint8_t), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3809) if (!p_cache)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3810) return QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3812) memcpy(p_cache, buf, length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3813) p_src = p_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3814) dword_count = length / sizeof(uint32_t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3815) /* Since the offset and legth are sector aligned, it will be always
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3816) * multiple of burst_iter_count (64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3817) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3818) burst_iter_count = dword_count / QLA8044_MAX_OPTROM_BURST_DWORDS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3819) erase_sec_count = length / QLA8044_SECTOR_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3821) /* Suspend HBA. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3822) scsi_block_requests(vha->host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3823) /* Lock and enable write for whole operation. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3824) qla8044_flash_lock(vha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3825) qla8044_unprotect_flash(vha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3827) /* Erasing the sectors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3828) for (i = 0; i < erase_sec_count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3829) rval = qla8044_erase_flash_sector(vha, erase_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3830) ql_dbg(ql_dbg_user, vha, 0xb138,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3831) "Done erase of sector=0x%x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3832) erase_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3833) if (rval) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3834) ql_log(ql_log_warn, vha, 0xb121,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3835) "Failed to erase the sector having address: "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3836) "0x%x.\n", erase_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3837) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3838) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3839) erase_offset += QLA8044_SECTOR_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3840) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3841) ql_dbg(ql_dbg_user, vha, 0xb13f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3842) "Got write for addr = 0x%x length=0x%x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3843) offset, length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3845) for (i = 0; i < burst_iter_count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3847) /* Go with write. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3848) rval = qla8044_write_flash_buffer_mode(vha, (uint32_t *)p_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3849) offset, QLA8044_MAX_OPTROM_BURST_DWORDS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3850) if (rval) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3851) /* Buffer Mode failed skip to dword mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3852) ql_log(ql_log_warn, vha, 0xb122,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3853) "Failed to write flash in buffer mode, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3854) "Reverting to slow-write.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3855) rval = qla8044_write_flash_dword_mode(vha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3856) (uint32_t *)p_src, offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3857) QLA8044_MAX_OPTROM_BURST_DWORDS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3858) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3859) p_src += sizeof(uint32_t) * QLA8044_MAX_OPTROM_BURST_DWORDS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3860) offset += sizeof(uint32_t) * QLA8044_MAX_OPTROM_BURST_DWORDS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3861) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3862) ql_dbg(ql_dbg_user, vha, 0xb133,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3863) "Done writing.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3865) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3866) qla8044_protect_flash(vha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3867) qla8044_flash_unlock(vha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3868) scsi_unblock_requests(vha->host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3869) kfree(p_cache);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3871) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3872) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3874) #define LEG_INT_PTR_B31 (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3875) #define LEG_INT_PTR_B30 (1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3876) #define PF_BITS_MASK (0xF << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3877) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3878) * qla8044_intr_handler() - Process interrupts for the ISP8044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3879) * @irq: interrupt number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3880) * @dev_id: SCSI driver HA context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3881) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3882) * Called by system whenever the host adapter generates an interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3883) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3884) * Returns handled flag.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3885) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3886) irqreturn_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3887) qla8044_intr_handler(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3888) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3889) scsi_qla_host_t *vha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3890) struct qla_hw_data *ha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3891) struct rsp_que *rsp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3892) struct device_reg_82xx __iomem *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3893) int status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3894) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3895) unsigned long iter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3896) uint32_t stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3897) uint16_t mb[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3898) uint32_t leg_int_ptr = 0, pf_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3900) rsp = (struct rsp_que *) dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3901) if (!rsp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3902) ql_log(ql_log_info, NULL, 0xb143,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3903) "%s(): NULL response queue pointer\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3904) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3905) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3906) ha = rsp->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3907) vha = pci_get_drvdata(ha->pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3909) if (unlikely(pci_channel_offline(ha->pdev)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3910) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3912) leg_int_ptr = qla8044_rd_reg(ha, LEG_INTR_PTR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3914) /* Legacy interrupt is valid if bit31 of leg_int_ptr is set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3915) if (!(leg_int_ptr & (LEG_INT_PTR_B31))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3916) ql_dbg(ql_dbg_p3p, vha, 0xb144,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3917) "%s: Legacy Interrupt Bit 31 not set, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3918) "spurious interrupt!\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3919) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3920) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3922) pf_bit = ha->portnum << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3923) /* Validate the PCIE function ID set in leg_int_ptr bits [19..16] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3924) if ((leg_int_ptr & (PF_BITS_MASK)) != pf_bit) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3925) ql_dbg(ql_dbg_p3p, vha, 0xb145,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3926) "%s: Incorrect function ID 0x%x in "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3927) "legacy interrupt register, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3928) "ha->pf_bit = 0x%x\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3929) (leg_int_ptr & (PF_BITS_MASK)), pf_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3930) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3931) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3933) /* To de-assert legacy interrupt, write 0 to Legacy Interrupt Trigger
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3934) * Control register and poll till Legacy Interrupt Pointer register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3935) * bit32 is 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3936) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3937) qla8044_wr_reg(ha, LEG_INTR_TRIG_OFFSET, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3938) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3939) leg_int_ptr = qla8044_rd_reg(ha, LEG_INTR_PTR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3940) if ((leg_int_ptr & (PF_BITS_MASK)) != pf_bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3941) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3942) } while (leg_int_ptr & (LEG_INT_PTR_B30));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3944) reg = &ha->iobase->isp82;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3945) spin_lock_irqsave(&ha->hardware_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3946) for (iter = 1; iter--; ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3948) if (rd_reg_dword(®->host_int)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3949) stat = rd_reg_dword(®->host_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3950) if ((stat & HSRX_RISC_INT) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3951) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3953) switch (stat & 0xff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3954) case 0x1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3955) case 0x2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3956) case 0x10:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3957) case 0x11:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3958) qla82xx_mbx_completion(vha, MSW(stat));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3959) status |= MBX_INTERRUPT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3960) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3961) case 0x12:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3962) mb[0] = MSW(stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3963) mb[1] = rd_reg_word(®->mailbox_out[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3964) mb[2] = rd_reg_word(®->mailbox_out[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3965) mb[3] = rd_reg_word(®->mailbox_out[3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3966) qla2x00_async_event(vha, rsp, mb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3967) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3968) case 0x13:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3969) qla24xx_process_response_queue(vha, rsp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3970) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3971) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3972) ql_dbg(ql_dbg_p3p, vha, 0xb146,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3973) "Unrecognized interrupt type "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3974) "(%d).\n", stat & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3975) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3976) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3977) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3978) wrt_reg_dword(®->host_int, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3979) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3981) qla2x00_handle_mbx_completion(ha, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3982) spin_unlock_irqrestore(&ha->hardware_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3984) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3985) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3987) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3988) qla8044_idc_dontreset(struct qla_hw_data *ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3989) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3990) uint32_t idc_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3992) idc_ctrl = qla8044_rd_reg(ha, QLA8044_IDC_DRV_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3993) return idc_ctrl & DONTRESET_BIT0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3994) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3996) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3997) qla8044_clear_rst_ready(scsi_qla_host_t *vha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3998) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3999) uint32_t drv_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4001) drv_state = qla8044_rd_direct(vha, QLA8044_CRB_DRV_STATE_INDEX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4003) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4004) * For ISP8044, drv_active register has 1 bit per function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4005) * shift 1 by func_num to set a bit for the function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4006) * For ISP82xx, drv_active has 4 bits per function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4007) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4008) drv_state &= ~(1 << vha->hw->portnum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4010) ql_dbg(ql_dbg_p3p, vha, 0xb13d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4011) "drv_state: 0x%08x\n", drv_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4012) qla8044_wr_direct(vha, QLA8044_CRB_DRV_STATE_INDEX, drv_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4013) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4015) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4016) qla8044_abort_isp(scsi_qla_host_t *vha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4017) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4018) int rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4019) uint32_t dev_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4020) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4022) qla8044_idc_lock(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4023) dev_state = qla8044_rd_direct(vha, QLA8044_CRB_DEV_STATE_INDEX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4025) if (ql2xdontresethba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4026) qla8044_set_idc_dontreset(vha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4028) /* If device_state is NEED_RESET, go ahead with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4029) * Reset,irrespective of ql2xdontresethba. This is to allow a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4030) * non-reset-owner to force a reset. Non-reset-owner sets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4031) * the IDC_CTRL BIT0 to prevent Reset-owner from doing a Reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4032) * and then forces a Reset by setting device_state to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4033) * NEED_RESET. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4034) if (dev_state == QLA8XXX_DEV_READY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4035) /* If IDC_CTRL DONTRESETHBA_BIT0 is set don't do reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4036) * recovery */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4037) if (qla8044_idc_dontreset(ha) == DONTRESET_BIT0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4038) ql_dbg(ql_dbg_p3p, vha, 0xb13e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4039) "Reset recovery disabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4040) rval = QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4041) goto exit_isp_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4042) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4044) ql_dbg(ql_dbg_p3p, vha, 0xb140,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4045) "HW State: NEED RESET\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4046) qla8044_wr_direct(vha, QLA8044_CRB_DEV_STATE_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4047) QLA8XXX_DEV_NEED_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4048) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4050) /* For ISP8044, Reset owner is NIC, iSCSI or FCOE based on priority
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4051) * and which drivers are present. Unlike ISP82XX, the function setting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4052) * NEED_RESET, may not be the Reset owner. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4053) qla83xx_reset_ownership(vha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4055) qla8044_idc_unlock(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4056) rval = qla8044_device_state_handler(vha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4057) qla8044_idc_lock(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4058) qla8044_clear_rst_ready(vha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4060) exit_isp_reset:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4061) qla8044_idc_unlock(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4062) if (rval == QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4063) ha->flags.isp82xx_fw_hung = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4064) ha->flags.nic_core_reset_hdlr_active = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4065) rval = qla82xx_restart_isp(vha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4066) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4068) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4069) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4071) void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4072) qla8044_fw_dump(scsi_qla_host_t *vha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4073) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4074) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4076) if (!ha->allow_cna_fw_dump)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4077) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4079) scsi_block_requests(vha->host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4080) ha->flags.isp82xx_no_md_cap = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4081) qla8044_idc_lock(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4082) qla82xx_set_reset_owner(vha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4083) qla8044_idc_unlock(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4084) qla2x00_wait_for_chip_reset(vha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4085) scsi_unblock_requests(vha->host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4086) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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