^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * QLogic Fibre Channel HBA Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (c) 2003-2014 QLogic Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include "qla_def.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/io-64-nonatomic-lo-hi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/ratelimit.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/vmalloc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <scsi/scsi_tcq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define MASK(n) ((1ULL<<(n))-1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) ((addr >> 25) & 0x3ff))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) ((addr >> 25) & 0x3ff))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define MS_WIN(addr) (addr & 0x0ffc0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define QLA82XX_PCI_MN_2M (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define QLA82XX_PCI_MS_2M (0x80000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define QLA82XX_PCI_OCM0_2M (0xc0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define VALID_OCM_ADDR(addr) (((addr) & 0x3f800) != 0x3f800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define GET_MEM_OFFS_2M(addr) (addr & MASK(18))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define BLOCK_PROTECT_BITS 0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /* CRB window related */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define CRB_BLK(off) ((off >> 20) & 0x3f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define CRB_SUBBLK(off) ((off >> 16) & 0xf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define CRB_WINDOW_2M (0x130060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define QLA82XX_PCI_CAMQM_2M_END (0x04800800UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define CRB_HI(off) ((qla82xx_crb_hub_agt[CRB_BLK(off)] << 20) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) ((off) & 0xf0000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define QLA82XX_PCI_CAMQM_2M_BASE (0x000ff800UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define CRB_INDIRECT_2M (0x1e0000UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define MAX_CRB_XFORM 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) static unsigned long crb_addr_xform[MAX_CRB_XFORM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) static int qla82xx_crb_table_initialized;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define qla82xx_crb_addr_transform(name) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) (crb_addr_xform[QLA82XX_HW_PX_MAP_CRB_##name] = \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) QLA82XX_HW_CRB_HUB_AGT_ADR_##name << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) const int MD_MIU_TEST_AGT_RDDATA[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 0x410000A8, 0x410000AC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 0x410000B8, 0x410000BC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) static void qla82xx_crb_addr_transform_setup(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) qla82xx_crb_addr_transform(XDMA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) qla82xx_crb_addr_transform(TIMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) qla82xx_crb_addr_transform(SRE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) qla82xx_crb_addr_transform(SQN3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) qla82xx_crb_addr_transform(SQN2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) qla82xx_crb_addr_transform(SQN1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) qla82xx_crb_addr_transform(SQN0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) qla82xx_crb_addr_transform(SQS3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) qla82xx_crb_addr_transform(SQS2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) qla82xx_crb_addr_transform(SQS1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) qla82xx_crb_addr_transform(SQS0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) qla82xx_crb_addr_transform(RPMX7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) qla82xx_crb_addr_transform(RPMX6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) qla82xx_crb_addr_transform(RPMX5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) qla82xx_crb_addr_transform(RPMX4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) qla82xx_crb_addr_transform(RPMX3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) qla82xx_crb_addr_transform(RPMX2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) qla82xx_crb_addr_transform(RPMX1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) qla82xx_crb_addr_transform(RPMX0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) qla82xx_crb_addr_transform(ROMUSB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) qla82xx_crb_addr_transform(SN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) qla82xx_crb_addr_transform(QMN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) qla82xx_crb_addr_transform(QMS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) qla82xx_crb_addr_transform(PGNI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) qla82xx_crb_addr_transform(PGND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) qla82xx_crb_addr_transform(PGN3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) qla82xx_crb_addr_transform(PGN2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) qla82xx_crb_addr_transform(PGN1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) qla82xx_crb_addr_transform(PGN0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) qla82xx_crb_addr_transform(PGSI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) qla82xx_crb_addr_transform(PGSD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) qla82xx_crb_addr_transform(PGS3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) qla82xx_crb_addr_transform(PGS2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) qla82xx_crb_addr_transform(PGS1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) qla82xx_crb_addr_transform(PGS0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) qla82xx_crb_addr_transform(PS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) qla82xx_crb_addr_transform(PH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) qla82xx_crb_addr_transform(NIU);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) qla82xx_crb_addr_transform(I2Q);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) qla82xx_crb_addr_transform(EG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) qla82xx_crb_addr_transform(MN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) qla82xx_crb_addr_transform(MS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) qla82xx_crb_addr_transform(CAS2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) qla82xx_crb_addr_transform(CAS1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) qla82xx_crb_addr_transform(CAS0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) qla82xx_crb_addr_transform(CAM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) qla82xx_crb_addr_transform(C2C1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) qla82xx_crb_addr_transform(C2C0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) qla82xx_crb_addr_transform(SMB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) qla82xx_crb_addr_transform(OCM0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * Used only in P3 just define it for P2 also.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) qla82xx_crb_addr_transform(I2C0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) qla82xx_crb_table_initialized = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static struct crb_128M_2M_block_map crb_128M_2M_map[64] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {{{0, 0, 0, 0} } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) {{{1, 0x0100000, 0x0102000, 0x120000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) {1, 0x0110000, 0x0120000, 0x130000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) {1, 0x0120000, 0x0122000, 0x124000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) {1, 0x0130000, 0x0132000, 0x126000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) {1, 0x0140000, 0x0142000, 0x128000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {1, 0x0150000, 0x0152000, 0x12a000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) {1, 0x0160000, 0x0170000, 0x110000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) {1, 0x0170000, 0x0172000, 0x12e000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) {1, 0x01e0000, 0x01e0800, 0x122000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {0, 0x0000000, 0x0000000, 0x000000} } } ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) {{{1, 0x0200000, 0x0210000, 0x180000} } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) {{{0, 0, 0, 0} } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) {{{1, 0x0400000, 0x0401000, 0x169000} } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) {{{1, 0x0500000, 0x0510000, 0x140000} } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) {{{1, 0x0600000, 0x0610000, 0x1c0000} } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) {{{1, 0x0700000, 0x0704000, 0x1b8000} } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {{{1, 0x0800000, 0x0802000, 0x170000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) {1, 0x08f0000, 0x08f2000, 0x172000} } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) {{{1, 0x0900000, 0x0902000, 0x174000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {1, 0x09f0000, 0x09f2000, 0x176000} } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) {{{0, 0x0a00000, 0x0a02000, 0x178000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {1, 0x0af0000, 0x0af2000, 0x17a000} } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {{{0, 0x0b00000, 0x0b02000, 0x17c000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {1, 0x0bf0000, 0x0bf2000, 0x17e000} } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {{{1, 0x0f00000, 0x0f01000, 0x164000} } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {{{0, 0x1000000, 0x1004000, 0x1a8000} } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {{{1, 0x1100000, 0x1101000, 0x160000} } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {{{1, 0x1200000, 0x1201000, 0x161000} } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {{{1, 0x1300000, 0x1301000, 0x162000} } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {{{1, 0x1400000, 0x1401000, 0x163000} } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {{{1, 0x1500000, 0x1501000, 0x165000} } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {{{1, 0x1600000, 0x1601000, 0x166000} } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {{{0, 0, 0, 0} } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {{{0, 0, 0, 0} } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {{{0, 0, 0, 0} } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {{{0, 0, 0, 0} } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {{{0, 0, 0, 0} } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {{{0, 0, 0, 0} } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {{{1, 0x1d00000, 0x1d10000, 0x190000} } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {{{1, 0x1f00000, 0x1f10000, 0x150000} } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {{{0} } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {{{1, 0x2100000, 0x2102000, 0x120000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {1, 0x2110000, 0x2120000, 0x130000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {1, 0x2120000, 0x2122000, 0x124000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {1, 0x2130000, 0x2132000, 0x126000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {1, 0x2140000, 0x2142000, 0x128000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {1, 0x2150000, 0x2152000, 0x12a000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {1, 0x2160000, 0x2170000, 0x110000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {1, 0x2170000, 0x2172000, 0x12e000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {0, 0x0000000, 0x0000000, 0x000000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {0, 0x0000000, 0x0000000, 0x000000} } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {{{1, 0x2200000, 0x2204000, 0x1b0000} } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {{{0} } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {{{0} } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {{{0} } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {{{0} } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {{{0} } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {{{1, 0x2800000, 0x2804000, 0x1a4000} } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {{{1, 0x2900000, 0x2901000, 0x16b000} } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {{{1, 0x3000000, 0x3000400, 0x1adc00} } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {{{0, 0x3100000, 0x3104000, 0x1a8000} } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {{{1, 0x3200000, 0x3204000, 0x1d4000} } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {{{1, 0x3300000, 0x3304000, 0x1a0000} } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {{{0} } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {{{1, 0x3500000, 0x3500400, 0x1ac000} } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {{{1, 0x3600000, 0x3600400, 0x1ae000} } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {{{1, 0x3700000, 0x3700400, 0x1ae400} } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {{{1, 0x3800000, 0x3804000, 0x1d0000} } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {{{1, 0x3900000, 0x3904000, 0x1b4000} } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {{{0} } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {{{0} } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {{{1, 0x3d00000, 0x3d04000, 0x1dc000} } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {{{1, 0x3e00000, 0x3e01000, 0x167000} } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {{{1, 0x3f00000, 0x3f01000, 0x168000} } }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) * top 12 bits of crb internal address (hub, agent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) static unsigned qla82xx_crb_hub_agt[64] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) QLA82XX_HW_CRB_HUB_AGT_ADR_PS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) QLA82XX_HW_CRB_HUB_AGT_ADR_MN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) QLA82XX_HW_CRB_HUB_AGT_ADR_MS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) QLA82XX_HW_CRB_HUB_AGT_ADR_SRE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) QLA82XX_HW_CRB_HUB_AGT_ADR_NIU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) QLA82XX_HW_CRB_HUB_AGT_ADR_QMN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) QLA82XX_HW_CRB_HUB_AGT_ADR_SQN0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) QLA82XX_HW_CRB_HUB_AGT_ADR_SQN1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) QLA82XX_HW_CRB_HUB_AGT_ADR_SQN2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) QLA82XX_HW_CRB_HUB_AGT_ADR_SQN3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) QLA82XX_HW_CRB_HUB_AGT_ADR_PGN4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) QLA82XX_HW_CRB_HUB_AGT_ADR_PGN0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) QLA82XX_HW_CRB_HUB_AGT_ADR_PGN1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) QLA82XX_HW_CRB_HUB_AGT_ADR_PGN2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) QLA82XX_HW_CRB_HUB_AGT_ADR_PGN3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) QLA82XX_HW_CRB_HUB_AGT_ADR_PGND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) QLA82XX_HW_CRB_HUB_AGT_ADR_PGNI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) QLA82XX_HW_CRB_HUB_AGT_ADR_PGS0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) QLA82XX_HW_CRB_HUB_AGT_ADR_PGS1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) QLA82XX_HW_CRB_HUB_AGT_ADR_PGS2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) QLA82XX_HW_CRB_HUB_AGT_ADR_PGS3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) QLA82XX_HW_CRB_HUB_AGT_ADR_PGSI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) QLA82XX_HW_CRB_HUB_AGT_ADR_SN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) QLA82XX_HW_CRB_HUB_AGT_ADR_EG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) QLA82XX_HW_CRB_HUB_AGT_ADR_PS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) QLA82XX_HW_CRB_HUB_AGT_ADR_CAM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) QLA82XX_HW_CRB_HUB_AGT_ADR_OCM0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) QLA82XX_HW_CRB_HUB_AGT_ADR_SMB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) QLA82XX_HW_CRB_HUB_AGT_ADR_I2C0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) QLA82XX_HW_CRB_HUB_AGT_ADR_I2C1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) QLA82XX_HW_CRB_HUB_AGT_ADR_PGNC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) /* Device states */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) static char *q_dev_state[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) "Unknown",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) "Cold",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) "Initializing",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) "Ready",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) "Need Reset",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) "Need Quiescent",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) "Failed",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) "Quiescent",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) char *qdev_state(uint32_t dev_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) return q_dev_state[dev_state];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) * In: 'off_in' is offset from CRB space in 128M pci map
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) * Out: 'off_out' is 2M pci map addr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) * side effect: lock crb window
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) qla82xx_pci_set_crbwindow_2M(struct qla_hw_data *ha, ulong off_in,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) void __iomem **off_out)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) u32 win_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) ha->crb_win = CRB_HI(off_in);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) writel(ha->crb_win, CRB_WINDOW_2M + ha->nx_pcibase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) /* Read back value to make sure write has gone through before trying
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) * to use it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) win_read = rd_reg_dword(CRB_WINDOW_2M + ha->nx_pcibase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) if (win_read != ha->crb_win) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) ql_dbg(ql_dbg_p3p, vha, 0xb000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) "%s: Written crbwin (0x%x) "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) "!= Read crbwin (0x%x), off=0x%lx.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) __func__, ha->crb_win, win_read, off_in);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) *off_out = (off_in & MASK(16)) + CRB_INDIRECT_2M + ha->nx_pcibase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) qla82xx_pci_get_crb_addr_2M(struct qla_hw_data *ha, ulong off_in,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) void __iomem **off_out)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) struct crb_128M_2M_sub_block_map *m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) if (off_in >= QLA82XX_CRB_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) if (off_in >= QLA82XX_PCI_CAMQM && off_in < QLA82XX_PCI_CAMQM_2M_END) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) *off_out = (off_in - QLA82XX_PCI_CAMQM) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) QLA82XX_PCI_CAMQM_2M_BASE + ha->nx_pcibase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) if (off_in < QLA82XX_PCI_CRBSPACE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) off_in -= QLA82XX_PCI_CRBSPACE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) /* Try direct map */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) m = &crb_128M_2M_map[CRB_BLK(off_in)].sub_block[CRB_SUBBLK(off_in)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) if (m->valid && (m->start_128M <= off_in) && (m->end_128M > off_in)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) *off_out = off_in + m->start_2M - m->start_128M + ha->nx_pcibase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) /* Not in direct map, use crb window */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) *off_out = (void __iomem *)off_in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #define CRB_WIN_LOCK_TIMEOUT 100000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) static int qla82xx_crb_win_lock(struct qla_hw_data *ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) int done = 0, timeout = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) while (!done) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) /* acquire semaphore3 from PCI HW block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_LOCK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) if (done == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) if (timeout >= CRB_WIN_LOCK_TIMEOUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) timeout++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) qla82xx_wr_32(ha, QLA82XX_CRB_WIN_LOCK_ID, ha->portnum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) qla82xx_wr_32(struct qla_hw_data *ha, ulong off_in, u32 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) void __iomem *off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) unsigned long flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) int rv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) rv = qla82xx_pci_get_crb_addr_2M(ha, off_in, &off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) BUG_ON(rv == -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) if (rv == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) #ifndef __CHECKER__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) write_lock_irqsave(&ha->hw_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) qla82xx_crb_win_lock(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) qla82xx_pci_set_crbwindow_2M(ha, off_in, &off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) writel(data, (void __iomem *)off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) if (rv == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) #ifndef __CHECKER__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) write_unlock_irqrestore(&ha->hw_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) qla82xx_rd_32(struct qla_hw_data *ha, ulong off_in)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) void __iomem *off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) unsigned long flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) int rv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) u32 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) rv = qla82xx_pci_get_crb_addr_2M(ha, off_in, &off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) BUG_ON(rv == -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) if (rv == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) #ifndef __CHECKER__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) write_lock_irqsave(&ha->hw_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) qla82xx_crb_win_lock(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) qla82xx_pci_set_crbwindow_2M(ha, off_in, &off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) data = rd_reg_dword(off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) if (rv == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) #ifndef __CHECKER__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) write_unlock_irqrestore(&ha->hw_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) return data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) #define IDC_LOCK_TIMEOUT 100000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) int qla82xx_idc_lock(struct qla_hw_data *ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) int done = 0, timeout = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) while (!done) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) /* acquire semaphore5 from PCI HW block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_LOCK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) if (done == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) if (timeout >= IDC_LOCK_TIMEOUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) timeout++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) /* Yield CPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) if (!in_interrupt())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) schedule();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) for (i = 0; i < 20; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) void qla82xx_idc_unlock(struct qla_hw_data *ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_UNLOCK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) * check memory access boundary.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) * used by test agent. support ddr access only for now
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) static unsigned long
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) qla82xx_pci_mem_bound_check(struct qla_hw_data *ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) unsigned long long addr, int size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) if (!addr_in_range(addr, QLA82XX_ADDR_DDR_NET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) QLA82XX_ADDR_DDR_NET_MAX) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) !addr_in_range(addr + size - 1, QLA82XX_ADDR_DDR_NET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) QLA82XX_ADDR_DDR_NET_MAX) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) ((size != 1) && (size != 2) && (size != 4) && (size != 8)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) static int qla82xx_pci_set_window_warning_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) static unsigned long
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) qla82xx_pci_set_window(struct qla_hw_data *ha, unsigned long long addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) int window;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) u32 win_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) if (addr_in_range(addr, QLA82XX_ADDR_DDR_NET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) QLA82XX_ADDR_DDR_NET_MAX)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) /* DDR network side */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) window = MN_WIN(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) ha->ddr_mn_window = window;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) qla82xx_wr_32(ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) ha->mn_win_crb | QLA82XX_PCI_CRBSPACE, window);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) win_read = qla82xx_rd_32(ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) ha->mn_win_crb | QLA82XX_PCI_CRBSPACE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) if ((win_read << 17) != window) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) ql_dbg(ql_dbg_p3p, vha, 0xb003,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) "%s: Written MNwin (0x%x) != Read MNwin (0x%x).\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) __func__, window, win_read);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_DDR_NET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) } else if (addr_in_range(addr, QLA82XX_ADDR_OCM0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) QLA82XX_ADDR_OCM0_MAX)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) unsigned int temp1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) if ((addr & 0x00ff800) == 0xff800) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) ql_log(ql_log_warn, vha, 0xb004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) "%s: QM access not handled.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) addr = -1UL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) window = OCM_WIN(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) ha->ddr_mn_window = window;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) qla82xx_wr_32(ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) ha->mn_win_crb | QLA82XX_PCI_CRBSPACE, window);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) win_read = qla82xx_rd_32(ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) ha->mn_win_crb | QLA82XX_PCI_CRBSPACE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) temp1 = ((window & 0x1FF) << 7) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) ((window & 0x0FFFE0000) >> 17);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) if (win_read != temp1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) ql_log(ql_log_warn, vha, 0xb005,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) "%s: Written OCMwin (0x%x) != Read OCMwin (0x%x).\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) __func__, temp1, win_read);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_OCM0_2M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) } else if (addr_in_range(addr, QLA82XX_ADDR_QDR_NET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) QLA82XX_P3_ADDR_QDR_NET_MAX)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) /* QDR network side */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) window = MS_WIN(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) ha->qdr_sn_window = window;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) qla82xx_wr_32(ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) ha->ms_win_crb | QLA82XX_PCI_CRBSPACE, window);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) win_read = qla82xx_rd_32(ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) ha->ms_win_crb | QLA82XX_PCI_CRBSPACE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) if (win_read != window) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) ql_log(ql_log_warn, vha, 0xb006,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) "%s: Written MSwin (0x%x) != Read MSwin (0x%x).\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) __func__, window, win_read);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_QDR_NET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) * peg gdb frequently accesses memory that doesn't exist,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) * this limits the chit chat so debugging isn't slowed down.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) if ((qla82xx_pci_set_window_warning_count++ < 8) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) (qla82xx_pci_set_window_warning_count%64 == 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) ql_log(ql_log_warn, vha, 0xb007,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) "%s: Warning:%s Unknown address range!.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) __func__, QLA2XXX_DRIVER_NAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) addr = -1UL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) return addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) /* check if address is in the same windows as the previous access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) static int qla82xx_pci_is_same_window(struct qla_hw_data *ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) unsigned long long addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) int window;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) unsigned long long qdr_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) qdr_max = QLA82XX_P3_ADDR_QDR_NET_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) /* DDR network side */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) if (addr_in_range(addr, QLA82XX_ADDR_DDR_NET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) QLA82XX_ADDR_DDR_NET_MAX))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) else if (addr_in_range(addr, QLA82XX_ADDR_OCM0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) QLA82XX_ADDR_OCM0_MAX))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) else if (addr_in_range(addr, QLA82XX_ADDR_OCM1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) QLA82XX_ADDR_OCM1_MAX))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) else if (addr_in_range(addr, QLA82XX_ADDR_QDR_NET, qdr_max)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) /* QDR network side */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) window = ((addr - QLA82XX_ADDR_QDR_NET) >> 22) & 0x3f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) if (ha->qdr_sn_window == window)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) static int qla82xx_pci_mem_read_direct(struct qla_hw_data *ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) u64 off, void *data, int size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) void __iomem *addr = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) u64 start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) uint8_t __iomem *mem_ptr = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) unsigned long mem_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) unsigned long mem_page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) write_lock_irqsave(&ha->hw_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) * If attempting to access unknown address or straddle hw windows,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) * do not access.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) start = qla82xx_pci_set_window(ha, off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) if ((start == -1UL) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) (qla82xx_pci_is_same_window(ha, off + size - 1) == 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) write_unlock_irqrestore(&ha->hw_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) ql_log(ql_log_fatal, vha, 0xb008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) "%s out of bound pci memory "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) "access, offset is 0x%llx.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) QLA2XXX_DRIVER_NAME, off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) write_unlock_irqrestore(&ha->hw_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) mem_base = pci_resource_start(ha->pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) mem_page = start & PAGE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) /* Map two pages whenever user tries to access addresses in two
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) * consecutive pages.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) if (mem_page != ((start + size - 1) & PAGE_MASK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) if (mem_ptr == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) *(u8 *)data = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) addr = mem_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) addr += start & (PAGE_SIZE - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) write_lock_irqsave(&ha->hw_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) switch (size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) *(u8 *)data = readb(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) *(u16 *)data = readw(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) *(u32 *)data = readl(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) *(u64 *)data = readq(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) ret = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) write_unlock_irqrestore(&ha->hw_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) if (mem_ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) iounmap(mem_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) qla82xx_pci_mem_write_direct(struct qla_hw_data *ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) u64 off, void *data, int size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) void __iomem *addr = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) u64 start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) uint8_t __iomem *mem_ptr = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) unsigned long mem_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) unsigned long mem_page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) write_lock_irqsave(&ha->hw_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) * If attempting to access unknown address or straddle hw windows,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) * do not access.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) start = qla82xx_pci_set_window(ha, off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) if ((start == -1UL) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) (qla82xx_pci_is_same_window(ha, off + size - 1) == 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) write_unlock_irqrestore(&ha->hw_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) ql_log(ql_log_fatal, vha, 0xb009,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) "%s out of bound memory "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) "access, offset is 0x%llx.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) QLA2XXX_DRIVER_NAME, off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) write_unlock_irqrestore(&ha->hw_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) mem_base = pci_resource_start(ha->pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) mem_page = start & PAGE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) /* Map two pages whenever user tries to access addresses in two
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) * consecutive pages.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) if (mem_page != ((start + size - 1) & PAGE_MASK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE*2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) if (mem_ptr == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) addr = mem_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) addr += start & (PAGE_SIZE - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) write_lock_irqsave(&ha->hw_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) switch (size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) writeb(*(u8 *)data, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) writew(*(u16 *)data, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) writel(*(u32 *)data, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) writeq(*(u64 *)data, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) ret = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) write_unlock_irqrestore(&ha->hw_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) if (mem_ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) iounmap(mem_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) #define MTU_FUDGE_FACTOR 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) static unsigned long
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) qla82xx_decode_crb_addr(unsigned long addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) unsigned long base_addr, offset, pci_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) if (!qla82xx_crb_table_initialized)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) qla82xx_crb_addr_transform_setup();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) pci_base = ADDR_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) base_addr = addr & 0xfff00000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) offset = addr & 0x000fffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) for (i = 0; i < MAX_CRB_XFORM; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) if (crb_addr_xform[i] == base_addr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) pci_base = i << 20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) if (pci_base == ADDR_ERROR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) return pci_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) return pci_base + offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) static long rom_max_timeout = 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) static long qla82xx_rom_lock_timeout = 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) qla82xx_rom_lock(struct qla_hw_data *ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) int done = 0, timeout = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) uint32_t lock_owner = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) while (!done) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) /* acquire semaphore2 from PCI HW block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_LOCK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) if (done == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) if (timeout >= qla82xx_rom_lock_timeout) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) lock_owner = qla82xx_rd_32(ha, QLA82XX_ROM_LOCK_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) ql_dbg(ql_dbg_p3p, vha, 0xb157,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) "%s: Simultaneous flash access by following ports, active port = %d: accessing port = %d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) __func__, ha->portnum, lock_owner);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) timeout++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) qla82xx_wr_32(ha, QLA82XX_ROM_LOCK_ID, ha->portnum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) qla82xx_rom_unlock(struct qla_hw_data *ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) qla82xx_wr_32(ha, QLA82XX_ROM_LOCK_ID, 0xffffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_UNLOCK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) qla82xx_wait_rom_busy(struct qla_hw_data *ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) long timeout = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) long done = 0 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) while (done == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) done = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) done &= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) timeout++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) if (timeout >= rom_max_timeout) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) ql_dbg(ql_dbg_p3p, vha, 0xb00a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) "%s: Timeout reached waiting for rom busy.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) QLA2XXX_DRIVER_NAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) qla82xx_wait_rom_done(struct qla_hw_data *ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) long timeout = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) long done = 0 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) while (done == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) done = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) done &= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) timeout++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) if (timeout >= rom_max_timeout) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) ql_dbg(ql_dbg_p3p, vha, 0xb00b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) "%s: Timeout reached waiting for rom done.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) QLA2XXX_DRIVER_NAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) qla82xx_md_rw_32(struct qla_hw_data *ha, uint32_t off, u32 data, uint8_t flag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) uint32_t off_value, rval = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) wrt_reg_dword(CRB_WINDOW_2M + ha->nx_pcibase, off & 0xFFFF0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) /* Read back value to make sure write has gone through */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) rd_reg_dword(CRB_WINDOW_2M + ha->nx_pcibase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) off_value = (off & 0x0000FFFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) if (flag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) wrt_reg_dword(off_value + CRB_INDIRECT_2M + ha->nx_pcibase,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) rval = rd_reg_dword(off_value + CRB_INDIRECT_2M +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) ha->nx_pcibase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) qla82xx_do_rom_fast_read(struct qla_hw_data *ha, int addr, int *valp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) /* Dword reads to flash. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) qla82xx_md_rw_32(ha, MD_DIRECT_ROM_WINDOW, (addr & 0xFFFF0000), 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) *valp = qla82xx_md_rw_32(ha, MD_DIRECT_ROM_READ_BASE +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) (addr & 0x0000FFFF), 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) qla82xx_rom_fast_read(struct qla_hw_data *ha, int addr, int *valp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) int ret, loops = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) uint32_t lock_owner = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) while ((qla82xx_rom_lock(ha) != 0) && (loops < 50000)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) schedule();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) loops++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) if (loops >= 50000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) lock_owner = qla82xx_rd_32(ha, QLA82XX_ROM_LOCK_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) ql_log(ql_log_fatal, vha, 0x00b9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) "Failed to acquire SEM2 lock, Lock Owner %u.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) lock_owner);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) ret = qla82xx_do_rom_fast_read(ha, addr, valp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) qla82xx_rom_unlock(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) qla82xx_read_status_reg(struct qla_hw_data *ha, uint32_t *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_RDSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) qla82xx_wait_rom_busy(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) if (qla82xx_wait_rom_done(ha)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) ql_log(ql_log_warn, vha, 0xb00c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) "Error waiting for rom done.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) *val = qla82xx_rd_32(ha, QLA82XX_ROMUSB_ROM_RDATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) qla82xx_flash_wait_write_finish(struct qla_hw_data *ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) uint32_t val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) for (i = 0; i < 50000; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) ret = qla82xx_read_status_reg(ha, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) if (ret < 0 || (val & 1) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) cond_resched();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) ql_log(ql_log_warn, vha, 0xb00d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) "Timeout reached waiting for write finish.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) qla82xx_flash_set_write_enable(struct qla_hw_data *ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) uint32_t val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) qla82xx_wait_rom_busy(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_WREN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) qla82xx_wait_rom_busy(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) if (qla82xx_wait_rom_done(ha))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) if (qla82xx_read_status_reg(ha, &val) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) if ((val & 2) != 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) qla82xx_write_status_reg(struct qla_hw_data *ha, uint32_t val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) if (qla82xx_flash_set_write_enable(ha))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_WDATA, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) if (qla82xx_wait_rom_done(ha)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) ql_log(ql_log_warn, vha, 0xb00e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) "Error waiting for rom done.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) return qla82xx_flash_wait_write_finish(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) qla82xx_write_disable_flash(struct qla_hw_data *ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_WRDI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) if (qla82xx_wait_rom_done(ha)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) ql_log(ql_log_warn, vha, 0xb00f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) "Error waiting for rom done.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) ql82xx_rom_lock_d(struct qla_hw_data *ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) int loops = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) uint32_t lock_owner = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) while ((qla82xx_rom_lock(ha) != 0) && (loops < 50000)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) cond_resched();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) loops++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) if (loops >= 50000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) lock_owner = qla82xx_rd_32(ha, QLA82XX_ROM_LOCK_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) ql_log(ql_log_warn, vha, 0xb010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) "ROM lock failed, Lock Owner %u.\n", lock_owner);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) qla82xx_write_flash_dword(struct qla_hw_data *ha, uint32_t flashaddr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) uint32_t data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) ret = ql82xx_rom_lock_d(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) ql_log(ql_log_warn, vha, 0xb011,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) "ROM lock failed.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) ret = qla82xx_flash_set_write_enable(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) goto done_write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_WDATA, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, flashaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_PP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) qla82xx_wait_rom_busy(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) if (qla82xx_wait_rom_done(ha)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) ql_log(ql_log_warn, vha, 0xb012,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) "Error waiting for rom done.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) ret = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) goto done_write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) ret = qla82xx_flash_wait_write_finish(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) done_write:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) qla82xx_rom_unlock(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) /* This routine does CRB initialize sequence
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) * to put the ISP into operational state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) qla82xx_pinit_from_rom(scsi_qla_host_t *vha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) int addr, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) int i ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) struct crb_addr_pair *buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) unsigned long off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) unsigned offset, n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) struct crb_addr_pair {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) long addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) long data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) /* Halt all the individual PEGs and other blocks of the ISP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) qla82xx_rom_lock(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) /* disable all I2Q */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x10, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x14, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x18, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x1c, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x20, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x24, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) /* disable all niu interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x40, 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) /* disable xge rx/tx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x70000, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) /* disable xg1 rx/tx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x80000, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) /* disable sideband mac */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x90000, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) /* disable ap0 mac */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0xa0000, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) /* disable ap1 mac */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0xb0000, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) /* halt sre */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) val = qla82xx_rd_32(ha, QLA82XX_CRB_SRE + 0x1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) qla82xx_wr_32(ha, QLA82XX_CRB_SRE + 0x1000, val & (~(0x1)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) /* halt epg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) qla82xx_wr_32(ha, QLA82XX_CRB_EPG + 0x1300, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) /* halt timers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x0, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x8, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x10, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x18, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x100, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x200, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) /* halt pegs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x3c, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1 + 0x3c, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2 + 0x3c, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3 + 0x3c, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_4 + 0x3c, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) msleep(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) /* big hammer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) if (test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) /* don't reset CAM block on reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xfeffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xffffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) qla82xx_rom_unlock(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) /* Read the signature value from the flash.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) * Offset 0: Contain signature (0xcafecafe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) * Offset 4: Offset and number of addr/value pairs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) * that present in CRB initialize sequence
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) n = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) if (qla82xx_rom_fast_read(ha, 0, &n) != 0 || n != 0xcafecafeUL ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) qla82xx_rom_fast_read(ha, 4, &n) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) ql_log(ql_log_fatal, vha, 0x006e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) "Error Reading crb_init area: n: %08x.\n", n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) /* Offset in flash = lower 16 bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) * Number of entries = upper 16 bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) offset = n & 0xffffU;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) n = (n >> 16) & 0xffffU;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) /* number of addr/value pair should not exceed 1024 entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) if (n >= 1024) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) ql_log(ql_log_fatal, vha, 0x0071,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) "Card flash not initialized:n=0x%x.\n", n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) ql_log(ql_log_info, vha, 0x0072,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) "%d CRB init values found in ROM.\n", n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) buf = kmalloc_array(n, sizeof(struct crb_addr_pair), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) if (buf == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) ql_log(ql_log_fatal, vha, 0x010c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) "Unable to allocate memory.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) for (i = 0; i < n; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) if (qla82xx_rom_fast_read(ha, 8*i + 4*offset, &val) != 0 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) qla82xx_rom_fast_read(ha, 8*i + 4*offset + 4, &addr) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) kfree(buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) buf[i].addr = addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) buf[i].data = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) for (i = 0; i < n; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) /* Translate internal CRB initialization
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) * address to PCI bus address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) off = qla82xx_decode_crb_addr((unsigned long)buf[i].addr) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) QLA82XX_PCI_CRBSPACE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) /* Not all CRB addr/value pair to be written,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) * some of them are skipped
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) /* skipping cold reboot MAGIC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) if (off == QLA82XX_CAM_RAM(0x1fc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) /* do not reset PCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) if (off == (ROMUSB_GLB + 0xbc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) /* skip core clock, so that firmware can increase the clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) if (off == (ROMUSB_GLB + 0xc8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) /* skip the function enable register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) if ((off & 0x0ff00000) == QLA82XX_CRB_SMB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) if ((off & 0x0ff00000) == QLA82XX_CRB_DDR_NET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) if (off == ADDR_ERROR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) ql_log(ql_log_fatal, vha, 0x0116,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) "Unknown addr: 0x%08lx.\n", buf[i].addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) qla82xx_wr_32(ha, off, buf[i].data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) /* ISP requires much bigger delay to settle down,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) * else crb_window returns 0xffffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) if (off == QLA82XX_ROMUSB_GLB_SW_RESET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) msleep(1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) /* ISP requires millisec delay between
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) * successive CRB register updation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) kfree(buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) /* Resetting the data and instruction cache */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0xec, 0x1e);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0x4c, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_I+0x4c, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) /* Clear all protocol processing engines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0x8, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0xc, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0x8, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0xc, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0x8, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0xc, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0x8, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0xc, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) qla82xx_pci_mem_write_2M(struct qla_hw_data *ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) u64 off, void *data, int size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) int i, j, ret = 0, loop, sz[2], off0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) int scale, shift_amount, startword;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) uint32_t temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) uint64_t off8, mem_crb, tmpw, word[2] = {0, 0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) * If not MN, go check for MS or invalid.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) mem_crb = QLA82XX_CRB_QDR_NET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) mem_crb = QLA82XX_CRB_DDR_NET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) if (qla82xx_pci_mem_bound_check(ha, off, size) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) return qla82xx_pci_mem_write_direct(ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) off, data, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) off0 = off & 0x7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) sz[0] = (size < (8 - off0)) ? size : (8 - off0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) sz[1] = size - sz[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) off8 = off & 0xfffffff0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) loop = (((off & 0xf) + size - 1) >> 4) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) shift_amount = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) scale = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) startword = (off & 0xf)/8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) for (i = 0; i < loop; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) if (qla82xx_pci_mem_read_2M(ha, off8 +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) (i << shift_amount), &word[i * scale], 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) switch (size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) tmpw = *((uint8_t *)data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) tmpw = *((uint16_t *)data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) tmpw = *((uint32_t *)data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) tmpw = *((uint64_t *)data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) if (sz[0] == 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) word[startword] = tmpw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) word[startword] &=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) word[startword] |= tmpw << (off0 * 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) if (sz[1] != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) word[startword+1] &= ~(~0ULL << (sz[1] * 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) word[startword+1] |= tmpw >> (sz[0] * 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) for (i = 0; i < loop; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) temp = off8 + (i << shift_amount);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_LO, temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) temp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_HI, temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) temp = word[i * scale] & 0xffffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_LO, temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) temp = (word[i * scale] >> 32) & 0xffffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_HI, temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) temp = word[i*scale + 1] & 0xffffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) qla82xx_wr_32(ha, mem_crb +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) MIU_TEST_AGT_WRDATA_UPPER_LO, temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) temp = (word[i*scale + 1] >> 32) & 0xffffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) qla82xx_wr_32(ha, mem_crb +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) MIU_TEST_AGT_WRDATA_UPPER_HI, temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) temp = MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) for (j = 0; j < MAX_CTL_CHECK; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) temp = qla82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) if ((temp & MIU_TA_CTL_BUSY) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) if (j >= MAX_CTL_CHECK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) if (printk_ratelimit())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) dev_err(&ha->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) "failed to write through agent.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) ret = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) qla82xx_fw_load_from_flash(struct qla_hw_data *ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) long size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) long flashaddr = ha->flt_region_bootload << 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) long memaddr = BOOTLD_START;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) u64 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) u32 high, low;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) size = (IMAGE_START - BOOTLD_START) / 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) for (i = 0; i < size; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) if ((qla82xx_rom_fast_read(ha, flashaddr, (int *)&low)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) (qla82xx_rom_fast_read(ha, flashaddr + 4, (int *)&high))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) data = ((u64)high << 32) | low ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) qla82xx_pci_mem_write_2M(ha, memaddr, &data, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) flashaddr += 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) memaddr += 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) if (i % 0x1000 == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) read_lock(&ha->hw_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x18, 0x1020);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001e);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) read_unlock(&ha->hw_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) qla82xx_pci_mem_read_2M(struct qla_hw_data *ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) u64 off, void *data, int size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) int i, j = 0, k, start, end, loop, sz[2], off0[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) int shift_amount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) uint32_t temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) uint64_t off8, val, mem_crb, word[2] = {0, 0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) * If not MN, go check for MS or invalid.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) mem_crb = QLA82XX_CRB_QDR_NET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) mem_crb = QLA82XX_CRB_DDR_NET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) if (qla82xx_pci_mem_bound_check(ha, off, size) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) return qla82xx_pci_mem_read_direct(ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) off, data, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) off8 = off & 0xfffffff0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) off0[0] = off & 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) sz[0] = (size < (16 - off0[0])) ? size : (16 - off0[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) shift_amount = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) loop = ((off0[0] + size - 1) >> shift_amount) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) off0[1] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) sz[1] = size - sz[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) for (i = 0; i < loop; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) temp = off8 + (i << shift_amount);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_LO, temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) temp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_HI, temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) temp = MIU_TA_CTL_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) for (j = 0; j < MAX_CTL_CHECK; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) temp = qla82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) if ((temp & MIU_TA_CTL_BUSY) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) if (j >= MAX_CTL_CHECK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) if (printk_ratelimit())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) dev_err(&ha->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) "failed to read through agent.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) start = off0[i] >> 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) end = (off0[i] + sz[i] - 1) >> 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) for (k = start; k <= end; k++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) temp = qla82xx_rd_32(ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) mem_crb + MIU_TEST_AGT_RDDATA(k));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) word[i] |= ((uint64_t)temp << (32 * (k & 1)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) if (j >= MAX_CTL_CHECK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) if ((off0[0] & 7) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) val = word[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) switch (size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) *(uint8_t *)data = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) *(uint16_t *)data = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) *(uint32_t *)data = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) *(uint64_t *)data = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) static struct qla82xx_uri_table_desc *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) qla82xx_get_table_desc(const u8 *unirom, int section)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) uint32_t i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) struct qla82xx_uri_table_desc *directory =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) (struct qla82xx_uri_table_desc *)&unirom[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) uint32_t offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) uint32_t tab_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) uint32_t entries = le32_to_cpu(directory->num_entries);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) for (i = 0; i < entries; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) offset = le32_to_cpu(directory->findex) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) (i * le32_to_cpu(directory->entry_size));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) tab_type = get_unaligned_le32((u32 *)&unirom[offset] + 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) if (tab_type == section)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) return (struct qla82xx_uri_table_desc *)&unirom[offset];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) static struct qla82xx_uri_data_desc *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) qla82xx_get_data_desc(struct qla_hw_data *ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) u32 section, u32 idx_offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) const u8 *unirom = ha->hablob->fw->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) int idx = get_unaligned_le32((u32 *)&unirom[ha->file_prd_off] +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) idx_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) struct qla82xx_uri_table_desc *tab_desc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) uint32_t offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) tab_desc = qla82xx_get_table_desc(unirom, section);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) if (!tab_desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) offset = le32_to_cpu(tab_desc->findex) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) (le32_to_cpu(tab_desc->entry_size) * idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) return (struct qla82xx_uri_data_desc *)&unirom[offset];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) static u8 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) qla82xx_get_bootld_offset(struct qla_hw_data *ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) u32 offset = BOOTLD_START;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) struct qla82xx_uri_data_desc *uri_desc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) if (ha->fw_type == QLA82XX_UNIFIED_ROMIMAGE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) uri_desc = qla82xx_get_data_desc(ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) QLA82XX_URI_DIR_SECT_BOOTLD, QLA82XX_URI_BOOTLD_IDX_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) if (uri_desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) offset = le32_to_cpu(uri_desc->findex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) return (u8 *)&ha->hablob->fw->data[offset];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) static u32 qla82xx_get_fw_size(struct qla_hw_data *ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) struct qla82xx_uri_data_desc *uri_desc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) if (ha->fw_type == QLA82XX_UNIFIED_ROMIMAGE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) uri_desc = qla82xx_get_data_desc(ha, QLA82XX_URI_DIR_SECT_FW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) QLA82XX_URI_FIRMWARE_IDX_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) if (uri_desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) return le32_to_cpu(uri_desc->size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) return get_unaligned_le32(&ha->hablob->fw->data[FW_SIZE_OFFSET]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) static u8 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) qla82xx_get_fw_offs(struct qla_hw_data *ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) u32 offset = IMAGE_START;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) struct qla82xx_uri_data_desc *uri_desc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) if (ha->fw_type == QLA82XX_UNIFIED_ROMIMAGE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) uri_desc = qla82xx_get_data_desc(ha, QLA82XX_URI_DIR_SECT_FW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) QLA82XX_URI_FIRMWARE_IDX_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) if (uri_desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) offset = le32_to_cpu(uri_desc->findex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) return (u8 *)&ha->hablob->fw->data[offset];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) /* PCI related functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) int qla82xx_pci_region_offset(struct pci_dev *pdev, int region)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) unsigned long val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) u32 control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) switch (region) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) pci_read_config_dword(pdev, QLA82XX_PCI_REG_MSIX_TBL, &control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) val = control + QLA82XX_MSIX_TBL_SPACE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) qla82xx_iospace_config(struct qla_hw_data *ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) uint32_t len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) if (pci_request_regions(ha->pdev, QLA2XXX_DRIVER_NAME)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) ql_log_pci(ql_log_fatal, ha->pdev, 0x000c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) "Failed to reserver selected regions.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) goto iospace_error_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) /* Use MMIO operations for all accesses. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) ql_log_pci(ql_log_fatal, ha->pdev, 0x000d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) "Region #0 not an MMIO resource, aborting.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) goto iospace_error_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) len = pci_resource_len(ha->pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) ha->nx_pcibase = ioremap(pci_resource_start(ha->pdev, 0), len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) if (!ha->nx_pcibase) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) ql_log_pci(ql_log_fatal, ha->pdev, 0x000e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) "Cannot remap pcibase MMIO, aborting.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) goto iospace_error_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) /* Mapping of IO base pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) if (IS_QLA8044(ha)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) ha->iobase = ha->nx_pcibase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) } else if (IS_QLA82XX(ha)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) ha->iobase = ha->nx_pcibase + 0xbc000 + (ha->pdev->devfn << 11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) if (!ql2xdbwr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) ha->nxdb_wr_ptr = ioremap((pci_resource_start(ha->pdev, 4) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) (ha->pdev->devfn << 12)), 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) if (!ha->nxdb_wr_ptr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) ql_log_pci(ql_log_fatal, ha->pdev, 0x000f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) "Cannot remap MMIO, aborting.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) goto iospace_error_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) /* Mapping of IO base pointer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) * door bell read and write pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) ha->nxdb_rd_ptr = ha->nx_pcibase + (512 * 1024) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) (ha->pdev->devfn * 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) ha->nxdb_wr_ptr = (void __iomem *)(ha->pdev->devfn == 6 ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) QLA82XX_CAMRAM_DB1 :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) QLA82XX_CAMRAM_DB2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) ha->max_req_queues = ha->max_rsp_queues = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) ha->msix_count = ha->max_rsp_queues + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc006,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) "nx_pci_base=%p iobase=%p "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) "max_req_queues=%d msix_count=%d.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) ha->nx_pcibase, ha->iobase,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) ha->max_req_queues, ha->msix_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) "nx_pci_base=%p iobase=%p "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) "max_req_queues=%d msix_count=%d.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) ha->nx_pcibase, ha->iobase,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) ha->max_req_queues, ha->msix_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) iospace_error_exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) /* GS related functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) /* Initialization related functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) * qla82xx_pci_config() - Setup ISP82xx PCI configuration registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) * @vha: HA context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) * Returns 0 on success.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) qla82xx_pci_config(scsi_qla_host_t *vha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) pci_set_master(ha->pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) ret = pci_set_mwi(ha->pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) ha->chip_revision = ha->pdev->revision;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) ql_dbg(ql_dbg_init, vha, 0x0043,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) "Chip revision:%d; pci_set_mwi() returned %d.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) ha->chip_revision, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) * qla82xx_reset_chip() - Setup ISP82xx PCI configuration registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) * @vha: HA context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) * Returns 0 on success.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) qla82xx_reset_chip(scsi_qla_host_t *vha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) ha->isp_ops->disable_intrs(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) return QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) void qla82xx_config_rings(struct scsi_qla_host *vha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) struct device_reg_82xx __iomem *reg = &ha->iobase->isp82;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) struct init_cb_81xx *icb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) struct req_que *req = ha->req_q_map[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) struct rsp_que *rsp = ha->rsp_q_map[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) /* Setup ring parameters in initialization control block. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) icb = (struct init_cb_81xx *)ha->init_cb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) icb->request_q_outpointer = cpu_to_le16(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) icb->response_q_inpointer = cpu_to_le16(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) icb->request_q_length = cpu_to_le16(req->length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) icb->response_q_length = cpu_to_le16(rsp->length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) put_unaligned_le64(req->dma, &icb->request_q_address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) put_unaligned_le64(rsp->dma, &icb->response_q_address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) wrt_reg_dword(®->req_q_out[0], 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) wrt_reg_dword(®->rsp_q_in[0], 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) wrt_reg_dword(®->rsp_q_out[0], 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) qla82xx_fw_load_from_blob(struct qla_hw_data *ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) u64 *ptr64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) u32 i, flashaddr, size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) __le64 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) size = (IMAGE_START - BOOTLD_START) / 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) ptr64 = (u64 *)qla82xx_get_bootld_offset(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) flashaddr = BOOTLD_START;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) for (i = 0; i < size; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) data = cpu_to_le64(ptr64[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) if (qla82xx_pci_mem_write_2M(ha, flashaddr, &data, 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) flashaddr += 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) flashaddr = FLASH_ADDR_START;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) size = qla82xx_get_fw_size(ha) / 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) ptr64 = (u64 *)qla82xx_get_fw_offs(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) for (i = 0; i < size; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) data = cpu_to_le64(ptr64[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) if (qla82xx_pci_mem_write_2M(ha, flashaddr, &data, 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) flashaddr += 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) /* Write a magic value to CAMRAM register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) * at a specified offset to indicate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) * that all data is written and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) * ready for firmware to initialize.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) qla82xx_wr_32(ha, QLA82XX_CAM_RAM(0x1fc), QLA82XX_BDINFO_MAGIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) read_lock(&ha->hw_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x18, 0x1020);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001e);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) read_unlock(&ha->hw_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) qla82xx_set_product_offset(struct qla_hw_data *ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) struct qla82xx_uri_table_desc *ptab_desc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) const uint8_t *unirom = ha->hablob->fw->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) uint32_t i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) uint32_t entries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) uint32_t flags, file_chiprev, offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) uint8_t chiprev = ha->chip_revision;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) /* Hardcoding mn_present flag for P3P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) int mn_present = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) uint32_t flagbit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) ptab_desc = qla82xx_get_table_desc(unirom,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) QLA82XX_URI_DIR_SECT_PRODUCT_TBL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) if (!ptab_desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) entries = le32_to_cpu(ptab_desc->num_entries);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) for (i = 0; i < entries; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) offset = le32_to_cpu(ptab_desc->findex) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) (i * le32_to_cpu(ptab_desc->entry_size));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) flags = le32_to_cpu(*((__le32 *)&unirom[offset] +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) QLA82XX_URI_FLAGS_OFF));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) file_chiprev = le32_to_cpu(*((__le32 *)&unirom[offset] +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) QLA82XX_URI_CHIP_REV_OFF));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) flagbit = mn_present ? 1 : 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) if ((chiprev == file_chiprev) && ((1ULL << flagbit) & flags)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) ha->file_prd_off = offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) qla82xx_validate_firmware_blob(scsi_qla_host_t *vha, uint8_t fw_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) uint32_t val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) uint32_t min_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) const struct firmware *fw = ha->hablob->fw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) ha->fw_type = fw_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) if (fw_type == QLA82XX_UNIFIED_ROMIMAGE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) if (qla82xx_set_product_offset(ha))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) min_size = QLA82XX_URI_FW_MIN_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) val = get_unaligned_le32(&fw->data[QLA82XX_FW_MAGIC_OFFSET]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) if (val != QLA82XX_BDINFO_MAGIC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) min_size = QLA82XX_FW_MIN_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) if (fw->size < min_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) qla82xx_check_cmdpeg_state(struct qla_hw_data *ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) int retries = 60;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) read_lock(&ha->hw_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) val = qla82xx_rd_32(ha, CRB_CMDPEG_STATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) read_unlock(&ha->hw_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) switch (val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) case PHAN_INITIALIZE_COMPLETE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) case PHAN_INITIALIZE_ACK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) return QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) case PHAN_INITIALIZE_FAILED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) ql_log(ql_log_info, vha, 0x00a8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) "CRB_CMDPEG_STATE: 0x%x and retries:0x%x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) val, retries);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) msleep(500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) } while (--retries);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) ql_log(ql_log_fatal, vha, 0x00a9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) "Cmd Peg initialization failed: 0x%x.\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) val = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_PEGTUNE_DONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) read_lock(&ha->hw_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) qla82xx_wr_32(ha, CRB_CMDPEG_STATE, PHAN_INITIALIZE_FAILED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) read_unlock(&ha->hw_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) return QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) qla82xx_check_rcvpeg_state(struct qla_hw_data *ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) int retries = 60;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) read_lock(&ha->hw_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) val = qla82xx_rd_32(ha, CRB_RCVPEG_STATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) read_unlock(&ha->hw_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) switch (val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) case PHAN_INITIALIZE_COMPLETE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) case PHAN_INITIALIZE_ACK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) return QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) case PHAN_INITIALIZE_FAILED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) ql_log(ql_log_info, vha, 0x00ab,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) "CRB_RCVPEG_STATE: 0x%x and retries: 0x%x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) val, retries);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) msleep(500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) } while (--retries);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) ql_log(ql_log_fatal, vha, 0x00ac,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) "Rcv Peg initialization failed: 0x%x.\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) read_lock(&ha->hw_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) qla82xx_wr_32(ha, CRB_RCVPEG_STATE, PHAN_INITIALIZE_FAILED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) read_unlock(&ha->hw_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) return QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) /* ISR related functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) static struct qla82xx_legacy_intr_set legacy_intr[] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) QLA82XX_LEGACY_INTR_CONFIG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) * qla82xx_mbx_completion() - Process mailbox command completions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) * @ha: SCSI driver HA context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) * @mb0: Mailbox0 register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) qla82xx_mbx_completion(scsi_qla_host_t *vha, uint16_t mb0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) uint16_t cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) __le16 __iomem *wptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) struct device_reg_82xx __iomem *reg = &ha->iobase->isp82;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) wptr = ®->mailbox_out[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) /* Load return mailbox registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) ha->flags.mbox_int = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) ha->mailbox_out[0] = mb0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) for (cnt = 1; cnt < ha->mbx_count; cnt++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) ha->mailbox_out[cnt] = rd_reg_word(wptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) wptr++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) if (!ha->mcp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) ql_dbg(ql_dbg_async, vha, 0x5053,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) "MBX pointer ERROR.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) * qla82xx_intr_handler() - Process interrupts for the ISP23xx and ISP63xx.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) * @irq: interrupt number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) * @dev_id: SCSI driver HA context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) * Called by system whenever the host adapter generates an interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) * Returns handled flag.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) irqreturn_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) qla82xx_intr_handler(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) scsi_qla_host_t *vha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) struct qla_hw_data *ha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) struct rsp_que *rsp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) struct device_reg_82xx __iomem *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) int status = 0, status1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) unsigned long iter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) uint32_t stat = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) uint16_t mb[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) rsp = (struct rsp_que *) dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) if (!rsp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) ql_log(ql_log_info, NULL, 0xb053,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) "%s: NULL response queue pointer.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) ha = rsp->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) if (!ha->flags.msi_enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) status = qla82xx_rd_32(ha, ISR_INT_VECTOR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) if (!(status & ha->nx_legacy_intr.int_vec_bit))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) status1 = qla82xx_rd_32(ha, ISR_INT_STATE_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) if (!ISR_IS_LEGACY_INTR_TRIGGERED(status1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) /* clear the interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_status_reg, 0xffffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) /* read twice to ensure write is flushed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) qla82xx_rd_32(ha, ISR_INT_VECTOR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) qla82xx_rd_32(ha, ISR_INT_VECTOR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) reg = &ha->iobase->isp82;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) spin_lock_irqsave(&ha->hardware_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) vha = pci_get_drvdata(ha->pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) for (iter = 1; iter--; ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) if (rd_reg_dword(®->host_int)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) stat = rd_reg_dword(®->host_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) switch (stat & 0xff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) case 0x1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) case 0x2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) case 0x10:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) case 0x11:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) qla82xx_mbx_completion(vha, MSW(stat));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) status |= MBX_INTERRUPT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) case 0x12:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) mb[0] = MSW(stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) mb[1] = rd_reg_word(®->mailbox_out[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) mb[2] = rd_reg_word(®->mailbox_out[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) mb[3] = rd_reg_word(®->mailbox_out[3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) qla2x00_async_event(vha, rsp, mb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) case 0x13:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) qla24xx_process_response_queue(vha, rsp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) ql_dbg(ql_dbg_async, vha, 0x5054,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) "Unrecognized interrupt type (%d).\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) stat & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) wrt_reg_dword(®->host_int, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) qla2x00_handle_mbx_completion(ha, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) spin_unlock_irqrestore(&ha->hardware_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) if (!ha->flags.msi_enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) irqreturn_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) qla82xx_msix_default(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) scsi_qla_host_t *vha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) struct qla_hw_data *ha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) struct rsp_que *rsp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) struct device_reg_82xx __iomem *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) int status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) uint32_t stat = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) uint32_t host_int = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) uint16_t mb[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) rsp = (struct rsp_que *) dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) if (!rsp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) printk(KERN_INFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) "%s(): NULL response queue pointer.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) ha = rsp->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) reg = &ha->iobase->isp82;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) spin_lock_irqsave(&ha->hardware_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) vha = pci_get_drvdata(ha->pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) host_int = rd_reg_dword(®->host_int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) if (qla2x00_check_reg32_for_disconnect(vha, host_int))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) if (host_int) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) stat = rd_reg_dword(®->host_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) switch (stat & 0xff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) case 0x1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) case 0x2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) case 0x10:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) case 0x11:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) qla82xx_mbx_completion(vha, MSW(stat));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) status |= MBX_INTERRUPT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) case 0x12:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) mb[0] = MSW(stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) mb[1] = rd_reg_word(®->mailbox_out[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) mb[2] = rd_reg_word(®->mailbox_out[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) mb[3] = rd_reg_word(®->mailbox_out[3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) qla2x00_async_event(vha, rsp, mb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) case 0x13:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) qla24xx_process_response_queue(vha, rsp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) ql_dbg(ql_dbg_async, vha, 0x5041,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) "Unrecognized interrupt type (%d).\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) stat & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) wrt_reg_dword(®->host_int, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) } while (0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) qla2x00_handle_mbx_completion(ha, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) spin_unlock_irqrestore(&ha->hardware_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) irqreturn_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) qla82xx_msix_rsp_q(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) scsi_qla_host_t *vha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) struct qla_hw_data *ha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) struct rsp_que *rsp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) struct device_reg_82xx __iomem *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) uint32_t host_int = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) rsp = (struct rsp_que *) dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) if (!rsp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) printk(KERN_INFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) "%s(): NULL response queue pointer.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) ha = rsp->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) reg = &ha->iobase->isp82;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) spin_lock_irqsave(&ha->hardware_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) vha = pci_get_drvdata(ha->pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) host_int = rd_reg_dword(®->host_int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) if (qla2x00_check_reg32_for_disconnect(vha, host_int))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) qla24xx_process_response_queue(vha, rsp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) wrt_reg_dword(®->host_int, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) spin_unlock_irqrestore(&ha->hardware_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) qla82xx_poll(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) scsi_qla_host_t *vha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) struct qla_hw_data *ha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) struct rsp_que *rsp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) struct device_reg_82xx __iomem *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) int status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) uint32_t stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) uint32_t host_int = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) uint16_t mb[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) rsp = (struct rsp_que *) dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) if (!rsp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) printk(KERN_INFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) "%s(): NULL response queue pointer.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) ha = rsp->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) reg = &ha->iobase->isp82;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) spin_lock_irqsave(&ha->hardware_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) vha = pci_get_drvdata(ha->pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) host_int = rd_reg_dword(®->host_int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) if (qla2x00_check_reg32_for_disconnect(vha, host_int))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) if (host_int) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) stat = rd_reg_dword(®->host_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) switch (stat & 0xff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) case 0x1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) case 0x2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) case 0x10:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) case 0x11:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) qla82xx_mbx_completion(vha, MSW(stat));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) status |= MBX_INTERRUPT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) case 0x12:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) mb[0] = MSW(stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) mb[1] = rd_reg_word(®->mailbox_out[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) mb[2] = rd_reg_word(®->mailbox_out[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) mb[3] = rd_reg_word(®->mailbox_out[3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) qla2x00_async_event(vha, rsp, mb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) case 0x13:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) qla24xx_process_response_queue(vha, rsp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) ql_dbg(ql_dbg_p3p, vha, 0xb013,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) "Unrecognized interrupt type (%d).\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) stat * 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) wrt_reg_dword(®->host_int, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) spin_unlock_irqrestore(&ha->hardware_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) qla82xx_enable_intrs(struct qla_hw_data *ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) qla82xx_mbx_intr_enable(vha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) spin_lock_irq(&ha->hardware_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) if (IS_QLA8044(ha))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) qla8044_wr_reg(ha, LEG_INTR_MASK_OFFSET, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) spin_unlock_irq(&ha->hardware_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) ha->interrupts_on = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) qla82xx_disable_intrs(struct qla_hw_data *ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) if (ha->interrupts_on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) qla82xx_mbx_intr_disable(vha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) spin_lock_irq(&ha->hardware_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) if (IS_QLA8044(ha))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) qla8044_wr_reg(ha, LEG_INTR_MASK_OFFSET, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0x0400);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) spin_unlock_irq(&ha->hardware_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) ha->interrupts_on = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) void qla82xx_init_flags(struct qla_hw_data *ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) struct qla82xx_legacy_intr_set *nx_legacy_intr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) /* ISP 8021 initializations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) rwlock_init(&ha->hw_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) ha->qdr_sn_window = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) ha->ddr_mn_window = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) ha->curr_window = 255;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) ha->portnum = PCI_FUNC(ha->pdev->devfn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) nx_legacy_intr = &legacy_intr[ha->portnum];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) ha->nx_legacy_intr.int_vec_bit = nx_legacy_intr->int_vec_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) ha->nx_legacy_intr.tgt_status_reg = nx_legacy_intr->tgt_status_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) ha->nx_legacy_intr.tgt_mask_reg = nx_legacy_intr->tgt_mask_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) ha->nx_legacy_intr.pci_int_reg = nx_legacy_intr->pci_int_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) qla82xx_set_idc_version(scsi_qla_host_t *vha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) int idc_ver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) uint32_t drv_active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) if (drv_active == (QLA82XX_DRV_ACTIVE << (ha->portnum * 4))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) QLA82XX_IDC_VERSION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) ql_log(ql_log_info, vha, 0xb082,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) "IDC version updated to %d\n", QLA82XX_IDC_VERSION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) idc_ver = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_IDC_VERSION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) if (idc_ver != QLA82XX_IDC_VERSION)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) ql_log(ql_log_info, vha, 0xb083,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) "qla2xxx driver IDC version %d is not compatible "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) "with IDC version %d of the other drivers\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) QLA82XX_IDC_VERSION, idc_ver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) qla82xx_set_drv_active(scsi_qla_host_t *vha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) uint32_t drv_active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) /* If reset value is all FF's, initialize DRV_ACTIVE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) if (drv_active == 0xffffffff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) QLA82XX_DRV_NOT_ACTIVE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) drv_active |= (QLA82XX_DRV_ACTIVE << (ha->portnum * 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, drv_active);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) qla82xx_clear_drv_active(struct qla_hw_data *ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) uint32_t drv_active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) drv_active &= ~(QLA82XX_DRV_ACTIVE << (ha->portnum * 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, drv_active);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) static inline int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) qla82xx_need_reset(struct qla_hw_data *ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) uint32_t drv_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) int rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) if (ha->flags.nic_core_reset_owner)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) rval = drv_state & (QLA82XX_DRVST_RST_RDY << (ha->portnum * 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) qla82xx_set_rst_ready(struct qla_hw_data *ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) uint32_t drv_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) /* If reset value is all FF's, initialize DRV_STATE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) if (drv_state == 0xffffffff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, QLA82XX_DRVST_NOT_RDY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) drv_state |= (QLA82XX_DRVST_RST_RDY << (ha->portnum * 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) ql_dbg(ql_dbg_init, vha, 0x00bb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) "drv_state = 0x%08x.\n", drv_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, drv_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) qla82xx_clear_rst_ready(struct qla_hw_data *ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) uint32_t drv_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) drv_state &= ~(QLA82XX_DRVST_RST_RDY << (ha->portnum * 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, drv_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) qla82xx_set_qsnt_ready(struct qla_hw_data *ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) uint32_t qsnt_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) qsnt_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) qsnt_state |= (QLA82XX_DRVST_QSNT_RDY << (ha->portnum * 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, qsnt_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) qla82xx_clear_qsnt_ready(scsi_qla_host_t *vha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) uint32_t qsnt_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) qsnt_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) qsnt_state &= ~(QLA82XX_DRVST_QSNT_RDY << (ha->portnum * 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, qsnt_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) qla82xx_load_fw(scsi_qla_host_t *vha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) int rst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) struct fw_blob *blob;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) if (qla82xx_pinit_from_rom(vha) != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) ql_log(ql_log_fatal, vha, 0x009f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) "Error during CRB initialization.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) return QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) udelay(500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) /* Bring QM and CAMRAM out of reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) rst = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) rst &= ~((1 << 28) | (1 << 24));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) * FW Load priority:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) * 1) Operational firmware residing in flash.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) * 2) Firmware via request-firmware interface (.bin file).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) if (ql2xfwloadbin == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) goto try_blob_fw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) ql_log(ql_log_info, vha, 0x00a0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) "Attempting to load firmware from flash.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) if (qla82xx_fw_load_from_flash(ha) == QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) ql_log(ql_log_info, vha, 0x00a1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) "Firmware loaded successfully from flash.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) return QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) ql_log(ql_log_warn, vha, 0x0108,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) "Firmware load from flash failed.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) try_blob_fw:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) ql_log(ql_log_info, vha, 0x00a2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) "Attempting to load firmware from blob.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) /* Load firmware blob. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) blob = ha->hablob = qla2x00_request_firmware(vha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) if (!blob) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) ql_log(ql_log_fatal, vha, 0x00a3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) "Firmware image not present.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) goto fw_load_failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) /* Validating firmware blob */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) if (qla82xx_validate_firmware_blob(vha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) QLA82XX_FLASH_ROMIMAGE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) /* Fallback to URI format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) if (qla82xx_validate_firmware_blob(vha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) QLA82XX_UNIFIED_ROMIMAGE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) ql_log(ql_log_fatal, vha, 0x00a4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) "No valid firmware image found.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) return QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) if (qla82xx_fw_load_from_blob(ha) == QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) ql_log(ql_log_info, vha, 0x00a5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) "Firmware loaded successfully from binary blob.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) return QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) ql_log(ql_log_fatal, vha, 0x00a6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) "Firmware load failed for binary blob.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) blob->fw = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) blob = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) fw_load_failed:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) return QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) qla82xx_start_firmware(scsi_qla_host_t *vha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) uint16_t lnk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) /* scrub dma mask expansion register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) qla82xx_wr_32(ha, CRB_DMA_SHIFT, QLA82XX_DMA_SHIFT_VALUE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) /* Put both the PEG CMD and RCV PEG to default state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) * of 0 before resetting the hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) qla82xx_wr_32(ha, CRB_CMDPEG_STATE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) qla82xx_wr_32(ha, CRB_RCVPEG_STATE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) /* Overwrite stale initialization register values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) qla82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) qla82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) if (qla82xx_load_fw(vha) != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) ql_log(ql_log_fatal, vha, 0x00a7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) "Error trying to start fw.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) return QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) /* Handshake with the card before we register the devices. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) if (qla82xx_check_cmdpeg_state(ha) != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) ql_log(ql_log_fatal, vha, 0x00aa,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) "Error during card handshake.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) return QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) /* Negotiated Link width */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) pcie_capability_read_word(ha->pdev, PCI_EXP_LNKSTA, &lnk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) ha->link_width = (lnk >> 4) & 0x3f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) /* Synchronize with Receive peg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) return qla82xx_check_rcvpeg_state(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) static __le32 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) qla82xx_read_flash_data(scsi_qla_host_t *vha, __le32 *dwptr, uint32_t faddr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) uint32_t length)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) uint32_t i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) uint32_t val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) /* Dword reads to flash. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) for (i = 0; i < length/4; i++, faddr += 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) if (qla82xx_rom_fast_read(ha, faddr, &val)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) ql_log(ql_log_warn, vha, 0x0106,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) "Do ROM fast read failed.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) goto done_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) dwptr[i] = cpu_to_le32(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) done_read:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) return dwptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530) qla82xx_unprotect_flash(struct qla_hw_data *ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) uint32_t val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) ret = ql82xx_rom_lock_d(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) ql_log(ql_log_warn, vha, 0xb014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) "ROM Lock failed.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) ret = qla82xx_read_status_reg(ha, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) goto done_unprotect;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) val &= ~(BLOCK_PROTECT_BITS << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) ret = qla82xx_write_status_reg(ha, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) val |= (BLOCK_PROTECT_BITS << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) qla82xx_write_status_reg(ha, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) if (qla82xx_write_disable_flash(ha) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) ql_log(ql_log_warn, vha, 0xb015,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) "Write disable failed.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) done_unprotect:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559) qla82xx_rom_unlock(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) qla82xx_protect_flash(struct qla_hw_data *ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567) uint32_t val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) ret = ql82xx_rom_lock_d(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) ql_log(ql_log_warn, vha, 0xb016,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) "ROM Lock failed.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) ret = qla82xx_read_status_reg(ha, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579) goto done_protect;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) val |= (BLOCK_PROTECT_BITS << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) /* LOCK all sectors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583) ret = qla82xx_write_status_reg(ha, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) ql_log(ql_log_warn, vha, 0xb017,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) "Write status register failed.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588) if (qla82xx_write_disable_flash(ha) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589) ql_log(ql_log_warn, vha, 0xb018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) "Write disable failed.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) done_protect:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592) qla82xx_rom_unlock(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) qla82xx_erase_sector(struct qla_hw_data *ha, int addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) ret = ql82xx_rom_lock_d(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) ql_log(ql_log_warn, vha, 0xb019,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605) "ROM Lock failed.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609) qla82xx_flash_set_write_enable(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612) qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_SE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614) if (qla82xx_wait_rom_done(ha)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615) ql_log(ql_log_warn, vha, 0xb01a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616) "Error waiting for rom done.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617) ret = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620) ret = qla82xx_flash_wait_write_finish(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621) done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622) qla82xx_rom_unlock(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) * Address and length are byte address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629) void *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630) qla82xx_read_optrom_data(struct scsi_qla_host *vha, void *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631) uint32_t offset, uint32_t length)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) scsi_block_requests(vha->host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634) qla82xx_read_flash_data(vha, buf, offset, length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635) scsi_unblock_requests(vha->host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636) return buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640) qla82xx_write_flash_data(struct scsi_qla_host *vha, __le32 *dwptr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641) uint32_t faddr, uint32_t dwords)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644) uint32_t liter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645) uint32_t rest_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646) dma_addr_t optrom_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647) void *optrom = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648) int page_mode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651) ret = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653) /* Prepare burst-capable write on supported ISPs. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654) if (page_mode && !(faddr & 0xfff) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655) dwords > OPTROM_BURST_DWORDS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656) optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657) &optrom_dma, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658) if (!optrom) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659) ql_log(ql_log_warn, vha, 0xb01b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660) "Unable to allocate memory "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661) "for optrom burst write (%x KB).\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662) OPTROM_BURST_SIZE / 1024);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666) rest_addr = ha->fdt_block_size - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668) ret = qla82xx_unprotect_flash(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670) ql_log(ql_log_warn, vha, 0xb01c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671) "Unable to unprotect flash for update.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672) goto write_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675) for (liter = 0; liter < dwords; liter++, faddr += 4, dwptr++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676) /* Are we at the beginning of a sector? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677) if ((faddr & rest_addr) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679) ret = qla82xx_erase_sector(ha, faddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681) ql_log(ql_log_warn, vha, 0xb01d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682) "Unable to erase sector: address=%x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683) faddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688) /* Go with burst-write. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689) if (optrom && (liter + OPTROM_BURST_DWORDS) <= dwords) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690) /* Copy data to DMA'ble buffer. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691) memcpy(optrom, dwptr, OPTROM_BURST_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693) ret = qla2x00_load_ram(vha, optrom_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694) (ha->flash_data_off | faddr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695) OPTROM_BURST_DWORDS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696) if (ret != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697) ql_log(ql_log_warn, vha, 0xb01e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698) "Unable to burst-write optrom segment "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699) "(%x/%x/%llx).\n", ret,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700) (ha->flash_data_off | faddr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701) (unsigned long long)optrom_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702) ql_log(ql_log_warn, vha, 0xb01f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703) "Reverting to slow-write.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705) dma_free_coherent(&ha->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706) OPTROM_BURST_SIZE, optrom, optrom_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707) optrom = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709) liter += OPTROM_BURST_DWORDS - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710) faddr += OPTROM_BURST_DWORDS - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711) dwptr += OPTROM_BURST_DWORDS - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716) ret = qla82xx_write_flash_dword(ha, faddr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717) le32_to_cpu(*dwptr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2719) ql_dbg(ql_dbg_p3p, vha, 0xb020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2720) "Unable to program flash address=%x data=%x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2721) faddr, *dwptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2722) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2723) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2724) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2726) ret = qla82xx_protect_flash(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2727) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2728) ql_log(ql_log_warn, vha, 0xb021,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2729) "Unable to protect flash after update.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2730) write_done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2731) if (optrom)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2732) dma_free_coherent(&ha->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2733) OPTROM_BURST_SIZE, optrom, optrom_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2734) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2735) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2737) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2738) qla82xx_write_optrom_data(struct scsi_qla_host *vha, void *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2739) uint32_t offset, uint32_t length)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2740) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2741) int rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2743) /* Suspend HBA. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2744) scsi_block_requests(vha->host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2745) rval = qla82xx_write_flash_data(vha, buf, offset, length >> 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2746) scsi_unblock_requests(vha->host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2748) /* Convert return ISP82xx to generic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2749) if (rval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2750) rval = QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2751) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2752) rval = QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2753) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2754) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2756) void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2757) qla82xx_start_iocbs(scsi_qla_host_t *vha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2758) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2759) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2760) struct req_que *req = ha->req_q_map[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2761) uint32_t dbval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2763) /* Adjust ring index. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2764) req->ring_index++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2765) if (req->ring_index == req->length) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2766) req->ring_index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2767) req->ring_ptr = req->ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2768) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2769) req->ring_ptr++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2771) dbval = 0x04 | (ha->portnum << 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2773) dbval = dbval | (req->id << 8) | (req->ring_index << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2774) if (ql2xdbwr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2775) qla82xx_wr_32(ha, (unsigned long)ha->nxdb_wr_ptr, dbval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2776) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2777) wrt_reg_dword(ha->nxdb_wr_ptr, dbval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2778) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2779) while (rd_reg_dword(ha->nxdb_rd_ptr) != dbval) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2780) wrt_reg_dword(ha->nxdb_wr_ptr, dbval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2781) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2782) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2783) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2784) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2786) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2787) qla82xx_rom_lock_recovery(struct qla_hw_data *ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2788) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2789) scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2790) uint32_t lock_owner = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2792) if (qla82xx_rom_lock(ha)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2793) lock_owner = qla82xx_rd_32(ha, QLA82XX_ROM_LOCK_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2794) /* Someone else is holding the lock. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2795) ql_log(ql_log_info, vha, 0xb022,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2796) "Resetting rom_lock, Lock Owner %u.\n", lock_owner);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2797) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2798) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2799) * Either we got the lock, or someone
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2800) * else died while holding it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2801) * In either case, unlock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2802) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2803) qla82xx_rom_unlock(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2804) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2806) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2807) * qla82xx_device_bootstrap
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2808) * Initialize device, set DEV_READY, start fw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2809) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2810) * Note:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2811) * IDC lock must be held upon entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2812) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2813) * Return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2814) * Success : 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2815) * Failed : 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2816) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2817) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2818) qla82xx_device_bootstrap(scsi_qla_host_t *vha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2819) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2820) int rval = QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2821) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2822) uint32_t old_count, count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2823) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2824) int need_reset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2826) need_reset = qla82xx_need_reset(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2828) if (need_reset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2829) /* We are trying to perform a recovery here. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2830) if (ha->flags.isp82xx_fw_hung)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2831) qla82xx_rom_lock_recovery(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2832) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2833) old_count = qla82xx_rd_32(ha, QLA82XX_PEG_ALIVE_COUNTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2834) for (i = 0; i < 10; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2835) msleep(200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2836) count = qla82xx_rd_32(ha, QLA82XX_PEG_ALIVE_COUNTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2837) if (count != old_count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2838) rval = QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2839) goto dev_ready;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2840) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2841) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2842) qla82xx_rom_lock_recovery(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2843) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2845) /* set to DEV_INITIALIZING */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2846) ql_log(ql_log_info, vha, 0x009e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2847) "HW State: INITIALIZING.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2848) qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_INITIALIZING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2850) qla82xx_idc_unlock(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2851) rval = qla82xx_start_firmware(vha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2852) qla82xx_idc_lock(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2854) if (rval != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2855) ql_log(ql_log_fatal, vha, 0x00ad,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2856) "HW State: FAILED.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2857) qla82xx_clear_drv_active(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2858) qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_FAILED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2859) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2860) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2862) dev_ready:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2863) ql_log(ql_log_info, vha, 0x00ae,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2864) "HW State: READY.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2865) qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_READY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2867) return QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2868) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2870) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2871) * qla82xx_need_qsnt_handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2872) * Code to start quiescence sequence
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2873) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2874) * Note:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2875) * IDC lock must be held upon entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2876) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2877) * Return: void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2878) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2880) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2881) qla82xx_need_qsnt_handler(scsi_qla_host_t *vha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2882) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2883) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2884) uint32_t dev_state, drv_state, drv_active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2885) unsigned long reset_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2887) if (vha->flags.online) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2888) /*Block any further I/O and wait for pending cmnds to complete*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2889) qla2x00_quiesce_io(vha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2890) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2892) /* Set the quiescence ready bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2893) qla82xx_set_qsnt_ready(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2895) /*wait for 30 secs for other functions to ack */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2896) reset_timeout = jiffies + (30 * HZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2898) drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2899) drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2900) /* Its 2 that is written when qsnt is acked, moving one bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2901) drv_active = drv_active << 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2903) while (drv_state != drv_active) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2905) if (time_after_eq(jiffies, reset_timeout)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2906) /* quiescence timeout, other functions didn't ack
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2907) * changing the state to DEV_READY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2908) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2909) ql_log(ql_log_info, vha, 0xb023,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2910) "%s : QUIESCENT TIMEOUT DRV_ACTIVE:%d "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2911) "DRV_STATE:%d.\n", QLA2XXX_DRIVER_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2912) drv_active, drv_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2913) qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2914) QLA8XXX_DEV_READY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2915) ql_log(ql_log_info, vha, 0xb025,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2916) "HW State: DEV_READY.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2917) qla82xx_idc_unlock(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2918) qla2x00_perform_loop_resync(vha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2919) qla82xx_idc_lock(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2921) qla82xx_clear_qsnt_ready(vha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2922) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2923) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2925) qla82xx_idc_unlock(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2926) msleep(1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2927) qla82xx_idc_lock(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2929) drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2930) drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2931) drv_active = drv_active << 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2932) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2933) dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2934) /* everyone acked so set the state to DEV_QUIESCENCE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2935) if (dev_state == QLA8XXX_DEV_NEED_QUIESCENT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2936) ql_log(ql_log_info, vha, 0xb026,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2937) "HW State: DEV_QUIESCENT.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2938) qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_QUIESCENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2939) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2940) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2942) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2943) * qla82xx_wait_for_state_change
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2944) * Wait for device state to change from given current state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2945) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2946) * Note:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2947) * IDC lock must not be held upon entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2948) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2949) * Return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2950) * Changed device state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2951) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2952) uint32_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2953) qla82xx_wait_for_state_change(scsi_qla_host_t *vha, uint32_t curr_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2954) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2955) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2956) uint32_t dev_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2958) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2959) msleep(1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2960) qla82xx_idc_lock(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2961) dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2962) qla82xx_idc_unlock(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2963) } while (dev_state == curr_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2965) return dev_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2966) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2968) void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2969) qla8xxx_dev_failed_handler(scsi_qla_host_t *vha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2970) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2971) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2973) /* Disable the board */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2974) ql_log(ql_log_fatal, vha, 0x00b8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2975) "Disabling the board.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2977) if (IS_QLA82XX(ha)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2978) qla82xx_clear_drv_active(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2979) qla82xx_idc_unlock(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2980) } else if (IS_QLA8044(ha)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2981) qla8044_clear_drv_active(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2982) qla8044_idc_unlock(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2983) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2985) /* Set DEV_FAILED flag to disable timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2986) vha->device_flags |= DFLG_DEV_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2987) qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2988) qla2x00_mark_all_devices_lost(vha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2989) vha->flags.online = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2990) vha->flags.init_done = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2991) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2993) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2994) * qla82xx_need_reset_handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2995) * Code to start reset sequence
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2996) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2997) * Note:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2998) * IDC lock must be held upon entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2999) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3000) * Return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3001) * Success : 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3002) * Failed : 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3003) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3004) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3005) qla82xx_need_reset_handler(scsi_qla_host_t *vha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3006) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3007) uint32_t dev_state, drv_state, drv_active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3008) uint32_t active_mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3009) unsigned long reset_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3010) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3011) struct req_que *req = ha->req_q_map[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3013) if (vha->flags.online) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3014) qla82xx_idc_unlock(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3015) qla2x00_abort_isp_cleanup(vha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3016) ha->isp_ops->get_flash_version(vha, req->ring);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3017) ha->isp_ops->nvram_config(vha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3018) qla82xx_idc_lock(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3019) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3021) drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3022) if (!ha->flags.nic_core_reset_owner) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3023) ql_dbg(ql_dbg_p3p, vha, 0xb028,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3024) "reset_acknowledged by 0x%x\n", ha->portnum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3025) qla82xx_set_rst_ready(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3026) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3027) active_mask = ~(QLA82XX_DRV_ACTIVE << (ha->portnum * 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3028) drv_active &= active_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3029) ql_dbg(ql_dbg_p3p, vha, 0xb029,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3030) "active_mask: 0x%08x\n", active_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3031) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3033) /* wait for 10 seconds for reset ack from all functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3034) reset_timeout = jiffies + (ha->fcoe_reset_timeout * HZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3036) drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3037) drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3038) dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3040) ql_dbg(ql_dbg_p3p, vha, 0xb02a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3041) "drv_state: 0x%08x, drv_active: 0x%08x, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3042) "dev_state: 0x%08x, active_mask: 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3043) drv_state, drv_active, dev_state, active_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3045) while (drv_state != drv_active &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3046) dev_state != QLA8XXX_DEV_INITIALIZING) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3047) if (time_after_eq(jiffies, reset_timeout)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3048) ql_log(ql_log_warn, vha, 0x00b5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3049) "Reset timeout.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3050) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3051) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3052) qla82xx_idc_unlock(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3053) msleep(1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3054) qla82xx_idc_lock(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3055) drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3056) drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3057) if (ha->flags.nic_core_reset_owner)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3058) drv_active &= active_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3059) dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3060) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3062) ql_dbg(ql_dbg_p3p, vha, 0xb02b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3063) "drv_state: 0x%08x, drv_active: 0x%08x, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3064) "dev_state: 0x%08x, active_mask: 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3065) drv_state, drv_active, dev_state, active_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3067) ql_log(ql_log_info, vha, 0x00b6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3068) "Device state is 0x%x = %s.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3069) dev_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3070) dev_state < MAX_STATES ? qdev_state(dev_state) : "Unknown");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3072) /* Force to DEV_COLD unless someone else is starting a reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3073) if (dev_state != QLA8XXX_DEV_INITIALIZING &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3074) dev_state != QLA8XXX_DEV_COLD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3075) ql_log(ql_log_info, vha, 0x00b7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3076) "HW State: COLD/RE-INIT.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3077) qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_COLD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3078) qla82xx_set_rst_ready(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3079) if (ql2xmdenable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3080) if (qla82xx_md_collect(vha))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3081) ql_log(ql_log_warn, vha, 0xb02c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3082) "Minidump not collected.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3083) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3084) ql_log(ql_log_warn, vha, 0xb04f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3085) "Minidump disabled.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3086) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3087) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3089) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3090) qla82xx_check_md_needed(scsi_qla_host_t *vha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3091) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3092) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3093) uint16_t fw_major_version, fw_minor_version, fw_subminor_version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3094) int rval = QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3096) fw_major_version = ha->fw_major_version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3097) fw_minor_version = ha->fw_minor_version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3098) fw_subminor_version = ha->fw_subminor_version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3100) rval = qla2x00_get_fw_version(vha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3101) if (rval != QLA_SUCCESS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3102) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3104) if (ql2xmdenable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3105) if (!ha->fw_dumped) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3106) if ((fw_major_version != ha->fw_major_version ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3107) fw_minor_version != ha->fw_minor_version ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3108) fw_subminor_version != ha->fw_subminor_version) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3109) (ha->prev_minidump_failed)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3110) ql_dbg(ql_dbg_p3p, vha, 0xb02d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3111) "Firmware version differs Previous version: %d:%d:%d - New version: %d:%d:%d, prev_minidump_failed: %d.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3112) fw_major_version, fw_minor_version,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3113) fw_subminor_version,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3114) ha->fw_major_version,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3115) ha->fw_minor_version,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3116) ha->fw_subminor_version,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3117) ha->prev_minidump_failed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3118) /* Release MiniDump resources */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3119) qla82xx_md_free(vha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3120) /* ALlocate MiniDump resources */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3121) qla82xx_md_prep(vha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3123) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3124) ql_log(ql_log_info, vha, 0xb02e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3125) "Firmware dump available to retrieve\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3127) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3131) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3132) qla82xx_check_fw_alive(scsi_qla_host_t *vha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3133) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3134) uint32_t fw_heartbeat_counter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3135) int status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3137) fw_heartbeat_counter = qla82xx_rd_32(vha->hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3138) QLA82XX_PEG_ALIVE_COUNTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3139) /* all 0xff, assume AER/EEH in progress, ignore */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3140) if (fw_heartbeat_counter == 0xffffffff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3141) ql_dbg(ql_dbg_timer, vha, 0x6003,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3142) "FW heartbeat counter is 0xffffffff, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3143) "returning status=%d.\n", status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3144) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3146) if (vha->fw_heartbeat_counter == fw_heartbeat_counter) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3147) vha->seconds_since_last_heartbeat++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3148) /* FW not alive after 2 seconds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3149) if (vha->seconds_since_last_heartbeat == 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3150) vha->seconds_since_last_heartbeat = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3151) status = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3153) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3154) vha->seconds_since_last_heartbeat = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3155) vha->fw_heartbeat_counter = fw_heartbeat_counter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3156) if (status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3157) ql_dbg(ql_dbg_timer, vha, 0x6004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3158) "Returning status=%d.\n", status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3159) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3162) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3163) * qla82xx_device_state_handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3164) * Main state handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3165) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3166) * Note:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3167) * IDC lock must be held upon entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3168) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3169) * Return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3170) * Success : 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3171) * Failed : 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3172) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3173) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3174) qla82xx_device_state_handler(scsi_qla_host_t *vha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3175) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3176) uint32_t dev_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3177) uint32_t old_dev_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3178) int rval = QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3179) unsigned long dev_init_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3180) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3181) int loopcount = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3183) qla82xx_idc_lock(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3184) if (!vha->flags.init_done) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3185) qla82xx_set_drv_active(vha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3186) qla82xx_set_idc_version(vha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3189) dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3190) old_dev_state = dev_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3191) ql_log(ql_log_info, vha, 0x009b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3192) "Device state is 0x%x = %s.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3193) dev_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3194) dev_state < MAX_STATES ? qdev_state(dev_state) : "Unknown");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3196) /* wait for 30 seconds for device to go ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3197) dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3199) while (1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3201) if (time_after_eq(jiffies, dev_init_timeout)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3202) ql_log(ql_log_fatal, vha, 0x009c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3203) "Device init failed.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3204) rval = QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3205) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3207) dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3208) if (old_dev_state != dev_state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3209) loopcount = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3210) old_dev_state = dev_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3212) if (loopcount < 5) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3213) ql_log(ql_log_info, vha, 0x009d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3214) "Device state is 0x%x = %s.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3215) dev_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3216) dev_state < MAX_STATES ? qdev_state(dev_state) :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3217) "Unknown");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3220) switch (dev_state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3221) case QLA8XXX_DEV_READY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3222) ha->flags.nic_core_reset_owner = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3223) goto rel_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3224) case QLA8XXX_DEV_COLD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3225) rval = qla82xx_device_bootstrap(vha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3226) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3227) case QLA8XXX_DEV_INITIALIZING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3228) qla82xx_idc_unlock(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3229) msleep(1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3230) qla82xx_idc_lock(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3231) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3232) case QLA8XXX_DEV_NEED_RESET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3233) if (!ql2xdontresethba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3234) qla82xx_need_reset_handler(vha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3235) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3236) qla82xx_idc_unlock(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3237) msleep(1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3238) qla82xx_idc_lock(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3240) dev_init_timeout = jiffies +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3241) (ha->fcoe_dev_init_timeout * HZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3242) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3243) case QLA8XXX_DEV_NEED_QUIESCENT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3244) qla82xx_need_qsnt_handler(vha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3245) /* Reset timeout value after quiescence handler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3246) dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3247) * HZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3248) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3249) case QLA8XXX_DEV_QUIESCENT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3250) /* Owner will exit and other will wait for the state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3251) * to get changed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3252) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3253) if (ha->flags.quiesce_owner)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3254) goto rel_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3256) qla82xx_idc_unlock(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3257) msleep(1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3258) qla82xx_idc_lock(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3260) /* Reset timeout value after quiescence handler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3261) dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3262) * HZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3263) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3264) case QLA8XXX_DEV_FAILED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3265) qla8xxx_dev_failed_handler(vha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3266) rval = QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3267) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3268) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3269) qla82xx_idc_unlock(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3270) msleep(1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3271) qla82xx_idc_lock(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3273) loopcount++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3275) rel_lock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3276) qla82xx_idc_unlock(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3277) exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3278) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3281) static int qla82xx_check_temp(scsi_qla_host_t *vha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3282) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3283) uint32_t temp, temp_state, temp_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3284) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3286) temp = qla82xx_rd_32(ha, CRB_TEMP_STATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3287) temp_state = qla82xx_get_temp_state(temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3288) temp_val = qla82xx_get_temp_val(temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3290) if (temp_state == QLA82XX_TEMP_PANIC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3291) ql_log(ql_log_warn, vha, 0x600e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3292) "Device temperature %d degrees C exceeds "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3293) " maximum allowed. Hardware has been shut down.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3294) temp_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3295) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3296) } else if (temp_state == QLA82XX_TEMP_WARN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3297) ql_log(ql_log_warn, vha, 0x600f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3298) "Device temperature %d degrees C exceeds "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3299) "operating range. Immediate action needed.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3300) temp_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3302) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3305) int qla82xx_read_temperature(scsi_qla_host_t *vha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3306) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3307) uint32_t temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3309) temp = qla82xx_rd_32(vha->hw, CRB_TEMP_STATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3310) return qla82xx_get_temp_val(temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3313) void qla82xx_clear_pending_mbx(scsi_qla_host_t *vha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3314) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3315) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3317) if (ha->flags.mbox_busy) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3318) ha->flags.mbox_int = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3319) ha->flags.mbox_busy = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3320) ql_log(ql_log_warn, vha, 0x6010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3321) "Doing premature completion of mbx command.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3322) if (test_and_clear_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3323) complete(&ha->mbx_intr_comp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3327) void qla82xx_watchdog(scsi_qla_host_t *vha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3328) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3329) uint32_t dev_state, halt_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3330) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3332) /* don't poll if reset is going on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3333) if (!ha->flags.nic_core_reset_hdlr_active) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3334) dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3335) if (qla82xx_check_temp(vha)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3336) set_bit(ISP_UNRECOVERABLE, &vha->dpc_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3337) ha->flags.isp82xx_fw_hung = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3338) qla82xx_clear_pending_mbx(vha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3339) } else if (dev_state == QLA8XXX_DEV_NEED_RESET &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3340) !test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3341) ql_log(ql_log_warn, vha, 0x6001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3342) "Adapter reset needed.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3343) set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3344) } else if (dev_state == QLA8XXX_DEV_NEED_QUIESCENT &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3345) !test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3346) ql_log(ql_log_warn, vha, 0x6002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3347) "Quiescent needed.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3348) set_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3349) } else if (dev_state == QLA8XXX_DEV_FAILED &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3350) !test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3351) vha->flags.online == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3352) ql_log(ql_log_warn, vha, 0xb055,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3353) "Adapter state is failed. Offlining.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3354) set_bit(ISP_UNRECOVERABLE, &vha->dpc_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3355) ha->flags.isp82xx_fw_hung = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3356) qla82xx_clear_pending_mbx(vha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3357) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3358) if (qla82xx_check_fw_alive(vha)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3359) ql_dbg(ql_dbg_timer, vha, 0x6011,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3360) "disabling pause transmit on port 0 & 1.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3361) qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x98,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3362) CRB_NIU_XG_PAUSE_CTL_P0|CRB_NIU_XG_PAUSE_CTL_P1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3363) halt_status = qla82xx_rd_32(ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3364) QLA82XX_PEG_HALT_STATUS1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3365) ql_log(ql_log_info, vha, 0x6005,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3366) "dumping hw/fw registers:.\n "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3367) " PEG_HALT_STATUS1: 0x%x, PEG_HALT_STATUS2: 0x%x,.\n "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3368) " PEG_NET_0_PC: 0x%x, PEG_NET_1_PC: 0x%x,.\n "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3369) " PEG_NET_2_PC: 0x%x, PEG_NET_3_PC: 0x%x,.\n "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3370) " PEG_NET_4_PC: 0x%x.\n", halt_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3371) qla82xx_rd_32(ha, QLA82XX_PEG_HALT_STATUS2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3372) qla82xx_rd_32(ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3373) QLA82XX_CRB_PEG_NET_0 + 0x3c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3374) qla82xx_rd_32(ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3375) QLA82XX_CRB_PEG_NET_1 + 0x3c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3376) qla82xx_rd_32(ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3377) QLA82XX_CRB_PEG_NET_2 + 0x3c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3378) qla82xx_rd_32(ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3379) QLA82XX_CRB_PEG_NET_3 + 0x3c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3380) qla82xx_rd_32(ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3381) QLA82XX_CRB_PEG_NET_4 + 0x3c));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3382) if (((halt_status & 0x1fffff00) >> 8) == 0x67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3383) ql_log(ql_log_warn, vha, 0xb052,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3384) "Firmware aborted with "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3385) "error code 0x00006700. Device is "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3386) "being reset.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3387) if (halt_status & HALT_STATUS_UNRECOVERABLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3388) set_bit(ISP_UNRECOVERABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3389) &vha->dpc_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3390) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3391) ql_log(ql_log_info, vha, 0x6006,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3392) "Detect abort needed.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3393) set_bit(ISP_ABORT_NEEDED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3394) &vha->dpc_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3396) ha->flags.isp82xx_fw_hung = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3397) ql_log(ql_log_warn, vha, 0x6007, "Firmware hung.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3398) qla82xx_clear_pending_mbx(vha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3404) int qla82xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3405) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3406) int rval = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3407) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3409) if (IS_QLA82XX(ha))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3410) rval = qla82xx_device_state_handler(vha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3411) else if (IS_QLA8044(ha)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3412) qla8044_idc_lock(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3413) /* Decide the reset ownership */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3414) qla83xx_reset_ownership(vha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3415) qla8044_idc_unlock(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3416) rval = qla8044_device_state_handler(vha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3418) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3419) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3421) void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3422) qla82xx_set_reset_owner(scsi_qla_host_t *vha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3423) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3424) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3425) uint32_t dev_state = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3427) if (IS_QLA82XX(ha))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3428) dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3429) else if (IS_QLA8044(ha))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3430) dev_state = qla8044_rd_direct(vha, QLA8044_CRB_DEV_STATE_INDEX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3432) if (dev_state == QLA8XXX_DEV_READY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3433) ql_log(ql_log_info, vha, 0xb02f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3434) "HW State: NEED RESET\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3435) if (IS_QLA82XX(ha)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3436) qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3437) QLA8XXX_DEV_NEED_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3438) ha->flags.nic_core_reset_owner = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3439) ql_dbg(ql_dbg_p3p, vha, 0xb030,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3440) "reset_owner is 0x%x\n", ha->portnum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3441) } else if (IS_QLA8044(ha))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3442) qla8044_wr_direct(vha, QLA8044_CRB_DEV_STATE_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3443) QLA8XXX_DEV_NEED_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3444) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3445) ql_log(ql_log_info, vha, 0xb031,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3446) "Device state is 0x%x = %s.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3447) dev_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3448) dev_state < MAX_STATES ? qdev_state(dev_state) : "Unknown");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3449) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3451) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3452) * qla82xx_abort_isp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3453) * Resets ISP and aborts all outstanding commands.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3454) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3455) * Input:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3456) * ha = adapter block pointer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3457) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3458) * Returns:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3459) * 0 = success
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3460) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3461) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3462) qla82xx_abort_isp(scsi_qla_host_t *vha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3463) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3464) int rval = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3465) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3467) if (vha->device_flags & DFLG_DEV_FAILED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3468) ql_log(ql_log_warn, vha, 0x8024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3469) "Device in failed state, exiting.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3470) return QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3472) ha->flags.nic_core_reset_hdlr_active = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3474) qla82xx_idc_lock(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3475) qla82xx_set_reset_owner(vha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3476) qla82xx_idc_unlock(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3478) if (IS_QLA82XX(ha))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3479) rval = qla82xx_device_state_handler(vha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3480) else if (IS_QLA8044(ha)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3481) qla8044_idc_lock(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3482) /* Decide the reset ownership */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3483) qla83xx_reset_ownership(vha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3484) qla8044_idc_unlock(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3485) rval = qla8044_device_state_handler(vha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3488) qla82xx_idc_lock(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3489) qla82xx_clear_rst_ready(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3490) qla82xx_idc_unlock(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3492) if (rval == QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3493) ha->flags.isp82xx_fw_hung = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3494) ha->flags.nic_core_reset_hdlr_active = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3495) qla82xx_restart_isp(vha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3496) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3498) if (rval) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3499) vha->flags.online = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3500) if (test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3501) if (ha->isp_abort_cnt == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3502) ql_log(ql_log_warn, vha, 0x8027,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3503) "ISP error recover failed - board "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3504) "disabled.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3505) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3506) * The next call disables the board
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3507) * completely.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3508) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3509) ha->isp_ops->reset_adapter(vha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3510) vha->flags.online = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3511) clear_bit(ISP_ABORT_RETRY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3512) &vha->dpc_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3513) rval = QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3514) } else { /* schedule another ISP abort */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3515) ha->isp_abort_cnt--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3516) ql_log(ql_log_warn, vha, 0x8036,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3517) "ISP abort - retry remaining %d.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3518) ha->isp_abort_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3519) rval = QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3520) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3521) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3522) ha->isp_abort_cnt = MAX_RETRIES_OF_ISP_ABORT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3523) ql_dbg(ql_dbg_taskm, vha, 0x8029,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3524) "ISP error recovery - retrying (%d) more times.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3525) ha->isp_abort_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3526) set_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3527) rval = QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3528) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3529) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3530) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3531) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3533) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3534) * qla82xx_fcoe_ctx_reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3535) * Perform a quick reset and aborts all outstanding commands.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3536) * This will only perform an FCoE context reset and avoids a full blown
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3537) * chip reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3538) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3539) * Input:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3540) * ha = adapter block pointer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3541) * is_reset_path = flag for identifying the reset path.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3542) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3543) * Returns:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3544) * 0 = success
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3545) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3546) int qla82xx_fcoe_ctx_reset(scsi_qla_host_t *vha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3547) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3548) int rval = QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3550) if (vha->flags.online) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3551) /* Abort all outstanding commands, so as to be requeued later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3552) qla2x00_abort_isp_cleanup(vha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3553) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3555) /* Stop currently executing firmware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3556) * This will destroy existing FCoE context at the F/W end.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3557) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3558) qla2x00_try_to_stop_firmware(vha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3560) /* Restart. Creates a new FCoE context on INIT_FIRMWARE. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3561) rval = qla82xx_restart_isp(vha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3563) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3564) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3566) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3567) * qla2x00_wait_for_fcoe_ctx_reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3568) * Wait till the FCoE context is reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3569) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3570) * Note:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3571) * Does context switching here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3572) * Release SPIN_LOCK (if any) before calling this routine.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3573) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3574) * Return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3575) * Success (fcoe_ctx reset is done) : 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3576) * Failed (fcoe_ctx reset not completed within max loop timout ) : 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3577) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3578) int qla2x00_wait_for_fcoe_ctx_reset(scsi_qla_host_t *vha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3579) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3580) int status = QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3581) unsigned long wait_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3583) wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3584) while ((test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3585) test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3586) && time_before(jiffies, wait_reset)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3588) set_current_state(TASK_UNINTERRUPTIBLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3589) schedule_timeout(HZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3591) if (!test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3592) !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3593) status = QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3594) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3595) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3596) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3597) ql_dbg(ql_dbg_p3p, vha, 0xb027,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3598) "%s: status=%d.\n", __func__, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3600) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3601) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3603) void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3604) qla82xx_chip_reset_cleanup(scsi_qla_host_t *vha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3605) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3606) int i, fw_state = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3607) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3608) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3610) /* Check if 82XX firmware is alive or not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3611) * We may have arrived here from NEED_RESET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3612) * detection only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3613) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3614) if (!ha->flags.isp82xx_fw_hung) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3615) for (i = 0; i < 2; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3616) msleep(1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3617) if (IS_QLA82XX(ha))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3618) fw_state = qla82xx_check_fw_alive(vha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3619) else if (IS_QLA8044(ha))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3620) fw_state = qla8044_check_fw_alive(vha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3621) if (fw_state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3622) ha->flags.isp82xx_fw_hung = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3623) qla82xx_clear_pending_mbx(vha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3624) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3625) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3626) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3627) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3628) ql_dbg(ql_dbg_init, vha, 0x00b0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3629) "Entered %s fw_hung=%d.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3630) __func__, ha->flags.isp82xx_fw_hung);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3632) /* Abort all commands gracefully if fw NOT hung */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3633) if (!ha->flags.isp82xx_fw_hung) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3634) int cnt, que;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3635) srb_t *sp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3636) struct req_que *req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3638) spin_lock_irqsave(&ha->hardware_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3639) for (que = 0; que < ha->max_req_queues; que++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3640) req = ha->req_q_map[que];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3641) if (!req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3642) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3643) for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3644) sp = req->outstanding_cmds[cnt];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3645) if (sp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3646) if ((!sp->u.scmd.crc_ctx ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3647) (sp->flags &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3648) SRB_FCP_CMND_DMA_VALID)) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3649) !ha->flags.isp82xx_fw_hung) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3650) spin_unlock_irqrestore(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3651) &ha->hardware_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3652) if (ha->isp_ops->abort_command(sp)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3653) ql_log(ql_log_info, vha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3654) 0x00b1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3655) "mbx abort failed.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3656) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3657) ql_log(ql_log_info, vha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3658) 0x00b2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3659) "mbx abort success.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3660) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3661) spin_lock_irqsave(&ha->hardware_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3662) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3663) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3664) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3665) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3666) spin_unlock_irqrestore(&ha->hardware_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3668) /* Wait for pending cmds (physical and virtual) to complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3669) if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3670) WAIT_HOST) == QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3671) ql_dbg(ql_dbg_init, vha, 0x00b3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3672) "Done wait for "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3673) "pending commands.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3674) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3675) WARN_ON_ONCE(true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3676) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3677) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3678) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3680) /* Minidump related functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3681) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3682) qla82xx_minidump_process_control(scsi_qla_host_t *vha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3683) qla82xx_md_entry_hdr_t *entry_hdr, __le32 **d_ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3684) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3685) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3686) struct qla82xx_md_entry_crb *crb_entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3687) uint32_t read_value, opcode, poll_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3688) uint32_t addr, index, crb_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3689) unsigned long wtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3690) struct qla82xx_md_template_hdr *tmplt_hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3691) uint32_t rval = QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3692) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3694) tmplt_hdr = (struct qla82xx_md_template_hdr *)ha->md_tmplt_hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3695) crb_entry = (struct qla82xx_md_entry_crb *)entry_hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3696) crb_addr = crb_entry->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3698) for (i = 0; i < crb_entry->op_count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3699) opcode = crb_entry->crb_ctrl.opcode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3700) if (opcode & QLA82XX_DBG_OPCODE_WR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3701) qla82xx_md_rw_32(ha, crb_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3702) crb_entry->value_1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3703) opcode &= ~QLA82XX_DBG_OPCODE_WR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3704) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3706) if (opcode & QLA82XX_DBG_OPCODE_RW) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3707) read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3708) qla82xx_md_rw_32(ha, crb_addr, read_value, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3709) opcode &= ~QLA82XX_DBG_OPCODE_RW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3710) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3712) if (opcode & QLA82XX_DBG_OPCODE_AND) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3713) read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3714) read_value &= crb_entry->value_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3715) opcode &= ~QLA82XX_DBG_OPCODE_AND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3716) if (opcode & QLA82XX_DBG_OPCODE_OR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3717) read_value |= crb_entry->value_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3718) opcode &= ~QLA82XX_DBG_OPCODE_OR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3719) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3720) qla82xx_md_rw_32(ha, crb_addr, read_value, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3721) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3723) if (opcode & QLA82XX_DBG_OPCODE_OR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3724) read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3725) read_value |= crb_entry->value_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3726) qla82xx_md_rw_32(ha, crb_addr, read_value, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3727) opcode &= ~QLA82XX_DBG_OPCODE_OR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3728) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3730) if (opcode & QLA82XX_DBG_OPCODE_POLL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3731) poll_time = crb_entry->crb_strd.poll_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3732) wtime = jiffies + poll_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3733) read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3735) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3736) if ((read_value & crb_entry->value_2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3737) == crb_entry->value_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3738) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3739) else if (time_after_eq(jiffies, wtime)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3740) /* capturing dump failed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3741) rval = QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3742) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3743) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3744) read_value = qla82xx_md_rw_32(ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3745) crb_addr, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3746) } while (1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3747) opcode &= ~QLA82XX_DBG_OPCODE_POLL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3748) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3750) if (opcode & QLA82XX_DBG_OPCODE_RDSTATE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3751) if (crb_entry->crb_strd.state_index_a) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3752) index = crb_entry->crb_strd.state_index_a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3753) addr = tmplt_hdr->saved_state_array[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3754) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3755) addr = crb_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3757) read_value = qla82xx_md_rw_32(ha, addr, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3758) index = crb_entry->crb_ctrl.state_index_v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3759) tmplt_hdr->saved_state_array[index] = read_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3760) opcode &= ~QLA82XX_DBG_OPCODE_RDSTATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3761) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3763) if (opcode & QLA82XX_DBG_OPCODE_WRSTATE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3764) if (crb_entry->crb_strd.state_index_a) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3765) index = crb_entry->crb_strd.state_index_a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3766) addr = tmplt_hdr->saved_state_array[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3767) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3768) addr = crb_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3770) if (crb_entry->crb_ctrl.state_index_v) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3771) index = crb_entry->crb_ctrl.state_index_v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3772) read_value =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3773) tmplt_hdr->saved_state_array[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3774) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3775) read_value = crb_entry->value_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3777) qla82xx_md_rw_32(ha, addr, read_value, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3778) opcode &= ~QLA82XX_DBG_OPCODE_WRSTATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3779) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3781) if (opcode & QLA82XX_DBG_OPCODE_MDSTATE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3782) index = crb_entry->crb_ctrl.state_index_v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3783) read_value = tmplt_hdr->saved_state_array[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3784) read_value <<= crb_entry->crb_ctrl.shl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3785) read_value >>= crb_entry->crb_ctrl.shr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3786) if (crb_entry->value_2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3787) read_value &= crb_entry->value_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3788) read_value |= crb_entry->value_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3789) read_value += crb_entry->value_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3790) tmplt_hdr->saved_state_array[index] = read_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3791) opcode &= ~QLA82XX_DBG_OPCODE_MDSTATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3792) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3793) crb_addr += crb_entry->crb_strd.addr_stride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3794) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3795) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3796) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3798) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3799) qla82xx_minidump_process_rdocm(scsi_qla_host_t *vha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3800) qla82xx_md_entry_hdr_t *entry_hdr, __le32 **d_ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3801) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3802) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3803) uint32_t r_addr, r_stride, loop_cnt, i, r_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3804) struct qla82xx_md_entry_rdocm *ocm_hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3805) __le32 *data_ptr = *d_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3807) ocm_hdr = (struct qla82xx_md_entry_rdocm *)entry_hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3808) r_addr = ocm_hdr->read_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3809) r_stride = ocm_hdr->read_addr_stride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3810) loop_cnt = ocm_hdr->op_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3812) for (i = 0; i < loop_cnt; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3813) r_value = rd_reg_dword(r_addr + ha->nx_pcibase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3814) *data_ptr++ = cpu_to_le32(r_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3815) r_addr += r_stride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3816) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3817) *d_ptr = data_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3818) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3820) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3821) qla82xx_minidump_process_rdmux(scsi_qla_host_t *vha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3822) qla82xx_md_entry_hdr_t *entry_hdr, __le32 **d_ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3823) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3824) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3825) uint32_t r_addr, s_stride, s_addr, s_value, loop_cnt, i, r_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3826) struct qla82xx_md_entry_mux *mux_hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3827) __le32 *data_ptr = *d_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3829) mux_hdr = (struct qla82xx_md_entry_mux *)entry_hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3830) r_addr = mux_hdr->read_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3831) s_addr = mux_hdr->select_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3832) s_stride = mux_hdr->select_value_stride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3833) s_value = mux_hdr->select_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3834) loop_cnt = mux_hdr->op_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3836) for (i = 0; i < loop_cnt; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3837) qla82xx_md_rw_32(ha, s_addr, s_value, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3838) r_value = qla82xx_md_rw_32(ha, r_addr, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3839) *data_ptr++ = cpu_to_le32(s_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3840) *data_ptr++ = cpu_to_le32(r_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3841) s_value += s_stride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3842) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3843) *d_ptr = data_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3844) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3846) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3847) qla82xx_minidump_process_rdcrb(scsi_qla_host_t *vha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3848) qla82xx_md_entry_hdr_t *entry_hdr, __le32 **d_ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3849) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3850) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3851) uint32_t r_addr, r_stride, loop_cnt, i, r_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3852) struct qla82xx_md_entry_crb *crb_hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3853) __le32 *data_ptr = *d_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3855) crb_hdr = (struct qla82xx_md_entry_crb *)entry_hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3856) r_addr = crb_hdr->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3857) r_stride = crb_hdr->crb_strd.addr_stride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3858) loop_cnt = crb_hdr->op_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3860) for (i = 0; i < loop_cnt; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3861) r_value = qla82xx_md_rw_32(ha, r_addr, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3862) *data_ptr++ = cpu_to_le32(r_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3863) *data_ptr++ = cpu_to_le32(r_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3864) r_addr += r_stride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3865) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3866) *d_ptr = data_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3867) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3869) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3870) qla82xx_minidump_process_l2tag(scsi_qla_host_t *vha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3871) qla82xx_md_entry_hdr_t *entry_hdr, __le32 **d_ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3872) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3873) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3874) uint32_t addr, r_addr, c_addr, t_r_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3875) uint32_t i, k, loop_count, t_value, r_cnt, r_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3876) unsigned long p_wait, w_time, p_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3877) uint32_t c_value_w, c_value_r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3878) struct qla82xx_md_entry_cache *cache_hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3879) int rval = QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3880) __le32 *data_ptr = *d_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3882) cache_hdr = (struct qla82xx_md_entry_cache *)entry_hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3883) loop_count = cache_hdr->op_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3884) r_addr = cache_hdr->read_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3885) c_addr = cache_hdr->control_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3886) c_value_w = cache_hdr->cache_ctrl.write_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3888) t_r_addr = cache_hdr->tag_reg_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3889) t_value = cache_hdr->addr_ctrl.init_tag_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3890) r_cnt = cache_hdr->read_ctrl.read_addr_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3891) p_wait = cache_hdr->cache_ctrl.poll_wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3892) p_mask = cache_hdr->cache_ctrl.poll_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3894) for (i = 0; i < loop_count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3895) qla82xx_md_rw_32(ha, t_r_addr, t_value, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3896) if (c_value_w)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3897) qla82xx_md_rw_32(ha, c_addr, c_value_w, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3899) if (p_mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3900) w_time = jiffies + p_wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3901) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3902) c_value_r = qla82xx_md_rw_32(ha, c_addr, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3903) if ((c_value_r & p_mask) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3904) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3905) else if (time_after_eq(jiffies, w_time)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3906) /* capturing dump failed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3907) ql_dbg(ql_dbg_p3p, vha, 0xb032,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3908) "c_value_r: 0x%x, poll_mask: 0x%lx, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3909) "w_time: 0x%lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3910) c_value_r, p_mask, w_time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3911) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3912) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3913) } while (1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3914) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3916) addr = r_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3917) for (k = 0; k < r_cnt; k++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3918) r_value = qla82xx_md_rw_32(ha, addr, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3919) *data_ptr++ = cpu_to_le32(r_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3920) addr += cache_hdr->read_ctrl.read_addr_stride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3921) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3922) t_value += cache_hdr->addr_ctrl.tag_value_stride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3923) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3924) *d_ptr = data_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3925) return QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3926) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3928) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3929) qla82xx_minidump_process_l1cache(scsi_qla_host_t *vha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3930) qla82xx_md_entry_hdr_t *entry_hdr, __le32 **d_ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3931) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3932) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3933) uint32_t addr, r_addr, c_addr, t_r_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3934) uint32_t i, k, loop_count, t_value, r_cnt, r_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3935) uint32_t c_value_w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3936) struct qla82xx_md_entry_cache *cache_hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3937) __le32 *data_ptr = *d_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3939) cache_hdr = (struct qla82xx_md_entry_cache *)entry_hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3940) loop_count = cache_hdr->op_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3941) r_addr = cache_hdr->read_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3942) c_addr = cache_hdr->control_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3943) c_value_w = cache_hdr->cache_ctrl.write_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3945) t_r_addr = cache_hdr->tag_reg_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3946) t_value = cache_hdr->addr_ctrl.init_tag_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3947) r_cnt = cache_hdr->read_ctrl.read_addr_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3949) for (i = 0; i < loop_count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3950) qla82xx_md_rw_32(ha, t_r_addr, t_value, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3951) qla82xx_md_rw_32(ha, c_addr, c_value_w, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3952) addr = r_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3953) for (k = 0; k < r_cnt; k++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3954) r_value = qla82xx_md_rw_32(ha, addr, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3955) *data_ptr++ = cpu_to_le32(r_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3956) addr += cache_hdr->read_ctrl.read_addr_stride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3957) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3958) t_value += cache_hdr->addr_ctrl.tag_value_stride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3959) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3960) *d_ptr = data_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3961) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3963) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3964) qla82xx_minidump_process_queue(scsi_qla_host_t *vha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3965) qla82xx_md_entry_hdr_t *entry_hdr, __le32 **d_ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3966) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3967) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3968) uint32_t s_addr, r_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3969) uint32_t r_stride, r_value, r_cnt, qid = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3970) uint32_t i, k, loop_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3971) struct qla82xx_md_entry_queue *q_hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3972) __le32 *data_ptr = *d_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3974) q_hdr = (struct qla82xx_md_entry_queue *)entry_hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3975) s_addr = q_hdr->select_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3976) r_cnt = q_hdr->rd_strd.read_addr_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3977) r_stride = q_hdr->rd_strd.read_addr_stride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3978) loop_cnt = q_hdr->op_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3980) for (i = 0; i < loop_cnt; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3981) qla82xx_md_rw_32(ha, s_addr, qid, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3982) r_addr = q_hdr->read_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3983) for (k = 0; k < r_cnt; k++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3984) r_value = qla82xx_md_rw_32(ha, r_addr, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3985) *data_ptr++ = cpu_to_le32(r_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3986) r_addr += r_stride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3987) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3988) qid += q_hdr->q_strd.queue_id_stride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3989) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3990) *d_ptr = data_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3991) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3993) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3994) qla82xx_minidump_process_rdrom(scsi_qla_host_t *vha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3995) qla82xx_md_entry_hdr_t *entry_hdr, __le32 **d_ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3996) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3997) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3998) uint32_t r_addr, r_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3999) uint32_t i, loop_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4000) struct qla82xx_md_entry_rdrom *rom_hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4001) __le32 *data_ptr = *d_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4003) rom_hdr = (struct qla82xx_md_entry_rdrom *)entry_hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4004) r_addr = rom_hdr->read_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4005) loop_cnt = rom_hdr->read_data_size/sizeof(uint32_t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4007) for (i = 0; i < loop_cnt; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4008) qla82xx_md_rw_32(ha, MD_DIRECT_ROM_WINDOW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4009) (r_addr & 0xFFFF0000), 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4010) r_value = qla82xx_md_rw_32(ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4011) MD_DIRECT_ROM_READ_BASE +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4012) (r_addr & 0x0000FFFF), 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4013) *data_ptr++ = cpu_to_le32(r_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4014) r_addr += sizeof(uint32_t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4015) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4016) *d_ptr = data_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4017) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4019) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4020) qla82xx_minidump_process_rdmem(scsi_qla_host_t *vha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4021) qla82xx_md_entry_hdr_t *entry_hdr, __le32 **d_ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4022) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4023) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4024) uint32_t r_addr, r_value, r_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4025) uint32_t i, j, loop_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4026) struct qla82xx_md_entry_rdmem *m_hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4027) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4028) int rval = QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4029) __le32 *data_ptr = *d_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4031) m_hdr = (struct qla82xx_md_entry_rdmem *)entry_hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4032) r_addr = m_hdr->read_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4033) loop_cnt = m_hdr->read_data_size/16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4035) if (r_addr & 0xf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4036) ql_log(ql_log_warn, vha, 0xb033,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4037) "Read addr 0x%x not 16 bytes aligned\n", r_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4038) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4039) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4041) if (m_hdr->read_data_size % 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4042) ql_log(ql_log_warn, vha, 0xb034,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4043) "Read data[0x%x] not multiple of 16 bytes\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4044) m_hdr->read_data_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4045) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4046) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4048) ql_dbg(ql_dbg_p3p, vha, 0xb035,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4049) "[%s]: rdmem_addr: 0x%x, read_data_size: 0x%x, loop_cnt: 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4050) __func__, r_addr, m_hdr->read_data_size, loop_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4052) write_lock_irqsave(&ha->hw_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4053) for (i = 0; i < loop_cnt; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4054) qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_ADDR_LO, r_addr, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4055) r_value = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4056) qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_ADDR_HI, r_value, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4057) r_value = MIU_TA_CTL_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4058) qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_CTRL, r_value, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4059) r_value = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4060) qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_CTRL, r_value, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4062) for (j = 0; j < MAX_CTL_CHECK; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4063) r_value = qla82xx_md_rw_32(ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4064) MD_MIU_TEST_AGT_CTRL, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4065) if ((r_value & MIU_TA_CTL_BUSY) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4066) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4067) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4069) if (j >= MAX_CTL_CHECK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4070) printk_ratelimited(KERN_ERR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4071) "failed to read through agent\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4072) write_unlock_irqrestore(&ha->hw_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4073) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4074) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4076) for (j = 0; j < 4; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4077) r_data = qla82xx_md_rw_32(ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4078) MD_MIU_TEST_AGT_RDDATA[j], 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4079) *data_ptr++ = cpu_to_le32(r_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4080) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4081) r_addr += 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4082) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4083) write_unlock_irqrestore(&ha->hw_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4084) *d_ptr = data_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4085) return QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4086) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4088) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4089) qla82xx_validate_template_chksum(scsi_qla_host_t *vha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4090) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4091) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4092) uint64_t chksum = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4093) uint32_t *d_ptr = (uint32_t *)ha->md_tmplt_hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4094) int count = ha->md_template_size/sizeof(uint32_t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4096) while (count-- > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4097) chksum += *d_ptr++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4098) while (chksum >> 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4099) chksum = (chksum & 0xFFFFFFFF) + (chksum >> 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4100) return ~chksum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4103) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4104) qla82xx_mark_entry_skipped(scsi_qla_host_t *vha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4105) qla82xx_md_entry_hdr_t *entry_hdr, int index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4107) entry_hdr->d_ctrl.driver_flags |= QLA82XX_DBG_SKIPPED_FLAG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4108) ql_dbg(ql_dbg_p3p, vha, 0xb036,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4109) "Skipping entry[%d]: "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4110) "ETYPE[0x%x]-ELEVEL[0x%x]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4111) index, entry_hdr->entry_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4112) entry_hdr->d_ctrl.entry_capture_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4115) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4116) qla82xx_md_collect(scsi_qla_host_t *vha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4118) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4119) int no_entry_hdr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4120) qla82xx_md_entry_hdr_t *entry_hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4121) struct qla82xx_md_template_hdr *tmplt_hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4122) __le32 *data_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4123) uint32_t total_data_size = 0, f_capture_mask, data_collected = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4124) int i = 0, rval = QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4126) tmplt_hdr = (struct qla82xx_md_template_hdr *)ha->md_tmplt_hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4127) data_ptr = ha->md_dump;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4129) if (ha->fw_dumped) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4130) ql_log(ql_log_warn, vha, 0xb037,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4131) "Firmware has been previously dumped (%p) "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4132) "-- ignoring request.\n", ha->fw_dump);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4133) goto md_failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4136) ha->fw_dumped = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4138) if (!ha->md_tmplt_hdr || !ha->md_dump) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4139) ql_log(ql_log_warn, vha, 0xb038,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4140) "Memory not allocated for minidump capture\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4141) goto md_failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4144) if (ha->flags.isp82xx_no_md_cap) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4145) ql_log(ql_log_warn, vha, 0xb054,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4146) "Forced reset from application, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4147) "ignore minidump capture\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4148) ha->flags.isp82xx_no_md_cap = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4149) goto md_failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4152) if (qla82xx_validate_template_chksum(vha)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4153) ql_log(ql_log_info, vha, 0xb039,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4154) "Template checksum validation error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4155) goto md_failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4158) no_entry_hdr = tmplt_hdr->num_of_entries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4159) ql_dbg(ql_dbg_p3p, vha, 0xb03a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4160) "No of entry headers in Template: 0x%x\n", no_entry_hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4162) ql_dbg(ql_dbg_p3p, vha, 0xb03b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4163) "Capture Mask obtained: 0x%x\n", tmplt_hdr->capture_debug_level);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4165) f_capture_mask = tmplt_hdr->capture_debug_level & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4167) /* Validate whether required debug level is set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4168) if ((f_capture_mask & 0x3) != 0x3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4169) ql_log(ql_log_warn, vha, 0xb03c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4170) "Minimum required capture mask[0x%x] level not set\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4171) f_capture_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4172) goto md_failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4174) tmplt_hdr->driver_capture_mask = ql2xmdcapmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4176) tmplt_hdr->driver_info[0] = vha->host_no;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4177) tmplt_hdr->driver_info[1] = (QLA_DRIVER_MAJOR_VER << 24) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4178) (QLA_DRIVER_MINOR_VER << 16) | (QLA_DRIVER_PATCH_VER << 8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4179) QLA_DRIVER_BETA_VER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4181) total_data_size = ha->md_dump_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4183) ql_dbg(ql_dbg_p3p, vha, 0xb03d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4184) "Total minidump data_size 0x%x to be captured\n", total_data_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4186) /* Check whether template obtained is valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4187) if (tmplt_hdr->entry_type != QLA82XX_TLHDR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4188) ql_log(ql_log_warn, vha, 0xb04e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4189) "Bad template header entry type: 0x%x obtained\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4190) tmplt_hdr->entry_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4191) goto md_failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4194) entry_hdr = (qla82xx_md_entry_hdr_t *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4195) (((uint8_t *)ha->md_tmplt_hdr) + tmplt_hdr->first_entry_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4197) /* Walk through the entry headers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4198) for (i = 0; i < no_entry_hdr; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4200) if (data_collected > total_data_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4201) ql_log(ql_log_warn, vha, 0xb03e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4202) "More MiniDump data collected: [0x%x]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4203) data_collected);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4204) goto md_failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4207) if (!(entry_hdr->d_ctrl.entry_capture_mask &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4208) ql2xmdcapmask)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4209) entry_hdr->d_ctrl.driver_flags |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4210) QLA82XX_DBG_SKIPPED_FLAG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4211) ql_dbg(ql_dbg_p3p, vha, 0xb03f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4212) "Skipping entry[%d]: "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4213) "ETYPE[0x%x]-ELEVEL[0x%x]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4214) i, entry_hdr->entry_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4215) entry_hdr->d_ctrl.entry_capture_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4216) goto skip_nxt_entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4219) ql_dbg(ql_dbg_p3p, vha, 0xb040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4220) "[%s]: data ptr[%d]: %p, entry_hdr: %p\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4221) "entry_type: 0x%x, capture_mask: 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4222) __func__, i, data_ptr, entry_hdr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4223) entry_hdr->entry_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4224) entry_hdr->d_ctrl.entry_capture_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4226) ql_dbg(ql_dbg_p3p, vha, 0xb041,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4227) "Data collected: [0x%x], Dump size left:[0x%x]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4228) data_collected, (ha->md_dump_size - data_collected));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4230) /* Decode the entry type and take
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4231) * required action to capture debug data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4232) switch (entry_hdr->entry_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4233) case QLA82XX_RDEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4234) qla82xx_mark_entry_skipped(vha, entry_hdr, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4235) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4236) case QLA82XX_CNTRL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4237) rval = qla82xx_minidump_process_control(vha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4238) entry_hdr, &data_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4239) if (rval != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4240) qla82xx_mark_entry_skipped(vha, entry_hdr, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4241) goto md_failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4243) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4244) case QLA82XX_RDCRB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4245) qla82xx_minidump_process_rdcrb(vha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4246) entry_hdr, &data_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4247) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4248) case QLA82XX_RDMEM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4249) rval = qla82xx_minidump_process_rdmem(vha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4250) entry_hdr, &data_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4251) if (rval != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4252) qla82xx_mark_entry_skipped(vha, entry_hdr, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4253) goto md_failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4255) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4256) case QLA82XX_BOARD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4257) case QLA82XX_RDROM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4258) qla82xx_minidump_process_rdrom(vha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4259) entry_hdr, &data_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4260) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4261) case QLA82XX_L2DTG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4262) case QLA82XX_L2ITG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4263) case QLA82XX_L2DAT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4264) case QLA82XX_L2INS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4265) rval = qla82xx_minidump_process_l2tag(vha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4266) entry_hdr, &data_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4267) if (rval != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4268) qla82xx_mark_entry_skipped(vha, entry_hdr, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4269) goto md_failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4271) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4272) case QLA82XX_L1DAT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4273) case QLA82XX_L1INS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4274) qla82xx_minidump_process_l1cache(vha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4275) entry_hdr, &data_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4276) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4277) case QLA82XX_RDOCM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4278) qla82xx_minidump_process_rdocm(vha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4279) entry_hdr, &data_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4280) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4281) case QLA82XX_RDMUX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4282) qla82xx_minidump_process_rdmux(vha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4283) entry_hdr, &data_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4284) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4285) case QLA82XX_QUEUE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4286) qla82xx_minidump_process_queue(vha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4287) entry_hdr, &data_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4288) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4289) case QLA82XX_RDNOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4290) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4291) qla82xx_mark_entry_skipped(vha, entry_hdr, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4292) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4295) ql_dbg(ql_dbg_p3p, vha, 0xb042,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4296) "[%s]: data ptr[%d]: %p\n", __func__, i, data_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4298) data_collected = (uint8_t *)data_ptr -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4299) (uint8_t *)ha->md_dump;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4300) skip_nxt_entry:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4301) entry_hdr = (qla82xx_md_entry_hdr_t *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4302) (((uint8_t *)entry_hdr) + entry_hdr->entry_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4305) if (data_collected != total_data_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4306) ql_dbg(ql_dbg_p3p, vha, 0xb043,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4307) "MiniDump data mismatch: Data collected: [0x%x],"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4308) "total_data_size:[0x%x]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4309) data_collected, total_data_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4310) goto md_failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4313) ql_log(ql_log_info, vha, 0xb044,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4314) "Firmware dump saved to temp buffer (%ld/%p %ld/%p).\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4315) vha->host_no, ha->md_tmplt_hdr, vha->host_no, ha->md_dump);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4316) ha->fw_dumped = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4317) qla2x00_post_uevent_work(vha, QLA_UEVENT_CODE_FW_DUMP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4319) md_failed:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4320) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4323) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4324) qla82xx_md_alloc(scsi_qla_host_t *vha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4325) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4326) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4327) int i, k;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4328) struct qla82xx_md_template_hdr *tmplt_hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4330) tmplt_hdr = (struct qla82xx_md_template_hdr *)ha->md_tmplt_hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4332) if (ql2xmdcapmask < 0x3 || ql2xmdcapmask > 0x7F) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4333) ql2xmdcapmask = tmplt_hdr->capture_debug_level & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4334) ql_log(ql_log_info, vha, 0xb045,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4335) "Forcing driver capture mask to firmware default capture mask: 0x%x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4336) ql2xmdcapmask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4339) for (i = 0x2, k = 1; (i & QLA82XX_DEFAULT_CAP_MASK); i <<= 1, k++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4340) if (i & ql2xmdcapmask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4341) ha->md_dump_size += tmplt_hdr->capture_size_array[k];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4344) if (ha->md_dump) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4345) ql_log(ql_log_warn, vha, 0xb046,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4346) "Firmware dump previously allocated.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4347) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4350) ha->md_dump = vmalloc(ha->md_dump_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4351) if (ha->md_dump == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4352) ql_log(ql_log_warn, vha, 0xb047,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4353) "Unable to allocate memory for Minidump size "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4354) "(0x%x).\n", ha->md_dump_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4355) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4357) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4360) void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4361) qla82xx_md_free(scsi_qla_host_t *vha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4362) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4363) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4365) /* Release the template header allocated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4366) if (ha->md_tmplt_hdr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4367) ql_log(ql_log_info, vha, 0xb048,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4368) "Free MiniDump template: %p, size (%d KB)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4369) ha->md_tmplt_hdr, ha->md_template_size / 1024);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4370) dma_free_coherent(&ha->pdev->dev, ha->md_template_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4371) ha->md_tmplt_hdr, ha->md_tmplt_hdr_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4372) ha->md_tmplt_hdr = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4373) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4375) /* Release the template data buffer allocated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4376) if (ha->md_dump) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4377) ql_log(ql_log_info, vha, 0xb049,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4378) "Free MiniDump memory: %p, size (%d KB)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4379) ha->md_dump, ha->md_dump_size / 1024);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4380) vfree(ha->md_dump);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4381) ha->md_dump_size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4382) ha->md_dump = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4383) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4386) void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4387) qla82xx_md_prep(scsi_qla_host_t *vha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4388) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4389) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4390) int rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4392) /* Get Minidump template size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4393) rval = qla82xx_md_get_template_size(vha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4394) if (rval == QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4395) ql_log(ql_log_info, vha, 0xb04a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4396) "MiniDump Template size obtained (%d KB)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4397) ha->md_template_size / 1024);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4399) /* Get Minidump template */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4400) if (IS_QLA8044(ha))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4401) rval = qla8044_md_get_template(vha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4402) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4403) rval = qla82xx_md_get_template(vha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4405) if (rval == QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4406) ql_dbg(ql_dbg_p3p, vha, 0xb04b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4407) "MiniDump Template obtained\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4409) /* Allocate memory for minidump */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4410) rval = qla82xx_md_alloc(vha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4411) if (rval == QLA_SUCCESS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4412) ql_log(ql_log_info, vha, 0xb04c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4413) "MiniDump memory allocated (%d KB)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4414) ha->md_dump_size / 1024);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4415) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4416) ql_log(ql_log_info, vha, 0xb04d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4417) "Free MiniDump template: %p, size: (%d KB)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4418) ha->md_tmplt_hdr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4419) ha->md_template_size / 1024);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4420) dma_free_coherent(&ha->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4421) ha->md_template_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4422) ha->md_tmplt_hdr, ha->md_tmplt_hdr_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4423) ha->md_tmplt_hdr = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4428) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4430) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4431) qla82xx_beacon_on(struct scsi_qla_host *vha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4432) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4434) int rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4435) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4437) qla82xx_idc_lock(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4438) rval = qla82xx_mbx_beacon_ctl(vha, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4440) if (rval) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4441) ql_log(ql_log_warn, vha, 0xb050,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4442) "mbx set led config failed in %s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4443) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4445) ha->beacon_blink_led = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4446) exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4447) qla82xx_idc_unlock(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4448) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4449) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4451) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4452) qla82xx_beacon_off(struct scsi_qla_host *vha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4453) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4455) int rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4456) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4458) qla82xx_idc_lock(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4459) rval = qla82xx_mbx_beacon_ctl(vha, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4461) if (rval) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4462) ql_log(ql_log_warn, vha, 0xb051,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4463) "mbx set led config failed in %s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4464) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4465) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4466) ha->beacon_blink_led = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4467) exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4468) qla82xx_idc_unlock(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4469) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4470) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4472) void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4473) qla82xx_fw_dump(scsi_qla_host_t *vha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4474) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4475) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4477) if (!ha->allow_cna_fw_dump)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4478) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4480) scsi_block_requests(vha->host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4481) ha->flags.isp82xx_no_md_cap = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4482) qla82xx_idc_lock(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4483) qla82xx_set_reset_owner(vha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4484) qla82xx_idc_unlock(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4485) qla2x00_wait_for_chip_reset(vha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4486) scsi_unblock_requests(vha->host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4487) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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