^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * QLogic Fibre Channel HBA Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (c) 2003-2017 QLogic Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #ifndef __QLA_NVME_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define __QLA_NVME_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <uapi/scsi/fc/fc_fs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <uapi/scsi/fc/fc_els.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/nvme-fc-driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include "qla_def.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "qla_dsd.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define NVME_ATIO_CMD_OFF 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define NVME_FIRST_PACKET_CMDLEN (64 - NVME_ATIO_CMD_OFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define Q2T_NVME_NUM_TAGS 2048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define QLA_MAX_FC_SEGMENTS 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) struct scsi_qla_host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) struct qla_hw_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) struct req_que;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) struct srb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) struct nvme_private {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) struct srb *sp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) struct nvmefc_ls_req *fd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) struct work_struct ls_work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) struct work_struct abort_work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) int comp_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) spinlock_t cmd_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) struct qla_nvme_rport {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) struct fc_port *fcport;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define COMMAND_NVME 0x88 /* Command Type FC-NVMe IOCB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) struct cmd_nvme {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) uint8_t entry_type; /* Entry type. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) uint8_t entry_count; /* Entry count. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) uint8_t sys_define; /* System defined. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) uint8_t entry_status; /* Entry Status. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) uint32_t handle; /* System handle. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) __le16 nport_handle; /* N_PORT handle. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) __le16 timeout; /* Command timeout. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) __le16 dseg_count; /* Data segment count. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) __le16 nvme_rsp_dsd_len; /* NVMe RSP DSD length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) uint64_t rsvd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) __le16 control_flags; /* Control Flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define CF_ADMIN_ASYNC_EVENT BIT_13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define CF_NVME_FIRST_BURST_ENABLE BIT_11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define CF_DIF_SEG_DESCR_ENABLE BIT_3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define CF_DATA_SEG_DESCR_ENABLE BIT_2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define CF_READ_DATA BIT_1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define CF_WRITE_DATA BIT_0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) __le16 nvme_cmnd_dseg_len; /* Data segment length. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) __le64 nvme_cmnd_dseg_address __packed;/* Data segment address. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) __le64 nvme_rsp_dseg_address __packed; /* Data segment address. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) __le32 byte_count; /* Total byte count. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) uint8_t port_id[3]; /* PortID of destination port. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) uint8_t vp_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) struct dsd64 nvme_dsd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define PT_LS4_REQUEST 0x89 /* Link Service pass-through IOCB (request) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct pt_ls4_request {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) uint8_t entry_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) uint8_t entry_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) uint8_t sys_define;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) uint8_t entry_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) uint32_t handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) __le16 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) __le16 nport_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) __le16 tx_dseg_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) uint8_t vp_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) uint8_t rsvd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) __le16 timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) __le16 control_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define CF_LS4_SHIFT 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define CF_LS4_ORIGINATOR 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define CF_LS4_RESPONDER 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define CF_LS4_RESPONDER_TERM 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) __le16 rx_dseg_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) __le16 rsvd2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) __le32 exchange_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) __le32 rsvd3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) __le32 rx_byte_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) __le32 tx_byte_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) struct dsd64 dsd[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define PT_LS4_UNSOL 0x56 /* pass-up unsolicited rec FC-NVMe request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) struct pt_ls4_rx_unsol {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) uint8_t entry_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) uint8_t entry_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) __le16 rsvd0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) __le16 rsvd1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) uint8_t vp_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) uint8_t rsvd2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) __le16 rsvd3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) __le16 nport_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) __le16 frame_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) __le16 rsvd4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) __le32 exchange_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) uint8_t d_id[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) uint8_t r_ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) be_id_t s_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) uint8_t cs_ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) uint8_t f_ctl[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) uint8_t type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) __le16 seq_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) uint8_t df_ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) uint8_t seq_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) __le16 rx_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) __le16 ox_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) __le32 param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) __le32 desc0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define PT_LS4_PAYLOAD_OFFSET 0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define PT_LS4_FIRST_PACKET_LEN 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) __le32 desc_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) __le32 payload[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * Global functions prototype in qla_nvme.c source file.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) int qla_nvme_register_hba(struct scsi_qla_host *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) int qla_nvme_register_remote(struct scsi_qla_host *, struct fc_port *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) void qla_nvme_delete(struct scsi_qla_host *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) void qla24xx_nvme_ls4_iocb(struct scsi_qla_host *, struct pt_ls4_request *,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) struct req_que *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) void qla24xx_async_gffid_sp_done(struct srb *sp, int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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