^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * QLogic Fibre Channel HBA Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (c) 2003-2014 QLogic Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #ifndef __QLA_MR_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define __QLA_MR_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include "qla_dsd.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * The PCI VendorID and DeviceID for our board.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define PCI_DEVICE_ID_QLOGIC_ISPF001 0xF001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) /* FX00 specific definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define FX00_COMMAND_TYPE_7 0x07 /* Command Type 7 entry for 7XXX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) struct cmd_type_7_fx00 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) uint8_t entry_type; /* Entry type. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) uint8_t entry_count; /* Entry count. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) uint8_t sys_define; /* System defined. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) uint8_t entry_status; /* Entry Status. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) uint32_t handle; /* System handle. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) uint8_t reserved_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) uint8_t port_path_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) uint16_t reserved_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) __le16 tgt_idx; /* Target Idx. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) uint16_t timeout; /* Command timeout. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) __le16 dseg_count; /* Data segment count. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) uint8_t scsi_rsp_dsd_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) uint8_t reserved_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) struct scsi_lun lun; /* LUN (LE). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) uint8_t cntrl_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) uint8_t task_mgmt_flags; /* Task management flags. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) uint8_t task;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) uint8_t crn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) uint8_t fcp_cdb[MAX_CMDSZ]; /* SCSI command words. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) __le32 byte_count; /* Total byte count. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) struct dsd64 dsd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define STATUS_TYPE_FX00 0x01 /* Status entry. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) struct sts_entry_fx00 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) uint8_t entry_type; /* Entry type. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) uint8_t entry_count; /* Entry count. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) uint8_t sys_define; /* System defined. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) uint8_t entry_status; /* Entry Status. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) uint32_t handle; /* System handle. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) uint32_t reserved_3; /* System handle. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) __le16 comp_status; /* Completion status. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) uint16_t reserved_0; /* OX_ID used by the firmware. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) __le32 residual_len; /* FW calc residual transfer length. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) uint16_t reserved_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) uint16_t state_flags; /* State flags. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) uint16_t reserved_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) __le16 scsi_status; /* SCSI status. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) uint32_t sense_len; /* FCP SENSE length. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) uint8_t data[32]; /* FCP response/sense information. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define MAX_HANDLE_COUNT 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define MULTI_STATUS_TYPE_FX00 0x0D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct multi_sts_entry_fx00 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) uint8_t entry_type; /* Entry type. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) uint8_t entry_count; /* Entry count. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) uint8_t handle_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) uint8_t entry_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) __le32 handles[MAX_HANDLE_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define TSK_MGMT_IOCB_TYPE_FX00 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) struct tsk_mgmt_entry_fx00 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) uint8_t entry_type; /* Entry type. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) uint8_t entry_count; /* Entry count. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) uint8_t sys_define;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) uint8_t entry_status; /* Entry Status. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) uint32_t handle; /* System handle. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) uint32_t reserved_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) __le16 tgt_id; /* Target Idx. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) uint16_t reserved_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) uint16_t reserved_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) uint16_t reserved_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct scsi_lun lun; /* LUN (LE). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) __le32 control_flags; /* Control Flags. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) uint8_t reserved_2[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define ABORT_IOCB_TYPE_FX00 0x08 /* Abort IOCB status. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct abort_iocb_entry_fx00 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) uint8_t entry_type; /* Entry type. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) uint8_t entry_count; /* Entry count. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) uint8_t sys_define; /* System defined. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) uint8_t entry_status; /* Entry Status. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) uint32_t handle; /* System handle. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) __le32 reserved_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) __le16 tgt_id_sts; /* Completion status. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) __le16 options;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) uint32_t abort_handle; /* System handle. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) __le32 reserved_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) __le16 req_que_no;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) uint8_t reserved_1[38];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define IOCTL_IOSB_TYPE_FX00 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) struct ioctl_iocb_entry_fx00 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) uint8_t entry_type; /* Entry type. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) uint8_t entry_count; /* Entry count. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) uint8_t sys_define; /* System defined. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) uint8_t entry_status; /* Entry Status. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) uint32_t handle; /* System handle. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) uint32_t reserved_0; /* System handle. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) uint16_t comp_func_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) __le16 fw_iotcl_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) __le32 dataword_r; /* Data word returned */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) uint32_t adapid; /* Adapter ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) uint32_t dataword_r_extra;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) __le32 seq_no;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) uint8_t reserved_2[20];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) uint32_t residuallen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) __le32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define STATUS_CONT_TYPE_FX00 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define FX00_IOCB_TYPE 0x0B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) struct fxdisc_entry_fx00 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) uint8_t entry_type; /* Entry type. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) uint8_t entry_count; /* Entry count. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) uint8_t sys_define; /* System Defined. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) uint8_t entry_status; /* Entry Status. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) uint32_t handle; /* System handle. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) __le32 reserved_0; /* System handle. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) __le16 func_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) __le16 req_xfrcnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) __le16 req_dsdcnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) __le16 rsp_xfrcnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) __le16 rsp_dsdcnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) uint8_t flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) uint8_t reserved_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) struct dsd64 dseg_rq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) struct dsd64 dseg_rsp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) __le32 dataword;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) __le32 adapid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) __le32 adapid_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) __le32 dataword_extra;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) struct qlafx00_tgt_node_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) uint8_t tgt_node_wwpn[WWN_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) uint8_t tgt_node_wwnn[WWN_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) uint32_t tgt_node_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) uint8_t reserved[128];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) uint32_t reserved_1[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) uint64_t reserved_2[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define QLAFX00_TGT_NODE_INFO sizeof(struct qlafx00_tgt_node_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define QLAFX00_LINK_STATUS_DOWN 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define QLAFX00_LINK_STATUS_UP 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define QLAFX00_PORT_SPEED_2G 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define QLAFX00_PORT_SPEED_4G 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define QLAFX00_PORT_SPEED_8G 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define QLAFX00_PORT_SPEED_10G 0xa
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) struct port_info_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) uint8_t port_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) uint8_t port_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) uint16_t port_identifier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) uint32_t up_port_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) uint8_t fw_ver_num[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) uint8_t portal_attrib;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) uint16_t host_option;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) uint8_t reset_delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) uint8_t pdwn_retry_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) uint16_t max_luns2tgt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) uint8_t risc_ver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) uint8_t pconn_option;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) uint16_t risc_option;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) uint16_t max_frame_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) uint16_t max_iocb_alloc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) uint16_t exec_throttle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) uint8_t retry_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) uint8_t retry_delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) uint8_t port_name[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) uint8_t port_id[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) uint8_t link_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) uint8_t plink_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) uint32_t link_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) uint16_t adap_haddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) uint8_t tgt_disc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) uint8_t log_tout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) uint8_t node_name[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) uint16_t erisc_opt1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) uint8_t resp_acc_tmr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) uint8_t intr_del_tmr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) uint8_t erisc_opt2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) uint8_t alt_port_name[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) uint8_t alt_node_name[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) uint8_t link_down_tout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) uint8_t conn_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) uint8_t fc_fw_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) uint32_t uiReserved[48];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /* OS Type Designations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define OS_TYPE_UNKNOWN 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define OS_TYPE_LINUX 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) /* Linux Info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define SYSNAME_LENGTH 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define NODENAME_LENGTH 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define RELEASE_LENGTH 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define VERSION_LENGTH 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define MACHINE_LENGTH 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define DOMNAME_LENGTH 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) struct host_system_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) uint32_t os_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) char sysname[SYSNAME_LENGTH];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) char nodename[NODENAME_LENGTH];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) char release[RELEASE_LENGTH];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) char version[VERSION_LENGTH];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) char machine[MACHINE_LENGTH];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) char domainname[DOMNAME_LENGTH];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) char hostdriver[VERSION_LENGTH];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) uint32_t reserved[64];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) struct register_host_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) struct host_system_info hsi; /* host system info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) uint64_t utc; /* UTC (system time) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) uint32_t reserved[64]; /* future additions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define QLAFX00_PORT_DATA_INFO (sizeof(struct port_info_data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define QLAFX00_TGT_NODE_LIST_SIZE (sizeof(uint32_t) * 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) struct config_info_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) uint8_t model_num[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) uint8_t model_description[80];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) uint8_t reserved0[160];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) uint8_t symbolic_name[64];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) uint8_t serial_num[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) uint8_t hw_version[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) uint8_t fw_version[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) uint8_t uboot_version[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) uint8_t fru_serial_num[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) uint8_t fc_port_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) uint8_t iscsi_port_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) uint8_t reserved1[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) uint8_t mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) uint8_t log_level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) uint8_t reserved2[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) uint32_t log_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) uint8_t tgt_pres_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) uint8_t iqn_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) uint8_t lun_mapping;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) uint64_t adapter_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) uint32_t cluster_key_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) uint8_t cluster_key[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) uint64_t cluster_master_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) uint64_t cluster_slave_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) uint8_t cluster_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) uint32_t enabled_capabilities;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) uint32_t nominal_temp_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define FXDISC_GET_CONFIG_INFO 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define FXDISC_GET_PORT_INFO 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define FXDISC_GET_TGT_NODE_INFO 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define FXDISC_GET_TGT_NODE_LIST 0x81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define FXDISC_REG_HOST_INFO 0x99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define FXDISC_ABORT_IOCTL 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define QLAFX00_HBA_ICNTRL_REG 0x20B08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define QLAFX00_ICR_ENB_MASK 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define QLAFX00_ICR_DIS_MASK 0x7fffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define QLAFX00_HST_RST_REG 0x18264
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define QLAFX00_SOC_TEMP_REG 0x184C4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define QLAFX00_HST_TO_HBA_REG 0x20A04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define QLAFX00_HBA_TO_HOST_REG 0x21B70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define QLAFX00_HST_INT_STS_BITS 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define QLAFX00_BAR1_BASE_ADDR_REG 0x40018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define QLAFX00_PEX0_WIN0_BASE_ADDR_REG 0x41824
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define QLAFX00_INTR_MB_CMPLT 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define QLAFX00_INTR_RSP_CMPLT 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define QLAFX00_INTR_ASYNC_CMPLT 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define QLAFX00_MBA_SYSTEM_ERR 0x8002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define QLAFX00_MBA_TEMP_OVER 0x8005
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define QLAFX00_MBA_TEMP_NORM 0x8006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define QLAFX00_MBA_TEMP_CRIT 0x8007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define QLAFX00_MBA_LINK_UP 0x8011
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define QLAFX00_MBA_LINK_DOWN 0x8012
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define QLAFX00_MBA_PORT_UPDATE 0x8014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define QLAFX00_MBA_SHUTDOWN_RQSTD 0x8062
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define SOC_SW_RST_CONTROL_REG_CORE0 0x0020800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define SOC_FABRIC_RST_CONTROL_REG 0x0020840
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define SOC_FABRIC_CONTROL_REG 0x0020200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define SOC_FABRIC_CONFIG_REG 0x0020204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define SOC_PWR_MANAGEMENT_PWR_DOWN_REG 0x001820C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define SOC_INTERRUPT_SOURCE_I_CONTROL_REG 0x0020B00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define SOC_CORE_TIMER_REG 0x0021850
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define SOC_IRQ_ACK_REG 0x00218b4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define CONTINUE_A64_TYPE_FX00 0x03 /* Continuation entry. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define QLAFX00_SET_HST_INTR(ha, value) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) wrt_reg_dword((ha)->cregbase + QLAFX00_HST_TO_HBA_REG, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define QLAFX00_CLR_HST_INTR(ha, value) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) wrt_reg_dword((ha)->cregbase + QLAFX00_HBA_TO_HOST_REG, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) ~value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define QLAFX00_RD_INTR_REG(ha) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) rd_reg_dword((ha)->cregbase + QLAFX00_HBA_TO_HOST_REG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define QLAFX00_CLR_INTR_REG(ha, value) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) wrt_reg_dword((ha)->cregbase + QLAFX00_HBA_TO_HOST_REG, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) ~value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define QLAFX00_SET_HBA_SOC_REG(ha, off, val)\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) wrt_reg_dword((ha)->cregbase + off, val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define QLAFX00_GET_HBA_SOC_REG(ha, off)\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) rd_reg_dword((ha)->cregbase + off)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define QLAFX00_HBA_RST_REG(ha, val)\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) wrt_reg_dword((ha)->cregbase + QLAFX00_HST_RST_REG, val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define QLAFX00_RD_ICNTRL_REG(ha) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) rd_reg_dword((ha)->cregbase + QLAFX00_HBA_ICNTRL_REG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define QLAFX00_ENABLE_ICNTRL_REG(ha) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) wrt_reg_dword((ha)->cregbase + QLAFX00_HBA_ICNTRL_REG, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) (QLAFX00_GET_HBA_SOC_REG(ha, QLAFX00_HBA_ICNTRL_REG) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) QLAFX00_ICR_ENB_MASK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define QLAFX00_DISABLE_ICNTRL_REG(ha) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) wrt_reg_dword((ha)->cregbase + QLAFX00_HBA_ICNTRL_REG, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) (QLAFX00_GET_HBA_SOC_REG(ha, QLAFX00_HBA_ICNTRL_REG) & \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) QLAFX00_ICR_DIS_MASK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define QLAFX00_RD_REG(ha, off) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) rd_reg_dword((ha)->cregbase + off)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define QLAFX00_WR_REG(ha, off, val) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) wrt_reg_dword((ha)->cregbase + off, val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) struct qla_mt_iocb_rqst_fx00 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) __le32 reserved_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) __le16 func_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) uint8_t flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) uint8_t reserved_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) __le32 dataword;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) __le32 adapid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) __le32 adapid_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) __le32 dataword_extra;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) __le16 req_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) __le16 reserved_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) __le16 rsp_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) __le16 reserved_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) struct qla_mt_iocb_rsp_fx00 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) uint32_t reserved_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) uint16_t func_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) __le16 ioctl_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) __le32 ioctl_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) uint32_t adapid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) uint32_t adapid_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) uint32_t reserved_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) __le32 seq_number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) uint8_t reserved_3[20];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) int32_t res_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) __le32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) #define MAILBOX_REGISTER_COUNT_FX00 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) #define AEN_MAILBOX_REGISTER_COUNT_FX00 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) #define MAX_FIBRE_DEVICES_FX00 512
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) #define MAX_LUNS_FX00 0x1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) #define MAX_TARGETS_FX00 MAX_ISA_DEVICES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) #define REQUEST_ENTRY_CNT_FX00 512 /* Number of request entries. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) #define RESPONSE_ENTRY_CNT_FX00 256 /* Number of response entries.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) * Firmware state codes for QLAFX00 adapters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) #define FSTATE_FX00_CONFIG_WAIT 0x0000 /* Waiting for driver to issue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) * Initialize FW Mbox cmd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) #define FSTATE_FX00_INITIALIZED 0x1000 /* FW has been initialized by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) * the driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) #define FX00_DEF_RATOV 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) struct mr_data_fx00 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) uint8_t symbolic_name[64];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) uint8_t serial_num[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) uint8_t hw_version[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) uint8_t fw_version[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) uint8_t uboot_version[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) uint8_t fru_serial_num[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) fc_port_t fcport; /* fcport used for requests
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) * that are not linked
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) * to a particular target
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) uint8_t fw_hbt_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) uint8_t fw_hbt_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) uint8_t fw_hbt_miss_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) uint32_t old_fw_hbt_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) uint16_t fw_reset_timer_tick;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) uint8_t fw_reset_timer_exp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) uint16_t fw_critemp_timer_tick;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) uint32_t old_aenmbx0_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) uint32_t critical_temperature;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) bool extended_io_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) bool host_info_resend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) uint8_t hinfo_resend_timer_tick;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) #define QLAFX00_EXTENDED_IO_EN_MASK 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) * SoC Junction Temperature is stored in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) * bits 9:1 of SoC Junction Temperature Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) * in a firmware specific format format.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) * To get the temperature in Celsius degrees
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) * the value from this bitfiled should be converted
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) * using this formula:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) * Temperature (degrees C) = ((3,153,000 - (10,000 * X)) / 13,825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) * where X is the bit field value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) * this macro reads the register, extracts the bitfield value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) * performs the calcualtions and returns temperature in Celsius
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) #define QLAFX00_GET_TEMPERATURE(ha) ((3153000 - (10000 * \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) ((QLAFX00_RD_REG(ha, QLAFX00_SOC_TEMP_REG) & 0x3FE) >> 1))) / 13825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) #define QLAFX00_LOOP_DOWN_TIME 615 /* 600 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) #define QLAFX00_HEARTBEAT_INTERVAL 6 /* number of seconds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) #define QLAFX00_HEARTBEAT_MISS_CNT 3 /* number of miss */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) #define QLAFX00_RESET_INTERVAL 120 /* number of seconds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) #define QLAFX00_MAX_RESET_INTERVAL 600 /* number of seconds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) #define QLAFX00_CRITEMP_INTERVAL 60 /* number of seconds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) #define QLAFX00_HINFO_RESEND_INTERVAL 60 /* number of seconds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) #define QLAFX00_CRITEMP_THRSHLD 80 /* Celsius degrees */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) /* Max conncurrent IOs that can be queued */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) #define QLAFX00_MAX_CANQUEUE 1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) /* IOCTL IOCB abort success */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) #define QLAFX00_IOCTL_ICOB_ABORT_SUCCESS 0x68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags