^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * QLogic Fibre Channel HBA Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (c) 2003-2014 QLogic Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include "qla_def.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include "qla_target.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/gfp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #ifdef CONFIG_PPC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define IS_PPCARCH true
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define IS_PPCARCH false
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) static struct mb_cmd_name {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) uint16_t cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) const char *str;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) } mb_str[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) {MBC_GET_PORT_DATABASE, "GPDB"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) {MBC_GET_ID_LIST, "GIDList"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) {MBC_GET_LINK_PRIV_STATS, "Stats"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) {MBC_GET_RESOURCE_COUNTS, "ResCnt"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) static const char *mb_to_str(uint16_t cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) struct mb_cmd_name *e;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) for (i = 0; i < ARRAY_SIZE(mb_str); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) e = mb_str + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) if (cmd == e->cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) return e->str;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) return "unknown";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) static struct rom_cmd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) uint16_t cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) } rom_cmds[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) { MBC_LOAD_RAM },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) { MBC_EXECUTE_FIRMWARE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) { MBC_READ_RAM_WORD },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) { MBC_MAILBOX_REGISTER_TEST },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) { MBC_VERIFY_CHECKSUM },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) { MBC_GET_FIRMWARE_VERSION },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) { MBC_LOAD_RISC_RAM },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) { MBC_DUMP_RISC_RAM },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) { MBC_LOAD_RISC_RAM_EXTENDED },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) { MBC_DUMP_RISC_RAM_EXTENDED },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) { MBC_WRITE_RAM_WORD_EXTENDED },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) { MBC_READ_RAM_EXTENDED },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) { MBC_GET_RESOURCE_COUNTS },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) { MBC_SET_FIRMWARE_OPTION },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) { MBC_MID_INITIALIZE_FIRMWARE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) { MBC_GET_FIRMWARE_STATE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) { MBC_GET_MEM_OFFLOAD_CNTRL_STAT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) { MBC_GET_RETRY_COUNT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) { MBC_TRACE_CONTROL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) { MBC_INITIALIZE_MULTIQ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) { MBC_IOCB_COMMAND_A64 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) { MBC_GET_ADAPTER_LOOP_ID },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) { MBC_READ_SFP },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) { MBC_SET_RNID_PARAMS },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) { MBC_GET_RNID_PARAMS },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) { MBC_GET_SET_ZIO_THRESHOLD },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static int is_rom_cmd(uint16_t cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct rom_cmd *wc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) for (i = 0; i < ARRAY_SIZE(rom_cmds); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) wc = rom_cmds + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) if (wc->cmd == cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * qla2x00_mailbox_command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * Issue mailbox command and waits for completion.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * Input:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * ha = adapter block pointer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * mcp = driver internal mbx struct pointer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * Output:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * mb[MAX_MAILBOX_REGISTER_COUNT] = returned mailbox data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * Returns:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * 0 : QLA_SUCCESS = cmd performed success
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * 1 : QLA_FUNCTION_FAILED (error encountered)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * 6 : QLA_FUNCTION_TIMEOUT (timeout condition encountered)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * Context:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * Kernel context.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) qla2x00_mailbox_command(scsi_qla_host_t *vha, mbx_cmd_t *mcp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) int rval, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) unsigned long flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) device_reg_t *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) uint8_t abort_active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) uint8_t io_lock_on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) uint16_t command = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) uint16_t *iptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) __le16 __iomem *optr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) uint32_t cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) uint32_t mboxes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) unsigned long wait_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) u32 chip_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) ql_dbg(ql_dbg_mbx, vha, 0x1000, "Entered %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) if (ha->pdev->error_state == pci_channel_io_perm_failure) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) ql_log(ql_log_warn, vha, 0x1001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) "PCI channel failed permanently, exiting.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) return QLA_FUNCTION_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) if (vha->device_flags & DFLG_DEV_FAILED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) ql_log(ql_log_warn, vha, 0x1002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) "Device in failed state, exiting.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) return QLA_FUNCTION_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /* if PCI error, then avoid mbx processing.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) if (test_bit(PFLG_DISCONNECTED, &base_vha->dpc_flags) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) test_bit(UNLOADING, &base_vha->dpc_flags)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) ql_log(ql_log_warn, vha, 0xd04e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) "PCI error, exiting.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) return QLA_FUNCTION_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) reg = ha->iobase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) io_lock_on = base_vha->flags.init_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) rval = QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) abort_active = test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) chip_reset = ha->chip_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) if (ha->flags.pci_channel_io_perm_failure) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) ql_log(ql_log_warn, vha, 0x1003,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) "Perm failure on EEH timeout MBX, exiting.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) return QLA_FUNCTION_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) if (IS_P3P_TYPE(ha) && ha->flags.isp82xx_fw_hung) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /* Setting Link-Down error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) mcp->mb[0] = MBS_LINK_DOWN_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) ql_log(ql_log_warn, vha, 0x1004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) "FW hung = %d.\n", ha->flags.isp82xx_fw_hung);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) return QLA_FUNCTION_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /* check if ISP abort is active and return cmd with timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) if ((test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) !is_rom_cmd(mcp->mb[0])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) ql_log(ql_log_info, vha, 0x1005,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) "Cmd 0x%x aborted with timeout since ISP Abort is pending\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) mcp->mb[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) return QLA_FUNCTION_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) atomic_inc(&ha->num_pend_mbx_stage1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) * Wait for active mailbox commands to finish by waiting at most tov
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) * seconds. This is to serialize actual issuing of mailbox cmds during
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) * non ISP abort time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) if (!wait_for_completion_timeout(&ha->mbx_cmd_comp, mcp->tov * HZ)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /* Timeout occurred. Return error. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) ql_log(ql_log_warn, vha, 0xd035,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) "Cmd access timeout, cmd=0x%x, Exiting.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) mcp->mb[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) atomic_dec(&ha->num_pend_mbx_stage1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) return QLA_FUNCTION_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) atomic_dec(&ha->num_pend_mbx_stage1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) if (ha->flags.purge_mbox || chip_reset != ha->chip_reset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) rval = QLA_ABORTED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) goto premature_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /* Save mailbox command for debug */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) ha->mcp = mcp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) ql_dbg(ql_dbg_mbx, vha, 0x1006,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) "Prepare to issue mbox cmd=0x%x.\n", mcp->mb[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) spin_lock_irqsave(&ha->hardware_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) if (ha->flags.purge_mbox || chip_reset != ha->chip_reset ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) ha->flags.mbox_busy) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) rval = QLA_ABORTED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) spin_unlock_irqrestore(&ha->hardware_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) goto premature_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) ha->flags.mbox_busy = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) /* Load mailbox registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) if (IS_P3P_TYPE(ha))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) optr = ®->isp82.mailbox_in[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) else if (IS_FWI2_CAPABLE(ha) && !(IS_P3P_TYPE(ha)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) optr = ®->isp24.mailbox0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) optr = MAILBOX_REG(ha, ®->isp, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) iptr = mcp->mb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) command = mcp->mb[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) mboxes = mcp->out_mb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) ql_dbg(ql_dbg_mbx, vha, 0x1111,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) "Mailbox registers (OUT):\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) for (cnt = 0; cnt < ha->mbx_count; cnt++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) if (IS_QLA2200(ha) && cnt == 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) optr = MAILBOX_REG(ha, ®->isp, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) if (mboxes & BIT_0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) ql_dbg(ql_dbg_mbx, vha, 0x1112,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) "mbox[%d]<-0x%04x\n", cnt, *iptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) wrt_reg_word(optr, *iptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) mboxes >>= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) optr++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) iptr++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1117,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) "I/O Address = %p.\n", optr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /* Issue set host interrupt command to send cmd out. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) ha->flags.mbox_int = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) /* Unlock mbx registers and wait for interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) ql_dbg(ql_dbg_mbx, vha, 0x100f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) "Going to unlock irq & waiting for interrupts. "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) "jiffies=%lx.\n", jiffies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) /* Wait for mbx cmd completion until timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) atomic_inc(&ha->num_pend_mbx_stage2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) if ((!abort_active && io_lock_on) || IS_NOPOLLING_TYPE(ha)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) set_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) if (IS_P3P_TYPE(ha))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) wrt_reg_dword(®->isp82.hint, HINT_MBX_INT_PENDING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) else if (IS_FWI2_CAPABLE(ha))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) wrt_reg_dword(®->isp24.hccr, HCCRX_SET_HOST_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) wrt_reg_word(®->isp.hccr, HCCR_SET_HOST_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) spin_unlock_irqrestore(&ha->hardware_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) wait_time = jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) atomic_inc(&ha->num_pend_mbx_stage3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) if (!wait_for_completion_timeout(&ha->mbx_intr_comp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) mcp->tov * HZ)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) if (chip_reset != ha->chip_reset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) spin_lock_irqsave(&ha->hardware_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) ha->flags.mbox_busy = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) spin_unlock_irqrestore(&ha->hardware_lock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) atomic_dec(&ha->num_pend_mbx_stage2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) atomic_dec(&ha->num_pend_mbx_stage3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) rval = QLA_ABORTED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) goto premature_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) ql_dbg(ql_dbg_mbx, vha, 0x117a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) "cmd=%x Timeout.\n", command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) spin_lock_irqsave(&ha->hardware_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) clear_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) spin_unlock_irqrestore(&ha->hardware_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) } else if (ha->flags.purge_mbox ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) chip_reset != ha->chip_reset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) spin_lock_irqsave(&ha->hardware_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) ha->flags.mbox_busy = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) spin_unlock_irqrestore(&ha->hardware_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) atomic_dec(&ha->num_pend_mbx_stage2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) atomic_dec(&ha->num_pend_mbx_stage3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) rval = QLA_ABORTED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) goto premature_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) atomic_dec(&ha->num_pend_mbx_stage3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) if (time_after(jiffies, wait_time + 5 * HZ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) ql_log(ql_log_warn, vha, 0x1015, "cmd=0x%x, waited %d msecs\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) command, jiffies_to_msecs(jiffies - wait_time));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) ql_dbg(ql_dbg_mbx, vha, 0x1011,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) "Cmd=%x Polling Mode.\n", command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) if (IS_P3P_TYPE(ha)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) if (rd_reg_dword(®->isp82.hint) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) HINT_MBX_INT_PENDING) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) ha->flags.mbox_busy = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) spin_unlock_irqrestore(&ha->hardware_lock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) atomic_dec(&ha->num_pend_mbx_stage2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) ql_dbg(ql_dbg_mbx, vha, 0x1012,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) "Pending mailbox timeout, exiting.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) rval = QLA_FUNCTION_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) goto premature_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) wrt_reg_dword(®->isp82.hint, HINT_MBX_INT_PENDING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) } else if (IS_FWI2_CAPABLE(ha))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) wrt_reg_dword(®->isp24.hccr, HCCRX_SET_HOST_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) wrt_reg_word(®->isp.hccr, HCCR_SET_HOST_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) spin_unlock_irqrestore(&ha->hardware_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) wait_time = jiffies + mcp->tov * HZ; /* wait at most tov secs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) while (!ha->flags.mbox_int) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) if (ha->flags.purge_mbox ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) chip_reset != ha->chip_reset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) spin_lock_irqsave(&ha->hardware_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) ha->flags.mbox_busy = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) spin_unlock_irqrestore(&ha->hardware_lock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) atomic_dec(&ha->num_pend_mbx_stage2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) rval = QLA_ABORTED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) goto premature_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) if (time_after(jiffies, wait_time))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) /* Check for pending interrupts. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) qla2x00_poll(ha->rsp_q_map[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) if (!ha->flags.mbox_int &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) !(IS_QLA2200(ha) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) command == MBC_LOAD_RISC_RAM_EXTENDED))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) msleep(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) } /* while */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) ql_dbg(ql_dbg_mbx, vha, 0x1013,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) "Waited %d sec.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) (uint)((jiffies - (wait_time - (mcp->tov * HZ)))/HZ));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) atomic_dec(&ha->num_pend_mbx_stage2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) /* Check whether we timed out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) if (ha->flags.mbox_int) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) uint16_t *iptr2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) ql_dbg(ql_dbg_mbx, vha, 0x1014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) "Cmd=%x completed.\n", command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) /* Got interrupt. Clear the flag. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) ha->flags.mbox_int = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) if (IS_P3P_TYPE(ha) && ha->flags.isp82xx_fw_hung) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) spin_lock_irqsave(&ha->hardware_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) ha->flags.mbox_busy = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) spin_unlock_irqrestore(&ha->hardware_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) /* Setting Link-Down error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) mcp->mb[0] = MBS_LINK_DOWN_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) ha->mcp = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) rval = QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) ql_log(ql_log_warn, vha, 0xd048,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) "FW hung = %d.\n", ha->flags.isp82xx_fw_hung);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) goto premature_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) if (ha->mailbox_out[0] != MBS_COMMAND_COMPLETE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) ql_dbg(ql_dbg_mbx, vha, 0x11ff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) "mb_out[0] = %#x <> %#x\n", ha->mailbox_out[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) MBS_COMMAND_COMPLETE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) rval = QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) /* Load return mailbox registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) iptr2 = mcp->mb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) iptr = (uint16_t *)&ha->mailbox_out[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) mboxes = mcp->in_mb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) ql_dbg(ql_dbg_mbx, vha, 0x1113,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) "Mailbox registers (IN):\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) for (cnt = 0; cnt < ha->mbx_count; cnt++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) if (mboxes & BIT_0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) *iptr2 = *iptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) ql_dbg(ql_dbg_mbx, vha, 0x1114,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) "mbox[%d]->0x%04x\n", cnt, *iptr2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) mboxes >>= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) iptr2++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) iptr++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) uint16_t mb[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) uint32_t ictrl, host_status, hccr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) uint16_t w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) if (IS_FWI2_CAPABLE(ha)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) mb[0] = rd_reg_word(®->isp24.mailbox0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) mb[1] = rd_reg_word(®->isp24.mailbox1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) mb[2] = rd_reg_word(®->isp24.mailbox2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) mb[3] = rd_reg_word(®->isp24.mailbox3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) mb[7] = rd_reg_word(®->isp24.mailbox7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) ictrl = rd_reg_dword(®->isp24.ictrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) host_status = rd_reg_dword(®->isp24.host_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) hccr = rd_reg_dword(®->isp24.hccr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) ql_log(ql_log_warn, vha, 0xd04c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) "MBX Command timeout for cmd %x, iocontrol=%x jiffies=%lx "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) "mb[0-3]=[0x%x 0x%x 0x%x 0x%x] mb7 0x%x host_status 0x%x hccr 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) command, ictrl, jiffies, mb[0], mb[1], mb[2], mb[3],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) mb[7], host_status, hccr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) mb[0] = RD_MAILBOX_REG(ha, ®->isp, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) ictrl = rd_reg_word(®->isp.ictrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1119,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) "MBX Command timeout for cmd %x, iocontrol=%x jiffies=%lx "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) "mb[0]=0x%x\n", command, ictrl, jiffies, mb[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) ql_dump_regs(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1019);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) /* Capture FW dump only, if PCI device active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) if (!pci_channel_offline(vha->hw->pdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) if (w == 0xffff || ictrl == 0xffffffff ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) (chip_reset != ha->chip_reset)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) /* This is special case if there is unload
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) * of driver happening and if PCI device go
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) * into bad state due to PCI error condition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) * then only PCI ERR flag would be set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) * we will do premature exit for above case.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) spin_lock_irqsave(&ha->hardware_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) ha->flags.mbox_busy = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) spin_unlock_irqrestore(&ha->hardware_lock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) rval = QLA_FUNCTION_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) goto premature_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) /* Attempt to capture firmware dump for further
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) * anallysis of the current formware state. we do not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) * need to do this if we are intentionally generating
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) * a dump
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) if (mcp->mb[0] != MBC_GEN_SYSTEM_ERROR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) qla2xxx_dump_fw(vha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) rval = QLA_FUNCTION_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) spin_lock_irqsave(&ha->hardware_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) ha->flags.mbox_busy = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) spin_unlock_irqrestore(&ha->hardware_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) /* Clean up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) ha->mcp = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) if ((abort_active || !io_lock_on) && !IS_NOPOLLING_TYPE(ha)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) ql_dbg(ql_dbg_mbx, vha, 0x101a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) "Checking for additional resp interrupt.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) /* polling mode for non isp_abort commands. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) qla2x00_poll(ha->rsp_q_map[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) if (rval == QLA_FUNCTION_TIMEOUT &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) mcp->mb[0] != MBC_GEN_SYSTEM_ERROR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) if (!io_lock_on || (mcp->flags & IOCTL_CMD) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) ha->flags.eeh_busy) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) /* not in dpc. schedule it for dpc to take over. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) ql_dbg(ql_dbg_mbx, vha, 0x101b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) "Timeout, schedule isp_abort_needed.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) if (!test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) !test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) if (IS_QLA82XX(ha)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) ql_dbg(ql_dbg_mbx, vha, 0x112a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) "disabling pause transmit on port "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) "0 & 1.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) qla82xx_wr_32(ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) QLA82XX_CRB_NIU + 0x98,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) CRB_NIU_XG_PAUSE_CTL_P0|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) CRB_NIU_XG_PAUSE_CTL_P1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) ql_log(ql_log_info, base_vha, 0x101c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) "Mailbox cmd timeout occurred, cmd=0x%x, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) "mb[0]=0x%x, eeh_busy=0x%x. Scheduling ISP "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) "abort.\n", command, mcp->mb[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) ha->flags.eeh_busy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) qla2xxx_wake_dpc(vha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) } else if (current == ha->dpc_thread) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) /* call abort directly since we are in the DPC thread */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) ql_dbg(ql_dbg_mbx, vha, 0x101d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) "Timeout, calling abort_isp.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) if (!test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) !test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) if (IS_QLA82XX(ha)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) ql_dbg(ql_dbg_mbx, vha, 0x112b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) "disabling pause transmit on port "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) "0 & 1.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) qla82xx_wr_32(ha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) QLA82XX_CRB_NIU + 0x98,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) CRB_NIU_XG_PAUSE_CTL_P0|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) CRB_NIU_XG_PAUSE_CTL_P1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) ql_log(ql_log_info, base_vha, 0x101e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) "Mailbox cmd timeout occurred, cmd=0x%x, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) "mb[0]=0x%x. Scheduling ISP abort ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) command, mcp->mb[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) set_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) /* Allow next mbx cmd to come in. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) complete(&ha->mbx_cmd_comp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) if (ha->isp_ops->abort_isp(vha)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) /* Failed. retry later. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) set_bit(ISP_ABORT_NEEDED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) &vha->dpc_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) clear_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) ql_dbg(ql_dbg_mbx, vha, 0x101f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) "Finished abort_isp.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) goto mbx_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) premature_exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) /* Allow next mbx cmd to come in. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) complete(&ha->mbx_cmd_comp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) mbx_done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) if (rval == QLA_ABORTED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) ql_log(ql_log_info, vha, 0xd035,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) "Chip Reset in progress. Purging Mbox cmd=0x%x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) mcp->mb[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) } else if (rval) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) if (ql2xextended_error_logging & (ql_dbg_disc|ql_dbg_mbx)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) pr_warn("%s [%s]-%04x:%ld: **** Failed=%x", QL_MSGHDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) dev_name(&ha->pdev->dev), 0x1020+0x800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) vha->host_no, rval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) mboxes = mcp->in_mb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) cnt = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) for (i = 0; i < ha->mbx_count && cnt; i++, mboxes >>= 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) if (mboxes & BIT_0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) printk(" mb[%u]=%x", i, mcp->mb[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) cnt--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) pr_warn(" cmd=%x ****\n", command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) if (IS_FWI2_CAPABLE(ha) && !(IS_P3P_TYPE(ha))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) ql_dbg(ql_dbg_mbx, vha, 0x1198,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) "host_status=%#x intr_ctrl=%#x intr_status=%#x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) rd_reg_dword(®->isp24.host_status),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) rd_reg_dword(®->isp24.ictrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) rd_reg_dword(®->isp24.istatus));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) ql_dbg(ql_dbg_mbx, vha, 0x1206,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) "ctrl_status=%#x ictrl=%#x istatus=%#x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) rd_reg_word(®->isp.ctrl_status),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) rd_reg_word(®->isp.ictrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) rd_reg_word(®->isp.istatus));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) ql_dbg(ql_dbg_mbx, base_vha, 0x1021, "Done %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) qla2x00_load_ram(scsi_qla_host_t *vha, dma_addr_t req_dma, uint32_t risc_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) uint32_t risc_code_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) int rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) mbx_cmd_t mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) mbx_cmd_t *mcp = &mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1022,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) "Entered %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) if (MSW(risc_addr) || IS_FWI2_CAPABLE(ha)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) mcp->mb[0] = MBC_LOAD_RISC_RAM_EXTENDED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) mcp->mb[8] = MSW(risc_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) mcp->out_mb = MBX_8|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) mcp->mb[0] = MBC_LOAD_RISC_RAM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) mcp->out_mb = MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) mcp->mb[1] = LSW(risc_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) mcp->mb[2] = MSW(req_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) mcp->mb[3] = LSW(req_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) mcp->mb[6] = MSW(MSD(req_dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) mcp->mb[7] = LSW(MSD(req_dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) mcp->out_mb |= MBX_7|MBX_6|MBX_3|MBX_2|MBX_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) if (IS_FWI2_CAPABLE(ha)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) mcp->mb[4] = MSW(risc_code_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) mcp->mb[5] = LSW(risc_code_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) mcp->out_mb |= MBX_5|MBX_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) mcp->mb[4] = LSW(risc_code_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) mcp->out_mb |= MBX_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) mcp->in_mb = MBX_1|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) mcp->tov = MBX_TOV_SECONDS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) mcp->flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) rval = qla2x00_mailbox_command(vha, mcp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) if (rval != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) ql_dbg(ql_dbg_mbx, vha, 0x1023,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) "Failed=%x mb[0]=%x mb[1]=%x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) rval, mcp->mb[0], mcp->mb[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) "Done %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) #define NVME_ENABLE_FLAG BIT_3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) * qla2x00_execute_fw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) * Start adapter firmware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) * Input:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) * ha = adapter block pointer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) * TARGET_QUEUE_LOCK must be released.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) * ADAPTER_STATE_LOCK must be released.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) * Returns:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) * qla2x00 local function return status code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) * Context:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) * Kernel context.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) qla2x00_execute_fw(scsi_qla_host_t *vha, uint32_t risc_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) int rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) mbx_cmd_t mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) mbx_cmd_t *mcp = &mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) u8 semaphore = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) #define EXE_FW_FORCE_SEMAPHORE BIT_7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) u8 retry = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1025,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) "Entered %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) again:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) mcp->mb[0] = MBC_EXECUTE_FIRMWARE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) mcp->out_mb = MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) mcp->in_mb = MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) if (IS_FWI2_CAPABLE(ha)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) mcp->mb[1] = MSW(risc_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) mcp->mb[2] = LSW(risc_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) mcp->mb[3] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) mcp->mb[4] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) mcp->mb[11] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) /* Enable BPM? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) if (ha->flags.lr_detected) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) mcp->mb[4] = BIT_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) if (IS_BPM_RANGE_CAPABLE(ha))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) mcp->mb[4] |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) ha->lr_distance << LR_DIST_FW_POS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) if (ql2xnvmeenable && (IS_QLA27XX(ha) || IS_QLA28XX(ha)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) mcp->mb[4] |= NVME_ENABLE_FLAG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) if (IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) struct nvram_81xx *nv = ha->nvram;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) /* set minimum speed if specified in nvram */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) if (nv->min_supported_speed >= 2 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) nv->min_supported_speed <= 5) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) mcp->mb[4] |= BIT_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) mcp->mb[11] |= nv->min_supported_speed & 0xF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) mcp->out_mb |= MBX_11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) mcp->in_mb |= BIT_5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) vha->min_supported_speed =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) nv->min_supported_speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) if (IS_PPCARCH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) mcp->mb[11] |= BIT_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) if (ha->flags.exlogins_enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) mcp->mb[4] |= ENABLE_EXTENDED_LOGIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) if (ha->flags.exchoffld_enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) mcp->mb[4] |= ENABLE_EXCHANGE_OFFLD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) if (semaphore)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) mcp->mb[11] |= EXE_FW_FORCE_SEMAPHORE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) mcp->out_mb |= MBX_4 | MBX_3 | MBX_2 | MBX_1 | MBX_11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) mcp->in_mb |= MBX_3 | MBX_2 | MBX_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) mcp->mb[1] = LSW(risc_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) mcp->out_mb |= MBX_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) mcp->mb[2] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) mcp->out_mb |= MBX_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) mcp->tov = MBX_TOV_SECONDS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) mcp->flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) rval = qla2x00_mailbox_command(vha, mcp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) if (rval != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) if (IS_QLA28XX(ha) && rval == QLA_COMMAND_ERROR &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) mcp->mb[1] == 0x27 && retry) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) semaphore = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) retry--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) ql_dbg(ql_dbg_async, vha, 0x1026,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) "Exe FW: force semaphore.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) goto again;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) ql_dbg(ql_dbg_mbx, vha, 0x1026,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) if (!IS_FWI2_CAPABLE(ha))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) ha->fw_ability_mask = mcp->mb[3] << 16 | mcp->mb[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) ql_dbg(ql_dbg_mbx, vha, 0x119a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) "fw_ability_mask=%x.\n", ha->fw_ability_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) ql_dbg(ql_dbg_mbx, vha, 0x1027, "exchanges=%x.\n", mcp->mb[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) ha->max_supported_speed = mcp->mb[2] & (BIT_0|BIT_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) ql_dbg(ql_dbg_mbx, vha, 0x119b, "max_supported_speed=%s.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) ha->max_supported_speed == 0 ? "16Gps" :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) ha->max_supported_speed == 1 ? "32Gps" :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) ha->max_supported_speed == 2 ? "64Gps" : "unknown");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) if (vha->min_supported_speed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) ha->min_supported_speed = mcp->mb[5] &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) (BIT_0 | BIT_1 | BIT_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) ql_dbg(ql_dbg_mbx, vha, 0x119c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) "min_supported_speed=%s.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) ha->min_supported_speed == 6 ? "64Gps" :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) ha->min_supported_speed == 5 ? "32Gps" :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) ha->min_supported_speed == 4 ? "16Gps" :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) ha->min_supported_speed == 3 ? "8Gps" :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) ha->min_supported_speed == 2 ? "4Gps" : "unknown");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1028,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) "Done %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) * qla_get_exlogin_status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) * Get extended login status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) * uses the memory offload control/status Mailbox
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) * Input:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) * ha: adapter state pointer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) * fwopt: firmware options
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) * Returns:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) * qla2x00 local function status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) * Context:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) * Kernel context.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) #define FETCH_XLOGINS_STAT 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) qla_get_exlogin_status(scsi_qla_host_t *vha, uint16_t *buf_sz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) uint16_t *ex_logins_cnt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) int rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) mbx_cmd_t mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) mbx_cmd_t *mcp = &mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x118f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) "Entered %s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) memset(mcp->mb, 0 , sizeof(mcp->mb));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) mcp->mb[0] = MBC_GET_MEM_OFFLOAD_CNTRL_STAT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) mcp->mb[1] = FETCH_XLOGINS_STAT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) mcp->out_mb = MBX_1|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) mcp->in_mb = MBX_10|MBX_4|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) mcp->tov = MBX_TOV_SECONDS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) mcp->flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) rval = qla2x00_mailbox_command(vha, mcp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) if (rval != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) ql_dbg(ql_dbg_mbx, vha, 0x1115, "Failed=%x.\n", rval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) *buf_sz = mcp->mb[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) *ex_logins_cnt = mcp->mb[10];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) ql_log(ql_log_info, vha, 0x1190,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) "buffer size 0x%x, exchange login count=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) mcp->mb[4], mcp->mb[10]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1116,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) "Done %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) * qla_set_exlogin_mem_cfg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) * set extended login memory configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) * Mbx needs to be issues before init_cb is set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) * Input:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) * ha: adapter state pointer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) * buffer: buffer pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) * phys_addr: physical address of buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) * size: size of buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) * TARGET_QUEUE_LOCK must be released
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) * ADAPTER_STATE_LOCK must be release
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) * Returns:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) * qla2x00 local funxtion status code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) * Context:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) * Kernel context.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) #define CONFIG_XLOGINS_MEM 0x9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) qla_set_exlogin_mem_cfg(scsi_qla_host_t *vha, dma_addr_t phys_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) int rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) mbx_cmd_t mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) mbx_cmd_t *mcp = &mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x111a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) "Entered %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) memset(mcp->mb, 0 , sizeof(mcp->mb));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) mcp->mb[0] = MBC_GET_MEM_OFFLOAD_CNTRL_STAT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) mcp->mb[1] = CONFIG_XLOGINS_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) mcp->mb[2] = MSW(phys_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) mcp->mb[3] = LSW(phys_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) mcp->mb[6] = MSW(MSD(phys_addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) mcp->mb[7] = LSW(MSD(phys_addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) mcp->mb[8] = MSW(ha->exlogin_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) mcp->mb[9] = LSW(ha->exlogin_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) mcp->out_mb = MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) mcp->in_mb = MBX_11|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) mcp->tov = MBX_TOV_SECONDS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) mcp->flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) rval = qla2x00_mailbox_command(vha, mcp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) if (rval != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) ql_dbg(ql_dbg_mbx, vha, 0x111b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) "EXlogin Failed=%x. MB0=%x MB11=%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) rval, mcp->mb[0], mcp->mb[11]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x118c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) "Done %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) * qla_get_exchoffld_status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) * Get exchange offload status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) * uses the memory offload control/status Mailbox
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) * Input:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) * ha: adapter state pointer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) * fwopt: firmware options
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) * Returns:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) * qla2x00 local function status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) * Context:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) * Kernel context.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) #define FETCH_XCHOFFLD_STAT 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) qla_get_exchoffld_status(scsi_qla_host_t *vha, uint16_t *buf_sz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) uint16_t *ex_logins_cnt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) int rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) mbx_cmd_t mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) mbx_cmd_t *mcp = &mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1019,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) "Entered %s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) memset(mcp->mb, 0 , sizeof(mcp->mb));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) mcp->mb[0] = MBC_GET_MEM_OFFLOAD_CNTRL_STAT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) mcp->mb[1] = FETCH_XCHOFFLD_STAT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) mcp->out_mb = MBX_1|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) mcp->in_mb = MBX_10|MBX_4|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) mcp->tov = MBX_TOV_SECONDS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) mcp->flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) rval = qla2x00_mailbox_command(vha, mcp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) if (rval != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) ql_dbg(ql_dbg_mbx, vha, 0x1155, "Failed=%x.\n", rval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) *buf_sz = mcp->mb[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) *ex_logins_cnt = mcp->mb[10];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) ql_log(ql_log_info, vha, 0x118e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) "buffer size 0x%x, exchange offload count=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) mcp->mb[4], mcp->mb[10]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1156,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) "Done %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) * qla_set_exchoffld_mem_cfg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) * Set exchange offload memory configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) * Mbx needs to be issues before init_cb is set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) * Input:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) * ha: adapter state pointer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) * buffer: buffer pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) * phys_addr: physical address of buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) * size: size of buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) * TARGET_QUEUE_LOCK must be released
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) * ADAPTER_STATE_LOCK must be release
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) * Returns:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) * qla2x00 local funxtion status code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) * Context:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) * Kernel context.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) #define CONFIG_XCHOFFLD_MEM 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) qla_set_exchoffld_mem_cfg(scsi_qla_host_t *vha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) int rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) mbx_cmd_t mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) mbx_cmd_t *mcp = &mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1157,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) "Entered %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) memset(mcp->mb, 0 , sizeof(mcp->mb));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) mcp->mb[0] = MBC_GET_MEM_OFFLOAD_CNTRL_STAT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) mcp->mb[1] = CONFIG_XCHOFFLD_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) mcp->mb[2] = MSW(ha->exchoffld_buf_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) mcp->mb[3] = LSW(ha->exchoffld_buf_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) mcp->mb[6] = MSW(MSD(ha->exchoffld_buf_dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) mcp->mb[7] = LSW(MSD(ha->exchoffld_buf_dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) mcp->mb[8] = MSW(ha->exchoffld_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) mcp->mb[9] = LSW(ha->exchoffld_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) mcp->out_mb = MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) mcp->in_mb = MBX_11|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) mcp->tov = MBX_TOV_SECONDS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) mcp->flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) rval = qla2x00_mailbox_command(vha, mcp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) if (rval != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) /*EMPTY*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) ql_dbg(ql_dbg_mbx, vha, 0x1158, "Failed=%x.\n", rval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1192,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) "Done %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) * qla2x00_get_fw_version
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) * Get firmware version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) * Input:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) * ha: adapter state pointer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) * major: pointer for major number.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) * minor: pointer for minor number.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) * subminor: pointer for subminor number.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) * Returns:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) * qla2x00 local function return status code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) * Context:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) * Kernel context.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) qla2x00_get_fw_version(scsi_qla_host_t *vha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) int rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) mbx_cmd_t mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) mbx_cmd_t *mcp = &mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1029,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) "Entered %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) mcp->mb[0] = MBC_GET_FIRMWARE_VERSION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) mcp->out_mb = MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) mcp->in_mb = MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) if (IS_QLA81XX(vha->hw) || IS_QLA8031(ha) || IS_QLA8044(ha))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) mcp->in_mb |= MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) if (IS_FWI2_CAPABLE(ha))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) mcp->in_mb |= MBX_17|MBX_16|MBX_15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) if (IS_QLA27XX(ha) || IS_QLA28XX(ha))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) mcp->in_mb |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) MBX_25|MBX_24|MBX_23|MBX_22|MBX_21|MBX_20|MBX_19|MBX_18|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) MBX_14|MBX_13|MBX_11|MBX_10|MBX_9|MBX_8|MBX_7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) mcp->flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) mcp->tov = MBX_TOV_SECONDS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) rval = qla2x00_mailbox_command(vha, mcp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) if (rval != QLA_SUCCESS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) goto failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) /* Return mailbox data. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) ha->fw_major_version = mcp->mb[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) ha->fw_minor_version = mcp->mb[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) ha->fw_subminor_version = mcp->mb[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) ha->fw_attributes = mcp->mb[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) if (IS_QLA2100(vha->hw) || IS_QLA2200(vha->hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) ha->fw_memory_size = 0x1FFFF; /* Defaults to 128KB. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) ha->fw_memory_size = (mcp->mb[5] << 16) | mcp->mb[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) if (IS_QLA81XX(vha->hw) || IS_QLA8031(vha->hw) || IS_QLA8044(ha)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) ha->mpi_version[0] = mcp->mb[10] & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) ha->mpi_version[1] = mcp->mb[11] >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) ha->mpi_version[2] = mcp->mb[11] & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) ha->mpi_capabilities = (mcp->mb[12] << 16) | mcp->mb[13];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) ha->phy_version[0] = mcp->mb[8] & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) ha->phy_version[1] = mcp->mb[9] >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) ha->phy_version[2] = mcp->mb[9] & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) if (IS_FWI2_CAPABLE(ha)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) ha->fw_attributes_h = mcp->mb[15];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) ha->fw_attributes_ext[0] = mcp->mb[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) ha->fw_attributes_ext[1] = mcp->mb[17];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1139,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) "%s: FW_attributes Upper: 0x%x, Lower: 0x%x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) __func__, mcp->mb[15], mcp->mb[6]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x112f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) "%s: Ext_FwAttributes Upper: 0x%x, Lower: 0x%x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) __func__, mcp->mb[17], mcp->mb[16]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) if (ha->fw_attributes_h & 0x4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x118d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) "%s: Firmware supports Extended Login 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) __func__, ha->fw_attributes_h);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) if (ha->fw_attributes_h & 0x8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1191,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) "%s: Firmware supports Exchange Offload 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) __func__, ha->fw_attributes_h);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) * FW supports nvme and driver load parameter requested nvme.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) * BIT 26 of fw_attributes indicates NVMe support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) if ((ha->fw_attributes_h &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) (FW_ATTR_H_NVME | FW_ATTR_H_NVME_UPDATED)) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) ql2xnvmeenable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) if (ha->fw_attributes_h & FW_ATTR_H_NVME_FBURST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) vha->flags.nvme_first_burst = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) vha->flags.nvme_enabled = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) ql_log(ql_log_info, vha, 0xd302,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) "%s: FC-NVMe is Enabled (0x%x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) __func__, ha->fw_attributes_h);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) /* BIT_13 of Extended FW Attributes informs about NVMe2 support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) if (ha->fw_attributes_ext[0] & FW_ATTR_EXT0_NVME2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) ql_log(ql_log_info, vha, 0xd302,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) "Firmware supports NVMe2 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) ha->fw_attributes_ext[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) vha->flags.nvme2_enabled = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) ha->serdes_version[0] = mcp->mb[7] & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) ha->serdes_version[1] = mcp->mb[8] >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) ha->serdes_version[2] = mcp->mb[8] & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) ha->mpi_version[0] = mcp->mb[10] & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) ha->mpi_version[1] = mcp->mb[11] >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) ha->mpi_version[2] = mcp->mb[11] & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) ha->pep_version[0] = mcp->mb[13] & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) ha->pep_version[1] = mcp->mb[14] >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) ha->pep_version[2] = mcp->mb[14] & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) ha->fw_shared_ram_start = (mcp->mb[19] << 16) | mcp->mb[18];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) ha->fw_shared_ram_end = (mcp->mb[21] << 16) | mcp->mb[20];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) ha->fw_ddr_ram_start = (mcp->mb[23] << 16) | mcp->mb[22];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) ha->fw_ddr_ram_end = (mcp->mb[25] << 16) | mcp->mb[24];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) if (IS_QLA28XX(ha)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) if (mcp->mb[16] & BIT_10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) ha->flags.secure_fw = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) ql_log(ql_log_info, vha, 0xffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) "Secure Flash Update in FW: %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) (ha->flags.secure_fw) ? "Supported" :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) "Not Supported");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) if (ha->flags.scm_supported_a &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) (ha->fw_attributes_ext[0] & FW_ATTR_EXT0_SCM_SUPPORTED)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) ha->flags.scm_supported_f = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) ha->sf_init_cb->flags |= cpu_to_le16(BIT_13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) ql_log(ql_log_info, vha, 0x11a3, "SCM in FW: %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) (ha->flags.scm_supported_f) ? "Supported" :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) "Not Supported");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) if (vha->flags.nvme2_enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) /* set BIT_15 of special feature control block for SLER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) ha->sf_init_cb->flags |= cpu_to_le16(BIT_15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) /* set BIT_14 of special feature control block for PI CTRL*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) ha->sf_init_cb->flags |= cpu_to_le16(BIT_14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) failed:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) if (rval != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) /*EMPTY*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) ql_dbg(ql_dbg_mbx, vha, 0x102a, "Failed=%x.\n", rval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) /*EMPTY*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x102b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) "Done %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) * qla2x00_get_fw_options
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) * Set firmware options.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) * Input:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) * ha = adapter block pointer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) * fwopt = pointer for firmware options.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) * Returns:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) * qla2x00 local function return status code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) * Context:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) * Kernel context.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) qla2x00_get_fw_options(scsi_qla_host_t *vha, uint16_t *fwopts)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) int rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) mbx_cmd_t mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) mbx_cmd_t *mcp = &mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x102c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) "Entered %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) mcp->mb[0] = MBC_GET_FIRMWARE_OPTION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) mcp->out_mb = MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) mcp->tov = MBX_TOV_SECONDS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) mcp->flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) rval = qla2x00_mailbox_command(vha, mcp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) if (rval != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) /*EMPTY*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) ql_dbg(ql_dbg_mbx, vha, 0x102d, "Failed=%x.\n", rval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) fwopts[0] = mcp->mb[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) fwopts[1] = mcp->mb[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) fwopts[2] = mcp->mb[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) fwopts[3] = mcp->mb[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x102e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) "Done %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) * qla2x00_set_fw_options
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) * Set firmware options.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) * Input:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) * ha = adapter block pointer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) * fwopt = pointer for firmware options.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) * Returns:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) * qla2x00 local function return status code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) * Context:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) * Kernel context.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) qla2x00_set_fw_options(scsi_qla_host_t *vha, uint16_t *fwopts)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) int rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) mbx_cmd_t mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) mbx_cmd_t *mcp = &mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x102f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) "Entered %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) mcp->mb[0] = MBC_SET_FIRMWARE_OPTION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) mcp->mb[1] = fwopts[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) mcp->mb[2] = fwopts[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) mcp->mb[3] = fwopts[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) mcp->in_mb = MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) if (IS_FWI2_CAPABLE(vha->hw)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) mcp->in_mb |= MBX_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) mcp->mb[10] = fwopts[10];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) mcp->out_mb |= MBX_10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) mcp->mb[10] = fwopts[10];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) mcp->mb[11] = fwopts[11];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) mcp->mb[12] = 0; /* Undocumented, but used */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) mcp->out_mb |= MBX_12|MBX_11|MBX_10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) mcp->tov = MBX_TOV_SECONDS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) mcp->flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) rval = qla2x00_mailbox_command(vha, mcp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) fwopts[0] = mcp->mb[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) if (rval != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) /*EMPTY*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) ql_dbg(ql_dbg_mbx, vha, 0x1030,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) "Failed=%x (%x/%x).\n", rval, mcp->mb[0], mcp->mb[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) /*EMPTY*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1031,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) "Done %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) * qla2x00_mbx_reg_test
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) * Mailbox register wrap test.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) * Input:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) * ha = adapter block pointer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) * TARGET_QUEUE_LOCK must be released.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) * ADAPTER_STATE_LOCK must be released.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) * Returns:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) * qla2x00 local function return status code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) * Context:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) * Kernel context.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) qla2x00_mbx_reg_test(scsi_qla_host_t *vha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) int rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) mbx_cmd_t mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) mbx_cmd_t *mcp = &mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1032,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) "Entered %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) mcp->mb[0] = MBC_MAILBOX_REGISTER_TEST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) mcp->mb[1] = 0xAAAA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) mcp->mb[2] = 0x5555;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) mcp->mb[3] = 0xAA55;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) mcp->mb[4] = 0x55AA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) mcp->mb[5] = 0xA5A5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) mcp->mb[6] = 0x5A5A;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) mcp->mb[7] = 0x2525;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) mcp->out_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) mcp->in_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) mcp->tov = MBX_TOV_SECONDS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) mcp->flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) rval = qla2x00_mailbox_command(vha, mcp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) if (rval == QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) if (mcp->mb[1] != 0xAAAA || mcp->mb[2] != 0x5555 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) mcp->mb[3] != 0xAA55 || mcp->mb[4] != 0x55AA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) rval = QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) if (mcp->mb[5] != 0xA5A5 || mcp->mb[6] != 0x5A5A ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) mcp->mb[7] != 0x2525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) rval = QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) if (rval != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) /*EMPTY*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) ql_dbg(ql_dbg_mbx, vha, 0x1033, "Failed=%x.\n", rval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) /*EMPTY*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1034,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) "Done %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) * qla2x00_verify_checksum
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) * Verify firmware checksum.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) * Input:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) * ha = adapter block pointer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) * TARGET_QUEUE_LOCK must be released.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) * ADAPTER_STATE_LOCK must be released.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) * Returns:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) * qla2x00 local function return status code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) * Context:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) * Kernel context.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) qla2x00_verify_checksum(scsi_qla_host_t *vha, uint32_t risc_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) int rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) mbx_cmd_t mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) mbx_cmd_t *mcp = &mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1035,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) "Entered %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) mcp->mb[0] = MBC_VERIFY_CHECKSUM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) mcp->out_mb = MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) mcp->in_mb = MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) if (IS_FWI2_CAPABLE(vha->hw)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) mcp->mb[1] = MSW(risc_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) mcp->mb[2] = LSW(risc_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) mcp->out_mb |= MBX_2|MBX_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) mcp->in_mb |= MBX_2|MBX_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) mcp->mb[1] = LSW(risc_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) mcp->out_mb |= MBX_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) mcp->in_mb |= MBX_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) mcp->tov = MBX_TOV_SECONDS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) mcp->flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) rval = qla2x00_mailbox_command(vha, mcp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) if (rval != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) ql_dbg(ql_dbg_mbx, vha, 0x1036,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) "Failed=%x chm sum=%x.\n", rval, IS_FWI2_CAPABLE(vha->hw) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) (mcp->mb[2] << 16) | mcp->mb[1] : mcp->mb[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1037,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) "Done %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) * qla2x00_issue_iocb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) * Issue IOCB using mailbox command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) * Input:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) * ha = adapter state pointer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) * buffer = buffer pointer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) * phys_addr = physical address of buffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) * size = size of buffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) * TARGET_QUEUE_LOCK must be released.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) * ADAPTER_STATE_LOCK must be released.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) * Returns:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) * qla2x00 local function return status code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) * Context:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) * Kernel context.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) qla2x00_issue_iocb_timeout(scsi_qla_host_t *vha, void *buffer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) dma_addr_t phys_addr, size_t size, uint32_t tov)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) int rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) mbx_cmd_t mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) mbx_cmd_t *mcp = &mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) if (!vha->hw->flags.fw_started)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) return QLA_INVALID_COMMAND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1038,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) "Entered %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) mcp->mb[0] = MBC_IOCB_COMMAND_A64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) mcp->mb[1] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) mcp->mb[2] = MSW(LSD(phys_addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) mcp->mb[3] = LSW(LSD(phys_addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) mcp->mb[6] = MSW(MSD(phys_addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) mcp->mb[7] = LSW(MSD(phys_addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) mcp->in_mb = MBX_1|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) mcp->tov = tov;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) mcp->flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) rval = qla2x00_mailbox_command(vha, mcp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) if (rval != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) /*EMPTY*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) ql_dbg(ql_dbg_mbx, vha, 0x1039, "Failed=%x.\n", rval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) sts_entry_t *sts_entry = buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) /* Mask reserved bits. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) sts_entry->entry_status &=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) IS_FWI2_CAPABLE(vha->hw) ? RF_MASK_24XX : RF_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) "Done %s (status=%x).\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) sts_entry->entry_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) qla2x00_issue_iocb(scsi_qla_host_t *vha, void *buffer, dma_addr_t phys_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) size_t size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) return qla2x00_issue_iocb_timeout(vha, buffer, phys_addr, size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) MBX_TOV_SECONDS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) * qla2x00_abort_command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) * Abort command aborts a specified IOCB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) * Input:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) * ha = adapter block pointer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) * sp = SB structure pointer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) * Returns:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) * qla2x00 local function return status code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) * Context:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) * Kernel context.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) qla2x00_abort_command(srb_t *sp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) unsigned long flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) int rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) uint32_t handle = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) mbx_cmd_t mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) mbx_cmd_t *mcp = &mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) fc_port_t *fcport = sp->fcport;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) scsi_qla_host_t *vha = fcport->vha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) struct req_que *req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) struct scsi_cmnd *cmd = GET_CMD_SP(sp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) "Entered %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) if (sp->qpair)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) req = sp->qpair->req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) req = vha->req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) spin_lock_irqsave(&ha->hardware_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) for (handle = 1; handle < req->num_outstanding_cmds; handle++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) if (req->outstanding_cmds[handle] == sp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) spin_unlock_irqrestore(&ha->hardware_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) if (handle == req->num_outstanding_cmds) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) /* command not found */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) return QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) mcp->mb[0] = MBC_ABORT_COMMAND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) if (HAS_EXTENDED_IDS(ha))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) mcp->mb[1] = fcport->loop_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) mcp->mb[1] = fcport->loop_id << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) mcp->mb[2] = (uint16_t)handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) mcp->mb[3] = (uint16_t)(handle >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) mcp->mb[6] = (uint16_t)cmd->device->lun;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) mcp->out_mb = MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) mcp->in_mb = MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) mcp->tov = MBX_TOV_SECONDS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) mcp->flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) rval = qla2x00_mailbox_command(vha, mcp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) if (rval != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) ql_dbg(ql_dbg_mbx, vha, 0x103c, "Failed=%x.\n", rval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) "Done %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) qla2x00_abort_target(struct fc_port *fcport, uint64_t l, int tag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) int rval, rval2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) mbx_cmd_t mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) mbx_cmd_t *mcp = &mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) scsi_qla_host_t *vha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) vha = fcport->vha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) "Entered %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) mcp->mb[0] = MBC_ABORT_TARGET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) mcp->out_mb = MBX_9|MBX_2|MBX_1|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) if (HAS_EXTENDED_IDS(vha->hw)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) mcp->mb[1] = fcport->loop_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) mcp->mb[10] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) mcp->out_mb |= MBX_10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) mcp->mb[1] = fcport->loop_id << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) mcp->mb[2] = vha->hw->loop_reset_delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) mcp->mb[9] = vha->vp_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) mcp->in_mb = MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) mcp->tov = MBX_TOV_SECONDS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) mcp->flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) rval = qla2x00_mailbox_command(vha, mcp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) if (rval != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) "Failed=%x.\n", rval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) /* Issue marker IOCB. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) rval2 = qla2x00_marker(vha, vha->hw->base_qpair, fcport->loop_id, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) MK_SYNC_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) if (rval2 != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) ql_dbg(ql_dbg_mbx, vha, 0x1040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) "Failed to issue marker IOCB (%x).\n", rval2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1041,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) "Done %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) qla2x00_lun_reset(struct fc_port *fcport, uint64_t l, int tag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) int rval, rval2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) mbx_cmd_t mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) mbx_cmd_t *mcp = &mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) scsi_qla_host_t *vha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) vha = fcport->vha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1042,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) "Entered %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) mcp->mb[0] = MBC_LUN_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) mcp->out_mb = MBX_9|MBX_3|MBX_2|MBX_1|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) if (HAS_EXTENDED_IDS(vha->hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) mcp->mb[1] = fcport->loop_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) mcp->mb[1] = fcport->loop_id << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) mcp->mb[2] = (u32)l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) mcp->mb[3] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) mcp->mb[9] = vha->vp_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) mcp->in_mb = MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) mcp->tov = MBX_TOV_SECONDS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) mcp->flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) rval = qla2x00_mailbox_command(vha, mcp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) if (rval != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) ql_dbg(ql_dbg_mbx, vha, 0x1043, "Failed=%x.\n", rval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) /* Issue marker IOCB. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) rval2 = qla2x00_marker(vha, vha->hw->base_qpair, fcport->loop_id, l,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) MK_SYNC_ID_LUN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) if (rval2 != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) ql_dbg(ql_dbg_mbx, vha, 0x1044,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) "Failed to issue marker IOCB (%x).\n", rval2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1045,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) "Done %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) * qla2x00_get_adapter_id
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) * Get adapter ID and topology.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) * Input:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) * ha = adapter block pointer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) * id = pointer for loop ID.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) * al_pa = pointer for AL_PA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) * area = pointer for area.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) * domain = pointer for domain.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) * top = pointer for topology.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) * TARGET_QUEUE_LOCK must be released.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) * ADAPTER_STATE_LOCK must be released.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) * Returns:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) * qla2x00 local function return status code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) * Context:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) * Kernel context.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) qla2x00_get_adapter_id(scsi_qla_host_t *vha, uint16_t *id, uint8_t *al_pa,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) uint8_t *area, uint8_t *domain, uint16_t *top, uint16_t *sw_cap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) int rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) mbx_cmd_t mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) mbx_cmd_t *mcp = &mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1046,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) "Entered %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) mcp->mb[0] = MBC_GET_ADAPTER_LOOP_ID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) mcp->mb[9] = vha->vp_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) mcp->out_mb = MBX_9|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) mcp->in_mb = MBX_9|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) if (IS_CNA_CAPABLE(vha->hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) mcp->in_mb |= MBX_13|MBX_12|MBX_11|MBX_10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) if (IS_FWI2_CAPABLE(vha->hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) mcp->in_mb |= MBX_19|MBX_18|MBX_17|MBX_16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) if (IS_QLA27XX(vha->hw) || IS_QLA28XX(vha->hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) mcp->in_mb |= MBX_15|MBX_21|MBX_22|MBX_23;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) mcp->tov = MBX_TOV_SECONDS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) mcp->flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) rval = qla2x00_mailbox_command(vha, mcp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) if (mcp->mb[0] == MBS_COMMAND_ERROR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) rval = QLA_COMMAND_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) else if (mcp->mb[0] == MBS_INVALID_COMMAND)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) rval = QLA_INVALID_COMMAND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) /* Return data. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) *id = mcp->mb[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) *al_pa = LSB(mcp->mb[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) *area = MSB(mcp->mb[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) *domain = LSB(mcp->mb[3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) *top = mcp->mb[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) *sw_cap = mcp->mb[7];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) if (rval != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) /*EMPTY*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) ql_dbg(ql_dbg_mbx, vha, 0x1047, "Failed=%x.\n", rval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1048,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) "Done %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) if (IS_CNA_CAPABLE(vha->hw)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) vha->fcoe_vlan_id = mcp->mb[9] & 0xfff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) vha->fcoe_fcf_idx = mcp->mb[10];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) vha->fcoe_vn_port_mac[5] = mcp->mb[11] >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) vha->fcoe_vn_port_mac[4] = mcp->mb[11] & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) vha->fcoe_vn_port_mac[3] = mcp->mb[12] >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) vha->fcoe_vn_port_mac[2] = mcp->mb[12] & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) vha->fcoe_vn_port_mac[1] = mcp->mb[13] >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) vha->fcoe_vn_port_mac[0] = mcp->mb[13] & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) /* If FA-WWN supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) if (IS_FAWWN_CAPABLE(vha->hw)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) if (mcp->mb[7] & BIT_14) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) vha->port_name[0] = MSB(mcp->mb[16]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) vha->port_name[1] = LSB(mcp->mb[16]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) vha->port_name[2] = MSB(mcp->mb[17]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) vha->port_name[3] = LSB(mcp->mb[17]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) vha->port_name[4] = MSB(mcp->mb[18]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) vha->port_name[5] = LSB(mcp->mb[18]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) vha->port_name[6] = MSB(mcp->mb[19]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) vha->port_name[7] = LSB(mcp->mb[19]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) fc_host_port_name(vha->host) =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) wwn_to_u64(vha->port_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) ql_dbg(ql_dbg_mbx, vha, 0x10ca,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) "FA-WWN acquired %016llx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) wwn_to_u64(vha->port_name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) if (IS_QLA27XX(vha->hw) || IS_QLA28XX(vha->hw)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) vha->bbcr = mcp->mb[15];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) if (mcp->mb[7] & SCM_EDC_ACC_RECEIVED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) ql_log(ql_log_info, vha, 0x11a4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) "SCM: EDC ELS completed, flags 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) mcp->mb[21]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) if (mcp->mb[7] & SCM_RDF_ACC_RECEIVED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) vha->hw->flags.scm_enabled = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) vha->scm_fabric_connection_flags |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) SCM_FLAG_RDF_COMPLETED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) ql_log(ql_log_info, vha, 0x11a5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) "SCM: RDF ELS completed, flags 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) mcp->mb[23]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) * qla2x00_get_retry_cnt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) * Get current firmware login retry count and delay.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) * Input:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) * ha = adapter block pointer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) * retry_cnt = pointer to login retry count.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) * tov = pointer to login timeout value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) * Returns:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) * qla2x00 local function return status code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) * Context:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) * Kernel context.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) qla2x00_get_retry_cnt(scsi_qla_host_t *vha, uint8_t *retry_cnt, uint8_t *tov,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) uint16_t *r_a_tov)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) int rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) uint16_t ratov;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) mbx_cmd_t mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) mbx_cmd_t *mcp = &mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1049,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) "Entered %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) mcp->mb[0] = MBC_GET_RETRY_COUNT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) mcp->out_mb = MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) mcp->tov = MBX_TOV_SECONDS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) mcp->flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) rval = qla2x00_mailbox_command(vha, mcp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) if (rval != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) /*EMPTY*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) ql_dbg(ql_dbg_mbx, vha, 0x104a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) /* Convert returned data and check our values. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) *r_a_tov = mcp->mb[3] / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) ratov = (mcp->mb[3]/2) / 10; /* mb[3] value is in 100ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) if (mcp->mb[1] * ratov > (*retry_cnt) * (*tov)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) /* Update to the larger values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) *retry_cnt = (uint8_t)mcp->mb[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) *tov = ratov;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x104b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) "Done %s mb3=%d ratov=%d.\n", __func__, mcp->mb[3], ratov);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) * qla2x00_init_firmware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) * Initialize adapter firmware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) * Input:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) * ha = adapter block pointer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) * dptr = Initialization control block pointer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) * size = size of initialization control block.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) * TARGET_QUEUE_LOCK must be released.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) * ADAPTER_STATE_LOCK must be released.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) * Returns:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) * qla2x00 local function return status code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) * Context:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) * Kernel context.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) qla2x00_init_firmware(scsi_qla_host_t *vha, uint16_t size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) int rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) mbx_cmd_t mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) mbx_cmd_t *mcp = &mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x104c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) "Entered %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) if (IS_P3P_TYPE(ha) && ql2xdbwr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) qla82xx_wr_32(ha, (uintptr_t __force)ha->nxdb_wr_ptr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) (0x04 | (ha->portnum << 5) | (0 << 8) | (0 << 16)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) if (ha->flags.npiv_supported)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) mcp->mb[0] = MBC_MID_INITIALIZE_FIRMWARE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) mcp->mb[0] = MBC_INITIALIZE_FIRMWARE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) mcp->mb[1] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) mcp->mb[2] = MSW(ha->init_cb_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) mcp->mb[3] = LSW(ha->init_cb_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) mcp->mb[6] = MSW(MSD(ha->init_cb_dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) mcp->mb[7] = LSW(MSD(ha->init_cb_dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) if (ha->ex_init_cb && ha->ex_init_cb->ex_version) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) mcp->mb[1] = BIT_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) mcp->mb[10] = MSW(ha->ex_init_cb_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) mcp->mb[11] = LSW(ha->ex_init_cb_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) mcp->mb[12] = MSW(MSD(ha->ex_init_cb_dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) mcp->mb[13] = LSW(MSD(ha->ex_init_cb_dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) mcp->mb[14] = sizeof(*ha->ex_init_cb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) mcp->out_mb |= MBX_14|MBX_13|MBX_12|MBX_11|MBX_10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) if (ha->flags.scm_supported_f || vha->flags.nvme2_enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) mcp->mb[1] |= BIT_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) mcp->mb[16] = MSW(ha->sf_init_cb_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) mcp->mb[17] = LSW(ha->sf_init_cb_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) mcp->mb[18] = MSW(MSD(ha->sf_init_cb_dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) mcp->mb[19] = LSW(MSD(ha->sf_init_cb_dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) mcp->mb[15] = sizeof(*ha->sf_init_cb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) mcp->out_mb |= MBX_19|MBX_18|MBX_17|MBX_16|MBX_15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) /* 1 and 2 should normally be captured. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) mcp->in_mb = MBX_2|MBX_1|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) if (IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) /* mb3 is additional info about the installed SFP. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) mcp->in_mb |= MBX_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) mcp->buf_size = size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) mcp->flags = MBX_DMA_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) mcp->tov = MBX_TOV_SECONDS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) rval = qla2x00_mailbox_command(vha, mcp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) if (rval != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) /*EMPTY*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) ql_dbg(ql_dbg_mbx, vha, 0x104d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) "Failed=%x mb[0]=%x, mb[1]=%x, mb[2]=%x, mb[3]=%x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) rval, mcp->mb[0], mcp->mb[1], mcp->mb[2], mcp->mb[3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) if (ha->init_cb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) ql_dbg(ql_dbg_mbx, vha, 0x104d, "init_cb:\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) ql_dump_buffer(ql_dbg_init + ql_dbg_verbose, vha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) 0x0104d, ha->init_cb, sizeof(*ha->init_cb));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) if (ha->ex_init_cb && ha->ex_init_cb->ex_version) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) ql_dbg(ql_dbg_mbx, vha, 0x104d, "ex_init_cb:\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) ql_dump_buffer(ql_dbg_init + ql_dbg_verbose, vha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) 0x0104d, ha->ex_init_cb, sizeof(*ha->ex_init_cb));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) if (mcp->mb[2] == 6 || mcp->mb[3] == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) ql_dbg(ql_dbg_mbx, vha, 0x119d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) "Invalid SFP/Validation Failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x104e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) "Done %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) * qla2x00_get_port_database
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) * Issue normal/enhanced get port database mailbox command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) * and copy device name as necessary.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) * Input:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) * ha = adapter state pointer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) * dev = structure pointer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) * opt = enhanced cmd option byte.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) * Returns:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) * qla2x00 local function return status code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) * Context:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) * Kernel context.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) qla2x00_get_port_database(scsi_qla_host_t *vha, fc_port_t *fcport, uint8_t opt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) int rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) mbx_cmd_t mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) mbx_cmd_t *mcp = &mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) port_database_t *pd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) struct port_database_24xx *pd24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) dma_addr_t pd_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x104f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) "Entered %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) pd24 = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) pd = dma_pool_zalloc(ha->s_dma_pool, GFP_KERNEL, &pd_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) if (pd == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) ql_log(ql_log_warn, vha, 0x1050,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) "Failed to allocate port database structure.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) fcport->query = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) return QLA_MEMORY_ALLOC_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) mcp->mb[0] = MBC_GET_PORT_DATABASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) if (opt != 0 && !IS_FWI2_CAPABLE(ha))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) mcp->mb[0] = MBC_ENHANCED_GET_PORT_DATABASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) mcp->mb[2] = MSW(pd_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) mcp->mb[3] = LSW(pd_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) mcp->mb[6] = MSW(MSD(pd_dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) mcp->mb[7] = LSW(MSD(pd_dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) mcp->mb[9] = vha->vp_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) mcp->out_mb = MBX_9|MBX_7|MBX_6|MBX_3|MBX_2|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) mcp->in_mb = MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) if (IS_FWI2_CAPABLE(ha)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) mcp->mb[1] = fcport->loop_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) mcp->mb[10] = opt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) mcp->out_mb |= MBX_10|MBX_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) mcp->in_mb |= MBX_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) } else if (HAS_EXTENDED_IDS(ha)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) mcp->mb[1] = fcport->loop_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) mcp->mb[10] = opt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) mcp->out_mb |= MBX_10|MBX_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) mcp->mb[1] = fcport->loop_id << 8 | opt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) mcp->out_mb |= MBX_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) mcp->buf_size = IS_FWI2_CAPABLE(ha) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) PORT_DATABASE_24XX_SIZE : PORT_DATABASE_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) mcp->flags = MBX_DMA_IN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) rval = qla2x00_mailbox_command(vha, mcp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) if (rval != QLA_SUCCESS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) goto gpd_error_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) if (IS_FWI2_CAPABLE(ha)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) uint64_t zero = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) u8 current_login_state, last_login_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) pd24 = (struct port_database_24xx *) pd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) /* Check for logged in state. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) if (NVME_TARGET(ha, fcport)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) current_login_state = pd24->current_login_state >> 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) last_login_state = pd24->last_login_state >> 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) current_login_state = pd24->current_login_state & 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) last_login_state = pd24->last_login_state & 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) fcport->current_login_state = pd24->current_login_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) fcport->last_login_state = pd24->last_login_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) /* Check for logged in state. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) if (current_login_state != PDS_PRLI_COMPLETE &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) last_login_state != PDS_PRLI_COMPLETE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) ql_dbg(ql_dbg_mbx, vha, 0x119a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) "Unable to verify login-state (%x/%x) for loop_id %x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) current_login_state, last_login_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) fcport->loop_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) rval = QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) if (!fcport->query)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) goto gpd_error_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) if (fcport->loop_id == FC_NO_LOOP_ID ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) (memcmp(fcport->port_name, (uint8_t *)&zero, 8) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) memcmp(fcport->port_name, pd24->port_name, 8))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) /* We lost the device mid way. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) rval = QLA_NOT_LOGGED_IN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) goto gpd_error_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) /* Names are little-endian. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) memcpy(fcport->node_name, pd24->node_name, WWN_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) memcpy(fcport->port_name, pd24->port_name, WWN_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) /* Get port_id of device. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) fcport->d_id.b.domain = pd24->port_id[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) fcport->d_id.b.area = pd24->port_id[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) fcport->d_id.b.al_pa = pd24->port_id[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) fcport->d_id.b.rsvd_1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) /* If not target must be initiator or unknown type. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) if ((pd24->prli_svc_param_word_3[0] & BIT_4) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) fcport->port_type = FCT_INITIATOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) fcport->port_type = FCT_TARGET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) /* Passback COS information. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) fcport->supported_classes = (pd24->flags & PDF_CLASS_2) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) FC_COS_CLASS2 : FC_COS_CLASS3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) if (pd24->prli_svc_param_word_3[0] & BIT_7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) fcport->flags |= FCF_CONF_COMP_SUPPORTED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) uint64_t zero = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) /* Check for logged in state. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) if (pd->master_state != PD_STATE_PORT_LOGGED_IN &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) pd->slave_state != PD_STATE_PORT_LOGGED_IN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) ql_dbg(ql_dbg_mbx, vha, 0x100a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) "Unable to verify login-state (%x/%x) - "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) "portid=%02x%02x%02x.\n", pd->master_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) pd->slave_state, fcport->d_id.b.domain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) fcport->d_id.b.area, fcport->d_id.b.al_pa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) rval = QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) goto gpd_error_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) if (fcport->loop_id == FC_NO_LOOP_ID ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) (memcmp(fcport->port_name, (uint8_t *)&zero, 8) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) memcmp(fcport->port_name, pd->port_name, 8))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) /* We lost the device mid way. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) rval = QLA_NOT_LOGGED_IN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) goto gpd_error_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) /* Names are little-endian. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) memcpy(fcport->node_name, pd->node_name, WWN_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) memcpy(fcport->port_name, pd->port_name, WWN_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) /* Get port_id of device. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) fcport->d_id.b.domain = pd->port_id[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) fcport->d_id.b.area = pd->port_id[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) fcport->d_id.b.al_pa = pd->port_id[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) fcport->d_id.b.rsvd_1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) /* If not target must be initiator or unknown type. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) if ((pd->prli_svc_param_word_3[0] & BIT_4) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) fcport->port_type = FCT_INITIATOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) fcport->port_type = FCT_TARGET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) /* Passback COS information. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) fcport->supported_classes = (pd->options & BIT_4) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) FC_COS_CLASS2 : FC_COS_CLASS3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) gpd_error_out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) dma_pool_free(ha->s_dma_pool, pd, pd_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) fcport->query = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) if (rval != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) ql_dbg(ql_dbg_mbx, vha, 0x1052,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) "Failed=%x mb[0]=%x mb[1]=%x.\n", rval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) mcp->mb[0], mcp->mb[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1053,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) "Done %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) qla24xx_get_port_database(scsi_qla_host_t *vha, u16 nport_handle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) struct port_database_24xx *pdb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) mbx_cmd_t mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) mbx_cmd_t *mcp = &mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) dma_addr_t pdb_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) int rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1115,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) "Entered %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) memset(pdb, 0, sizeof(*pdb));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) pdb_dma = dma_map_single(&vha->hw->pdev->dev, pdb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) sizeof(*pdb), DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) if (!pdb_dma) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) ql_log(ql_log_warn, vha, 0x1116, "Failed to map dma buffer.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) return QLA_MEMORY_ALLOC_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) mcp->mb[0] = MBC_GET_PORT_DATABASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) mcp->mb[1] = nport_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) mcp->mb[2] = MSW(LSD(pdb_dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) mcp->mb[3] = LSW(LSD(pdb_dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) mcp->mb[6] = MSW(MSD(pdb_dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) mcp->mb[7] = LSW(MSD(pdb_dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) mcp->mb[9] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) mcp->mb[10] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) mcp->out_mb = MBX_10|MBX_9|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) mcp->in_mb = MBX_1|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) mcp->buf_size = sizeof(*pdb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) mcp->flags = MBX_DMA_IN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) mcp->tov = vha->hw->login_timeout * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) rval = qla2x00_mailbox_command(vha, mcp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) if (rval != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) ql_dbg(ql_dbg_mbx, vha, 0x111a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) "Failed=%x mb[0]=%x mb[1]=%x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) rval, mcp->mb[0], mcp->mb[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x111b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) "Done %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) dma_unmap_single(&vha->hw->pdev->dev, pdb_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) sizeof(*pdb), DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) * qla2x00_get_firmware_state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) * Get adapter firmware state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) * Input:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) * ha = adapter block pointer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) * dptr = pointer for firmware state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) * TARGET_QUEUE_LOCK must be released.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) * ADAPTER_STATE_LOCK must be released.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) * Returns:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) * qla2x00 local function return status code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) * Context:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) * Kernel context.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) qla2x00_get_firmware_state(scsi_qla_host_t *vha, uint16_t *states)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) int rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) mbx_cmd_t mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) mbx_cmd_t *mcp = &mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1054,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) "Entered %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) mcp->mb[0] = MBC_GET_FIRMWARE_STATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) mcp->out_mb = MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) if (IS_FWI2_CAPABLE(vha->hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) mcp->in_mb = MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) mcp->in_mb = MBX_1|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) mcp->tov = MBX_TOV_SECONDS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) mcp->flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) rval = qla2x00_mailbox_command(vha, mcp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) /* Return firmware states. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) states[0] = mcp->mb[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) if (IS_FWI2_CAPABLE(vha->hw)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) states[1] = mcp->mb[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) states[2] = mcp->mb[3]; /* SFP info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) states[3] = mcp->mb[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) states[4] = mcp->mb[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) states[5] = mcp->mb[6]; /* DPORT status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) if (rval != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) /*EMPTY*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) ql_dbg(ql_dbg_mbx, vha, 0x1055, "Failed=%x.\n", rval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) if (mcp->mb[2] == 6 || mcp->mb[3] == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) ql_dbg(ql_dbg_mbx, vha, 0x119e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) "Invalid SFP/Validation Failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1056,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) "Done %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) * qla2x00_get_port_name
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) * Issue get port name mailbox command.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) * Returned name is in big endian format.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) * Input:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) * ha = adapter block pointer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) * loop_id = loop ID of device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) * name = pointer for name.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) * TARGET_QUEUE_LOCK must be released.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) * ADAPTER_STATE_LOCK must be released.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) * Returns:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) * qla2x00 local function return status code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) * Context:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) * Kernel context.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) qla2x00_get_port_name(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) uint8_t opt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) int rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) mbx_cmd_t mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) mbx_cmd_t *mcp = &mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1057,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) "Entered %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) mcp->mb[0] = MBC_GET_PORT_NAME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) mcp->mb[9] = vha->vp_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) mcp->out_mb = MBX_9|MBX_1|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) if (HAS_EXTENDED_IDS(vha->hw)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) mcp->mb[1] = loop_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) mcp->mb[10] = opt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) mcp->out_mb |= MBX_10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) mcp->mb[1] = loop_id << 8 | opt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) mcp->in_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) mcp->tov = MBX_TOV_SECONDS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) mcp->flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) rval = qla2x00_mailbox_command(vha, mcp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) if (rval != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) /*EMPTY*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) ql_dbg(ql_dbg_mbx, vha, 0x1058, "Failed=%x.\n", rval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) if (name != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) /* This function returns name in big endian. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) name[0] = MSB(mcp->mb[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) name[1] = LSB(mcp->mb[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) name[2] = MSB(mcp->mb[3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) name[3] = LSB(mcp->mb[3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) name[4] = MSB(mcp->mb[6]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) name[5] = LSB(mcp->mb[6]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) name[6] = MSB(mcp->mb[7]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) name[7] = LSB(mcp->mb[7]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1059,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) "Done %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) * qla24xx_link_initialization
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) * Issue link initialization mailbox command.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) * Input:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) * ha = adapter block pointer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) * TARGET_QUEUE_LOCK must be released.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) * ADAPTER_STATE_LOCK must be released.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) * Returns:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) * qla2x00 local function return status code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) * Context:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) * Kernel context.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) qla24xx_link_initialize(scsi_qla_host_t *vha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) int rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) mbx_cmd_t mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) mbx_cmd_t *mcp = &mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1152,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) "Entered %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) if (!IS_FWI2_CAPABLE(vha->hw) || IS_CNA_CAPABLE(vha->hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) return QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) mcp->mb[0] = MBC_LINK_INITIALIZATION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) mcp->mb[1] = BIT_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) if (vha->hw->operating_mode == LOOP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) mcp->mb[1] |= BIT_6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) mcp->mb[1] |= BIT_5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) mcp->mb[2] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) mcp->mb[3] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) mcp->in_mb = MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) mcp->tov = MBX_TOV_SECONDS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) mcp->flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) rval = qla2x00_mailbox_command(vha, mcp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) if (rval != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) ql_dbg(ql_dbg_mbx, vha, 0x1153, "Failed=%x.\n", rval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1154,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) "Done %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) * qla2x00_lip_reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) * Issue LIP reset mailbox command.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) * Input:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) * ha = adapter block pointer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) * TARGET_QUEUE_LOCK must be released.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) * ADAPTER_STATE_LOCK must be released.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) * Returns:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) * qla2x00 local function return status code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) * Context:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) * Kernel context.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) qla2x00_lip_reset(scsi_qla_host_t *vha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) int rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) mbx_cmd_t mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) mbx_cmd_t *mcp = &mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) ql_dbg(ql_dbg_disc, vha, 0x105a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) "Entered %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) if (IS_CNA_CAPABLE(vha->hw)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) /* Logout across all FCFs. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) mcp->mb[0] = MBC_LIP_FULL_LOGIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) mcp->mb[1] = BIT_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) mcp->mb[2] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) mcp->out_mb = MBX_2|MBX_1|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) } else if (IS_FWI2_CAPABLE(vha->hw)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) mcp->mb[0] = MBC_LIP_FULL_LOGIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) mcp->mb[1] = BIT_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) mcp->mb[2] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) mcp->mb[3] = vha->hw->loop_reset_delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) mcp->mb[0] = MBC_LIP_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) if (HAS_EXTENDED_IDS(vha->hw)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) mcp->mb[1] = 0x00ff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) mcp->mb[10] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) mcp->out_mb |= MBX_10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) mcp->mb[1] = 0xff00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) mcp->mb[2] = vha->hw->loop_reset_delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) mcp->mb[3] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) mcp->in_mb = MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) mcp->tov = MBX_TOV_SECONDS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) mcp->flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) rval = qla2x00_mailbox_command(vha, mcp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) if (rval != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) /*EMPTY*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) ql_dbg(ql_dbg_mbx, vha, 0x105b, "Failed=%x.\n", rval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) /*EMPTY*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x105c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) "Done %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) * qla2x00_send_sns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) * Send SNS command.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) * Input:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) * ha = adapter block pointer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) * sns = pointer for command.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) * cmd_size = command size.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) * buf_size = response/command size.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) * TARGET_QUEUE_LOCK must be released.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) * ADAPTER_STATE_LOCK must be released.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) * Returns:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) * qla2x00 local function return status code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) * Context:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) * Kernel context.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) qla2x00_send_sns(scsi_qla_host_t *vha, dma_addr_t sns_phys_address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) uint16_t cmd_size, size_t buf_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) int rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) mbx_cmd_t mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) mbx_cmd_t *mcp = &mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x105d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) "Entered %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x105e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) "Retry cnt=%d ratov=%d total tov=%d.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) vha->hw->retry_count, vha->hw->login_timeout, mcp->tov);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) mcp->mb[0] = MBC_SEND_SNS_COMMAND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) mcp->mb[1] = cmd_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) mcp->mb[2] = MSW(sns_phys_address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) mcp->mb[3] = LSW(sns_phys_address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) mcp->mb[6] = MSW(MSD(sns_phys_address));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) mcp->mb[7] = LSW(MSD(sns_phys_address));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) mcp->in_mb = MBX_0|MBX_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) mcp->buf_size = buf_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) mcp->flags = MBX_DMA_OUT|MBX_DMA_IN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) mcp->tov = (vha->hw->login_timeout * 2) + (vha->hw->login_timeout / 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) rval = qla2x00_mailbox_command(vha, mcp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) if (rval != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) /*EMPTY*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) ql_dbg(ql_dbg_mbx, vha, 0x105f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) "Failed=%x mb[0]=%x mb[1]=%x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) rval, mcp->mb[0], mcp->mb[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) /*EMPTY*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1060,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) "Done %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) qla24xx_login_fabric(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) uint8_t area, uint8_t al_pa, uint16_t *mb, uint8_t opt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) int rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) struct logio_entry_24xx *lg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) dma_addr_t lg_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) uint32_t iop[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) struct req_que *req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1061,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) "Entered %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) if (vha->vp_idx && vha->qpair)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) req = vha->qpair->req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) req = ha->req_q_map[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) lg = dma_pool_zalloc(ha->s_dma_pool, GFP_KERNEL, &lg_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) if (lg == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) ql_log(ql_log_warn, vha, 0x1062,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) "Failed to allocate login IOCB.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) return QLA_MEMORY_ALLOC_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) lg->entry_type = LOGINOUT_PORT_IOCB_TYPE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) lg->entry_count = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) lg->handle = make_handle(req->id, lg->handle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) lg->nport_handle = cpu_to_le16(loop_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) lg->control_flags = cpu_to_le16(LCF_COMMAND_PLOGI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) if (opt & BIT_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) lg->control_flags |= cpu_to_le16(LCF_COND_PLOGI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) if (opt & BIT_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) lg->control_flags |= cpu_to_le16(LCF_SKIP_PRLI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) lg->port_id[0] = al_pa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) lg->port_id[1] = area;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) lg->port_id[2] = domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) lg->vp_index = vha->vp_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) rval = qla2x00_issue_iocb_timeout(vha, lg, lg_dma, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) (ha->r_a_tov / 10 * 2) + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) if (rval != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) ql_dbg(ql_dbg_mbx, vha, 0x1063,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) "Failed to issue login IOCB (%x).\n", rval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) } else if (lg->entry_status != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) ql_dbg(ql_dbg_mbx, vha, 0x1064,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) "Failed to complete IOCB -- error status (%x).\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) lg->entry_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) rval = QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) } else if (lg->comp_status != cpu_to_le16(CS_COMPLETE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) iop[0] = le32_to_cpu(lg->io_parameter[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) iop[1] = le32_to_cpu(lg->io_parameter[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) ql_dbg(ql_dbg_mbx, vha, 0x1065,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) "Failed to complete IOCB -- completion status (%x) "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) "ioparam=%x/%x.\n", le16_to_cpu(lg->comp_status),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) iop[0], iop[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) switch (iop[0]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) case LSC_SCODE_PORTID_USED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) mb[0] = MBS_PORT_ID_USED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) mb[1] = LSW(iop[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) case LSC_SCODE_NPORT_USED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) mb[0] = MBS_LOOP_ID_USED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) case LSC_SCODE_NOLINK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) case LSC_SCODE_NOIOCB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) case LSC_SCODE_NOXCB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) case LSC_SCODE_CMD_FAILED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) case LSC_SCODE_NOFABRIC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) case LSC_SCODE_FW_NOT_READY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) case LSC_SCODE_NOT_LOGGED_IN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) case LSC_SCODE_NOPCB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) case LSC_SCODE_ELS_REJECT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) case LSC_SCODE_CMD_PARAM_ERR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) case LSC_SCODE_NONPORT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) case LSC_SCODE_LOGGED_IN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) case LSC_SCODE_NOFLOGI_ACC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) mb[0] = MBS_COMMAND_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1066,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) "Done %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) iop[0] = le32_to_cpu(lg->io_parameter[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) mb[0] = MBS_COMMAND_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) mb[1] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) if (iop[0] & BIT_4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) if (iop[0] & BIT_8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) mb[1] |= BIT_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) mb[1] = BIT_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) /* Passback COS information. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) mb[10] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) if (lg->io_parameter[7] || lg->io_parameter[8])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) mb[10] |= BIT_0; /* Class 2. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) if (lg->io_parameter[9] || lg->io_parameter[10])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) mb[10] |= BIT_1; /* Class 3. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) if (lg->io_parameter[0] & cpu_to_le32(BIT_7))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) mb[10] |= BIT_7; /* Confirmed Completion
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) * Allowed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) dma_pool_free(ha->s_dma_pool, lg, lg_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562) * qla2x00_login_fabric
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) * Issue login fabric port mailbox command.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) * Input:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) * ha = adapter block pointer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567) * loop_id = device loop ID.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) * domain = device domain.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) * area = device area.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) * al_pa = device AL_PA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571) * status = pointer for return status.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) * opt = command options.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) * TARGET_QUEUE_LOCK must be released.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) * ADAPTER_STATE_LOCK must be released.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) * Returns:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) * qla2x00 local function return status code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579) * Context:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580) * Kernel context.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583) qla2x00_login_fabric(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584) uint8_t area, uint8_t al_pa, uint16_t *mb, uint8_t opt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) int rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) mbx_cmd_t mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588) mbx_cmd_t *mcp = &mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1067,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592) "Entered %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) mcp->mb[0] = MBC_LOGIN_FABRIC_PORT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595) mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596) if (HAS_EXTENDED_IDS(ha)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) mcp->mb[1] = loop_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598) mcp->mb[10] = opt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) mcp->out_mb |= MBX_10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601) mcp->mb[1] = (loop_id << 8) | opt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603) mcp->mb[2] = domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) mcp->mb[3] = area << 8 | al_pa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606) mcp->in_mb = MBX_7|MBX_6|MBX_2|MBX_1|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607) mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608) mcp->flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609) rval = qla2x00_mailbox_command(vha, mcp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) /* Return mailbox statuses. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612) if (mb != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) mb[0] = mcp->mb[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614) mb[1] = mcp->mb[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615) mb[2] = mcp->mb[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616) mb[6] = mcp->mb[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617) mb[7] = mcp->mb[7];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618) /* COS retrieved from Get-Port-Database mailbox command. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619) mb[10] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622) if (rval != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623) /* RLU tmp code: need to change main mailbox_command function to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624) * return ok even when the mailbox completion value is not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625) * SUCCESS. The caller needs to be responsible to interpret
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626) * the return values of this mailbox command if we're not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) * to change too much of the existing code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629) if (mcp->mb[0] == 0x4001 || mcp->mb[0] == 0x4002 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630) mcp->mb[0] == 0x4003 || mcp->mb[0] == 0x4005 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631) mcp->mb[0] == 0x4006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632) rval = QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634) /*EMPTY*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635) ql_dbg(ql_dbg_mbx, vha, 0x1068,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636) "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637) rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639) /*EMPTY*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1069,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641) "Done %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648) * qla2x00_login_local_device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649) * Issue login loop port mailbox command.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651) * Input:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652) * ha = adapter block pointer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653) * loop_id = device loop ID.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654) * opt = command options.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656) * Returns:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657) * Return status code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659) * Context:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660) * Kernel context.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664) qla2x00_login_local_device(scsi_qla_host_t *vha, fc_port_t *fcport,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665) uint16_t *mb_ret, uint8_t opt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667) int rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668) mbx_cmd_t mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669) mbx_cmd_t *mcp = &mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x106a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673) "Entered %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675) if (IS_FWI2_CAPABLE(ha))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676) return qla24xx_login_fabric(vha, fcport->loop_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677) fcport->d_id.b.domain, fcport->d_id.b.area,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678) fcport->d_id.b.al_pa, mb_ret, opt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680) mcp->mb[0] = MBC_LOGIN_LOOP_PORT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681) if (HAS_EXTENDED_IDS(ha))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682) mcp->mb[1] = fcport->loop_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684) mcp->mb[1] = fcport->loop_id << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685) mcp->mb[2] = opt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686) mcp->out_mb = MBX_2|MBX_1|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687) mcp->in_mb = MBX_7|MBX_6|MBX_1|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688) mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689) mcp->flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690) rval = qla2x00_mailbox_command(vha, mcp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692) /* Return mailbox statuses. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693) if (mb_ret != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694) mb_ret[0] = mcp->mb[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695) mb_ret[1] = mcp->mb[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696) mb_ret[6] = mcp->mb[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697) mb_ret[7] = mcp->mb[7];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700) if (rval != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701) /* AV tmp code: need to change main mailbox_command function to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702) * return ok even when the mailbox completion value is not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703) * SUCCESS. The caller needs to be responsible to interpret
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704) * the return values of this mailbox command if we're not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705) * to change too much of the existing code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707) if (mcp->mb[0] == 0x4005 || mcp->mb[0] == 0x4006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708) rval = QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710) ql_dbg(ql_dbg_mbx, vha, 0x106b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711) "Failed=%x mb[0]=%x mb[1]=%x mb[6]=%x mb[7]=%x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712) rval, mcp->mb[0], mcp->mb[1], mcp->mb[6], mcp->mb[7]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714) /*EMPTY*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x106c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716) "Done %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2719) return (rval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2720) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2722) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2723) qla24xx_fabric_logout(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2724) uint8_t area, uint8_t al_pa)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2725) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2726) int rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2727) struct logio_entry_24xx *lg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2728) dma_addr_t lg_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2729) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2730) struct req_que *req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2732) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x106d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2733) "Entered %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2735) lg = dma_pool_zalloc(ha->s_dma_pool, GFP_KERNEL, &lg_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2736) if (lg == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2737) ql_log(ql_log_warn, vha, 0x106e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2738) "Failed to allocate logout IOCB.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2739) return QLA_MEMORY_ALLOC_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2740) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2742) req = vha->req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2743) lg->entry_type = LOGINOUT_PORT_IOCB_TYPE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2744) lg->entry_count = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2745) lg->handle = make_handle(req->id, lg->handle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2746) lg->nport_handle = cpu_to_le16(loop_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2747) lg->control_flags =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2748) cpu_to_le16(LCF_COMMAND_LOGO|LCF_IMPL_LOGO|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2749) LCF_FREE_NPORT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2750) lg->port_id[0] = al_pa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2751) lg->port_id[1] = area;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2752) lg->port_id[2] = domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2753) lg->vp_index = vha->vp_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2754) rval = qla2x00_issue_iocb_timeout(vha, lg, lg_dma, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2755) (ha->r_a_tov / 10 * 2) + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2756) if (rval != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2757) ql_dbg(ql_dbg_mbx, vha, 0x106f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2758) "Failed to issue logout IOCB (%x).\n", rval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2759) } else if (lg->entry_status != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2760) ql_dbg(ql_dbg_mbx, vha, 0x1070,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2761) "Failed to complete IOCB -- error status (%x).\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2762) lg->entry_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2763) rval = QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2764) } else if (lg->comp_status != cpu_to_le16(CS_COMPLETE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2765) ql_dbg(ql_dbg_mbx, vha, 0x1071,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2766) "Failed to complete IOCB -- completion status (%x) "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2767) "ioparam=%x/%x.\n", le16_to_cpu(lg->comp_status),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2768) le32_to_cpu(lg->io_parameter[0]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2769) le32_to_cpu(lg->io_parameter[1]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2770) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2771) /*EMPTY*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2772) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1072,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2773) "Done %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2774) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2776) dma_pool_free(ha->s_dma_pool, lg, lg_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2778) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2779) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2781) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2782) * qla2x00_fabric_logout
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2783) * Issue logout fabric port mailbox command.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2784) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2785) * Input:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2786) * ha = adapter block pointer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2787) * loop_id = device loop ID.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2788) * TARGET_QUEUE_LOCK must be released.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2789) * ADAPTER_STATE_LOCK must be released.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2790) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2791) * Returns:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2792) * qla2x00 local function return status code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2793) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2794) * Context:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2795) * Kernel context.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2796) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2797) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2798) qla2x00_fabric_logout(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2799) uint8_t area, uint8_t al_pa)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2800) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2801) int rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2802) mbx_cmd_t mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2803) mbx_cmd_t *mcp = &mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2805) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1073,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2806) "Entered %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2808) mcp->mb[0] = MBC_LOGOUT_FABRIC_PORT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2809) mcp->out_mb = MBX_1|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2810) if (HAS_EXTENDED_IDS(vha->hw)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2811) mcp->mb[1] = loop_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2812) mcp->mb[10] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2813) mcp->out_mb |= MBX_10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2814) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2815) mcp->mb[1] = loop_id << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2816) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2818) mcp->in_mb = MBX_1|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2819) mcp->tov = MBX_TOV_SECONDS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2820) mcp->flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2821) rval = qla2x00_mailbox_command(vha, mcp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2823) if (rval != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2824) /*EMPTY*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2825) ql_dbg(ql_dbg_mbx, vha, 0x1074,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2826) "Failed=%x mb[1]=%x.\n", rval, mcp->mb[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2827) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2828) /*EMPTY*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2829) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1075,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2830) "Done %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2831) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2833) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2834) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2836) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2837) * qla2x00_full_login_lip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2838) * Issue full login LIP mailbox command.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2839) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2840) * Input:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2841) * ha = adapter block pointer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2842) * TARGET_QUEUE_LOCK must be released.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2843) * ADAPTER_STATE_LOCK must be released.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2844) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2845) * Returns:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2846) * qla2x00 local function return status code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2847) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2848) * Context:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2849) * Kernel context.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2850) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2851) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2852) qla2x00_full_login_lip(scsi_qla_host_t *vha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2853) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2854) int rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2855) mbx_cmd_t mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2856) mbx_cmd_t *mcp = &mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2858) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1076,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2859) "Entered %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2861) mcp->mb[0] = MBC_LIP_FULL_LOGIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2862) mcp->mb[1] = IS_FWI2_CAPABLE(vha->hw) ? BIT_4 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2863) mcp->mb[2] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2864) mcp->mb[3] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2865) mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2866) mcp->in_mb = MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2867) mcp->tov = MBX_TOV_SECONDS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2868) mcp->flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2869) rval = qla2x00_mailbox_command(vha, mcp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2871) if (rval != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2872) /*EMPTY*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2873) ql_dbg(ql_dbg_mbx, vha, 0x1077, "Failed=%x.\n", rval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2874) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2875) /*EMPTY*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2876) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1078,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2877) "Done %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2878) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2880) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2881) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2883) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2884) * qla2x00_get_id_list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2885) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2886) * Input:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2887) * ha = adapter block pointer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2888) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2889) * Returns:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2890) * qla2x00 local function return status code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2891) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2892) * Context:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2893) * Kernel context.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2894) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2895) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2896) qla2x00_get_id_list(scsi_qla_host_t *vha, void *id_list, dma_addr_t id_list_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2897) uint16_t *entries)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2898) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2899) int rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2900) mbx_cmd_t mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2901) mbx_cmd_t *mcp = &mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2903) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1079,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2904) "Entered %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2906) if (id_list == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2907) return QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2909) mcp->mb[0] = MBC_GET_ID_LIST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2910) mcp->out_mb = MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2911) if (IS_FWI2_CAPABLE(vha->hw)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2912) mcp->mb[2] = MSW(id_list_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2913) mcp->mb[3] = LSW(id_list_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2914) mcp->mb[6] = MSW(MSD(id_list_dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2915) mcp->mb[7] = LSW(MSD(id_list_dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2916) mcp->mb[8] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2917) mcp->mb[9] = vha->vp_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2918) mcp->out_mb |= MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2919) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2920) mcp->mb[1] = MSW(id_list_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2921) mcp->mb[2] = LSW(id_list_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2922) mcp->mb[3] = MSW(MSD(id_list_dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2923) mcp->mb[6] = LSW(MSD(id_list_dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2924) mcp->out_mb |= MBX_6|MBX_3|MBX_2|MBX_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2925) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2926) mcp->in_mb = MBX_1|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2927) mcp->tov = MBX_TOV_SECONDS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2928) mcp->flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2929) rval = qla2x00_mailbox_command(vha, mcp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2931) if (rval != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2932) /*EMPTY*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2933) ql_dbg(ql_dbg_mbx, vha, 0x107a, "Failed=%x.\n", rval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2934) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2935) *entries = mcp->mb[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2936) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x107b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2937) "Done %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2938) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2940) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2941) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2943) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2944) * qla2x00_get_resource_cnts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2945) * Get current firmware resource counts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2946) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2947) * Input:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2948) * ha = adapter block pointer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2949) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2950) * Returns:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2951) * qla2x00 local function return status code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2952) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2953) * Context:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2954) * Kernel context.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2955) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2956) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2957) qla2x00_get_resource_cnts(scsi_qla_host_t *vha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2958) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2959) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2960) int rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2961) mbx_cmd_t mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2962) mbx_cmd_t *mcp = &mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2964) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x107c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2965) "Entered %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2967) mcp->mb[0] = MBC_GET_RESOURCE_COUNTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2968) mcp->out_mb = MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2969) mcp->in_mb = MBX_11|MBX_10|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2970) if (IS_QLA81XX(ha) || IS_QLA83XX(ha) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2971) IS_QLA27XX(ha) || IS_QLA28XX(ha))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2972) mcp->in_mb |= MBX_12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2973) mcp->tov = MBX_TOV_SECONDS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2974) mcp->flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2975) rval = qla2x00_mailbox_command(vha, mcp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2977) if (rval != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2978) /*EMPTY*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2979) ql_dbg(ql_dbg_mbx, vha, 0x107d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2980) "Failed mb[0]=%x.\n", mcp->mb[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2981) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2982) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x107e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2983) "Done %s mb1=%x mb2=%x mb3=%x mb6=%x mb7=%x mb10=%x "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2984) "mb11=%x mb12=%x.\n", __func__, mcp->mb[1], mcp->mb[2],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2985) mcp->mb[3], mcp->mb[6], mcp->mb[7], mcp->mb[10],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2986) mcp->mb[11], mcp->mb[12]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2988) ha->orig_fw_tgt_xcb_count = mcp->mb[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2989) ha->cur_fw_tgt_xcb_count = mcp->mb[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2990) ha->cur_fw_xcb_count = mcp->mb[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2991) ha->orig_fw_xcb_count = mcp->mb[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2992) ha->cur_fw_iocb_count = mcp->mb[7];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2993) ha->orig_fw_iocb_count = mcp->mb[10];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2994) if (ha->flags.npiv_supported)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2995) ha->max_npiv_vports = mcp->mb[11];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2996) if (IS_QLA81XX(ha) || IS_QLA83XX(ha))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2997) ha->fw_max_fcf_count = mcp->mb[12];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2998) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3000) return (rval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3001) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3003) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3004) * qla2x00_get_fcal_position_map
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3005) * Get FCAL (LILP) position map using mailbox command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3006) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3007) * Input:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3008) * ha = adapter state pointer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3009) * pos_map = buffer pointer (can be NULL).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3010) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3011) * Returns:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3012) * qla2x00 local function return status code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3013) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3014) * Context:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3015) * Kernel context.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3016) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3017) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3018) qla2x00_get_fcal_position_map(scsi_qla_host_t *vha, char *pos_map)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3019) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3020) int rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3021) mbx_cmd_t mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3022) mbx_cmd_t *mcp = &mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3023) char *pmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3024) dma_addr_t pmap_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3025) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3027) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x107f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3028) "Entered %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3030) pmap = dma_pool_zalloc(ha->s_dma_pool, GFP_KERNEL, &pmap_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3031) if (pmap == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3032) ql_log(ql_log_warn, vha, 0x1080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3033) "Memory alloc failed.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3034) return QLA_MEMORY_ALLOC_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3035) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3037) mcp->mb[0] = MBC_GET_FC_AL_POSITION_MAP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3038) mcp->mb[2] = MSW(pmap_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3039) mcp->mb[3] = LSW(pmap_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3040) mcp->mb[6] = MSW(MSD(pmap_dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3041) mcp->mb[7] = LSW(MSD(pmap_dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3042) mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3043) mcp->in_mb = MBX_1|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3044) mcp->buf_size = FCAL_MAP_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3045) mcp->flags = MBX_DMA_IN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3046) mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3047) rval = qla2x00_mailbox_command(vha, mcp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3049) if (rval == QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3050) ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1081,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3051) "mb0/mb1=%x/%X FC/AL position map size (%x).\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3052) mcp->mb[0], mcp->mb[1], (unsigned)pmap[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3053) ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x111d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3054) pmap, pmap[0] + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3056) if (pos_map)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3057) memcpy(pos_map, pmap, FCAL_MAP_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3058) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3059) dma_pool_free(ha->s_dma_pool, pmap, pmap_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3061) if (rval != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3062) ql_dbg(ql_dbg_mbx, vha, 0x1082, "Failed=%x.\n", rval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3063) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3064) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1083,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3065) "Done %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3066) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3068) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3069) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3071) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3072) * qla2x00_get_link_status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3073) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3074) * Input:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3075) * ha = adapter block pointer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3076) * loop_id = device loop ID.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3077) * ret_buf = pointer to link status return buffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3078) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3079) * Returns:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3080) * 0 = success.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3081) * BIT_0 = mem alloc error.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3082) * BIT_1 = mailbox error.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3083) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3084) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3085) qla2x00_get_link_status(scsi_qla_host_t *vha, uint16_t loop_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3086) struct link_statistics *stats, dma_addr_t stats_dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3087) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3088) int rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3089) mbx_cmd_t mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3090) mbx_cmd_t *mcp = &mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3091) uint32_t *iter = (uint32_t *)stats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3092) ushort dwords = offsetof(typeof(*stats), link_up_cnt)/sizeof(*iter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3093) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3095) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1084,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3096) "Entered %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3098) mcp->mb[0] = MBC_GET_LINK_STATUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3099) mcp->mb[2] = MSW(LSD(stats_dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3100) mcp->mb[3] = LSW(LSD(stats_dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3101) mcp->mb[6] = MSW(MSD(stats_dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3102) mcp->mb[7] = LSW(MSD(stats_dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3103) mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3104) mcp->in_mb = MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3105) if (IS_FWI2_CAPABLE(ha)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3106) mcp->mb[1] = loop_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3107) mcp->mb[4] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3108) mcp->mb[10] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3109) mcp->out_mb |= MBX_10|MBX_4|MBX_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3110) mcp->in_mb |= MBX_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3111) } else if (HAS_EXTENDED_IDS(ha)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3112) mcp->mb[1] = loop_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3113) mcp->mb[10] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3114) mcp->out_mb |= MBX_10|MBX_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3115) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3116) mcp->mb[1] = loop_id << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3117) mcp->out_mb |= MBX_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3119) mcp->tov = MBX_TOV_SECONDS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3120) mcp->flags = IOCTL_CMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3121) rval = qla2x00_mailbox_command(vha, mcp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3123) if (rval == QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3124) if (mcp->mb[0] != MBS_COMMAND_COMPLETE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3125) ql_dbg(ql_dbg_mbx, vha, 0x1085,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3126) "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3127) rval = QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3128) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3129) /* Re-endianize - firmware data is le32. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3130) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1086,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3131) "Done %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3132) for ( ; dwords--; iter++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3133) le32_to_cpus(iter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3135) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3136) /* Failed. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3137) ql_dbg(ql_dbg_mbx, vha, 0x1087, "Failed=%x.\n", rval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3140) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3143) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3144) qla24xx_get_isp_stats(scsi_qla_host_t *vha, struct link_statistics *stats,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3145) dma_addr_t stats_dma, uint16_t options)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3146) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3147) int rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3148) mbx_cmd_t mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3149) mbx_cmd_t *mcp = &mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3150) uint32_t *iter = (uint32_t *)stats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3151) ushort dwords = sizeof(*stats)/sizeof(*iter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3153) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1088,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3154) "Entered %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3156) memset(&mc, 0, sizeof(mc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3157) mc.mb[0] = MBC_GET_LINK_PRIV_STATS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3158) mc.mb[2] = MSW(LSD(stats_dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3159) mc.mb[3] = LSW(LSD(stats_dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3160) mc.mb[6] = MSW(MSD(stats_dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3161) mc.mb[7] = LSW(MSD(stats_dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3162) mc.mb[8] = dwords;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3163) mc.mb[9] = vha->vp_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3164) mc.mb[10] = options;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3166) rval = qla24xx_send_mb_cmd(vha, &mc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3168) if (rval == QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3169) if (mcp->mb[0] != MBS_COMMAND_COMPLETE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3170) ql_dbg(ql_dbg_mbx, vha, 0x1089,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3171) "Failed mb[0]=%x.\n", mcp->mb[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3172) rval = QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3173) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3174) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x108a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3175) "Done %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3176) /* Re-endianize - firmware data is le32. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3177) for ( ; dwords--; iter++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3178) le32_to_cpus(iter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3180) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3181) /* Failed. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3182) ql_dbg(ql_dbg_mbx, vha, 0x108b, "Failed=%x.\n", rval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3185) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3188) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3189) qla24xx_abort_command(srb_t *sp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3190) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3191) int rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3192) unsigned long flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3194) struct abort_entry_24xx *abt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3195) dma_addr_t abt_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3196) uint32_t handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3197) fc_port_t *fcport = sp->fcport;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3198) struct scsi_qla_host *vha = fcport->vha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3199) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3200) struct req_que *req = vha->req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3201) struct qla_qpair *qpair = sp->qpair;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3203) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x108c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3204) "Entered %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3206) if (sp->qpair)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3207) req = sp->qpair->req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3208) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3209) return QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3211) if (ql2xasynctmfenable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3212) return qla24xx_async_abort_command(sp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3214) spin_lock_irqsave(qpair->qp_lock_ptr, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3215) for (handle = 1; handle < req->num_outstanding_cmds; handle++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3216) if (req->outstanding_cmds[handle] == sp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3217) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3219) spin_unlock_irqrestore(qpair->qp_lock_ptr, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3220) if (handle == req->num_outstanding_cmds) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3221) /* Command not found. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3222) return QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3225) abt = dma_pool_zalloc(ha->s_dma_pool, GFP_KERNEL, &abt_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3226) if (abt == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3227) ql_log(ql_log_warn, vha, 0x108d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3228) "Failed to allocate abort IOCB.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3229) return QLA_MEMORY_ALLOC_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3232) abt->entry_type = ABORT_IOCB_TYPE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3233) abt->entry_count = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3234) abt->handle = make_handle(req->id, abt->handle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3235) abt->nport_handle = cpu_to_le16(fcport->loop_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3236) abt->handle_to_abort = make_handle(req->id, handle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3237) abt->port_id[0] = fcport->d_id.b.al_pa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3238) abt->port_id[1] = fcport->d_id.b.area;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3239) abt->port_id[2] = fcport->d_id.b.domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3240) abt->vp_index = fcport->vha->vp_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3242) abt->req_que_no = cpu_to_le16(req->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3244) rval = qla2x00_issue_iocb(vha, abt, abt_dma, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3245) if (rval != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3246) ql_dbg(ql_dbg_mbx, vha, 0x108e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3247) "Failed to issue IOCB (%x).\n", rval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3248) } else if (abt->entry_status != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3249) ql_dbg(ql_dbg_mbx, vha, 0x108f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3250) "Failed to complete IOCB -- error status (%x).\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3251) abt->entry_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3252) rval = QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3253) } else if (abt->nport_handle != cpu_to_le16(0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3254) ql_dbg(ql_dbg_mbx, vha, 0x1090,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3255) "Failed to complete IOCB -- completion status (%x).\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3256) le16_to_cpu(abt->nport_handle));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3257) if (abt->nport_handle == cpu_to_le16(CS_IOCB_ERROR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3258) rval = QLA_FUNCTION_PARAMETER_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3259) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3260) rval = QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3261) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3262) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1091,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3263) "Done %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3266) dma_pool_free(ha->s_dma_pool, abt, abt_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3268) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3271) struct tsk_mgmt_cmd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3272) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3273) struct tsk_mgmt_entry tsk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3274) struct sts_entry_24xx sts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3275) } p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3276) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3278) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3279) __qla24xx_issue_tmf(char *name, uint32_t type, struct fc_port *fcport,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3280) uint64_t l, int tag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3281) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3282) int rval, rval2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3283) struct tsk_mgmt_cmd *tsk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3284) struct sts_entry_24xx *sts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3285) dma_addr_t tsk_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3286) scsi_qla_host_t *vha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3287) struct qla_hw_data *ha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3288) struct req_que *req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3289) struct qla_qpair *qpair;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3291) vha = fcport->vha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3292) ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3293) req = vha->req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3295) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1092,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3296) "Entered %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3298) if (vha->vp_idx && vha->qpair) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3299) /* NPIV port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3300) qpair = vha->qpair;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3301) req = qpair->req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3304) tsk = dma_pool_zalloc(ha->s_dma_pool, GFP_KERNEL, &tsk_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3305) if (tsk == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3306) ql_log(ql_log_warn, vha, 0x1093,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3307) "Failed to allocate task management IOCB.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3308) return QLA_MEMORY_ALLOC_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3311) tsk->p.tsk.entry_type = TSK_MGMT_IOCB_TYPE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3312) tsk->p.tsk.entry_count = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3313) tsk->p.tsk.handle = make_handle(req->id, tsk->p.tsk.handle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3314) tsk->p.tsk.nport_handle = cpu_to_le16(fcport->loop_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3315) tsk->p.tsk.timeout = cpu_to_le16(ha->r_a_tov / 10 * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3316) tsk->p.tsk.control_flags = cpu_to_le32(type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3317) tsk->p.tsk.port_id[0] = fcport->d_id.b.al_pa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3318) tsk->p.tsk.port_id[1] = fcport->d_id.b.area;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3319) tsk->p.tsk.port_id[2] = fcport->d_id.b.domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3320) tsk->p.tsk.vp_index = fcport->vha->vp_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3321) if (type == TCF_LUN_RESET) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3322) int_to_scsilun(l, &tsk->p.tsk.lun);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3323) host_to_fcp_swap((uint8_t *)&tsk->p.tsk.lun,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3324) sizeof(tsk->p.tsk.lun));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3327) sts = &tsk->p.sts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3328) rval = qla2x00_issue_iocb(vha, tsk, tsk_dma, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3329) if (rval != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3330) ql_dbg(ql_dbg_mbx, vha, 0x1094,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3331) "Failed to issue %s reset IOCB (%x).\n", name, rval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3332) } else if (sts->entry_status != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3333) ql_dbg(ql_dbg_mbx, vha, 0x1095,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3334) "Failed to complete IOCB -- error status (%x).\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3335) sts->entry_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3336) rval = QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3337) } else if (sts->comp_status != cpu_to_le16(CS_COMPLETE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3338) ql_dbg(ql_dbg_mbx, vha, 0x1096,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3339) "Failed to complete IOCB -- completion status (%x).\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3340) le16_to_cpu(sts->comp_status));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3341) rval = QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3342) } else if (le16_to_cpu(sts->scsi_status) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3343) SS_RESPONSE_INFO_LEN_VALID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3344) if (le32_to_cpu(sts->rsp_data_len) < 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3345) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1097,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3346) "Ignoring inconsistent data length -- not enough "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3347) "response info (%d).\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3348) le32_to_cpu(sts->rsp_data_len));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3349) } else if (sts->data[3]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3350) ql_dbg(ql_dbg_mbx, vha, 0x1098,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3351) "Failed to complete IOCB -- response (%x).\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3352) sts->data[3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3353) rval = QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3357) /* Issue marker IOCB. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3358) rval2 = qla2x00_marker(vha, ha->base_qpair, fcport->loop_id, l,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3359) type == TCF_LUN_RESET ? MK_SYNC_ID_LUN : MK_SYNC_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3360) if (rval2 != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3361) ql_dbg(ql_dbg_mbx, vha, 0x1099,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3362) "Failed to issue marker IOCB (%x).\n", rval2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3363) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3364) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x109a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3365) "Done %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3368) dma_pool_free(ha->s_dma_pool, tsk, tsk_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3370) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3373) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3374) qla24xx_abort_target(struct fc_port *fcport, uint64_t l, int tag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3375) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3376) struct qla_hw_data *ha = fcport->vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3378) if ((ql2xasynctmfenable) && IS_FWI2_CAPABLE(ha))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3379) return qla2x00_async_tm_cmd(fcport, TCF_TARGET_RESET, l, tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3381) return __qla24xx_issue_tmf("Target", TCF_TARGET_RESET, fcport, l, tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3384) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3385) qla24xx_lun_reset(struct fc_port *fcport, uint64_t l, int tag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3386) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3387) struct qla_hw_data *ha = fcport->vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3389) if ((ql2xasynctmfenable) && IS_FWI2_CAPABLE(ha))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3390) return qla2x00_async_tm_cmd(fcport, TCF_LUN_RESET, l, tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3392) return __qla24xx_issue_tmf("Lun", TCF_LUN_RESET, fcport, l, tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3395) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3396) qla2x00_system_error(scsi_qla_host_t *vha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3397) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3398) int rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3399) mbx_cmd_t mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3400) mbx_cmd_t *mcp = &mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3401) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3403) if (!IS_QLA23XX(ha) && !IS_FWI2_CAPABLE(ha))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3404) return QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3406) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x109b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3407) "Entered %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3409) mcp->mb[0] = MBC_GEN_SYSTEM_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3410) mcp->out_mb = MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3411) mcp->in_mb = MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3412) mcp->tov = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3413) mcp->flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3414) rval = qla2x00_mailbox_command(vha, mcp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3416) if (rval != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3417) ql_dbg(ql_dbg_mbx, vha, 0x109c, "Failed=%x.\n", rval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3418) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3419) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x109d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3420) "Done %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3421) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3423) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3426) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3427) qla2x00_write_serdes_word(scsi_qla_host_t *vha, uint16_t addr, uint16_t data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3428) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3429) int rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3430) mbx_cmd_t mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3431) mbx_cmd_t *mcp = &mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3433) if (!IS_QLA25XX(vha->hw) && !IS_QLA2031(vha->hw) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3434) !IS_QLA27XX(vha->hw) && !IS_QLA28XX(vha->hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3435) return QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3437) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1182,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3438) "Entered %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3440) mcp->mb[0] = MBC_WRITE_SERDES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3441) mcp->mb[1] = addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3442) if (IS_QLA2031(vha->hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3443) mcp->mb[2] = data & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3444) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3445) mcp->mb[2] = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3447) mcp->mb[3] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3448) mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3449) mcp->in_mb = MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3450) mcp->tov = MBX_TOV_SECONDS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3451) mcp->flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3452) rval = qla2x00_mailbox_command(vha, mcp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3454) if (rval != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3455) ql_dbg(ql_dbg_mbx, vha, 0x1183,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3456) "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3457) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3458) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1184,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3459) "Done %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3460) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3462) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3463) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3465) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3466) qla2x00_read_serdes_word(scsi_qla_host_t *vha, uint16_t addr, uint16_t *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3467) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3468) int rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3469) mbx_cmd_t mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3470) mbx_cmd_t *mcp = &mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3472) if (!IS_QLA25XX(vha->hw) && !IS_QLA2031(vha->hw) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3473) !IS_QLA27XX(vha->hw) && !IS_QLA28XX(vha->hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3474) return QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3476) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1185,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3477) "Entered %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3479) mcp->mb[0] = MBC_READ_SERDES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3480) mcp->mb[1] = addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3481) mcp->mb[3] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3482) mcp->out_mb = MBX_3|MBX_1|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3483) mcp->in_mb = MBX_1|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3484) mcp->tov = MBX_TOV_SECONDS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3485) mcp->flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3486) rval = qla2x00_mailbox_command(vha, mcp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3488) if (IS_QLA2031(vha->hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3489) *data = mcp->mb[1] & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3490) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3491) *data = mcp->mb[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3493) if (rval != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3494) ql_dbg(ql_dbg_mbx, vha, 0x1186,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3495) "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3496) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3497) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1187,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3498) "Done %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3499) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3501) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3502) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3504) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3505) qla8044_write_serdes_word(scsi_qla_host_t *vha, uint32_t addr, uint32_t data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3506) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3507) int rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3508) mbx_cmd_t mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3509) mbx_cmd_t *mcp = &mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3511) if (!IS_QLA8044(vha->hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3512) return QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3514) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x11a0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3515) "Entered %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3517) mcp->mb[0] = MBC_SET_GET_ETH_SERDES_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3518) mcp->mb[1] = HCS_WRITE_SERDES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3519) mcp->mb[3] = LSW(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3520) mcp->mb[4] = MSW(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3521) mcp->mb[5] = LSW(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3522) mcp->mb[6] = MSW(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3523) mcp->out_mb = MBX_6|MBX_5|MBX_4|MBX_3|MBX_1|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3524) mcp->in_mb = MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3525) mcp->tov = MBX_TOV_SECONDS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3526) mcp->flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3527) rval = qla2x00_mailbox_command(vha, mcp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3529) if (rval != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3530) ql_dbg(ql_dbg_mbx, vha, 0x11a1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3531) "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3532) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3533) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1188,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3534) "Done %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3535) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3537) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3538) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3540) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3541) qla8044_read_serdes_word(scsi_qla_host_t *vha, uint32_t addr, uint32_t *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3542) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3543) int rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3544) mbx_cmd_t mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3545) mbx_cmd_t *mcp = &mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3547) if (!IS_QLA8044(vha->hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3548) return QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3550) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1189,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3551) "Entered %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3553) mcp->mb[0] = MBC_SET_GET_ETH_SERDES_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3554) mcp->mb[1] = HCS_READ_SERDES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3555) mcp->mb[3] = LSW(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3556) mcp->mb[4] = MSW(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3557) mcp->out_mb = MBX_4|MBX_3|MBX_1|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3558) mcp->in_mb = MBX_2|MBX_1|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3559) mcp->tov = MBX_TOV_SECONDS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3560) mcp->flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3561) rval = qla2x00_mailbox_command(vha, mcp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3563) *data = mcp->mb[2] << 16 | mcp->mb[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3565) if (rval != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3566) ql_dbg(ql_dbg_mbx, vha, 0x118a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3567) "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3568) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3569) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x118b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3570) "Done %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3571) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3573) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3574) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3576) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3577) * qla2x00_set_serdes_params() -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3578) * @vha: HA context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3579) * @sw_em_1g: serial link options
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3580) * @sw_em_2g: serial link options
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3581) * @sw_em_4g: serial link options
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3582) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3583) * Returns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3584) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3585) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3586) qla2x00_set_serdes_params(scsi_qla_host_t *vha, uint16_t sw_em_1g,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3587) uint16_t sw_em_2g, uint16_t sw_em_4g)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3588) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3589) int rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3590) mbx_cmd_t mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3591) mbx_cmd_t *mcp = &mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3593) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x109e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3594) "Entered %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3596) mcp->mb[0] = MBC_SERDES_PARAMS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3597) mcp->mb[1] = BIT_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3598) mcp->mb[2] = sw_em_1g | BIT_15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3599) mcp->mb[3] = sw_em_2g | BIT_15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3600) mcp->mb[4] = sw_em_4g | BIT_15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3601) mcp->out_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3602) mcp->in_mb = MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3603) mcp->tov = MBX_TOV_SECONDS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3604) mcp->flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3605) rval = qla2x00_mailbox_command(vha, mcp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3607) if (rval != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3608) /*EMPTY*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3609) ql_dbg(ql_dbg_mbx, vha, 0x109f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3610) "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3611) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3612) /*EMPTY*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3613) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3614) "Done %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3615) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3617) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3618) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3620) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3621) qla2x00_stop_firmware(scsi_qla_host_t *vha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3622) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3623) int rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3624) mbx_cmd_t mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3625) mbx_cmd_t *mcp = &mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3627) if (!IS_FWI2_CAPABLE(vha->hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3628) return QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3630) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3631) "Entered %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3633) mcp->mb[0] = MBC_STOP_FIRMWARE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3634) mcp->mb[1] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3635) mcp->out_mb = MBX_1|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3636) mcp->in_mb = MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3637) mcp->tov = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3638) mcp->flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3639) rval = qla2x00_mailbox_command(vha, mcp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3641) if (rval != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3642) ql_dbg(ql_dbg_mbx, vha, 0x10a2, "Failed=%x.\n", rval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3643) if (mcp->mb[0] == MBS_INVALID_COMMAND)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3644) rval = QLA_INVALID_COMMAND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3645) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3646) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3647) "Done %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3648) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3650) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3651) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3653) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3654) qla2x00_enable_eft_trace(scsi_qla_host_t *vha, dma_addr_t eft_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3655) uint16_t buffers)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3656) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3657) int rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3658) mbx_cmd_t mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3659) mbx_cmd_t *mcp = &mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3661) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3662) "Entered %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3664) if (!IS_FWI2_CAPABLE(vha->hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3665) return QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3667) if (unlikely(pci_channel_offline(vha->hw->pdev)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3668) return QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3670) mcp->mb[0] = MBC_TRACE_CONTROL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3671) mcp->mb[1] = TC_EFT_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3672) mcp->mb[2] = LSW(eft_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3673) mcp->mb[3] = MSW(eft_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3674) mcp->mb[4] = LSW(MSD(eft_dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3675) mcp->mb[5] = MSW(MSD(eft_dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3676) mcp->mb[6] = buffers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3677) mcp->mb[7] = TC_AEN_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3678) mcp->out_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3679) mcp->in_mb = MBX_1|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3680) mcp->tov = MBX_TOV_SECONDS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3681) mcp->flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3682) rval = qla2x00_mailbox_command(vha, mcp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3683) if (rval != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3684) ql_dbg(ql_dbg_mbx, vha, 0x10a5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3685) "Failed=%x mb[0]=%x mb[1]=%x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3686) rval, mcp->mb[0], mcp->mb[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3687) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3688) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3689) "Done %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3690) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3692) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3693) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3695) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3696) qla2x00_disable_eft_trace(scsi_qla_host_t *vha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3697) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3698) int rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3699) mbx_cmd_t mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3700) mbx_cmd_t *mcp = &mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3702) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3703) "Entered %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3705) if (!IS_FWI2_CAPABLE(vha->hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3706) return QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3708) if (unlikely(pci_channel_offline(vha->hw->pdev)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3709) return QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3711) mcp->mb[0] = MBC_TRACE_CONTROL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3712) mcp->mb[1] = TC_EFT_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3713) mcp->out_mb = MBX_1|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3714) mcp->in_mb = MBX_1|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3715) mcp->tov = MBX_TOV_SECONDS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3716) mcp->flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3717) rval = qla2x00_mailbox_command(vha, mcp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3718) if (rval != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3719) ql_dbg(ql_dbg_mbx, vha, 0x10a8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3720) "Failed=%x mb[0]=%x mb[1]=%x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3721) rval, mcp->mb[0], mcp->mb[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3722) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3723) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3724) "Done %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3725) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3727) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3728) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3730) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3731) qla2x00_enable_fce_trace(scsi_qla_host_t *vha, dma_addr_t fce_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3732) uint16_t buffers, uint16_t *mb, uint32_t *dwords)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3733) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3734) int rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3735) mbx_cmd_t mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3736) mbx_cmd_t *mcp = &mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3738) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10aa,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3739) "Entered %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3741) if (!IS_QLA25XX(vha->hw) && !IS_QLA81XX(vha->hw) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3742) !IS_QLA83XX(vha->hw) && !IS_QLA27XX(vha->hw) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3743) !IS_QLA28XX(vha->hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3744) return QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3746) if (unlikely(pci_channel_offline(vha->hw->pdev)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3747) return QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3749) mcp->mb[0] = MBC_TRACE_CONTROL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3750) mcp->mb[1] = TC_FCE_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3751) mcp->mb[2] = LSW(fce_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3752) mcp->mb[3] = MSW(fce_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3753) mcp->mb[4] = LSW(MSD(fce_dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3754) mcp->mb[5] = MSW(MSD(fce_dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3755) mcp->mb[6] = buffers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3756) mcp->mb[7] = TC_AEN_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3757) mcp->mb[8] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3758) mcp->mb[9] = TC_FCE_DEFAULT_RX_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3759) mcp->mb[10] = TC_FCE_DEFAULT_TX_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3760) mcp->out_mb = MBX_10|MBX_9|MBX_8|MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3761) MBX_1|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3762) mcp->in_mb = MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3763) mcp->tov = MBX_TOV_SECONDS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3764) mcp->flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3765) rval = qla2x00_mailbox_command(vha, mcp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3766) if (rval != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3767) ql_dbg(ql_dbg_mbx, vha, 0x10ab,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3768) "Failed=%x mb[0]=%x mb[1]=%x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3769) rval, mcp->mb[0], mcp->mb[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3770) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3771) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ac,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3772) "Done %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3774) if (mb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3775) memcpy(mb, mcp->mb, 8 * sizeof(*mb));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3776) if (dwords)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3777) *dwords = buffers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3778) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3780) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3781) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3783) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3784) qla2x00_disable_fce_trace(scsi_qla_host_t *vha, uint64_t *wr, uint64_t *rd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3785) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3786) int rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3787) mbx_cmd_t mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3788) mbx_cmd_t *mcp = &mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3790) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ad,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3791) "Entered %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3793) if (!IS_FWI2_CAPABLE(vha->hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3794) return QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3796) if (unlikely(pci_channel_offline(vha->hw->pdev)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3797) return QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3799) mcp->mb[0] = MBC_TRACE_CONTROL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3800) mcp->mb[1] = TC_FCE_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3801) mcp->mb[2] = TC_FCE_DISABLE_TRACE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3802) mcp->out_mb = MBX_2|MBX_1|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3803) mcp->in_mb = MBX_9|MBX_8|MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3804) MBX_1|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3805) mcp->tov = MBX_TOV_SECONDS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3806) mcp->flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3807) rval = qla2x00_mailbox_command(vha, mcp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3808) if (rval != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3809) ql_dbg(ql_dbg_mbx, vha, 0x10ae,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3810) "Failed=%x mb[0]=%x mb[1]=%x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3811) rval, mcp->mb[0], mcp->mb[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3812) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3813) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10af,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3814) "Done %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3816) if (wr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3817) *wr = (uint64_t) mcp->mb[5] << 48 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3818) (uint64_t) mcp->mb[4] << 32 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3819) (uint64_t) mcp->mb[3] << 16 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3820) (uint64_t) mcp->mb[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3821) if (rd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3822) *rd = (uint64_t) mcp->mb[9] << 48 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3823) (uint64_t) mcp->mb[8] << 32 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3824) (uint64_t) mcp->mb[7] << 16 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3825) (uint64_t) mcp->mb[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3826) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3828) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3829) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3831) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3832) qla2x00_get_idma_speed(scsi_qla_host_t *vha, uint16_t loop_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3833) uint16_t *port_speed, uint16_t *mb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3834) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3835) int rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3836) mbx_cmd_t mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3837) mbx_cmd_t *mcp = &mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3839) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3840) "Entered %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3842) if (!IS_IIDMA_CAPABLE(vha->hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3843) return QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3845) mcp->mb[0] = MBC_PORT_PARAMS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3846) mcp->mb[1] = loop_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3847) mcp->mb[2] = mcp->mb[3] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3848) mcp->mb[9] = vha->vp_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3849) mcp->out_mb = MBX_9|MBX_3|MBX_2|MBX_1|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3850) mcp->in_mb = MBX_3|MBX_1|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3851) mcp->tov = MBX_TOV_SECONDS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3852) mcp->flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3853) rval = qla2x00_mailbox_command(vha, mcp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3855) /* Return mailbox statuses. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3856) if (mb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3857) mb[0] = mcp->mb[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3858) mb[1] = mcp->mb[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3859) mb[3] = mcp->mb[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3860) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3862) if (rval != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3863) ql_dbg(ql_dbg_mbx, vha, 0x10b1, "Failed=%x.\n", rval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3864) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3865) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3866) "Done %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3867) if (port_speed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3868) *port_speed = mcp->mb[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3869) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3871) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3872) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3874) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3875) qla2x00_set_idma_speed(scsi_qla_host_t *vha, uint16_t loop_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3876) uint16_t port_speed, uint16_t *mb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3877) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3878) int rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3879) mbx_cmd_t mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3880) mbx_cmd_t *mcp = &mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3882) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3883) "Entered %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3885) if (!IS_IIDMA_CAPABLE(vha->hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3886) return QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3888) mcp->mb[0] = MBC_PORT_PARAMS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3889) mcp->mb[1] = loop_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3890) mcp->mb[2] = BIT_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3891) mcp->mb[3] = port_speed & 0x3F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3892) mcp->mb[9] = vha->vp_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3893) mcp->out_mb = MBX_9|MBX_3|MBX_2|MBX_1|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3894) mcp->in_mb = MBX_3|MBX_1|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3895) mcp->tov = MBX_TOV_SECONDS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3896) mcp->flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3897) rval = qla2x00_mailbox_command(vha, mcp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3899) /* Return mailbox statuses. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3900) if (mb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3901) mb[0] = mcp->mb[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3902) mb[1] = mcp->mb[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3903) mb[3] = mcp->mb[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3904) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3906) if (rval != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3907) ql_dbg(ql_dbg_mbx, vha, 0x10b4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3908) "Failed=%x.\n", rval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3909) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3910) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3911) "Done %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3912) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3914) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3915) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3917) void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3918) qla24xx_report_id_acquisition(scsi_qla_host_t *vha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3919) struct vp_rpt_id_entry_24xx *rptid_entry)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3920) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3921) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3922) scsi_qla_host_t *vp = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3923) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3924) int found;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3925) port_id_t id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3926) struct fc_port *fcport;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3928) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3929) "Entered %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3931) if (rptid_entry->entry_status != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3932) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3934) id.b.domain = rptid_entry->port_id[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3935) id.b.area = rptid_entry->port_id[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3936) id.b.al_pa = rptid_entry->port_id[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3937) id.b.rsvd_1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3938) ha->flags.n2n_ae = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3940) if (rptid_entry->format == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3941) /* loop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3942) ql_dbg(ql_dbg_async, vha, 0x10b7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3943) "Format 0 : Number of VPs setup %d, number of "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3944) "VPs acquired %d.\n", rptid_entry->vp_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3945) rptid_entry->vp_acquired);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3946) ql_dbg(ql_dbg_async, vha, 0x10b8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3947) "Primary port id %02x%02x%02x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3948) rptid_entry->port_id[2], rptid_entry->port_id[1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3949) rptid_entry->port_id[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3950) ha->current_topology = ISP_CFG_NL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3951) qlt_update_host_map(vha, id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3953) } else if (rptid_entry->format == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3954) /* fabric */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3955) ql_dbg(ql_dbg_async, vha, 0x10b9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3956) "Format 1: VP[%d] enabled - status %d - with "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3957) "port id %02x%02x%02x.\n", rptid_entry->vp_idx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3958) rptid_entry->vp_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3959) rptid_entry->port_id[2], rptid_entry->port_id[1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3960) rptid_entry->port_id[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3961) ql_dbg(ql_dbg_async, vha, 0x5075,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3962) "Format 1: Remote WWPN %8phC.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3963) rptid_entry->u.f1.port_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3965) ql_dbg(ql_dbg_async, vha, 0x5075,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3966) "Format 1: WWPN %8phC.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3967) vha->port_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3969) switch (rptid_entry->u.f1.flags & TOPO_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3970) case TOPO_N2N:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3971) ha->current_topology = ISP_CFG_N;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3972) spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3973) list_for_each_entry(fcport, &vha->vp_fcports, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3974) fcport->scan_state = QLA_FCPORT_SCAN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3975) fcport->n2n_flag = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3976) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3977) id.b24 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3978) if (wwn_to_u64(vha->port_name) >
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3979) wwn_to_u64(rptid_entry->u.f1.port_name)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3980) vha->d_id.b24 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3981) vha->d_id.b.al_pa = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3982) ha->flags.n2n_bigger = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3984) id.b.al_pa = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3985) ql_dbg(ql_dbg_async, vha, 0x5075,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3986) "Format 1: assign local id %x remote id %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3987) vha->d_id.b24, id.b24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3988) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3989) ql_dbg(ql_dbg_async, vha, 0x5075,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3990) "Format 1: Remote login - Waiting for WWPN %8phC.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3991) rptid_entry->u.f1.port_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3992) ha->flags.n2n_bigger = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3993) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3995) fcport = qla2x00_find_fcport_by_wwpn(vha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3996) rptid_entry->u.f1.port_name, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3997) spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4000) if (fcport) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4001) fcport->plogi_nack_done_deadline = jiffies + HZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4002) fcport->dm_login_expire = jiffies +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4003) QLA_N2N_WAIT_TIME * HZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4004) fcport->scan_state = QLA_FCPORT_FOUND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4005) fcport->n2n_flag = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4006) fcport->keep_nport_handle = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4008) if (wwn_to_u64(vha->port_name) >
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4009) wwn_to_u64(fcport->port_name)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4010) fcport->d_id = id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4011) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4013) switch (fcport->disc_state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4014) case DSC_DELETED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4015) set_bit(RELOGIN_NEEDED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4016) &vha->dpc_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4017) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4018) case DSC_DELETE_PEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4019) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4020) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4021) qlt_schedule_sess_for_deletion(fcport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4022) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4023) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4024) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4025) qla24xx_post_newsess_work(vha, &id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4026) rptid_entry->u.f1.port_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4027) rptid_entry->u.f1.node_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4028) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4029) FS_FCP_IS_N2N);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4030) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4032) /* if our portname is higher then initiate N2N login */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4034) set_bit(N2N_LOGIN_NEEDED, &vha->dpc_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4035) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4036) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4037) case TOPO_FL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4038) ha->current_topology = ISP_CFG_FL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4039) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4040) case TOPO_F:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4041) ha->current_topology = ISP_CFG_F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4042) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4043) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4044) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4045) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4047) ha->flags.gpsc_supported = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4048) ha->current_topology = ISP_CFG_F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4049) /* buffer to buffer credit flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4050) vha->flags.bbcr_enable = (rptid_entry->u.f1.bbcr & 0xf) != 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4052) if (rptid_entry->vp_idx == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4053) if (rptid_entry->vp_status == VP_STAT_COMPL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4054) /* FA-WWN is only for physical port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4055) if (qla_ini_mode_enabled(vha) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4056) ha->flags.fawwpn_enabled &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4057) (rptid_entry->u.f1.flags &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4058) BIT_6)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4059) memcpy(vha->port_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4060) rptid_entry->u.f1.port_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4061) WWN_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4062) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4064) qlt_update_host_map(vha, id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4065) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4067) set_bit(REGISTER_FC4_NEEDED, &vha->dpc_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4068) set_bit(REGISTER_FDMI_NEEDED, &vha->dpc_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4069) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4070) if (rptid_entry->vp_status != VP_STAT_COMPL &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4071) rptid_entry->vp_status != VP_STAT_ID_CHG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4072) ql_dbg(ql_dbg_mbx, vha, 0x10ba,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4073) "Could not acquire ID for VP[%d].\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4074) rptid_entry->vp_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4075) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4076) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4078) found = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4079) spin_lock_irqsave(&ha->vport_slock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4080) list_for_each_entry(vp, &ha->vp_list, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4081) if (rptid_entry->vp_idx == vp->vp_idx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4082) found = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4083) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4084) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4085) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4086) spin_unlock_irqrestore(&ha->vport_slock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4088) if (!found)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4089) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4091) qlt_update_host_map(vp, id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4093) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4094) * Cannot configure here as we are still sitting on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4095) * response queue. Handle it in dpc context.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4096) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4097) set_bit(VP_IDX_ACQUIRED, &vp->vp_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4098) set_bit(REGISTER_FC4_NEEDED, &vp->dpc_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4099) set_bit(REGISTER_FDMI_NEEDED, &vp->dpc_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4101) set_bit(VP_DPC_NEEDED, &vha->dpc_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4102) qla2xxx_wake_dpc(vha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4103) } else if (rptid_entry->format == 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4104) ql_dbg(ql_dbg_async, vha, 0x505f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4105) "RIDA: format 2/N2N Primary port id %02x%02x%02x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4106) rptid_entry->port_id[2], rptid_entry->port_id[1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4107) rptid_entry->port_id[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4109) ql_dbg(ql_dbg_async, vha, 0x5075,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4110) "N2N: Remote WWPN %8phC.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4111) rptid_entry->u.f2.port_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4113) /* N2N. direct connect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4114) ha->current_topology = ISP_CFG_N;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4115) ha->flags.rida_fmt2 = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4116) vha->d_id.b.domain = rptid_entry->port_id[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4117) vha->d_id.b.area = rptid_entry->port_id[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4118) vha->d_id.b.al_pa = rptid_entry->port_id[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4120) ha->flags.n2n_ae = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4121) spin_lock_irqsave(&ha->vport_slock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4122) qlt_update_vp_map(vha, SET_AL_PA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4123) spin_unlock_irqrestore(&ha->vport_slock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4125) list_for_each_entry(fcport, &vha->vp_fcports, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4126) fcport->scan_state = QLA_FCPORT_SCAN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4127) fcport->n2n_flag = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4130) fcport = qla2x00_find_fcport_by_wwpn(vha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4131) rptid_entry->u.f2.port_name, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4133) if (fcport) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4134) fcport->login_retry = vha->hw->login_retry_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4135) fcport->plogi_nack_done_deadline = jiffies + HZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4136) fcport->scan_state = QLA_FCPORT_FOUND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4137) fcport->keep_nport_handle = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4138) fcport->n2n_flag = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4139) fcport->d_id.b.domain =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4140) rptid_entry->u.f2.remote_nport_id[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4141) fcport->d_id.b.area =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4142) rptid_entry->u.f2.remote_nport_id[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4143) fcport->d_id.b.al_pa =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4144) rptid_entry->u.f2.remote_nport_id[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4149) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4150) * qla24xx_modify_vp_config
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4151) * Change VP configuration for vha
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4152) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4153) * Input:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4154) * vha = adapter block pointer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4155) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4156) * Returns:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4157) * qla2xxx local function return status code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4158) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4159) * Context:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4160) * Kernel context.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4161) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4162) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4163) qla24xx_modify_vp_config(scsi_qla_host_t *vha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4164) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4165) int rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4166) struct vp_config_entry_24xx *vpmod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4167) dma_addr_t vpmod_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4168) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4169) struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4171) /* This can be called by the parent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4173) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10bb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4174) "Entered %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4176) vpmod = dma_pool_zalloc(ha->s_dma_pool, GFP_KERNEL, &vpmod_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4177) if (!vpmod) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4178) ql_log(ql_log_warn, vha, 0x10bc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4179) "Failed to allocate modify VP IOCB.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4180) return QLA_MEMORY_ALLOC_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4183) vpmod->entry_type = VP_CONFIG_IOCB_TYPE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4184) vpmod->entry_count = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4185) vpmod->command = VCT_COMMAND_MOD_ENABLE_VPS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4186) vpmod->vp_count = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4187) vpmod->vp_index1 = vha->vp_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4188) vpmod->options_idx1 = BIT_3|BIT_4|BIT_5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4190) qlt_modify_vp_config(vha, vpmod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4192) memcpy(vpmod->node_name_idx1, vha->node_name, WWN_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4193) memcpy(vpmod->port_name_idx1, vha->port_name, WWN_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4194) vpmod->entry_count = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4196) rval = qla2x00_issue_iocb(base_vha, vpmod, vpmod_dma, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4197) if (rval != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4198) ql_dbg(ql_dbg_mbx, vha, 0x10bd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4199) "Failed to issue VP config IOCB (%x).\n", rval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4200) } else if (vpmod->comp_status != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4201) ql_dbg(ql_dbg_mbx, vha, 0x10be,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4202) "Failed to complete IOCB -- error status (%x).\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4203) vpmod->comp_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4204) rval = QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4205) } else if (vpmod->comp_status != cpu_to_le16(CS_COMPLETE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4206) ql_dbg(ql_dbg_mbx, vha, 0x10bf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4207) "Failed to complete IOCB -- completion status (%x).\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4208) le16_to_cpu(vpmod->comp_status));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4209) rval = QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4210) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4211) /* EMPTY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4212) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10c0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4213) "Done %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4214) fc_vport_set_state(vha->fc_vport, FC_VPORT_INITIALIZING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4216) dma_pool_free(ha->s_dma_pool, vpmod, vpmod_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4218) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4221) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4222) * qla2x00_send_change_request
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4223) * Receive or disable RSCN request from fabric controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4224) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4225) * Input:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4226) * ha = adapter block pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4227) * format = registration format:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4228) * 0 - Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4229) * 1 - Fabric detected registration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4230) * 2 - N_port detected registration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4231) * 3 - Full registration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4232) * FF - clear registration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4233) * vp_idx = Virtual port index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4234) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4235) * Returns:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4236) * qla2x00 local function return status code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4237) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4238) * Context:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4239) * Kernel Context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4240) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4242) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4243) qla2x00_send_change_request(scsi_qla_host_t *vha, uint16_t format,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4244) uint16_t vp_idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4245) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4246) int rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4247) mbx_cmd_t mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4248) mbx_cmd_t *mcp = &mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4250) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10c7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4251) "Entered %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4253) mcp->mb[0] = MBC_SEND_CHANGE_REQUEST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4254) mcp->mb[1] = format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4255) mcp->mb[9] = vp_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4256) mcp->out_mb = MBX_9|MBX_1|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4257) mcp->in_mb = MBX_0|MBX_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4258) mcp->tov = MBX_TOV_SECONDS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4259) mcp->flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4260) rval = qla2x00_mailbox_command(vha, mcp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4262) if (rval == QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4263) if (mcp->mb[0] != MBS_COMMAND_COMPLETE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4264) rval = BIT_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4266) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4267) rval = BIT_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4269) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4272) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4273) qla2x00_dump_ram(scsi_qla_host_t *vha, dma_addr_t req_dma, uint32_t addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4274) uint32_t size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4275) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4276) int rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4277) mbx_cmd_t mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4278) mbx_cmd_t *mcp = &mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4280) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1009,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4281) "Entered %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4283) if (MSW(addr) || IS_FWI2_CAPABLE(vha->hw)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4284) mcp->mb[0] = MBC_DUMP_RISC_RAM_EXTENDED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4285) mcp->mb[8] = MSW(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4286) mcp->mb[10] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4287) mcp->out_mb = MBX_10|MBX_8|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4288) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4289) mcp->mb[0] = MBC_DUMP_RISC_RAM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4290) mcp->out_mb = MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4292) mcp->mb[1] = LSW(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4293) mcp->mb[2] = MSW(req_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4294) mcp->mb[3] = LSW(req_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4295) mcp->mb[6] = MSW(MSD(req_dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4296) mcp->mb[7] = LSW(MSD(req_dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4297) mcp->out_mb |= MBX_7|MBX_6|MBX_3|MBX_2|MBX_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4298) if (IS_FWI2_CAPABLE(vha->hw)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4299) mcp->mb[4] = MSW(size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4300) mcp->mb[5] = LSW(size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4301) mcp->out_mb |= MBX_5|MBX_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4302) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4303) mcp->mb[4] = LSW(size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4304) mcp->out_mb |= MBX_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4307) mcp->in_mb = MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4308) mcp->tov = MBX_TOV_SECONDS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4309) mcp->flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4310) rval = qla2x00_mailbox_command(vha, mcp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4312) if (rval != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4313) ql_dbg(ql_dbg_mbx, vha, 0x1008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4314) "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4315) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4316) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1007,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4317) "Done %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4320) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4322) /* 84XX Support **************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4324) struct cs84xx_mgmt_cmd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4325) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4326) struct verify_chip_entry_84xx req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4327) struct verify_chip_rsp_84xx rsp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4328) } p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4329) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4331) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4332) qla84xx_verify_chip(struct scsi_qla_host *vha, uint16_t *status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4333) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4334) int rval, retry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4335) struct cs84xx_mgmt_cmd *mn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4336) dma_addr_t mn_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4337) uint16_t options;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4338) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4339) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4341) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10c8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4342) "Entered %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4344) mn = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &mn_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4345) if (mn == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4346) return QLA_MEMORY_ALLOC_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4349) /* Force Update? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4350) options = ha->cs84xx->fw_update ? VCO_FORCE_UPDATE : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4351) /* Diagnostic firmware? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4352) /* options |= MENLO_DIAG_FW; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4353) /* We update the firmware with only one data sequence. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4354) options |= VCO_END_OF_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4356) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4357) retry = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4358) memset(mn, 0, sizeof(*mn));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4359) mn->p.req.entry_type = VERIFY_CHIP_IOCB_TYPE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4360) mn->p.req.entry_count = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4361) mn->p.req.options = cpu_to_le16(options);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4363) ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x111c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4364) "Dump of Verify Request.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4365) ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x111e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4366) mn, sizeof(*mn));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4368) rval = qla2x00_issue_iocb_timeout(vha, mn, mn_dma, 0, 120);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4369) if (rval != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4370) ql_dbg(ql_dbg_mbx, vha, 0x10cb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4371) "Failed to issue verify IOCB (%x).\n", rval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4372) goto verify_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4373) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4375) ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1110,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4376) "Dump of Verify Response.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4377) ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1118,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4378) mn, sizeof(*mn));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4380) status[0] = le16_to_cpu(mn->p.rsp.comp_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4381) status[1] = status[0] == CS_VCS_CHIP_FAILURE ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4382) le16_to_cpu(mn->p.rsp.failure_code) : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4383) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ce,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4384) "cs=%x fc=%x.\n", status[0], status[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4386) if (status[0] != CS_COMPLETE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4387) rval = QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4388) if (!(options & VCO_DONT_UPDATE_FW)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4389) ql_dbg(ql_dbg_mbx, vha, 0x10cf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4390) "Firmware update failed. Retrying "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4391) "without update firmware.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4392) options |= VCO_DONT_UPDATE_FW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4393) options &= ~VCO_FORCE_UPDATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4394) retry = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4396) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4397) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4398) "Firmware updated to %x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4399) le32_to_cpu(mn->p.rsp.fw_ver));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4401) /* NOTE: we only update OP firmware. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4402) spin_lock_irqsave(&ha->cs84xx->access_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4403) ha->cs84xx->op_fw_version =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4404) le32_to_cpu(mn->p.rsp.fw_ver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4405) spin_unlock_irqrestore(&ha->cs84xx->access_lock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4406) flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4407) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4408) } while (retry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4410) verify_done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4411) dma_pool_free(ha->s_dma_pool, mn, mn_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4413) if (rval != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4414) ql_dbg(ql_dbg_mbx, vha, 0x10d1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4415) "Failed=%x.\n", rval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4416) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4417) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4418) "Done %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4419) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4421) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4424) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4425) qla25xx_init_req_que(struct scsi_qla_host *vha, struct req_que *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4426) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4427) int rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4428) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4429) mbx_cmd_t mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4430) mbx_cmd_t *mcp = &mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4431) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4433) if (!ha->flags.fw_started)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4434) return QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4436) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4437) "Entered %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4439) if (IS_SHADOW_REG_CAPABLE(ha))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4440) req->options |= BIT_13;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4442) mcp->mb[0] = MBC_INITIALIZE_MULTIQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4443) mcp->mb[1] = req->options;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4444) mcp->mb[2] = MSW(LSD(req->dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4445) mcp->mb[3] = LSW(LSD(req->dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4446) mcp->mb[6] = MSW(MSD(req->dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4447) mcp->mb[7] = LSW(MSD(req->dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4448) mcp->mb[5] = req->length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4449) if (req->rsp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4450) mcp->mb[10] = req->rsp->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4451) mcp->mb[12] = req->qos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4452) mcp->mb[11] = req->vp_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4453) mcp->mb[13] = req->rid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4454) if (IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4455) mcp->mb[15] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4457) mcp->mb[4] = req->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4458) /* que in ptr index */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4459) mcp->mb[8] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4460) /* que out ptr index */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4461) mcp->mb[9] = *req->out_ptr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4462) mcp->out_mb = MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8|MBX_7|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4463) MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4464) mcp->in_mb = MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4465) mcp->flags = MBX_DMA_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4466) mcp->tov = MBX_TOV_SECONDS * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4468) if (IS_QLA81XX(ha) || IS_QLA83XX(ha) || IS_QLA27XX(ha) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4469) IS_QLA28XX(ha))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4470) mcp->in_mb |= MBX_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4471) if (IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4472) mcp->out_mb |= MBX_15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4473) /* debug q create issue in SR-IOV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4474) mcp->in_mb |= MBX_9 | MBX_8 | MBX_7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4477) spin_lock_irqsave(&ha->hardware_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4478) if (!(req->options & BIT_0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4479) wrt_reg_dword(req->req_q_in, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4480) if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha) && !IS_QLA28XX(ha))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4481) wrt_reg_dword(req->req_q_out, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4482) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4483) spin_unlock_irqrestore(&ha->hardware_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4485) rval = qla2x00_mailbox_command(vha, mcp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4486) if (rval != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4487) ql_dbg(ql_dbg_mbx, vha, 0x10d4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4488) "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4489) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4490) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4491) "Done %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4492) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4494) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4495) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4497) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4498) qla25xx_init_rsp_que(struct scsi_qla_host *vha, struct rsp_que *rsp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4499) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4500) int rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4501) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4502) mbx_cmd_t mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4503) mbx_cmd_t *mcp = &mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4504) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4506) if (!ha->flags.fw_started)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4507) return QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4509) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4510) "Entered %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4512) if (IS_SHADOW_REG_CAPABLE(ha))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4513) rsp->options |= BIT_13;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4515) mcp->mb[0] = MBC_INITIALIZE_MULTIQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4516) mcp->mb[1] = rsp->options;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4517) mcp->mb[2] = MSW(LSD(rsp->dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4518) mcp->mb[3] = LSW(LSD(rsp->dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4519) mcp->mb[6] = MSW(MSD(rsp->dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4520) mcp->mb[7] = LSW(MSD(rsp->dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4521) mcp->mb[5] = rsp->length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4522) mcp->mb[14] = rsp->msix->entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4523) mcp->mb[13] = rsp->rid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4524) if (IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4525) mcp->mb[15] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4527) mcp->mb[4] = rsp->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4528) /* que in ptr index */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4529) mcp->mb[8] = *rsp->in_ptr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4530) /* que out ptr index */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4531) mcp->mb[9] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4532) mcp->out_mb = MBX_14|MBX_13|MBX_9|MBX_8|MBX_7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4533) |MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4534) mcp->in_mb = MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4535) mcp->flags = MBX_DMA_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4536) mcp->tov = MBX_TOV_SECONDS * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4538) if (IS_QLA81XX(ha)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4539) mcp->out_mb |= MBX_12|MBX_11|MBX_10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4540) mcp->in_mb |= MBX_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4541) } else if (IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4542) mcp->out_mb |= MBX_15|MBX_12|MBX_11|MBX_10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4543) mcp->in_mb |= MBX_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4544) /* debug q create issue in SR-IOV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4545) mcp->in_mb |= MBX_9 | MBX_8 | MBX_7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4546) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4548) spin_lock_irqsave(&ha->hardware_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4549) if (!(rsp->options & BIT_0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4550) wrt_reg_dword(rsp->rsp_q_out, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4551) if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha) && !IS_QLA28XX(ha))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4552) wrt_reg_dword(rsp->rsp_q_in, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4553) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4555) spin_unlock_irqrestore(&ha->hardware_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4557) rval = qla2x00_mailbox_command(vha, mcp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4558) if (rval != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4559) ql_dbg(ql_dbg_mbx, vha, 0x10d7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4560) "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4561) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4562) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4563) "Done %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4564) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4566) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4567) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4569) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4570) qla81xx_idc_ack(scsi_qla_host_t *vha, uint16_t *mb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4571) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4572) int rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4573) mbx_cmd_t mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4574) mbx_cmd_t *mcp = &mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4576) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4577) "Entered %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4579) mcp->mb[0] = MBC_IDC_ACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4580) memcpy(&mcp->mb[1], mb, QLA_IDC_ACK_REGS * sizeof(uint16_t));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4581) mcp->out_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4582) mcp->in_mb = MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4583) mcp->tov = MBX_TOV_SECONDS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4584) mcp->flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4585) rval = qla2x00_mailbox_command(vha, mcp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4587) if (rval != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4588) ql_dbg(ql_dbg_mbx, vha, 0x10da,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4589) "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4590) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4591) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10db,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4592) "Done %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4593) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4595) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4596) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4598) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4599) qla81xx_fac_get_sector_size(scsi_qla_host_t *vha, uint32_t *sector_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4600) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4601) int rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4602) mbx_cmd_t mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4603) mbx_cmd_t *mcp = &mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4605) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10dc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4606) "Entered %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4608) if (!IS_QLA81XX(vha->hw) && !IS_QLA83XX(vha->hw) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4609) !IS_QLA27XX(vha->hw) && !IS_QLA28XX(vha->hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4610) return QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4612) mcp->mb[0] = MBC_FLASH_ACCESS_CTRL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4613) mcp->mb[1] = FAC_OPT_CMD_GET_SECTOR_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4614) mcp->out_mb = MBX_1|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4615) mcp->in_mb = MBX_1|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4616) mcp->tov = MBX_TOV_SECONDS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4617) mcp->flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4618) rval = qla2x00_mailbox_command(vha, mcp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4620) if (rval != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4621) ql_dbg(ql_dbg_mbx, vha, 0x10dd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4622) "Failed=%x mb[0]=%x mb[1]=%x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4623) rval, mcp->mb[0], mcp->mb[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4624) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4625) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10de,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4626) "Done %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4627) *sector_size = mcp->mb[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4628) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4630) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4631) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4633) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4634) qla81xx_fac_do_write_enable(scsi_qla_host_t *vha, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4635) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4636) int rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4637) mbx_cmd_t mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4638) mbx_cmd_t *mcp = &mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4640) if (!IS_QLA81XX(vha->hw) && !IS_QLA83XX(vha->hw) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4641) !IS_QLA27XX(vha->hw) && !IS_QLA28XX(vha->hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4642) return QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4644) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10df,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4645) "Entered %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4647) mcp->mb[0] = MBC_FLASH_ACCESS_CTRL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4648) mcp->mb[1] = enable ? FAC_OPT_CMD_WRITE_ENABLE :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4649) FAC_OPT_CMD_WRITE_PROTECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4650) mcp->out_mb = MBX_1|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4651) mcp->in_mb = MBX_1|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4652) mcp->tov = MBX_TOV_SECONDS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4653) mcp->flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4654) rval = qla2x00_mailbox_command(vha, mcp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4656) if (rval != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4657) ql_dbg(ql_dbg_mbx, vha, 0x10e0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4658) "Failed=%x mb[0]=%x mb[1]=%x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4659) rval, mcp->mb[0], mcp->mb[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4660) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4661) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4662) "Done %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4663) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4665) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4666) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4668) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4669) qla81xx_fac_erase_sector(scsi_qla_host_t *vha, uint32_t start, uint32_t finish)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4670) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4671) int rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4672) mbx_cmd_t mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4673) mbx_cmd_t *mcp = &mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4675) if (!IS_QLA81XX(vha->hw) && !IS_QLA83XX(vha->hw) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4676) !IS_QLA27XX(vha->hw) && !IS_QLA28XX(vha->hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4677) return QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4679) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4680) "Entered %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4682) mcp->mb[0] = MBC_FLASH_ACCESS_CTRL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4683) mcp->mb[1] = FAC_OPT_CMD_ERASE_SECTOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4684) mcp->mb[2] = LSW(start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4685) mcp->mb[3] = MSW(start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4686) mcp->mb[4] = LSW(finish);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4687) mcp->mb[5] = MSW(finish);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4688) mcp->out_mb = MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4689) mcp->in_mb = MBX_2|MBX_1|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4690) mcp->tov = MBX_TOV_SECONDS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4691) mcp->flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4692) rval = qla2x00_mailbox_command(vha, mcp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4694) if (rval != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4695) ql_dbg(ql_dbg_mbx, vha, 0x10e3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4696) "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4697) rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4698) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4699) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4700) "Done %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4701) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4703) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4704) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4706) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4707) qla81xx_fac_semaphore_access(scsi_qla_host_t *vha, int lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4708) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4709) int rval = QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4710) mbx_cmd_t mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4711) mbx_cmd_t *mcp = &mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4712) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4714) if (!IS_QLA81XX(ha) && !IS_QLA83XX(ha) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4715) !IS_QLA27XX(ha) && !IS_QLA28XX(ha))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4716) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4718) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4719) "Entered %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4721) mcp->mb[0] = MBC_FLASH_ACCESS_CTRL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4722) mcp->mb[1] = (lock ? FAC_OPT_CMD_LOCK_SEMAPHORE :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4723) FAC_OPT_CMD_UNLOCK_SEMAPHORE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4724) mcp->out_mb = MBX_1|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4725) mcp->in_mb = MBX_1|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4726) mcp->tov = MBX_TOV_SECONDS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4727) mcp->flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4728) rval = qla2x00_mailbox_command(vha, mcp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4730) if (rval != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4731) ql_dbg(ql_dbg_mbx, vha, 0x10e3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4732) "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4733) rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4734) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4735) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4736) "Done %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4737) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4739) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4740) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4742) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4743) qla81xx_restart_mpi_firmware(scsi_qla_host_t *vha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4744) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4745) int rval = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4746) mbx_cmd_t mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4747) mbx_cmd_t *mcp = &mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4749) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4750) "Entered %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4752) mcp->mb[0] = MBC_RESTART_MPI_FW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4753) mcp->out_mb = MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4754) mcp->in_mb = MBX_0|MBX_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4755) mcp->tov = MBX_TOV_SECONDS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4756) mcp->flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4757) rval = qla2x00_mailbox_command(vha, mcp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4759) if (rval != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4760) ql_dbg(ql_dbg_mbx, vha, 0x10e6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4761) "Failed=%x mb[0]=%x mb[1]=%x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4762) rval, mcp->mb[0], mcp->mb[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4763) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4764) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4765) "Done %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4766) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4768) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4769) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4771) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4772) qla82xx_set_driver_version(scsi_qla_host_t *vha, char *version)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4773) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4774) int rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4775) mbx_cmd_t mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4776) mbx_cmd_t *mcp = &mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4777) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4778) int len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4779) __le16 *str;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4780) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4782) if (!IS_P3P_TYPE(ha))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4783) return QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4785) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x117b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4786) "Entered %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4788) str = (__force __le16 *)version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4789) len = strlen(version);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4791) mcp->mb[0] = MBC_SET_RNID_PARAMS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4792) mcp->mb[1] = RNID_TYPE_SET_VERSION << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4793) mcp->out_mb = MBX_1|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4794) for (i = 4; i < 16 && len; i++, str++, len -= 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4795) mcp->mb[i] = le16_to_cpup(str);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4796) mcp->out_mb |= 1<<i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4797) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4798) for (; i < 16; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4799) mcp->mb[i] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4800) mcp->out_mb |= 1<<i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4801) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4802) mcp->in_mb = MBX_1|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4803) mcp->tov = MBX_TOV_SECONDS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4804) mcp->flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4805) rval = qla2x00_mailbox_command(vha, mcp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4807) if (rval != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4808) ql_dbg(ql_dbg_mbx, vha, 0x117c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4809) "Failed=%x mb[0]=%x,%x.\n", rval, mcp->mb[0], mcp->mb[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4810) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4811) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x117d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4812) "Done %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4813) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4815) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4816) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4818) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4819) qla25xx_set_driver_version(scsi_qla_host_t *vha, char *version)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4820) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4821) int rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4822) mbx_cmd_t mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4823) mbx_cmd_t *mcp = &mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4824) int len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4825) uint16_t dwlen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4826) uint8_t *str;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4827) dma_addr_t str_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4828) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4830) if (!IS_FWI2_CAPABLE(ha) || IS_QLA24XX_TYPE(ha) || IS_QLA81XX(ha) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4831) IS_P3P_TYPE(ha))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4832) return QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4834) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x117e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4835) "Entered %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4837) str = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &str_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4838) if (!str) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4839) ql_log(ql_log_warn, vha, 0x117f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4840) "Failed to allocate driver version param.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4841) return QLA_MEMORY_ALLOC_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4842) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4844) memcpy(str, "\x7\x3\x11\x0", 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4845) dwlen = str[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4846) len = dwlen * 4 - 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4847) memset(str + 4, 0, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4848) if (len > strlen(version))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4849) len = strlen(version);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4850) memcpy(str + 4, version, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4852) mcp->mb[0] = MBC_SET_RNID_PARAMS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4853) mcp->mb[1] = RNID_TYPE_SET_VERSION << 8 | dwlen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4854) mcp->mb[2] = MSW(LSD(str_dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4855) mcp->mb[3] = LSW(LSD(str_dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4856) mcp->mb[6] = MSW(MSD(str_dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4857) mcp->mb[7] = LSW(MSD(str_dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4858) mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4859) mcp->in_mb = MBX_1|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4860) mcp->tov = MBX_TOV_SECONDS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4861) mcp->flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4862) rval = qla2x00_mailbox_command(vha, mcp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4864) if (rval != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4865) ql_dbg(ql_dbg_mbx, vha, 0x1180,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4866) "Failed=%x mb[0]=%x,%x.\n", rval, mcp->mb[0], mcp->mb[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4867) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4868) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1181,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4869) "Done %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4870) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4872) dma_pool_free(ha->s_dma_pool, str, str_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4874) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4875) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4877) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4878) qla24xx_get_port_login_templ(scsi_qla_host_t *vha, dma_addr_t buf_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4879) void *buf, uint16_t bufsiz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4880) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4881) int rval, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4882) mbx_cmd_t mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4883) mbx_cmd_t *mcp = &mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4884) uint32_t *bp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4886) if (!IS_FWI2_CAPABLE(vha->hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4887) return QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4889) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1159,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4890) "Entered %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4892) mcp->mb[0] = MBC_GET_RNID_PARAMS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4893) mcp->mb[1] = RNID_TYPE_PORT_LOGIN << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4894) mcp->mb[2] = MSW(buf_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4895) mcp->mb[3] = LSW(buf_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4896) mcp->mb[6] = MSW(MSD(buf_dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4897) mcp->mb[7] = LSW(MSD(buf_dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4898) mcp->mb[8] = bufsiz/4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4899) mcp->out_mb = MBX_8|MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4900) mcp->in_mb = MBX_1|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4901) mcp->tov = MBX_TOV_SECONDS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4902) mcp->flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4903) rval = qla2x00_mailbox_command(vha, mcp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4905) if (rval != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4906) ql_dbg(ql_dbg_mbx, vha, 0x115a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4907) "Failed=%x mb[0]=%x,%x.\n", rval, mcp->mb[0], mcp->mb[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4908) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4909) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x115b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4910) "Done %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4911) bp = (uint32_t *) buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4912) for (i = 0; i < (bufsiz-4)/4; i++, bp++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4913) *bp = le32_to_cpu((__force __le32)*bp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4914) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4916) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4917) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4919) #define PUREX_CMD_COUNT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4920) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4921) qla25xx_set_els_cmds_supported(scsi_qla_host_t *vha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4922) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4923) int rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4924) mbx_cmd_t mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4925) mbx_cmd_t *mcp = &mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4926) uint8_t *els_cmd_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4927) dma_addr_t els_cmd_map_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4928) uint8_t cmd_opcode[PUREX_CMD_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4929) uint8_t i, index, purex_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4930) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4932) if (!IS_QLA25XX(ha) && !IS_QLA2031(ha) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4933) !IS_QLA27XX(ha) && !IS_QLA28XX(ha))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4934) return QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4936) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1197,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4937) "Entered %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4939) els_cmd_map = dma_alloc_coherent(&ha->pdev->dev, ELS_CMD_MAP_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4940) &els_cmd_map_dma, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4941) if (!els_cmd_map) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4942) ql_log(ql_log_warn, vha, 0x7101,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4943) "Failed to allocate RDP els command param.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4944) return QLA_MEMORY_ALLOC_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4945) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4947) /* List of Purex ELS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4948) cmd_opcode[0] = ELS_FPIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4949) cmd_opcode[1] = ELS_RDP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4951) for (i = 0; i < PUREX_CMD_COUNT; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4952) index = cmd_opcode[i] / 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4953) purex_bit = cmd_opcode[i] % 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4954) els_cmd_map[index] |= 1 << purex_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4955) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4957) mcp->mb[0] = MBC_SET_RNID_PARAMS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4958) mcp->mb[1] = RNID_TYPE_ELS_CMD << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4959) mcp->mb[2] = MSW(LSD(els_cmd_map_dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4960) mcp->mb[3] = LSW(LSD(els_cmd_map_dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4961) mcp->mb[6] = MSW(MSD(els_cmd_map_dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4962) mcp->mb[7] = LSW(MSD(els_cmd_map_dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4963) mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4964) mcp->in_mb = MBX_1|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4965) mcp->tov = MBX_TOV_SECONDS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4966) mcp->flags = MBX_DMA_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4967) mcp->buf_size = ELS_CMD_MAP_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4968) rval = qla2x00_mailbox_command(vha, mcp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4970) if (rval != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4971) ql_dbg(ql_dbg_mbx, vha, 0x118d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4972) "Failed=%x (%x,%x).\n", rval, mcp->mb[0], mcp->mb[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4973) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4974) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x118c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4975) "Done %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4976) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4978) dma_free_coherent(&ha->pdev->dev, ELS_CMD_MAP_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4979) els_cmd_map, els_cmd_map_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4981) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4982) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4984) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4985) qla2x00_read_asic_temperature(scsi_qla_host_t *vha, uint16_t *temp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4986) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4987) int rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4988) mbx_cmd_t mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4989) mbx_cmd_t *mcp = &mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4991) if (!IS_FWI2_CAPABLE(vha->hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4992) return QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4994) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1159,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4995) "Entered %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4997) mcp->mb[0] = MBC_GET_RNID_PARAMS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4998) mcp->mb[1] = RNID_TYPE_ASIC_TEMP << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4999) mcp->out_mb = MBX_1|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5000) mcp->in_mb = MBX_1|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5001) mcp->tov = MBX_TOV_SECONDS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5002) mcp->flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5003) rval = qla2x00_mailbox_command(vha, mcp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5004) *temp = mcp->mb[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5006) if (rval != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5007) ql_dbg(ql_dbg_mbx, vha, 0x115a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5008) "Failed=%x mb[0]=%x,%x.\n", rval, mcp->mb[0], mcp->mb[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5009) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5010) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x115b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5011) "Done %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5012) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5014) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5015) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5017) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5018) qla2x00_read_sfp(scsi_qla_host_t *vha, dma_addr_t sfp_dma, uint8_t *sfp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5019) uint16_t dev, uint16_t off, uint16_t len, uint16_t opt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5020) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5021) int rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5022) mbx_cmd_t mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5023) mbx_cmd_t *mcp = &mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5024) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5026) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5027) "Entered %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5029) if (!IS_FWI2_CAPABLE(ha))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5030) return QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5032) if (len == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5033) opt |= BIT_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5035) mcp->mb[0] = MBC_READ_SFP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5036) mcp->mb[1] = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5037) mcp->mb[2] = MSW(LSD(sfp_dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5038) mcp->mb[3] = LSW(LSD(sfp_dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5039) mcp->mb[6] = MSW(MSD(sfp_dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5040) mcp->mb[7] = LSW(MSD(sfp_dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5041) mcp->mb[8] = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5042) mcp->mb[9] = off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5043) mcp->mb[10] = opt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5044) mcp->out_mb = MBX_10|MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5045) mcp->in_mb = MBX_1|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5046) mcp->tov = MBX_TOV_SECONDS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5047) mcp->flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5048) rval = qla2x00_mailbox_command(vha, mcp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5050) if (opt & BIT_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5051) *sfp = mcp->mb[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5053) if (rval != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5054) ql_dbg(ql_dbg_mbx, vha, 0x10e9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5055) "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5056) if (mcp->mb[0] == MBS_COMMAND_ERROR && mcp->mb[1] == 0x22) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5057) /* sfp is not there */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5058) rval = QLA_INTERFACE_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5059) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5060) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5061) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ea,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5062) "Done %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5063) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5065) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5066) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5068) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5069) qla2x00_write_sfp(scsi_qla_host_t *vha, dma_addr_t sfp_dma, uint8_t *sfp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5070) uint16_t dev, uint16_t off, uint16_t len, uint16_t opt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5071) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5072) int rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5073) mbx_cmd_t mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5074) mbx_cmd_t *mcp = &mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5075) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5077) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10eb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5078) "Entered %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5080) if (!IS_FWI2_CAPABLE(ha))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5081) return QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5083) if (len == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5084) opt |= BIT_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5086) if (opt & BIT_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5087) len = *sfp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5089) mcp->mb[0] = MBC_WRITE_SFP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5090) mcp->mb[1] = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5091) mcp->mb[2] = MSW(LSD(sfp_dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5092) mcp->mb[3] = LSW(LSD(sfp_dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5093) mcp->mb[6] = MSW(MSD(sfp_dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5094) mcp->mb[7] = LSW(MSD(sfp_dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5095) mcp->mb[8] = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5096) mcp->mb[9] = off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5097) mcp->mb[10] = opt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5098) mcp->out_mb = MBX_10|MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5099) mcp->in_mb = MBX_1|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5100) mcp->tov = MBX_TOV_SECONDS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5101) mcp->flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5102) rval = qla2x00_mailbox_command(vha, mcp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5104) if (rval != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5105) ql_dbg(ql_dbg_mbx, vha, 0x10ec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5106) "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5107) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5108) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ed,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5109) "Done %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5112) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5115) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5116) qla2x00_get_xgmac_stats(scsi_qla_host_t *vha, dma_addr_t stats_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5117) uint16_t size_in_bytes, uint16_t *actual_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5118) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5119) int rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5120) mbx_cmd_t mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5121) mbx_cmd_t *mcp = &mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5123) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ee,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5124) "Entered %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5126) if (!IS_CNA_CAPABLE(vha->hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5127) return QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5129) mcp->mb[0] = MBC_GET_XGMAC_STATS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5130) mcp->mb[2] = MSW(stats_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5131) mcp->mb[3] = LSW(stats_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5132) mcp->mb[6] = MSW(MSD(stats_dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5133) mcp->mb[7] = LSW(MSD(stats_dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5134) mcp->mb[8] = size_in_bytes >> 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5135) mcp->out_mb = MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5136) mcp->in_mb = MBX_2|MBX_1|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5137) mcp->tov = MBX_TOV_SECONDS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5138) mcp->flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5139) rval = qla2x00_mailbox_command(vha, mcp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5141) if (rval != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5142) ql_dbg(ql_dbg_mbx, vha, 0x10ef,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5143) "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5144) rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5145) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5146) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5147) "Done %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5150) *actual_size = mcp->mb[2] << 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5153) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5156) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5157) qla2x00_get_dcbx_params(scsi_qla_host_t *vha, dma_addr_t tlv_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5158) uint16_t size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5159) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5160) int rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5161) mbx_cmd_t mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5162) mbx_cmd_t *mcp = &mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5164) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5165) "Entered %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5167) if (!IS_CNA_CAPABLE(vha->hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5168) return QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5170) mcp->mb[0] = MBC_GET_DCBX_PARAMS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5171) mcp->mb[1] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5172) mcp->mb[2] = MSW(tlv_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5173) mcp->mb[3] = LSW(tlv_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5174) mcp->mb[6] = MSW(MSD(tlv_dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5175) mcp->mb[7] = LSW(MSD(tlv_dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5176) mcp->mb[8] = size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5177) mcp->out_mb = MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5178) mcp->in_mb = MBX_2|MBX_1|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5179) mcp->tov = MBX_TOV_SECONDS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5180) mcp->flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5181) rval = qla2x00_mailbox_command(vha, mcp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5183) if (rval != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5184) ql_dbg(ql_dbg_mbx, vha, 0x10f2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5185) "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5186) rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5187) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5188) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5189) "Done %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5192) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5195) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5196) qla2x00_read_ram_word(scsi_qla_host_t *vha, uint32_t risc_addr, uint32_t *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5197) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5198) int rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5199) mbx_cmd_t mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5200) mbx_cmd_t *mcp = &mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5202) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5203) "Entered %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5205) if (!IS_FWI2_CAPABLE(vha->hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5206) return QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5208) mcp->mb[0] = MBC_READ_RAM_EXTENDED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5209) mcp->mb[1] = LSW(risc_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5210) mcp->mb[8] = MSW(risc_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5211) mcp->out_mb = MBX_8|MBX_1|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5212) mcp->in_mb = MBX_3|MBX_2|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5213) mcp->tov = MBX_TOV_SECONDS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5214) mcp->flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5215) rval = qla2x00_mailbox_command(vha, mcp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5216) if (rval != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5217) ql_dbg(ql_dbg_mbx, vha, 0x10f5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5218) "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5219) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5220) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5221) "Done %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5222) *data = mcp->mb[3] << 16 | mcp->mb[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5225) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5228) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5229) qla2x00_loopback_test(scsi_qla_host_t *vha, struct msg_echo_lb *mreq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5230) uint16_t *mresp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5231) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5232) int rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5233) mbx_cmd_t mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5234) mbx_cmd_t *mcp = &mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5236) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5237) "Entered %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5239) memset(mcp->mb, 0 , sizeof(mcp->mb));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5240) mcp->mb[0] = MBC_DIAGNOSTIC_LOOP_BACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5241) mcp->mb[1] = mreq->options | BIT_6; // BIT_6 specifies 64 bit addressing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5243) /* transfer count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5244) mcp->mb[10] = LSW(mreq->transfer_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5245) mcp->mb[11] = MSW(mreq->transfer_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5247) /* send data address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5248) mcp->mb[14] = LSW(mreq->send_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5249) mcp->mb[15] = MSW(mreq->send_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5250) mcp->mb[20] = LSW(MSD(mreq->send_dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5251) mcp->mb[21] = MSW(MSD(mreq->send_dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5253) /* receive data address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5254) mcp->mb[16] = LSW(mreq->rcv_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5255) mcp->mb[17] = MSW(mreq->rcv_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5256) mcp->mb[6] = LSW(MSD(mreq->rcv_dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5257) mcp->mb[7] = MSW(MSD(mreq->rcv_dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5259) /* Iteration count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5260) mcp->mb[18] = LSW(mreq->iteration_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5261) mcp->mb[19] = MSW(mreq->iteration_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5263) mcp->out_mb = MBX_21|MBX_20|MBX_19|MBX_18|MBX_17|MBX_16|MBX_15|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5264) MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_7|MBX_6|MBX_1|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5265) if (IS_CNA_CAPABLE(vha->hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5266) mcp->out_mb |= MBX_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5267) mcp->in_mb = MBX_19|MBX_18|MBX_3|MBX_2|MBX_1|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5269) mcp->buf_size = mreq->transfer_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5270) mcp->tov = MBX_TOV_SECONDS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5271) mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5273) rval = qla2x00_mailbox_command(vha, mcp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5275) if (rval != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5276) ql_dbg(ql_dbg_mbx, vha, 0x10f8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5277) "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x mb[3]=%x mb[18]=%x "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5278) "mb[19]=%x.\n", rval, mcp->mb[0], mcp->mb[1], mcp->mb[2],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5279) mcp->mb[3], mcp->mb[18], mcp->mb[19]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5280) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5281) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5282) "Done %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5285) /* Copy mailbox information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5286) memcpy( mresp, mcp->mb, 64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5287) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5290) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5291) qla2x00_echo_test(scsi_qla_host_t *vha, struct msg_echo_lb *mreq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5292) uint16_t *mresp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5293) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5294) int rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5295) mbx_cmd_t mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5296) mbx_cmd_t *mcp = &mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5297) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5299) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10fa,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5300) "Entered %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5302) memset(mcp->mb, 0 , sizeof(mcp->mb));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5303) mcp->mb[0] = MBC_DIAGNOSTIC_ECHO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5304) /* BIT_6 specifies 64bit address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5305) mcp->mb[1] = mreq->options | BIT_15 | BIT_6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5306) if (IS_CNA_CAPABLE(ha)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5307) mcp->mb[2] = vha->fcoe_fcf_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5309) mcp->mb[16] = LSW(mreq->rcv_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5310) mcp->mb[17] = MSW(mreq->rcv_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5311) mcp->mb[6] = LSW(MSD(mreq->rcv_dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5312) mcp->mb[7] = MSW(MSD(mreq->rcv_dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5314) mcp->mb[10] = LSW(mreq->transfer_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5316) mcp->mb[14] = LSW(mreq->send_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5317) mcp->mb[15] = MSW(mreq->send_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5318) mcp->mb[20] = LSW(MSD(mreq->send_dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5319) mcp->mb[21] = MSW(MSD(mreq->send_dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5321) mcp->out_mb = MBX_21|MBX_20|MBX_17|MBX_16|MBX_15|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5322) MBX_14|MBX_10|MBX_7|MBX_6|MBX_1|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5323) if (IS_CNA_CAPABLE(ha))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5324) mcp->out_mb |= MBX_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5326) mcp->in_mb = MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5327) if (IS_CNA_CAPABLE(ha) || IS_QLA24XX_TYPE(ha) || IS_QLA25XX(ha) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5328) IS_QLA2031(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5329) mcp->in_mb |= MBX_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5330) if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5331) IS_QLA28XX(ha))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5332) mcp->in_mb |= MBX_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5334) mcp->tov = MBX_TOV_SECONDS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5335) mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5336) mcp->buf_size = mreq->transfer_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5338) rval = qla2x00_mailbox_command(vha, mcp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5340) if (rval != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5341) ql_dbg(ql_dbg_mbx, vha, 0x10fb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5342) "Failed=%x mb[0]=%x mb[1]=%x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5343) rval, mcp->mb[0], mcp->mb[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5344) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5345) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10fc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5346) "Done %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5349) /* Copy mailbox information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5350) memcpy(mresp, mcp->mb, 64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5351) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5354) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5355) qla84xx_reset_chip(scsi_qla_host_t *vha, uint16_t enable_diagnostic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5356) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5357) int rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5358) mbx_cmd_t mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5359) mbx_cmd_t *mcp = &mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5361) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10fd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5362) "Entered %s enable_diag=%d.\n", __func__, enable_diagnostic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5364) mcp->mb[0] = MBC_ISP84XX_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5365) mcp->mb[1] = enable_diagnostic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5366) mcp->out_mb = MBX_1|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5367) mcp->in_mb = MBX_1|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5368) mcp->tov = MBX_TOV_SECONDS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5369) mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5370) rval = qla2x00_mailbox_command(vha, mcp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5372) if (rval != QLA_SUCCESS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5373) ql_dbg(ql_dbg_mbx, vha, 0x10fe, "Failed=%x.\n", rval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5374) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5375) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5376) "Done %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5378) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5381) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5382) qla2x00_write_ram_word(scsi_qla_host_t *vha, uint32_t risc_addr, uint32_t data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5383) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5384) int rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5385) mbx_cmd_t mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5386) mbx_cmd_t *mcp = &mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5388) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5389) "Entered %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5391) if (!IS_FWI2_CAPABLE(vha->hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5392) return QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5394) mcp->mb[0] = MBC_WRITE_RAM_WORD_EXTENDED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5395) mcp->mb[1] = LSW(risc_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5396) mcp->mb[2] = LSW(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5397) mcp->mb[3] = MSW(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5398) mcp->mb[8] = MSW(risc_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5399) mcp->out_mb = MBX_8|MBX_3|MBX_2|MBX_1|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5400) mcp->in_mb = MBX_1|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5401) mcp->tov = MBX_TOV_SECONDS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5402) mcp->flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5403) rval = qla2x00_mailbox_command(vha, mcp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5404) if (rval != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5405) ql_dbg(ql_dbg_mbx, vha, 0x1101,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5406) "Failed=%x mb[0]=%x mb[1]=%x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5407) rval, mcp->mb[0], mcp->mb[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5408) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5409) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1102,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5410) "Done %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5413) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5416) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5417) qla81xx_write_mpi_register(scsi_qla_host_t *vha, uint16_t *mb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5418) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5419) int rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5420) uint32_t stat, timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5421) uint16_t mb0 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5422) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5423) struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5425) rval = QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5427) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1103,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5428) "Entered %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5430) clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5432) /* Write the MBC data to the registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5433) wrt_reg_word(®->mailbox0, MBC_WRITE_MPI_REGISTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5434) wrt_reg_word(®->mailbox1, mb[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5435) wrt_reg_word(®->mailbox2, mb[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5436) wrt_reg_word(®->mailbox3, mb[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5437) wrt_reg_word(®->mailbox4, mb[3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5439) wrt_reg_dword(®->hccr, HCCRX_SET_HOST_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5441) /* Poll for MBC interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5442) for (timer = 6000000; timer; timer--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5443) /* Check for pending interrupts. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5444) stat = rd_reg_dword(®->host_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5445) if (stat & HSRX_RISC_INT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5446) stat &= 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5448) if (stat == 0x1 || stat == 0x2 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5449) stat == 0x10 || stat == 0x11) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5450) set_bit(MBX_INTERRUPT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5451) &ha->mbx_cmd_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5452) mb0 = rd_reg_word(®->mailbox0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5453) wrt_reg_dword(®->hccr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5454) HCCRX_CLR_RISC_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5455) rd_reg_dword(®->hccr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5456) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5458) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5459) udelay(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5460) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5462) if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5463) rval = mb0 & MBS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5464) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5465) rval = QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5467) if (rval != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5468) ql_dbg(ql_dbg_mbx, vha, 0x1104,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5469) "Failed=%x mb[0]=%x.\n", rval, mb[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5470) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5471) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1105,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5472) "Done %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5473) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5475) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5476) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5478) /* Set the specified data rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5479) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5480) qla2x00_set_data_rate(scsi_qla_host_t *vha, uint16_t mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5481) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5482) int rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5483) mbx_cmd_t mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5484) mbx_cmd_t *mcp = &mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5485) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5486) uint16_t val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5488) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1106,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5489) "Entered %s speed:0x%x mode:0x%x.\n", __func__, ha->set_data_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5490) mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5492) if (!IS_FWI2_CAPABLE(ha))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5493) return QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5495) memset(mcp, 0, sizeof(*mcp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5496) switch (ha->set_data_rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5497) case PORT_SPEED_AUTO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5498) case PORT_SPEED_4GB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5499) case PORT_SPEED_8GB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5500) case PORT_SPEED_16GB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5501) case PORT_SPEED_32GB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5502) val = ha->set_data_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5503) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5504) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5505) ql_log(ql_log_warn, vha, 0x1199,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5506) "Unrecognized speed setting:%d. Setting Autoneg\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5507) ha->set_data_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5508) val = ha->set_data_rate = PORT_SPEED_AUTO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5509) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5510) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5512) mcp->mb[0] = MBC_DATA_RATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5513) mcp->mb[1] = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5514) mcp->mb[2] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5516) mcp->out_mb = MBX_2|MBX_1|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5517) mcp->in_mb = MBX_2|MBX_1|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5518) if (IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5519) mcp->in_mb |= MBX_4|MBX_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5520) mcp->tov = MBX_TOV_SECONDS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5521) mcp->flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5522) rval = qla2x00_mailbox_command(vha, mcp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5523) if (rval != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5524) ql_dbg(ql_dbg_mbx, vha, 0x1107,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5525) "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5526) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5527) if (mcp->mb[1] != 0x7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5528) ql_dbg(ql_dbg_mbx, vha, 0x1179,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5529) "Speed set:0x%x\n", mcp->mb[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5531) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1108,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5532) "Done %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5533) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5535) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5536) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5538) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5539) qla2x00_get_data_rate(scsi_qla_host_t *vha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5540) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5541) int rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5542) mbx_cmd_t mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5543) mbx_cmd_t *mcp = &mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5544) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5546) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1106,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5547) "Entered %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5549) if (!IS_FWI2_CAPABLE(ha))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5550) return QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5552) mcp->mb[0] = MBC_DATA_RATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5553) mcp->mb[1] = QLA_GET_DATA_RATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5554) mcp->out_mb = MBX_1|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5555) mcp->in_mb = MBX_2|MBX_1|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5556) if (IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5557) mcp->in_mb |= MBX_4|MBX_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5558) mcp->tov = MBX_TOV_SECONDS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5559) mcp->flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5560) rval = qla2x00_mailbox_command(vha, mcp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5561) if (rval != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5562) ql_dbg(ql_dbg_mbx, vha, 0x1107,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5563) "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5564) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5565) if (mcp->mb[1] != 0x7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5566) ha->link_data_rate = mcp->mb[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5568) if (IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5569) if (mcp->mb[4] & BIT_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5570) ql_log(ql_log_info, vha, 0x11a2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5571) "FEC=enabled (data rate).\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5572) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5574) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1108,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5575) "Done %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5576) if (mcp->mb[1] != 0x7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5577) ha->link_data_rate = mcp->mb[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5578) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5580) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5581) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5583) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5584) qla81xx_get_port_config(scsi_qla_host_t *vha, uint16_t *mb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5585) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5586) int rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5587) mbx_cmd_t mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5588) mbx_cmd_t *mcp = &mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5589) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5591) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1109,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5592) "Entered %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5594) if (!IS_QLA81XX(ha) && !IS_QLA83XX(ha) && !IS_QLA8044(ha) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5595) !IS_QLA27XX(ha) && !IS_QLA28XX(ha))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5596) return QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5597) mcp->mb[0] = MBC_GET_PORT_CONFIG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5598) mcp->out_mb = MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5599) mcp->in_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5600) mcp->tov = MBX_TOV_SECONDS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5601) mcp->flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5603) rval = qla2x00_mailbox_command(vha, mcp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5605) if (rval != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5606) ql_dbg(ql_dbg_mbx, vha, 0x110a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5607) "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5608) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5609) /* Copy all bits to preserve original value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5610) memcpy(mb, &mcp->mb[1], sizeof(uint16_t) * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5612) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x110b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5613) "Done %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5614) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5615) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5616) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5618) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5619) qla81xx_set_port_config(scsi_qla_host_t *vha, uint16_t *mb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5620) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5621) int rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5622) mbx_cmd_t mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5623) mbx_cmd_t *mcp = &mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5625) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x110c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5626) "Entered %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5628) mcp->mb[0] = MBC_SET_PORT_CONFIG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5629) /* Copy all bits to preserve original setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5630) memcpy(&mcp->mb[1], mb, sizeof(uint16_t) * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5631) mcp->out_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5632) mcp->in_mb = MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5633) mcp->tov = MBX_TOV_SECONDS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5634) mcp->flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5635) rval = qla2x00_mailbox_command(vha, mcp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5637) if (rval != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5638) ql_dbg(ql_dbg_mbx, vha, 0x110d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5639) "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5640) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5641) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x110e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5642) "Done %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5644) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5645) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5648) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5649) qla24xx_set_fcp_prio(scsi_qla_host_t *vha, uint16_t loop_id, uint16_t priority,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5650) uint16_t *mb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5651) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5652) int rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5653) mbx_cmd_t mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5654) mbx_cmd_t *mcp = &mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5655) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5657) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x110f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5658) "Entered %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5660) if (!IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5661) return QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5663) mcp->mb[0] = MBC_PORT_PARAMS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5664) mcp->mb[1] = loop_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5665) if (ha->flags.fcp_prio_enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5666) mcp->mb[2] = BIT_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5667) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5668) mcp->mb[2] = BIT_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5669) mcp->mb[4] = priority & 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5670) mcp->mb[9] = vha->vp_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5671) mcp->out_mb = MBX_9|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5672) mcp->in_mb = MBX_4|MBX_3|MBX_1|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5673) mcp->tov = MBX_TOV_SECONDS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5674) mcp->flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5675) rval = qla2x00_mailbox_command(vha, mcp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5676) if (mb != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5677) mb[0] = mcp->mb[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5678) mb[1] = mcp->mb[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5679) mb[3] = mcp->mb[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5680) mb[4] = mcp->mb[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5681) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5683) if (rval != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5684) ql_dbg(ql_dbg_mbx, vha, 0x10cd, "Failed=%x.\n", rval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5685) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5686) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10cc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5687) "Done %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5688) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5690) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5691) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5693) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5694) qla2x00_get_thermal_temp(scsi_qla_host_t *vha, uint16_t *temp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5695) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5696) int rval = QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5697) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5698) uint8_t byte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5700) if (!IS_FWI2_CAPABLE(ha) || IS_QLA24XX_TYPE(ha) || IS_QLA81XX(ha)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5701) ql_dbg(ql_dbg_mbx, vha, 0x1150,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5702) "Thermal not supported by this card.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5703) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5704) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5706) if (IS_QLA25XX(ha)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5707) if (ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5708) ha->pdev->subsystem_device == 0x0175) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5709) rval = qla2x00_read_sfp(vha, 0, &byte,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5710) 0x98, 0x1, 1, BIT_13|BIT_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5711) *temp = byte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5712) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5713) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5714) if (ha->pdev->subsystem_vendor == PCI_VENDOR_ID_HP &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5715) ha->pdev->subsystem_device == 0x338e) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5716) rval = qla2x00_read_sfp(vha, 0, &byte,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5717) 0x98, 0x1, 1, BIT_15|BIT_14|BIT_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5718) *temp = byte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5719) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5720) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5721) ql_dbg(ql_dbg_mbx, vha, 0x10c9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5722) "Thermal not supported by this card.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5723) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5724) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5726) if (IS_QLA82XX(ha)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5727) *temp = qla82xx_read_temperature(vha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5728) rval = QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5729) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5730) } else if (IS_QLA8044(ha)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5731) *temp = qla8044_read_temperature(vha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5732) rval = QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5733) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5734) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5736) rval = qla2x00_read_asic_temperature(vha, temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5737) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5738) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5740) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5741) qla82xx_mbx_intr_enable(scsi_qla_host_t *vha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5742) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5743) int rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5744) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5745) mbx_cmd_t mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5746) mbx_cmd_t *mcp = &mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5748) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1017,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5749) "Entered %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5751) if (!IS_FWI2_CAPABLE(ha))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5752) return QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5754) memset(mcp, 0, sizeof(mbx_cmd_t));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5755) mcp->mb[0] = MBC_TOGGLE_INTERRUPT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5756) mcp->mb[1] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5758) mcp->out_mb = MBX_1|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5759) mcp->in_mb = MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5760) mcp->tov = MBX_TOV_SECONDS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5761) mcp->flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5763) rval = qla2x00_mailbox_command(vha, mcp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5764) if (rval != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5765) ql_dbg(ql_dbg_mbx, vha, 0x1016,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5766) "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5767) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5768) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x100e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5769) "Done %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5770) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5772) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5773) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5775) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5776) qla82xx_mbx_intr_disable(scsi_qla_host_t *vha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5777) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5778) int rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5779) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5780) mbx_cmd_t mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5781) mbx_cmd_t *mcp = &mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5783) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x100d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5784) "Entered %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5786) if (!IS_P3P_TYPE(ha))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5787) return QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5789) memset(mcp, 0, sizeof(mbx_cmd_t));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5790) mcp->mb[0] = MBC_TOGGLE_INTERRUPT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5791) mcp->mb[1] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5793) mcp->out_mb = MBX_1|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5794) mcp->in_mb = MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5795) mcp->tov = MBX_TOV_SECONDS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5796) mcp->flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5798) rval = qla2x00_mailbox_command(vha, mcp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5799) if (rval != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5800) ql_dbg(ql_dbg_mbx, vha, 0x100c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5801) "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5802) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5803) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x100b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5804) "Done %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5805) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5807) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5808) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5810) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5811) qla82xx_md_get_template_size(scsi_qla_host_t *vha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5812) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5813) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5814) mbx_cmd_t mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5815) mbx_cmd_t *mcp = &mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5816) int rval = QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5818) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x111f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5819) "Entered %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5821) memset(mcp->mb, 0 , sizeof(mcp->mb));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5822) mcp->mb[0] = LSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5823) mcp->mb[1] = MSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5824) mcp->mb[2] = LSW(RQST_TMPLT_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5825) mcp->mb[3] = MSW(RQST_TMPLT_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5827) mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5828) mcp->in_mb = MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5829) MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5831) mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5832) mcp->tov = MBX_TOV_SECONDS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5833) rval = qla2x00_mailbox_command(vha, mcp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5835) /* Always copy back return mailbox values. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5836) if (rval != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5837) ql_dbg(ql_dbg_mbx, vha, 0x1120,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5838) "mailbox command FAILED=0x%x, subcode=%x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5839) (mcp->mb[1] << 16) | mcp->mb[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5840) (mcp->mb[3] << 16) | mcp->mb[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5841) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5842) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1121,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5843) "Done %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5844) ha->md_template_size = ((mcp->mb[3] << 16) | mcp->mb[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5845) if (!ha->md_template_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5846) ql_dbg(ql_dbg_mbx, vha, 0x1122,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5847) "Null template size obtained.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5848) rval = QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5849) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5850) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5851) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5852) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5854) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5855) qla82xx_md_get_template(scsi_qla_host_t *vha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5856) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5857) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5858) mbx_cmd_t mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5859) mbx_cmd_t *mcp = &mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5860) int rval = QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5862) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1123,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5863) "Entered %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5865) ha->md_tmplt_hdr = dma_alloc_coherent(&ha->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5866) ha->md_template_size, &ha->md_tmplt_hdr_dma, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5867) if (!ha->md_tmplt_hdr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5868) ql_log(ql_log_warn, vha, 0x1124,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5869) "Unable to allocate memory for Minidump template.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5870) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5871) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5873) memset(mcp->mb, 0 , sizeof(mcp->mb));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5874) mcp->mb[0] = LSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5875) mcp->mb[1] = MSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5876) mcp->mb[2] = LSW(RQST_TMPLT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5877) mcp->mb[3] = MSW(RQST_TMPLT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5878) mcp->mb[4] = LSW(LSD(ha->md_tmplt_hdr_dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5879) mcp->mb[5] = MSW(LSD(ha->md_tmplt_hdr_dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5880) mcp->mb[6] = LSW(MSD(ha->md_tmplt_hdr_dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5881) mcp->mb[7] = MSW(MSD(ha->md_tmplt_hdr_dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5882) mcp->mb[8] = LSW(ha->md_template_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5883) mcp->mb[9] = MSW(ha->md_template_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5885) mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5886) mcp->tov = MBX_TOV_SECONDS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5887) mcp->out_mb = MBX_11|MBX_10|MBX_9|MBX_8|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5888) MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5889) mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5890) rval = qla2x00_mailbox_command(vha, mcp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5892) if (rval != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5893) ql_dbg(ql_dbg_mbx, vha, 0x1125,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5894) "mailbox command FAILED=0x%x, subcode=%x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5895) ((mcp->mb[1] << 16) | mcp->mb[0]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5896) ((mcp->mb[3] << 16) | mcp->mb[2]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5897) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5898) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1126,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5899) "Done %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5900) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5901) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5903) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5904) qla8044_md_get_template(scsi_qla_host_t *vha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5905) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5906) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5907) mbx_cmd_t mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5908) mbx_cmd_t *mcp = &mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5909) int rval = QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5910) int offset = 0, size = MINIDUMP_SIZE_36K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5912) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0xb11f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5913) "Entered %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5915) ha->md_tmplt_hdr = dma_alloc_coherent(&ha->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5916) ha->md_template_size, &ha->md_tmplt_hdr_dma, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5917) if (!ha->md_tmplt_hdr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5918) ql_log(ql_log_warn, vha, 0xb11b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5919) "Unable to allocate memory for Minidump template.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5920) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5921) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5923) memset(mcp->mb, 0 , sizeof(mcp->mb));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5924) while (offset < ha->md_template_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5925) mcp->mb[0] = LSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5926) mcp->mb[1] = MSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5927) mcp->mb[2] = LSW(RQST_TMPLT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5928) mcp->mb[3] = MSW(RQST_TMPLT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5929) mcp->mb[4] = LSW(LSD(ha->md_tmplt_hdr_dma + offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5930) mcp->mb[5] = MSW(LSD(ha->md_tmplt_hdr_dma + offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5931) mcp->mb[6] = LSW(MSD(ha->md_tmplt_hdr_dma + offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5932) mcp->mb[7] = MSW(MSD(ha->md_tmplt_hdr_dma + offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5933) mcp->mb[8] = LSW(size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5934) mcp->mb[9] = MSW(size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5935) mcp->mb[10] = offset & 0x0000FFFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5936) mcp->mb[11] = offset & 0xFFFF0000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5937) mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5938) mcp->tov = MBX_TOV_SECONDS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5939) mcp->out_mb = MBX_11|MBX_10|MBX_9|MBX_8|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5940) MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5941) mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5942) rval = qla2x00_mailbox_command(vha, mcp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5944) if (rval != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5945) ql_dbg(ql_dbg_mbx, vha, 0xb11c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5946) "mailbox command FAILED=0x%x, subcode=%x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5947) ((mcp->mb[1] << 16) | mcp->mb[0]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5948) ((mcp->mb[3] << 16) | mcp->mb[2]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5949) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5950) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5951) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0xb11d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5952) "Done %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5953) offset = offset + size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5954) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5955) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5956) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5958) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5959) qla81xx_set_led_config(scsi_qla_host_t *vha, uint16_t *led_cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5960) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5961) int rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5962) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5963) mbx_cmd_t mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5964) mbx_cmd_t *mcp = &mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5966) if (!IS_QLA81XX(ha) && !IS_QLA8031(ha))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5967) return QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5969) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1133,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5970) "Entered %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5972) memset(mcp, 0, sizeof(mbx_cmd_t));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5973) mcp->mb[0] = MBC_SET_LED_CONFIG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5974) mcp->mb[1] = led_cfg[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5975) mcp->mb[2] = led_cfg[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5976) if (IS_QLA8031(ha)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5977) mcp->mb[3] = led_cfg[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5978) mcp->mb[4] = led_cfg[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5979) mcp->mb[5] = led_cfg[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5980) mcp->mb[6] = led_cfg[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5981) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5983) mcp->out_mb = MBX_2|MBX_1|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5984) if (IS_QLA8031(ha))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5985) mcp->out_mb |= MBX_6|MBX_5|MBX_4|MBX_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5986) mcp->in_mb = MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5987) mcp->tov = MBX_TOV_SECONDS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5988) mcp->flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5990) rval = qla2x00_mailbox_command(vha, mcp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5991) if (rval != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5992) ql_dbg(ql_dbg_mbx, vha, 0x1134,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5993) "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5994) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5995) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1135,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5996) "Done %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5997) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5999) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6000) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6002) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6003) qla81xx_get_led_config(scsi_qla_host_t *vha, uint16_t *led_cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6004) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6005) int rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6006) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6007) mbx_cmd_t mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6008) mbx_cmd_t *mcp = &mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6010) if (!IS_QLA81XX(ha) && !IS_QLA8031(ha))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6011) return QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6013) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1136,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6014) "Entered %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6016) memset(mcp, 0, sizeof(mbx_cmd_t));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6017) mcp->mb[0] = MBC_GET_LED_CONFIG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6019) mcp->out_mb = MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6020) mcp->in_mb = MBX_2|MBX_1|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6021) if (IS_QLA8031(ha))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6022) mcp->in_mb |= MBX_6|MBX_5|MBX_4|MBX_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6023) mcp->tov = MBX_TOV_SECONDS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6024) mcp->flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6026) rval = qla2x00_mailbox_command(vha, mcp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6027) if (rval != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6028) ql_dbg(ql_dbg_mbx, vha, 0x1137,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6029) "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6030) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6031) led_cfg[0] = mcp->mb[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6032) led_cfg[1] = mcp->mb[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6033) if (IS_QLA8031(ha)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6034) led_cfg[2] = mcp->mb[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6035) led_cfg[3] = mcp->mb[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6036) led_cfg[4] = mcp->mb[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6037) led_cfg[5] = mcp->mb[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6038) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6039) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1138,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6040) "Done %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6041) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6043) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6044) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6046) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6047) qla82xx_mbx_beacon_ctl(scsi_qla_host_t *vha, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6048) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6049) int rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6050) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6051) mbx_cmd_t mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6052) mbx_cmd_t *mcp = &mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6054) if (!IS_P3P_TYPE(ha))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6055) return QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6057) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1127,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6058) "Entered %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6060) memset(mcp, 0, sizeof(mbx_cmd_t));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6061) mcp->mb[0] = MBC_SET_LED_CONFIG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6062) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6063) mcp->mb[7] = 0xE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6064) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6065) mcp->mb[7] = 0xD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6067) mcp->out_mb = MBX_7|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6068) mcp->in_mb = MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6069) mcp->tov = MBX_TOV_SECONDS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6070) mcp->flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6072) rval = qla2x00_mailbox_command(vha, mcp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6073) if (rval != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6074) ql_dbg(ql_dbg_mbx, vha, 0x1128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6075) "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6076) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6077) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1129,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6078) "Done %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6079) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6081) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6082) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6084) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6085) qla83xx_wr_reg(scsi_qla_host_t *vha, uint32_t reg, uint32_t data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6086) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6087) int rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6088) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6089) mbx_cmd_t mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6090) mbx_cmd_t *mcp = &mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6092) if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha) && !IS_QLA28XX(ha))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6093) return QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6095) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1130,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6096) "Entered %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6098) mcp->mb[0] = MBC_WRITE_REMOTE_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6099) mcp->mb[1] = LSW(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6100) mcp->mb[2] = MSW(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6101) mcp->mb[3] = LSW(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6102) mcp->mb[4] = MSW(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6103) mcp->out_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6105) mcp->in_mb = MBX_1|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6106) mcp->tov = MBX_TOV_SECONDS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6107) mcp->flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6108) rval = qla2x00_mailbox_command(vha, mcp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6110) if (rval != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6111) ql_dbg(ql_dbg_mbx, vha, 0x1131,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6112) "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6113) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6114) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1132,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6115) "Done %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6118) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6121) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6122) qla2x00_port_logout(scsi_qla_host_t *vha, struct fc_port *fcport)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6124) int rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6125) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6126) mbx_cmd_t mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6127) mbx_cmd_t *mcp = &mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6129) if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6130) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x113b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6131) "Implicit LOGO Unsupported.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6132) return QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6136) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x113c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6137) "Entering %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6139) /* Perform Implicit LOGO. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6140) mcp->mb[0] = MBC_PORT_LOGOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6141) mcp->mb[1] = fcport->loop_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6142) mcp->mb[10] = BIT_15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6143) mcp->out_mb = MBX_10|MBX_1|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6144) mcp->in_mb = MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6145) mcp->tov = MBX_TOV_SECONDS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6146) mcp->flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6147) rval = qla2x00_mailbox_command(vha, mcp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6148) if (rval != QLA_SUCCESS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6149) ql_dbg(ql_dbg_mbx, vha, 0x113d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6150) "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6151) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6152) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x113e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6153) "Done %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6155) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6158) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6159) qla83xx_rd_reg(scsi_qla_host_t *vha, uint32_t reg, uint32_t *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6160) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6161) int rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6162) mbx_cmd_t mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6163) mbx_cmd_t *mcp = &mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6164) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6165) unsigned long retry_max_time = jiffies + (2 * HZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6167) if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha) && !IS_QLA28XX(ha))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6168) return QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6170) ql_dbg(ql_dbg_mbx, vha, 0x114b, "Entered %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6172) retry_rd_reg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6173) mcp->mb[0] = MBC_READ_REMOTE_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6174) mcp->mb[1] = LSW(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6175) mcp->mb[2] = MSW(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6176) mcp->out_mb = MBX_2|MBX_1|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6177) mcp->in_mb = MBX_4|MBX_3|MBX_1|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6178) mcp->tov = MBX_TOV_SECONDS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6179) mcp->flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6180) rval = qla2x00_mailbox_command(vha, mcp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6182) if (rval != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6183) ql_dbg(ql_dbg_mbx, vha, 0x114c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6184) "Failed=%x mb[0]=%x mb[1]=%x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6185) rval, mcp->mb[0], mcp->mb[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6186) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6187) *data = (mcp->mb[3] | (mcp->mb[4] << 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6188) if (*data == QLA8XXX_BAD_VALUE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6189) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6190) * During soft-reset CAMRAM register reads might
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6191) * return 0xbad0bad0. So retry for MAX of 2 sec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6192) * while reading camram registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6193) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6194) if (time_after(jiffies, retry_max_time)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6195) ql_dbg(ql_dbg_mbx, vha, 0x1141,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6196) "Failure to read CAMRAM register. "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6197) "data=0x%x.\n", *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6198) return QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6200) msleep(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6201) goto retry_rd_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6203) ql_dbg(ql_dbg_mbx, vha, 0x1142, "Done %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6206) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6209) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6210) qla83xx_restart_nic_firmware(scsi_qla_host_t *vha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6211) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6212) int rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6213) mbx_cmd_t mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6214) mbx_cmd_t *mcp = &mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6215) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6217) if (!IS_QLA83XX(ha))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6218) return QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6220) ql_dbg(ql_dbg_mbx, vha, 0x1143, "Entered %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6222) mcp->mb[0] = MBC_RESTART_NIC_FIRMWARE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6223) mcp->out_mb = MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6224) mcp->in_mb = MBX_1|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6225) mcp->tov = MBX_TOV_SECONDS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6226) mcp->flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6227) rval = qla2x00_mailbox_command(vha, mcp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6229) if (rval != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6230) ql_dbg(ql_dbg_mbx, vha, 0x1144,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6231) "Failed=%x mb[0]=%x mb[1]=%x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6232) rval, mcp->mb[0], mcp->mb[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6233) qla2xxx_dump_fw(vha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6234) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6235) ql_dbg(ql_dbg_mbx, vha, 0x1145, "Done %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6238) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6241) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6242) qla83xx_access_control(scsi_qla_host_t *vha, uint16_t options,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6243) uint32_t start_addr, uint32_t end_addr, uint16_t *sector_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6244) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6245) int rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6246) mbx_cmd_t mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6247) mbx_cmd_t *mcp = &mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6248) uint8_t subcode = (uint8_t)options;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6249) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6251) if (!IS_QLA8031(ha))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6252) return QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6254) ql_dbg(ql_dbg_mbx, vha, 0x1146, "Entered %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6256) mcp->mb[0] = MBC_SET_ACCESS_CONTROL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6257) mcp->mb[1] = options;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6258) mcp->out_mb = MBX_1|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6259) if (subcode & BIT_2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6260) mcp->mb[2] = LSW(start_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6261) mcp->mb[3] = MSW(start_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6262) mcp->mb[4] = LSW(end_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6263) mcp->mb[5] = MSW(end_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6264) mcp->out_mb |= MBX_5|MBX_4|MBX_3|MBX_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6266) mcp->in_mb = MBX_2|MBX_1|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6267) if (!(subcode & (BIT_2 | BIT_5)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6268) mcp->in_mb |= MBX_4|MBX_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6269) mcp->tov = MBX_TOV_SECONDS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6270) mcp->flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6271) rval = qla2x00_mailbox_command(vha, mcp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6273) if (rval != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6274) ql_dbg(ql_dbg_mbx, vha, 0x1147,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6275) "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x mb[3]=%x mb[4]=%x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6276) rval, mcp->mb[0], mcp->mb[1], mcp->mb[2], mcp->mb[3],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6277) mcp->mb[4]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6278) qla2xxx_dump_fw(vha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6279) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6280) if (subcode & BIT_5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6281) *sector_size = mcp->mb[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6282) else if (subcode & (BIT_6 | BIT_7)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6283) ql_dbg(ql_dbg_mbx, vha, 0x1148,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6284) "Driver-lock id=%x%x", mcp->mb[4], mcp->mb[3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6285) } else if (subcode & (BIT_3 | BIT_4)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6286) ql_dbg(ql_dbg_mbx, vha, 0x1149,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6287) "Flash-lock id=%x%x", mcp->mb[4], mcp->mb[3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6289) ql_dbg(ql_dbg_mbx, vha, 0x114a, "Done %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6292) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6295) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6296) qla2x00_dump_mctp_data(scsi_qla_host_t *vha, dma_addr_t req_dma, uint32_t addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6297) uint32_t size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6298) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6299) int rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6300) mbx_cmd_t mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6301) mbx_cmd_t *mcp = &mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6303) if (!IS_MCTP_CAPABLE(vha->hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6304) return QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6306) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x114f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6307) "Entered %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6309) mcp->mb[0] = MBC_DUMP_RISC_RAM_EXTENDED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6310) mcp->mb[1] = LSW(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6311) mcp->mb[2] = MSW(req_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6312) mcp->mb[3] = LSW(req_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6313) mcp->mb[4] = MSW(size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6314) mcp->mb[5] = LSW(size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6315) mcp->mb[6] = MSW(MSD(req_dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6316) mcp->mb[7] = LSW(MSD(req_dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6317) mcp->mb[8] = MSW(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6318) /* Setting RAM ID to valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6319) /* For MCTP RAM ID is 0x40 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6320) mcp->mb[10] = BIT_7 | 0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6322) mcp->out_mb |= MBX_10|MBX_8|MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6323) MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6325) mcp->in_mb = MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6326) mcp->tov = MBX_TOV_SECONDS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6327) mcp->flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6328) rval = qla2x00_mailbox_command(vha, mcp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6330) if (rval != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6331) ql_dbg(ql_dbg_mbx, vha, 0x114e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6332) "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6333) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6334) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x114d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6335) "Done %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6338) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6341) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6342) qla26xx_dport_diagnostics(scsi_qla_host_t *vha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6343) void *dd_buf, uint size, uint options)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6344) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6345) int rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6346) mbx_cmd_t mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6347) mbx_cmd_t *mcp = &mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6348) dma_addr_t dd_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6350) if (!IS_QLA83XX(vha->hw) && !IS_QLA27XX(vha->hw) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6351) !IS_QLA28XX(vha->hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6352) return QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6354) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x119f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6355) "Entered %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6357) dd_dma = dma_map_single(&vha->hw->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6358) dd_buf, size, DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6359) if (dma_mapping_error(&vha->hw->pdev->dev, dd_dma)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6360) ql_log(ql_log_warn, vha, 0x1194, "Failed to map dma buffer.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6361) return QLA_MEMORY_ALLOC_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6362) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6364) memset(dd_buf, 0, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6366) mcp->mb[0] = MBC_DPORT_DIAGNOSTICS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6367) mcp->mb[1] = options;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6368) mcp->mb[2] = MSW(LSD(dd_dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6369) mcp->mb[3] = LSW(LSD(dd_dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6370) mcp->mb[6] = MSW(MSD(dd_dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6371) mcp->mb[7] = LSW(MSD(dd_dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6372) mcp->mb[8] = size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6373) mcp->out_mb = MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6374) mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6375) mcp->buf_size = size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6376) mcp->flags = MBX_DMA_IN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6377) mcp->tov = MBX_TOV_SECONDS * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6378) rval = qla2x00_mailbox_command(vha, mcp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6380) if (rval != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6381) ql_dbg(ql_dbg_mbx, vha, 0x1195, "Failed=%x.\n", rval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6382) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6383) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1196,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6384) "Done %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6387) dma_unmap_single(&vha->hw->pdev->dev, dd_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6388) size, DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6390) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6393) static void qla2x00_async_mb_sp_done(srb_t *sp, int res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6394) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6395) sp->u.iocb_cmd.u.mbx.rc = res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6397) complete(&sp->u.iocb_cmd.u.mbx.comp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6398) /* don't free sp here. Let the caller do the free */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6401) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6402) * This mailbox uses the iocb interface to send MB command.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6403) * This allows non-critial (non chip setup) command to go
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6404) * out in parrallel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6405) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6406) int qla24xx_send_mb_cmd(struct scsi_qla_host *vha, mbx_cmd_t *mcp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6407) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6408) int rval = QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6409) srb_t *sp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6410) struct srb_iocb *c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6412) if (!vha->hw->flags.fw_started)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6413) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6415) sp = qla2x00_get_sp(vha, NULL, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6416) if (!sp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6417) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6419) sp->type = SRB_MB_IOCB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6420) sp->name = mb_to_str(mcp->mb[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6422) c = &sp->u.iocb_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6423) c->timeout = qla2x00_async_iocb_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6424) init_completion(&c->u.mbx.comp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6426) qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6428) memcpy(sp->u.iocb_cmd.u.mbx.out_mb, mcp->mb, SIZEOF_IOCB_MB_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6430) sp->done = qla2x00_async_mb_sp_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6432) rval = qla2x00_start_sp(sp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6433) if (rval != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6434) ql_dbg(ql_dbg_mbx, vha, 0x1018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6435) "%s: %s Failed submission. %x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6436) __func__, sp->name, rval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6437) goto done_free_sp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6440) ql_dbg(ql_dbg_mbx, vha, 0x113f, "MB:%s hndl %x submitted\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6441) sp->name, sp->handle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6443) wait_for_completion(&c->u.mbx.comp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6444) memcpy(mcp->mb, sp->u.iocb_cmd.u.mbx.in_mb, SIZEOF_IOCB_MB_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6446) rval = c->u.mbx.rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6447) switch (rval) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6448) case QLA_FUNCTION_TIMEOUT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6449) ql_dbg(ql_dbg_mbx, vha, 0x1140, "%s: %s Timeout. %x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6450) __func__, sp->name, rval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6451) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6452) case QLA_SUCCESS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6453) ql_dbg(ql_dbg_mbx, vha, 0x119d, "%s: %s done.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6454) __func__, sp->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6455) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6456) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6457) ql_dbg(ql_dbg_mbx, vha, 0x119e, "%s: %s Failed. %x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6458) __func__, sp->name, rval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6459) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6460) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6462) done_free_sp:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6463) sp->free(sp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6464) done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6465) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6466) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6468) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6469) * qla24xx_gpdb_wait
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6470) * NOTE: Do not call this routine from DPC thread
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6471) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6472) int qla24xx_gpdb_wait(struct scsi_qla_host *vha, fc_port_t *fcport, u8 opt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6473) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6474) int rval = QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6475) dma_addr_t pd_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6476) struct port_database_24xx *pd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6477) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6478) mbx_cmd_t mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6480) if (!vha->hw->flags.fw_started)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6481) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6483) pd = dma_pool_zalloc(ha->s_dma_pool, GFP_KERNEL, &pd_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6484) if (pd == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6485) ql_log(ql_log_warn, vha, 0xd047,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6486) "Failed to allocate port database structure.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6487) goto done_free_sp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6488) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6490) memset(&mc, 0, sizeof(mc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6491) mc.mb[0] = MBC_GET_PORT_DATABASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6492) mc.mb[1] = fcport->loop_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6493) mc.mb[2] = MSW(pd_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6494) mc.mb[3] = LSW(pd_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6495) mc.mb[6] = MSW(MSD(pd_dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6496) mc.mb[7] = LSW(MSD(pd_dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6497) mc.mb[9] = vha->vp_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6498) mc.mb[10] = opt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6500) rval = qla24xx_send_mb_cmd(vha, &mc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6501) if (rval != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6502) ql_dbg(ql_dbg_mbx, vha, 0x1193,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6503) "%s: %8phC fail\n", __func__, fcport->port_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6504) goto done_free_sp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6505) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6507) rval = __qla24xx_parse_gpdb(vha, fcport, pd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6509) ql_dbg(ql_dbg_mbx, vha, 0x1197, "%s: %8phC done\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6510) __func__, fcport->port_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6512) done_free_sp:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6513) if (pd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6514) dma_pool_free(ha->s_dma_pool, pd, pd_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6515) done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6516) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6517) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6519) int __qla24xx_parse_gpdb(struct scsi_qla_host *vha, fc_port_t *fcport,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6520) struct port_database_24xx *pd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6521) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6522) int rval = QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6523) uint64_t zero = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6524) u8 current_login_state, last_login_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6526) if (NVME_TARGET(vha->hw, fcport)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6527) current_login_state = pd->current_login_state >> 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6528) last_login_state = pd->last_login_state >> 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6529) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6530) current_login_state = pd->current_login_state & 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6531) last_login_state = pd->last_login_state & 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6532) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6534) /* Check for logged in state. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6535) if (current_login_state != PDS_PRLI_COMPLETE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6536) ql_dbg(ql_dbg_mbx, vha, 0x119a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6537) "Unable to verify login-state (%x/%x) for loop_id %x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6538) current_login_state, last_login_state, fcport->loop_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6539) rval = QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6540) goto gpd_error_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6541) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6543) if (fcport->loop_id == FC_NO_LOOP_ID ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6544) (memcmp(fcport->port_name, (uint8_t *)&zero, 8) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6545) memcmp(fcport->port_name, pd->port_name, 8))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6546) /* We lost the device mid way. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6547) rval = QLA_NOT_LOGGED_IN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6548) goto gpd_error_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6549) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6551) /* Names are little-endian. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6552) memcpy(fcport->node_name, pd->node_name, WWN_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6553) memcpy(fcport->port_name, pd->port_name, WWN_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6555) /* Get port_id of device. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6556) fcport->d_id.b.domain = pd->port_id[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6557) fcport->d_id.b.area = pd->port_id[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6558) fcport->d_id.b.al_pa = pd->port_id[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6559) fcport->d_id.b.rsvd_1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6561) if (NVME_TARGET(vha->hw, fcport)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6562) fcport->port_type = FCT_NVME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6563) if ((pd->prli_svc_param_word_3[0] & BIT_5) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6564) fcport->port_type |= FCT_NVME_INITIATOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6565) if ((pd->prli_svc_param_word_3[0] & BIT_4) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6566) fcport->port_type |= FCT_NVME_TARGET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6567) if ((pd->prli_svc_param_word_3[0] & BIT_3) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6568) fcport->port_type |= FCT_NVME_DISCOVERY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6569) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6570) /* If not target must be initiator or unknown type. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6571) if ((pd->prli_svc_param_word_3[0] & BIT_4) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6572) fcport->port_type = FCT_INITIATOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6573) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6574) fcport->port_type = FCT_TARGET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6575) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6576) /* Passback COS information. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6577) fcport->supported_classes = (pd->flags & PDF_CLASS_2) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6578) FC_COS_CLASS2 : FC_COS_CLASS3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6580) if (pd->prli_svc_param_word_3[0] & BIT_7) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6581) fcport->flags |= FCF_CONF_COMP_SUPPORTED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6582) fcport->conf_compl_supported = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6583) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6585) gpd_error_out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6586) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6587) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6589) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6590) * qla24xx_gidlist__wait
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6591) * NOTE: don't call this routine from DPC thread.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6592) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6593) int qla24xx_gidlist_wait(struct scsi_qla_host *vha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6594) void *id_list, dma_addr_t id_list_dma, uint16_t *entries)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6595) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6596) int rval = QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6597) mbx_cmd_t mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6599) if (!vha->hw->flags.fw_started)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6600) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6602) memset(&mc, 0, sizeof(mc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6603) mc.mb[0] = MBC_GET_ID_LIST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6604) mc.mb[2] = MSW(id_list_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6605) mc.mb[3] = LSW(id_list_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6606) mc.mb[6] = MSW(MSD(id_list_dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6607) mc.mb[7] = LSW(MSD(id_list_dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6608) mc.mb[8] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6609) mc.mb[9] = vha->vp_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6611) rval = qla24xx_send_mb_cmd(vha, &mc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6612) if (rval != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6613) ql_dbg(ql_dbg_mbx, vha, 0x119b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6614) "%s: fail\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6615) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6616) *entries = mc.mb[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6617) ql_dbg(ql_dbg_mbx, vha, 0x119c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6618) "%s: done\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6619) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6620) done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6621) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6622) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6624) int qla27xx_set_zio_threshold(scsi_qla_host_t *vha, uint16_t value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6625) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6626) int rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6627) mbx_cmd_t mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6628) mbx_cmd_t *mcp = &mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6630) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6631) "Entered %s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6633) memset(mcp->mb, 0 , sizeof(mcp->mb));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6634) mcp->mb[0] = MBC_GET_SET_ZIO_THRESHOLD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6635) mcp->mb[1] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6636) mcp->mb[2] = value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6637) mcp->out_mb = MBX_2 | MBX_1 | MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6638) mcp->in_mb = MBX_2 | MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6639) mcp->tov = MBX_TOV_SECONDS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6640) mcp->flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6642) rval = qla2x00_mailbox_command(vha, mcp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6644) ql_dbg(ql_dbg_mbx, vha, 0x1201, "%s %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6645) (rval != QLA_SUCCESS) ? "Failed" : "Done", rval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6647) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6648) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6650) int qla27xx_get_zio_threshold(scsi_qla_host_t *vha, uint16_t *value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6651) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6652) int rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6653) mbx_cmd_t mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6654) mbx_cmd_t *mcp = &mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6656) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1203,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6657) "Entered %s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6659) memset(mcp->mb, 0, sizeof(mcp->mb));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6660) mcp->mb[0] = MBC_GET_SET_ZIO_THRESHOLD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6661) mcp->mb[1] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6662) mcp->out_mb = MBX_1 | MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6663) mcp->in_mb = MBX_2 | MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6664) mcp->tov = MBX_TOV_SECONDS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6665) mcp->flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6667) rval = qla2x00_mailbox_command(vha, mcp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6668) if (rval == QLA_SUCCESS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6669) *value = mc.mb[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6671) ql_dbg(ql_dbg_mbx, vha, 0x1205, "%s %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6672) (rval != QLA_SUCCESS) ? "Failed" : "Done", rval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6674) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6675) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6677) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6678) qla2x00_read_sfp_dev(struct scsi_qla_host *vha, char *buf, int count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6679) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6680) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6681) uint16_t iter, addr, offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6682) dma_addr_t phys_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6683) int rval, c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6684) u8 *sfp_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6686) memset(ha->sfp_data, 0, SFP_DEV_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6687) addr = 0xa0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6688) phys_addr = ha->sfp_data_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6689) sfp_data = ha->sfp_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6690) offset = c = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6692) for (iter = 0; iter < SFP_DEV_SIZE / SFP_BLOCK_SIZE; iter++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6693) if (iter == 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6694) /* Skip to next device address. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6695) addr = 0xa2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6696) offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6697) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6699) rval = qla2x00_read_sfp(vha, phys_addr, sfp_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6700) addr, offset, SFP_BLOCK_SIZE, BIT_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6701) if (rval != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6702) ql_log(ql_log_warn, vha, 0x706d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6703) "Unable to read SFP data (%x/%x/%x).\n", rval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6704) addr, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6706) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6707) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6709) if (buf && (c < count)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6710) u16 sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6712) if ((count - c) >= SFP_BLOCK_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6713) sz = SFP_BLOCK_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6714) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6715) sz = count - c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6717) memcpy(buf, sfp_data, sz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6718) buf += SFP_BLOCK_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6719) c += sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6720) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6721) phys_addr += SFP_BLOCK_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6722) sfp_data += SFP_BLOCK_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6723) offset += SFP_BLOCK_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6724) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6726) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6727) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6729) int qla24xx_res_count_wait(struct scsi_qla_host *vha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6730) uint16_t *out_mb, int out_mb_sz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6731) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6732) int rval = QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6733) mbx_cmd_t mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6735) if (!vha->hw->flags.fw_started)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6736) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6738) memset(&mc, 0, sizeof(mc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6739) mc.mb[0] = MBC_GET_RESOURCE_COUNTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6741) rval = qla24xx_send_mb_cmd(vha, &mc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6742) if (rval != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6743) ql_dbg(ql_dbg_mbx, vha, 0xffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6744) "%s: fail\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6745) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6746) if (out_mb_sz <= SIZEOF_IOCB_MB_REG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6747) memcpy(out_mb, mc.mb, out_mb_sz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6748) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6749) memcpy(out_mb, mc.mb, SIZEOF_IOCB_MB_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6751) ql_dbg(ql_dbg_mbx, vha, 0xffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6752) "%s: done\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6753) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6754) done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6755) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6756) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6758) int qla28xx_secure_flash_update(scsi_qla_host_t *vha, uint16_t opts,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6759) uint16_t region, uint32_t len, dma_addr_t sfub_dma_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6760) uint32_t sfub_len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6761) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6762) int rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6763) mbx_cmd_t mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6764) mbx_cmd_t *mcp = &mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6766) mcp->mb[0] = MBC_SECURE_FLASH_UPDATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6767) mcp->mb[1] = opts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6768) mcp->mb[2] = region;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6769) mcp->mb[3] = MSW(len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6770) mcp->mb[4] = LSW(len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6771) mcp->mb[5] = MSW(sfub_dma_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6772) mcp->mb[6] = LSW(sfub_dma_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6773) mcp->mb[7] = MSW(MSD(sfub_dma_addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6774) mcp->mb[8] = LSW(MSD(sfub_dma_addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6775) mcp->mb[9] = sfub_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6776) mcp->out_mb =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6777) MBX_9|MBX_8|MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6778) mcp->in_mb = MBX_2|MBX_1|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6779) mcp->tov = MBX_TOV_SECONDS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6780) mcp->flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6781) rval = qla2x00_mailbox_command(vha, mcp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6783) if (rval != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6784) ql_dbg(ql_dbg_mbx, vha, 0xffff, "%s(%ld): failed rval 0x%x, %x %x %x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6785) __func__, vha->host_no, rval, mcp->mb[0], mcp->mb[1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6786) mcp->mb[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6787) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6789) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6790) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6792) int qla2xxx_write_remote_register(scsi_qla_host_t *vha, uint32_t addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6793) uint32_t data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6794) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6795) int rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6796) mbx_cmd_t mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6797) mbx_cmd_t *mcp = &mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6799) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6800) "Entered %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6802) mcp->mb[0] = MBC_WRITE_REMOTE_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6803) mcp->mb[1] = LSW(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6804) mcp->mb[2] = MSW(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6805) mcp->mb[3] = LSW(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6806) mcp->mb[4] = MSW(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6807) mcp->out_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6808) mcp->in_mb = MBX_1|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6809) mcp->tov = MBX_TOV_SECONDS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6810) mcp->flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6811) rval = qla2x00_mailbox_command(vha, mcp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6813) if (rval != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6814) ql_dbg(ql_dbg_mbx, vha, 0x10e9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6815) "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6816) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6817) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ea,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6818) "Done %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6819) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6821) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6822) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6824) int qla2xxx_read_remote_register(scsi_qla_host_t *vha, uint32_t addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6825) uint32_t *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6826) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6827) int rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6828) mbx_cmd_t mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6829) mbx_cmd_t *mcp = &mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6831) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6832) "Entered %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6834) mcp->mb[0] = MBC_READ_REMOTE_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6835) mcp->mb[1] = LSW(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6836) mcp->mb[2] = MSW(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6837) mcp->out_mb = MBX_2|MBX_1|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6838) mcp->in_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6839) mcp->tov = MBX_TOV_SECONDS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6840) mcp->flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6841) rval = qla2x00_mailbox_command(vha, mcp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6843) *data = (uint32_t)((((uint32_t)mcp->mb[4]) << 16) | mcp->mb[3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6845) if (rval != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6846) ql_dbg(ql_dbg_mbx, vha, 0x10e9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6847) "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6848) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6849) ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ea,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6850) "Done %s.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6851) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6853) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6854) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6856) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6857) ql26xx_led_config(scsi_qla_host_t *vha, uint16_t options, uint16_t *led)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6858) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6859) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6860) mbx_cmd_t mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6861) mbx_cmd_t *mcp = &mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6862) int rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6864) if (!IS_QLA2031(ha) && !IS_QLA27XX(ha) && !IS_QLA28XX(ha))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6865) return QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6867) ql_dbg(ql_dbg_mbx, vha, 0x7070, "Entered %s (options=%x).\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6868) __func__, options);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6870) mcp->mb[0] = MBC_SET_GET_FC_LED_CONFIG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6871) mcp->mb[1] = options;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6872) mcp->out_mb = MBX_1|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6873) mcp->in_mb = MBX_1|MBX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6874) if (options & BIT_0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6875) if (options & BIT_1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6876) mcp->mb[2] = led[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6877) mcp->out_mb |= MBX_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6878) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6879) if (options & BIT_2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6880) mcp->mb[3] = led[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6881) mcp->out_mb |= MBX_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6882) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6883) if (options & BIT_3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6884) mcp->mb[4] = led[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6885) mcp->out_mb |= MBX_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6886) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6887) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6888) mcp->in_mb |= MBX_4|MBX_3|MBX_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6889) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6890) mcp->tov = MBX_TOV_SECONDS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6891) mcp->flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6892) rval = qla2x00_mailbox_command(vha, mcp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6893) if (rval) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6894) ql_dbg(ql_dbg_mbx, vha, 0x7071, "Failed %s %x (mb=%x,%x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6895) __func__, rval, mcp->mb[0], mcp->mb[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6896) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6897) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6899) if (options & BIT_0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6900) ha->beacon_blink_led = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6901) ql_dbg(ql_dbg_mbx, vha, 0x7072, "Done %s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6902) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6903) led[2] = mcp->mb[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6904) led[0] = mcp->mb[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6905) led[1] = mcp->mb[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6906) ql_dbg(ql_dbg_mbx, vha, 0x7073, "Done %s (led=%x,%x,%x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6907) __func__, led[0], led[1], led[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6908) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6910) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6911) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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