Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * QLogic Fibre Channel HBA Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Copyright (c)  2003-2014 QLogic Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include "qla_target.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * qla24xx_calc_iocbs() - Determine number of Command Type 3 and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * Continuation Type 1 IOCBs to allocate.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  * @vha: HA context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  * @dsds: number of data segment descriptors needed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  * Returns the number of IOCB entries needed to store @dsds.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) static inline uint16_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) qla24xx_calc_iocbs(scsi_qla_host_t *vha, uint16_t dsds)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 	uint16_t iocbs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 	iocbs = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 	if (dsds > 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 		iocbs += (dsds - 1) / 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 		if ((dsds - 1) % 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 			iocbs++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	return iocbs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32)  * qla2x00_debounce_register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33)  *      Debounce register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35)  * Input:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36)  *      port = register address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38)  * Returns:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39)  *      register value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) static __inline__ uint16_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) qla2x00_debounce_register(volatile __le16 __iomem *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	volatile uint16_t first;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	volatile uint16_t second;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 		first = rd_reg_word(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 		barrier();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 		cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 		second = rd_reg_word(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	} while (first != second);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	return (first);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) qla2x00_poll(struct rsp_que *rsp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	struct qla_hw_data *ha = rsp->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	if (IS_P3P_TYPE(ha))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 		qla82xx_poll(0, rsp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 		ha->isp_ops->intr_handler(0, rsp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) static inline uint8_t *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) host_to_fcp_swap(uint8_t *fcp, uint32_t bsize)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71)        uint32_t *ifcp = (uint32_t *) fcp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72)        uint32_t *ofcp = (uint32_t *) fcp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73)        uint32_t iter = bsize >> 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75)        for (; iter ; iter--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76)                *ofcp++ = swab32(*ifcp++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78)        return fcp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) host_to_adap(uint8_t *src, uint8_t *dst, uint32_t bsize)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	uint32_t *isrc = (uint32_t *) src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	__le32 *odest = (__le32 *) dst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	uint32_t iter = bsize >> 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	for ( ; iter--; isrc++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 		*odest++ = cpu_to_le32(*isrc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) qla2x00_clean_dsd_pool(struct qla_hw_data *ha, struct crc_context *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	struct dsd_dma *dsd, *tdsd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	/* clean up allocated prev pool */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	list_for_each_entry_safe(dsd, tdsd, &ctx->dsd_list, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 		dma_pool_free(ha->dl_dma_pool, dsd->dsd_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 		    dsd->dsd_list_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 		list_del(&dsd->list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 		kfree(dsd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	INIT_LIST_HEAD(&ctx->dsd_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) qla2x00_set_fcport_disc_state(fc_port_t *fcport, int state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	int old_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	uint8_t shiftbits, mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	/* This will have to change when the max no. of states > 16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	shiftbits = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	mask = (1 << shiftbits) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	fcport->disc_state = state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	while (1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 		old_val = atomic_read(&fcport->shadow_disc_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 		if (old_val == atomic_cmpxchg(&fcport->shadow_disc_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 		    old_val, (old_val << shiftbits) | state)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 			ql_dbg(ql_dbg_disc, fcport->vha, 0x2134,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 			    "FCPort %8phC disc_state transition: %s to %s - portid=%06x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 			    fcport->port_name, port_dstate_str[old_val & mask],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 			    port_dstate_str[state], fcport->d_id.b24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 			return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static inline int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) qla2x00_hba_err_chk_enabled(srb_t *sp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	 * Uncomment when corresponding SCSI changes are done.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	if (!sp->cmd->prot_chk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	switch (scsi_get_prot_op(GET_CMD_SP(sp))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	case SCSI_PROT_READ_STRIP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	case SCSI_PROT_WRITE_INSERT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 		if (ql2xenablehba_err_chk >= 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 			return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	case SCSI_PROT_READ_PASS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	case SCSI_PROT_WRITE_PASS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 		if (ql2xenablehba_err_chk >= 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 			return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	case SCSI_PROT_READ_INSERT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	case SCSI_PROT_WRITE_STRIP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static inline int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) qla2x00_reset_active(scsi_qla_host_t *vha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	scsi_qla_host_t *base_vha = pci_get_drvdata(vha->hw->pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	/* Test appropriate base-vha and vha flags. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	return test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	    test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	    test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	    test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	    test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static inline int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) qla2x00_chip_is_down(scsi_qla_host_t *vha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	return (qla2x00_reset_active(vha) || !vha->hw->flags.fw_started);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) static void qla2xxx_init_sp(srb_t *sp, scsi_qla_host_t *vha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 			    struct qla_qpair *qpair, fc_port_t *fcport)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	memset(sp, 0, sizeof(*sp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	sp->fcport = fcport;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	sp->iocbs = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	sp->vha = vha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	sp->qpair = qpair;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	sp->cmd_type = TYPE_SRB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	INIT_LIST_HEAD(&sp->elem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static inline srb_t *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) qla2xxx_get_qpair_sp(scsi_qla_host_t *vha, struct qla_qpair *qpair,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)     fc_port_t *fcport, gfp_t flag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	srb_t *sp = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	uint8_t bail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	QLA_QPAIR_MARK_BUSY(qpair, bail);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	if (unlikely(bail))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 		return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	sp = mempool_alloc(qpair->srb_mempool, flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	if (sp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		qla2xxx_init_sp(sp, vha, qpair, fcport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 		QLA_QPAIR_MARK_NOT_BUSY(qpair);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	return sp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) void qla2xxx_rel_done_warning(srb_t *sp, int res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) void qla2xxx_rel_free_warning(srb_t *sp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) qla2xxx_rel_qpair_sp(struct qla_qpair *qpair, srb_t *sp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	sp->qpair = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	sp->done = qla2xxx_rel_done_warning;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	sp->free = qla2xxx_rel_free_warning;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	mempool_free(sp, qpair->srb_mempool);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	QLA_QPAIR_MARK_NOT_BUSY(qpair);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static inline srb_t *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) qla2x00_get_sp(scsi_qla_host_t *vha, fc_port_t *fcport, gfp_t flag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	srb_t *sp = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	uint8_t bail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	struct qla_qpair *qpair;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	QLA_VHA_MARK_BUSY(vha, bail);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	if (unlikely(bail))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 		return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	qpair = vha->hw->base_qpair;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	sp = qla2xxx_get_qpair_sp(vha, qpair, fcport, flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	if (!sp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 		goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	sp->vha = vha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	if (!sp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 		QLA_VHA_MARK_NOT_BUSY(vha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	return sp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) qla2x00_rel_sp(srb_t *sp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	QLA_VHA_MARK_NOT_BUSY(sp->vha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	qla2xxx_rel_qpair_sp(sp->qpair, sp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) static inline int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) qla2x00_gid_list_size(struct qla_hw_data *ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	if (IS_QLAFX00(ha))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 		return sizeof(uint32_t) * 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 		return sizeof(struct gid_list_info) * ha->max_fibre_devices;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) qla2x00_handle_mbx_completion(struct qla_hw_data *ha, int status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	if (test_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	    (status & MBX_INTERRUPT) && ha->flags.mbox_int) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 		set_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 		clear_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 		complete(&ha->mbx_intr_comp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) qla2x00_set_retry_delay_timestamp(fc_port_t *fcport, uint16_t sts_qual)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	u8 scope;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	u16 qual;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define SQ_SCOPE_MASK		0xc000 /* SAM-6 rev5 5.3.2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define SQ_SCOPE_SHIFT		14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define SQ_QUAL_MASK		0x3fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define SQ_MAX_WAIT_SEC		60 /* Max I/O hold off time in seconds. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define SQ_MAX_WAIT_TIME	(SQ_MAX_WAIT_SEC * 10) /* in 100ms. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	if (!sts_qual) /* Common case. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	scope = (sts_qual & SQ_SCOPE_MASK) >> SQ_SCOPE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	/* Handle only scope 1 or 2, which is for I-T nexus. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	if (scope != 1 && scope != 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	/* Skip processing, if retry delay timer is already in effect. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	if (fcport->retry_delay_timestamp &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	    time_before(jiffies, fcport->retry_delay_timestamp))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	qual = sts_qual & SQ_QUAL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	if (qual < 1 || qual > 0x3fef)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	qual = min(qual, (u16)SQ_MAX_WAIT_TIME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	/* qual is expressed in 100ms increments. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	fcport->retry_delay_timestamp = jiffies + (qual * HZ / 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	ql_log(ql_log_warn, fcport->vha, 0x5101,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	       "%8phC: I/O throttling requested (status qualifier = %04xh), holding off I/Os for %ums.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	       fcport->port_name, sts_qual, qual * 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) static inline bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) qla_is_exch_offld_enabled(struct scsi_qla_host *vha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	if (qla_ini_mode_enabled(vha) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	    (vha->ql2xiniexchg > FW_DEF_EXCHANGES_CNT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 		return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	else if (qla_tgt_mode_enabled(vha) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	    (vha->ql2xexchoffld > FW_DEF_EXCHANGES_CNT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 		return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	else if (qla_dual_mode_enabled(vha) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	    ((vha->ql2xiniexchg + vha->ql2xexchoffld) > FW_DEF_EXCHANGES_CNT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 		return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 		return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) qla_cpu_update(struct qla_qpair *qpair, uint16_t cpuid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	qpair->cpuid = cpuid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	if (!list_empty(&qpair->hints_list)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 		struct qla_qpair_hint *h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 		list_for_each_entry(h, &qpair->hints_list, hint_elem)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 			h->cpuid = qpair->cpuid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) static inline struct qla_qpair_hint *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) qla_qpair_to_hint(struct qla_tgt *tgt, struct qla_qpair *qpair)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	struct qla_qpair_hint *h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	u16 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	for (i = 0; i < tgt->ha->max_qpairs + 1; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 		h = &tgt->qphints[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 		if (h->qpair == qpair)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 			return h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) qla_83xx_start_iocbs(struct qla_qpair *qpair)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	struct req_que *req = qpair->req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 	req->ring_index++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	if (req->ring_index == req->length) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 		req->ring_index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 		req->ring_ptr = req->ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	} else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 		req->ring_ptr++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	wrt_reg_dword(req->req_q_in, req->ring_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) static inline int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) qla2xxx_get_fc4_priority(struct scsi_qla_host *vha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	uint32_t data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	data =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	    ((uint8_t *)vha->hw->nvram)[NVRAM_DUAL_FCP_NVME_FLAG_OFFSET];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	return (data >> 6) & BIT_0 ? FC4_PRIORITY_FCP : FC4_PRIORITY_NVME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	RESOURCE_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 	RESOURCE_INI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) static inline int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) qla_get_iocbs(struct qla_qpair *qp, struct iocb_resource *iores)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	u16 iocbs_used, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 	struct qla_hw_data *ha = qp->vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 	if (!ql2xenforce_iocb_limit) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 		iores->res_type = RESOURCE_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 	if ((iores->iocb_cnt + qp->fwres.iocbs_used) < qp->fwres.iocbs_qp_limit) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 		qp->fwres.iocbs_used += iores->iocb_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 		/* no need to acquire qpair lock. It's just rough calculation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 		iocbs_used = ha->base_qpair->fwres.iocbs_used;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 		for (i = 0; i < ha->max_qpairs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 			if (ha->queue_pair_map[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 				iocbs_used += ha->queue_pair_map[i]->fwres.iocbs_used;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 		if ((iores->iocb_cnt + iocbs_used) < qp->fwres.iocbs_limit) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 			qp->fwres.iocbs_used += iores->iocb_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 			return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 		} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 			iores->res_type = RESOURCE_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 			return -ENOSPC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) qla_put_iocbs(struct qla_qpair *qp, struct iocb_resource *iores)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 	switch (iores->res_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 	case RESOURCE_NONE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 		if (qp->fwres.iocbs_used >= iores->iocb_cnt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 			qp->fwres.iocbs_used -= iores->iocb_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 		} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 			// should not happen
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 			qp->fwres.iocbs_used = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 	iores->res_type = RESOURCE_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) }