^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * QLogic Fibre Channel HBA Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (c) 2003-2014 QLogic Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #ifndef __QLA_FW_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define __QLA_FW_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/nvme.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/nvme-fc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include "qla_dsd.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define MBS_CHECKSUM_ERROR 0x4010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define MBS_INVALID_PRODUCT_KEY 0x4020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * Firmware Options.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define FO1_ENABLE_PUREX BIT_10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define FO1_DISABLE_LED_CTRL BIT_6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define FO1_ENABLE_8016 BIT_0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define FO2_ENABLE_SEL_CLASS2 BIT_5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define FO3_NO_ABTS_ON_LINKDOWN BIT_14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define FO3_HOLD_STS_IOCB BIT_12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * Port Database structure definition for ISP 24xx.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define PDO_FORCE_ADISC BIT_1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define PDO_FORCE_PLOGI BIT_0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) struct buffer_credit_24xx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) u32 parameter[28];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define PORT_DATABASE_24XX_SIZE 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) struct port_database_24xx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) uint16_t flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define PDF_TASK_RETRY_ID BIT_14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define PDF_FC_TAPE BIT_7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define PDF_ACK0_CAPABLE BIT_6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define PDF_FCP2_CONF BIT_5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define PDF_CLASS_2 BIT_4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define PDF_HARD_ADDR BIT_1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * for NVMe, the login_state field has been
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * split into nibbles.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * The lower nibble is for FCP.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * The upper nibble is for NVMe.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) uint8_t current_login_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) uint8_t last_login_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define PDS_PLOGI_PENDING 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define PDS_PLOGI_COMPLETE 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define PDS_PRLI_PENDING 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define PDS_PRLI_COMPLETE 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define PDS_PORT_UNAVAILABLE 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define PDS_PRLO_PENDING 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define PDS_LOGO_PENDING 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define PDS_PRLI2_PENDING 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) uint8_t hard_address[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) uint8_t reserved_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) uint8_t port_id[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) uint8_t sequence_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) uint16_t port_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) uint16_t nport_handle; /* N_PORT handle. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) uint16_t receive_data_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) uint16_t reserved_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) uint8_t prli_svc_param_word_0[2]; /* Big endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /* Bits 15-0 of word 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) uint8_t prli_svc_param_word_3[2]; /* Big endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* Bits 15-0 of word 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) uint8_t port_name[WWN_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) uint8_t node_name[WWN_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) uint8_t reserved_3[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) uint16_t prli_nvme_svc_param_word_0; /* Bits 15-0 of word 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) uint16_t prli_nvme_svc_param_word_3; /* Bits 15-0 of word 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) uint16_t nvme_first_burst_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) uint8_t reserved_4[14];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * MB 75h returns a list of DB entries similar to port_database_24xx(64B).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * However, in this case it returns 1st 40 bytes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) struct get_name_list_extended {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) __le16 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) u8 current_login_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) u8 last_login_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) u8 hard_address[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) u8 reserved_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) u8 port_id[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) u8 sequence_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) __le16 port_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) __le16 nport_handle; /* N_PORT handle. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) __le16 receive_data_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) __le16 reserved_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /* PRLI SVC Param are Big endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) u8 prli_svc_param_word_0[2]; /* Bits 15-0 of word 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) u8 prli_svc_param_word_3[2]; /* Bits 15-0 of word 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) u8 port_name[WWN_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) u8 node_name[WWN_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /* MB 75h: This is the short version of the database */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct get_name_list {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) u8 port_node_name[WWN_SIZE]; /* B7 most sig, B0 least sig */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) __le16 nport_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) u8 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct vp_database_24xx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) uint16_t vp_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) uint8_t options;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) uint8_t id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) uint8_t port_name[WWN_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) uint8_t node_name[WWN_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) uint16_t port_id_low;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) uint16_t port_id_high;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct nvram_24xx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /* NVRAM header. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) uint8_t id[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) __le16 nvram_version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) uint16_t reserved_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /* Firmware Initialization Control Block. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) __le16 version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) uint16_t reserved_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) __le16 frame_payload_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) __le16 execution_throttle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) __le16 exchange_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) __le16 hard_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) uint8_t port_name[WWN_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) uint8_t node_name[WWN_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) __le16 login_retry_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) __le16 link_down_on_nos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) __le16 interrupt_delay_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) __le16 login_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) __le32 firmware_options_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) __le32 firmware_options_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) __le32 firmware_options_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /* Offset 56. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) * BIT 0 = Control Enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * BIT 1-15 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) * BIT 0-7 = Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * BIT 8-10 = Output Swing 1G
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) * BIT 11-13 = Output Emphasis 1G
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) * BIT 14-15 = Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) * BIT 0-7 = Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * BIT 8-10 = Output Swing 2G
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) * BIT 11-13 = Output Emphasis 2G
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) * BIT 14-15 = Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) * BIT 0-7 = Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) * BIT 8-10 = Output Swing 4G
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) * BIT 11-13 = Output Emphasis 4G
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) * BIT 14-15 = Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) __le16 seriallink_options[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) uint16_t reserved_2[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) /* Offset 96. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) uint16_t reserved_3[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) /* PCIe table entries. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) uint16_t reserved_4[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /* Offset 160. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) uint16_t reserved_5[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) /* Offset 192. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) uint16_t reserved_6[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) /* Offset 224. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) uint16_t reserved_7[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) * BIT 0 = Enable spinup delay
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) * BIT 1 = Disable BIOS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) * BIT 2 = Enable Memory Map BIOS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) * BIT 3 = Enable Selectable Boot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) * BIT 4 = Disable RISC code load
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) * BIT 5 = Disable Serdes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) * BIT 6 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) * BIT 7 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) * BIT 8 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) * BIT 9 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) * BIT 10 = Enable lip full login
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) * BIT 11 = Enable target reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) * BIT 12 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) * BIT 13 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) * BIT 14 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) * BIT 15 = Enable alternate WWN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) * BIT 16-31 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) __le32 host_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) uint8_t alternate_port_name[WWN_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) uint8_t alternate_node_name[WWN_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) uint8_t boot_port_name[WWN_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) __le16 boot_lun_number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) uint16_t reserved_8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) uint8_t alt1_boot_port_name[WWN_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) __le16 alt1_boot_lun_number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) uint16_t reserved_9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) uint8_t alt2_boot_port_name[WWN_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) __le16 alt2_boot_lun_number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) uint16_t reserved_10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) uint8_t alt3_boot_port_name[WWN_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) __le16 alt3_boot_lun_number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) uint16_t reserved_11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) * BIT 0 = Selective Login
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) * BIT 1 = Alt-Boot Enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) * BIT 2 = Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) * BIT 3 = Boot Order List
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) * BIT 4 = Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) * BIT 5 = Selective LUN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) * BIT 6 = Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) * BIT 7-31 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) __le32 efi_parameters;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) uint8_t reset_delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) uint8_t reserved_12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) uint16_t reserved_13;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) __le16 boot_id_number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) uint16_t reserved_14;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) __le16 max_luns_per_target;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) uint16_t reserved_15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) __le16 port_down_retry_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) __le16 link_down_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) /* FCode parameters. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) __le16 fcode_parameter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) uint16_t reserved_16[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) /* Offset 352. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) uint8_t prev_drv_ver_major;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) uint8_t prev_drv_ver_submajob;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) uint8_t prev_drv_ver_minor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) uint8_t prev_drv_ver_subminor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) __le16 prev_bios_ver_major;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) __le16 prev_bios_ver_minor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) __le16 prev_efi_ver_major;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) __le16 prev_efi_ver_minor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) __le16 prev_fw_ver_major;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) uint8_t prev_fw_ver_minor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) uint8_t prev_fw_ver_subminor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) uint16_t reserved_17[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) /* Offset 384. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) uint16_t reserved_18[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) /* Offset 416. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) uint16_t reserved_19[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) /* Offset 448. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) uint16_t reserved_20[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) /* Offset 480. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) uint8_t model_name[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) uint16_t reserved_21[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) /* Offset 500. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) /* HW Parameter Block. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) uint16_t pcie_table_sig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) uint16_t pcie_table_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) uint16_t subsystem_vendor_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) uint16_t subsystem_device_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) __le32 checksum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) * ISP Initialization Control Block.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) * Little endian except where noted.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define ICB_VERSION 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) struct init_cb_24xx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) __le16 version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) uint16_t reserved_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) __le16 frame_payload_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) __le16 execution_throttle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) __le16 exchange_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) __le16 hard_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) uint8_t port_name[WWN_SIZE]; /* Big endian. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) uint8_t node_name[WWN_SIZE]; /* Big endian. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) __le16 response_q_inpointer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) __le16 request_q_outpointer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) __le16 login_retry_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) __le16 prio_request_q_outpointer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) __le16 response_q_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) __le16 request_q_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) __le16 link_down_on_nos; /* Milliseconds. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) __le16 prio_request_q_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) __le64 request_q_address __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) __le64 response_q_address __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) __le64 prio_request_q_address __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) __le16 msix;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) __le16 msix_atio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) uint8_t reserved_2[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) __le16 atio_q_inpointer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) __le16 atio_q_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) __le64 atio_q_address __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) __le16 interrupt_delay_timer; /* 100us increments. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) __le16 login_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) * BIT 0 = Enable Hard Loop Id
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) * BIT 1 = Enable Fairness
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) * BIT 2 = Enable Full-Duplex
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) * BIT 3 = Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) * BIT 4 = Enable Target Mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) * BIT 5 = Disable Initiator Mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) * BIT 6 = Acquire FA-WWN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) * BIT 7 = Enable D-port Diagnostics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) * BIT 8 = Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) * BIT 9 = Non Participating LIP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) * BIT 10 = Descending Loop ID Search
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) * BIT 11 = Acquire Loop ID in LIPA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) * BIT 12 = Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) * BIT 13 = Full Login after LIP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) * BIT 14 = Node Name Option
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) * BIT 15-31 = Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) __le32 firmware_options_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) * BIT 0 = Operation Mode bit 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) * BIT 1 = Operation Mode bit 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) * BIT 2 = Operation Mode bit 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) * BIT 3 = Operation Mode bit 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) * BIT 4 = Connection Options bit 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) * BIT 5 = Connection Options bit 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) * BIT 6 = Connection Options bit 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) * BIT 7 = Enable Non part on LIHA failure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) * BIT 8 = Enable Class 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) * BIT 9 = Enable ACK0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) * BIT 10 = Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) * BIT 11 = Enable FC-SP Security
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) * BIT 12 = FC Tape Enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) * BIT 13 = Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) * BIT 14 = Enable Target PRLI Control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) * BIT 15-31 = Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) __le32 firmware_options_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) * BIT 0 = Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) * BIT 1 = Soft ID only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) * BIT 2 = Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) * BIT 3 = Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) * BIT 4 = FCP RSP Payload bit 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) * BIT 5 = FCP RSP Payload bit 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) * BIT 6 = Enable Receive Out-of-Order data frame handling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) * BIT 7 = Disable Automatic PLOGI on Local Loop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) * BIT 8 = Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) * BIT 9 = Enable Out-of-Order FCP_XFER_RDY relative offset handling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) * BIT 10 = Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) * BIT 11 = Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) * BIT 12 = Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) * BIT 13 = Data Rate bit 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) * BIT 14 = Data Rate bit 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) * BIT 15 = Data Rate bit 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) * BIT 16 = Enable 75 ohm Termination Select
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) * BIT 17-28 = Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) * BIT 29 = Enable response queue 0 in index shadowing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) * BIT 30 = Enable request queue 0 out index shadowing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) * BIT 31 = Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) __le32 firmware_options_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) __le16 qos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) __le16 rid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) uint8_t reserved_3[20];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) * ISP queue - command entry structure definition.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) #define COMMAND_BIDIRECTIONAL 0x75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) struct cmd_bidir {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) uint8_t entry_type; /* Entry type. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) uint8_t entry_count; /* Entry count. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) uint8_t sys_define; /* System defined */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) uint8_t entry_status; /* Entry status. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) uint32_t handle; /* System handle. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) __le16 nport_handle; /* N_PORT handle. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) __le16 timeout; /* Command timeout. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) __le16 wr_dseg_count; /* Write Data segment count. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) __le16 rd_dseg_count; /* Read Data segment count. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) struct scsi_lun lun; /* FCP LUN (BE). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) __le16 control_flags; /* Control flags. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) #define BD_WRAP_BACK BIT_3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) #define BD_READ_DATA BIT_1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) #define BD_WRITE_DATA BIT_0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) __le16 fcp_cmnd_dseg_len; /* Data segment length. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) __le64 fcp_cmnd_dseg_address __packed;/* Data segment address. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) uint16_t reserved[2]; /* Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) __le32 rd_byte_count; /* Total Byte count Read. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) __le32 wr_byte_count; /* Total Byte count write. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) uint8_t port_id[3]; /* PortID of destination port.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) uint8_t vp_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) struct dsd64 fcp_dsd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) #define COMMAND_TYPE_6 0x48 /* Command Type 6 entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) struct cmd_type_6 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) uint8_t entry_type; /* Entry type. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) uint8_t entry_count; /* Entry count. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) uint8_t sys_define; /* System defined. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) uint8_t entry_status; /* Entry Status. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) uint32_t handle; /* System handle. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) __le16 nport_handle; /* N_PORT handle. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) __le16 timeout; /* Command timeout. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) __le16 dseg_count; /* Data segment count. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) __le16 fcp_rsp_dsd_len; /* FCP_RSP DSD length. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) struct scsi_lun lun; /* FCP LUN (BE). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) __le16 control_flags; /* Control flags. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) #define CF_DIF_SEG_DESCR_ENABLE BIT_3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) #define CF_DATA_SEG_DESCR_ENABLE BIT_2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) #define CF_READ_DATA BIT_1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) #define CF_WRITE_DATA BIT_0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) __le16 fcp_cmnd_dseg_len; /* Data segment length. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) /* Data segment address. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) __le64 fcp_cmnd_dseg_address __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) /* Data segment address. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) __le64 fcp_rsp_dseg_address __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) __le32 byte_count; /* Total byte count. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) uint8_t port_id[3]; /* PortID of destination port. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) uint8_t vp_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) struct dsd64 fcp_dsd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) #define COMMAND_TYPE_7 0x18 /* Command Type 7 entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) struct cmd_type_7 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) uint8_t entry_type; /* Entry type. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) uint8_t entry_count; /* Entry count. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) uint8_t sys_define; /* System defined. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) uint8_t entry_status; /* Entry Status. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) uint32_t handle; /* System handle. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) __le16 nport_handle; /* N_PORT handle. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) __le16 timeout; /* Command timeout. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) #define FW_MAX_TIMEOUT 0x1999
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) __le16 dseg_count; /* Data segment count. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) uint16_t reserved_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) struct scsi_lun lun; /* FCP LUN (BE). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) __le16 task_mgmt_flags; /* Task management flags. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) #define TMF_CLEAR_ACA BIT_14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) #define TMF_TARGET_RESET BIT_13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) #define TMF_LUN_RESET BIT_12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) #define TMF_CLEAR_TASK_SET BIT_10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) #define TMF_ABORT_TASK_SET BIT_9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) #define TMF_DSD_LIST_ENABLE BIT_2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) #define TMF_READ_DATA BIT_1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) #define TMF_WRITE_DATA BIT_0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) uint8_t task;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) #define TSK_SIMPLE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) #define TSK_HEAD_OF_QUEUE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) #define TSK_ORDERED 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) #define TSK_ACA 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) #define TSK_UNTAGGED 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) uint8_t crn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) uint8_t fcp_cdb[MAX_CMDSZ]; /* SCSI command words. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) __le32 byte_count; /* Total byte count. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) uint8_t port_id[3]; /* PortID of destination port. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) uint8_t vp_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) struct dsd64 dsd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) #define COMMAND_TYPE_CRC_2 0x6A /* Command Type CRC_2 (Type 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) * (T10-DIF) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) struct cmd_type_crc_2 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) uint8_t entry_type; /* Entry type. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) uint8_t entry_count; /* Entry count. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) uint8_t sys_define; /* System defined. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) uint8_t entry_status; /* Entry Status. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) uint32_t handle; /* System handle. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) __le16 nport_handle; /* N_PORT handle. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) __le16 timeout; /* Command timeout. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) __le16 dseg_count; /* Data segment count. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) __le16 fcp_rsp_dseg_len; /* FCP_RSP DSD length. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) struct scsi_lun lun; /* FCP LUN (BE). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) __le16 control_flags; /* Control flags. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) __le16 fcp_cmnd_dseg_len; /* Data segment length. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) __le64 fcp_cmnd_dseg_address __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) /* Data segment address. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) __le64 fcp_rsp_dseg_address __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) __le32 byte_count; /* Total byte count. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) uint8_t port_id[3]; /* PortID of destination port. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) uint8_t vp_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) __le64 crc_context_address __packed; /* Data segment address. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) __le16 crc_context_len; /* Data segment length. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) uint16_t reserved_1; /* MUST be set to 0. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) * ISP queue - status entry structure definition.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) #define STATUS_TYPE 0x03 /* Status entry. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) struct sts_entry_24xx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) uint8_t entry_type; /* Entry type. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) uint8_t entry_count; /* Entry count. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) uint8_t sys_define; /* System defined. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) uint8_t entry_status; /* Entry Status. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) uint32_t handle; /* System handle. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) __le16 comp_status; /* Completion status. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) __le16 ox_id; /* OX_ID used by the firmware. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) __le32 residual_len; /* FW calc residual transfer length. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) __le16 reserved_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) __le16 nvme_rsp_pyld_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) __le16 state_flags; /* State flags. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) #define SF_TRANSFERRED_DATA BIT_11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) #define SF_NVME_ERSP BIT_6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) #define SF_FCP_RSP_DMA BIT_0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) __le16 status_qualifier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) __le16 scsi_status; /* SCSI status. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) #define SS_CONFIRMATION_REQ BIT_12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) __le32 rsp_residual_count; /* FCP RSP residual count. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) __le32 sense_len; /* FCP SENSE length. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) __le32 rsp_data_len; /* FCP response data length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) uint8_t data[28]; /* FCP rsp/sense information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) struct nvme_fc_ersp_iu nvme_ersp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) uint8_t nvme_ersp_data[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) * If DIF Error is set in comp_status, these additional fields are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) * defined:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) * !!! NOTE: Firmware sends expected/actual DIF data in big endian
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) * format; but all of the "data" field gets swab32-d in the beginning
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) * of qla2x00_status_entry().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) * &data[10] : uint8_t report_runt_bg[2]; - computed guard
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) * &data[12] : uint8_t actual_dif[8]; - DIF Data received
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) * &data[20] : uint8_t expected_dif[8]; - DIF Data computed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) * Status entry completion status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) #define CS_DATA_REASSEMBLY_ERROR 0x11 /* Data Reassembly Error.. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) #define CS_ABTS_BY_TARGET 0x13 /* Target send ABTS to abort IOCB. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) #define CS_FW_RESOURCE 0x2C /* Firmware Resource Unavailable. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) #define CS_TASK_MGMT_OVERRUN 0x30 /* Task management overrun (8+). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) #define CS_ABORT_BY_TARGET 0x47 /* Abort By Target. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) * ISP queue - marker entry structure definition.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) #define MARKER_TYPE 0x04 /* Marker entry. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) struct mrk_entry_24xx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) uint8_t entry_type; /* Entry type. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) uint8_t entry_count; /* Entry count. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) uint8_t handle_count; /* Handle count. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) uint8_t entry_status; /* Entry Status. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) uint32_t handle; /* System handle. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) __le16 nport_handle; /* N_PORT handle. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) uint8_t modifier; /* Modifier (7-0). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) #define MK_SYNC_ID_LUN 0 /* Synchronize ID/LUN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) #define MK_SYNC_ID 1 /* Synchronize ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) #define MK_SYNC_ALL 2 /* Synchronize all ID/LUN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) uint8_t reserved_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) uint8_t reserved_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) uint8_t vp_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) uint16_t reserved_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) uint8_t lun[8]; /* FCP LUN (BE). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) uint8_t reserved_4[40];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) * ISP queue - CT Pass-Through entry structure definition.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) #define CT_IOCB_TYPE 0x29 /* CT Pass-Through IOCB entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) struct ct_entry_24xx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) uint8_t entry_type; /* Entry type. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) uint8_t entry_count; /* Entry count. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) uint8_t sys_define; /* System Defined. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) uint8_t entry_status; /* Entry Status. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) uint32_t handle; /* System handle. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) __le16 comp_status; /* Completion status. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) __le16 nport_handle; /* N_PORT handle. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) __le16 cmd_dsd_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) uint8_t vp_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) uint8_t reserved_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) __le16 timeout; /* Command timeout. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) uint16_t reserved_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) __le16 rsp_dsd_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) uint8_t reserved_3[10];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) __le32 rsp_byte_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) __le32 cmd_byte_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) struct dsd64 dsd[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) #define PURX_ELS_HEADER_SIZE 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) * ISP queue - PUREX IOCB entry structure definition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) #define PUREX_IOCB_TYPE 0x51 /* CT Pass Through IOCB entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) struct purex_entry_24xx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) uint8_t entry_type; /* Entry type. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) uint8_t entry_count; /* Entry count. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) uint8_t sys_define; /* System defined. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) uint8_t entry_status; /* Entry Status. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) __le16 reserved1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) uint8_t vp_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) uint8_t reserved2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) __le16 status_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) __le16 nport_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) __le16 frame_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) __le16 trunc_frame_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) __le32 rx_xchg_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) uint8_t d_id[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) uint8_t r_ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) uint8_t s_id[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) uint8_t cs_ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) uint8_t f_ctl[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) uint8_t type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) __le16 seq_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) uint8_t df_ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) uint8_t seq_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) __le16 rx_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) __le16 ox_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) __le32 param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) uint8_t els_frame_payload[20];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) * ISP queue - ELS Pass-Through entry structure definition.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) #define ELS_IOCB_TYPE 0x53 /* ELS Pass-Through IOCB entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) struct els_entry_24xx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) uint8_t entry_type; /* Entry type. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) uint8_t entry_count; /* Entry count. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) uint8_t sys_define; /* System Defined. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) uint8_t entry_status; /* Entry Status. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) uint32_t handle; /* System handle. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) __le16 comp_status; /* response only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) __le16 nport_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) __le16 tx_dsd_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) uint8_t vp_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) uint8_t sof_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) #define EST_SOFI3 (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) #define EST_SOFI2 (3 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) __le32 rx_xchg_address; /* Receive exchange address. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) __le16 rx_dsd_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) uint8_t opcode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) uint8_t reserved_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) uint8_t d_id[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) uint8_t s_id[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) __le16 control_flags; /* Control flags. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) #define ECF_PAYLOAD_DESCR_MASK (BIT_15|BIT_14|BIT_13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) #define EPD_ELS_COMMAND (0 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) #define EPD_ELS_ACC (1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) #define EPD_ELS_RJT (2 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) #define EPD_RX_XCHG (3 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) #define ECF_CLR_PASSTHRU_PEND BIT_12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) #define ECF_INCL_FRAME_HDR BIT_11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) __le32 rx_byte_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) __le32 tx_byte_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) __le64 tx_address __packed; /* DSD 0 address. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) __le32 tx_len; /* DSD 0 length. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) __le64 rx_address __packed; /* DSD 1 address. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) __le32 rx_len; /* DSD 1 length. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) __le32 total_byte_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) __le32 error_subcode_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) __le32 error_subcode_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) __le32 error_subcode_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) struct els_sts_entry_24xx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) uint8_t entry_type; /* Entry type. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) uint8_t entry_count; /* Entry count. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) uint8_t sys_define; /* System Defined. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) uint8_t entry_status; /* Entry Status. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) __le32 handle; /* System handle. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) __le16 comp_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) __le16 nport_handle; /* N_PORT handle. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) __le16 reserved_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) uint8_t vp_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) uint8_t sof_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) __le32 rx_xchg_address; /* Receive exchange address. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) __le16 reserved_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) uint8_t opcode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) uint8_t reserved_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) uint8_t d_id[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) uint8_t s_id[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) __le16 control_flags; /* Control flags. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) __le32 total_byte_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) __le32 error_subcode_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) __le32 error_subcode_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) __le32 error_subcode_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) __le32 reserved_4[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) * ISP queue - Mailbox Command entry structure definition.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) #define MBX_IOCB_TYPE 0x39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) struct mbx_entry_24xx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) uint8_t entry_type; /* Entry type. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) uint8_t entry_count; /* Entry count. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) uint8_t handle_count; /* Handle count. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) uint8_t entry_status; /* Entry Status. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) uint32_t handle; /* System handle. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) uint16_t mbx[28];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) #define LOGINOUT_PORT_IOCB_TYPE 0x52 /* Login/Logout Port entry. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) struct logio_entry_24xx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) uint8_t entry_type; /* Entry type. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) uint8_t entry_count; /* Entry count. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) uint8_t sys_define; /* System defined. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) uint8_t entry_status; /* Entry Status. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) uint32_t handle; /* System handle. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) __le16 comp_status; /* Completion status. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) #define CS_LOGIO_ERROR 0x31 /* Login/Logout IOCB error. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) __le16 nport_handle; /* N_PORT handle. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) __le16 control_flags; /* Control flags. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) /* Modifiers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) #define LCF_INCLUDE_SNS BIT_10 /* Include SNS (FFFFFC) during LOGO. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) #define LCF_FCP2_OVERRIDE BIT_9 /* Set/Reset word 3 of PRLI. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) #define LCF_CLASS_2 BIT_8 /* Enable class 2 during PLOGI. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) #define LCF_FREE_NPORT BIT_7 /* Release NPORT handle after LOGO. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) #define LCF_EXPL_LOGO BIT_6 /* Perform an explicit LOGO. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) #define LCF_NVME_PRLI BIT_6 /* Perform NVME FC4 PRLI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) #define LCF_SKIP_PRLI BIT_5 /* Skip PRLI after PLOGI. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) #define LCF_IMPL_LOGO_ALL BIT_5 /* Implicit LOGO to all ports. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) #define LCF_COND_PLOGI BIT_4 /* PLOGI only if not logged-in. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) #define LCF_IMPL_LOGO BIT_4 /* Perform an implicit LOGO. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) #define LCF_IMPL_PRLO BIT_4 /* Perform an implicit PRLO. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) /* Commands. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) #define LCF_COMMAND_PLOGI 0x00 /* PLOGI. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) #define LCF_COMMAND_PRLI 0x01 /* PRLI. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) #define LCF_COMMAND_PDISC 0x02 /* PDISC. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) #define LCF_COMMAND_ADISC 0x03 /* ADISC. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) #define LCF_COMMAND_LOGO 0x08 /* LOGO. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) #define LCF_COMMAND_PRLO 0x09 /* PRLO. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) #define LCF_COMMAND_TPRLO 0x0A /* TPRLO. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) uint8_t vp_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) uint8_t reserved_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) uint8_t port_id[3]; /* PortID of destination port. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) uint8_t rsp_size; /* Response size in 32bit words. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) __le32 io_parameter[11]; /* General I/O parameters. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) #define LSC_SCODE_NOLINK 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) #define LSC_SCODE_NOIOCB 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) #define LSC_SCODE_NOXCB 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) #define LSC_SCODE_CMD_FAILED 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) #define LSC_SCODE_NOFABRIC 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) #define LSC_SCODE_FW_NOT_READY 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) #define LSC_SCODE_NOT_LOGGED_IN 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) #define LSC_SCODE_NOPCB 0x0A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) #define LSC_SCODE_ELS_REJECT 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) #define LSC_SCODE_CMD_PARAM_ERR 0x19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) #define LSC_SCODE_PORTID_USED 0x1A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) #define LSC_SCODE_NPORT_USED 0x1B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) #define LSC_SCODE_NONPORT 0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) #define LSC_SCODE_LOGGED_IN 0x1D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) #define LSC_SCODE_NOFLOGI_ACC 0x1F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) #define TSK_MGMT_IOCB_TYPE 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) struct tsk_mgmt_entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) uint8_t entry_type; /* Entry type. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) uint8_t entry_count; /* Entry count. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) uint8_t handle_count; /* Handle count. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) uint8_t entry_status; /* Entry Status. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) uint32_t handle; /* System handle. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) __le16 nport_handle; /* N_PORT handle. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) uint16_t reserved_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) __le16 delay; /* Activity delay in seconds. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) __le16 timeout; /* Command timeout. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) struct scsi_lun lun; /* FCP LUN (BE). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) __le32 control_flags; /* Control Flags. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) #define TCF_NOTMCMD_TO_TARGET BIT_31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) #define TCF_LUN_RESET BIT_4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) #define TCF_ABORT_TASK_SET BIT_3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) #define TCF_CLEAR_TASK_SET BIT_2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) #define TCF_TARGET_RESET BIT_1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) #define TCF_CLEAR_ACA BIT_0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) uint8_t reserved_2[20];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) uint8_t port_id[3]; /* PortID of destination port. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) uint8_t vp_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) uint8_t reserved_3[12];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) #define ABORT_IOCB_TYPE 0x33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) struct abort_entry_24xx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) uint8_t entry_type; /* Entry type. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) uint8_t entry_count; /* Entry count. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) uint8_t handle_count; /* Handle count. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) uint8_t entry_status; /* Entry Status. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) uint32_t handle; /* System handle. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) __le16 nport_handle; /* N_PORT handle. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) /* or Completion status. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) __le16 options; /* Options. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) #define AOF_NO_ABTS BIT_0 /* Do not send any ABTS. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) uint32_t handle_to_abort; /* System handle to abort. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) __le16 req_que_no;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) uint8_t reserved_1[30];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) uint8_t port_id[3]; /* PortID of destination port. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) uint8_t vp_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) uint8_t reserved_2[12];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) #define ABTS_RCV_TYPE 0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) #define ABTS_RSP_TYPE 0x55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) struct abts_entry_24xx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) uint8_t entry_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) uint8_t entry_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) uint8_t handle_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) uint8_t entry_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) __le32 handle; /* type 0x55 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) __le16 comp_status; /* type 0x55 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) __le16 nport_handle; /* type 0x54 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) __le16 control_flags; /* type 0x55 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) uint8_t vp_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) uint8_t sof_type; /* sof_type is upper nibble */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) __le32 rx_xch_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) uint8_t d_id[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) uint8_t r_ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) uint8_t s_id[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) uint8_t cs_ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) uint8_t f_ctl[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) uint8_t type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) __le16 seq_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) uint8_t df_ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) uint8_t seq_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) __le16 rx_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) __le16 ox_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) __le32 param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) __le32 subcode3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) __le32 rsvd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) __le32 subcode1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) __le32 subcode2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) } error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) __le16 rsrvd1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) uint8_t last_seq_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) uint8_t seq_id_valid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) __le16 aborted_rx_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) __le16 aborted_ox_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) __le16 high_seq_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) __le16 low_seq_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) } ba_acc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) uint8_t vendor_unique;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) uint8_t explanation;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) uint8_t reason;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) } ba_rjt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) } payload;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) __le32 rx_xch_addr_to_abort;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) /* ABTS payload explanation values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) #define BA_RJT_EXP_NO_ADDITIONAL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) #define BA_RJT_EXP_INV_OX_RX_ID 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) #define BA_RJT_EXP_SEQ_ABORTED 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) /* ABTS payload reason values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) #define BA_RJT_RSN_INV_CMD_CODE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) #define BA_RJT_RSN_LOGICAL_ERROR 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) #define BA_RJT_RSN_LOGICAL_BUSY 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) #define BA_RJT_RSN_PROTOCOL_ERROR 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) #define BA_RJT_RSN_UNABLE_TO_PERFORM 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) #define BA_RJT_RSN_VENDOR_SPECIFIC 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) /* FC_F values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) #define FC_TYPE_BLD 0x000 /* Basic link data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) #define FC_F_CTL_RSP_CNTXT 0x800000 /* Responder of exchange */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) #define FC_F_CTL_LAST_SEQ 0x100000 /* Last sequence */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) #define FC_F_CTL_END_SEQ 0x80000 /* Last sequence */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) #define FC_F_CTL_SEQ_INIT 0x010000 /* Sequence initiative */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) #define FC_ROUTING_BLD 0x80 /* Basic link data frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) #define FC_R_CTL_BLD_BA_ACC 0x04 /* BA_ACC (basic accept) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) * ISP I/O Register Set structure definitions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) struct device_reg_24xx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) __le32 flash_addr; /* Flash/NVRAM BIOS address. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) #define FARX_DATA_FLAG BIT_31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) #define FARX_ACCESS_FLASH_CONF 0x7FFD0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) #define FARX_ACCESS_FLASH_DATA 0x7FF00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) #define FARX_ACCESS_NVRAM_CONF 0x7FFF0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) #define FARX_ACCESS_NVRAM_DATA 0x7FFE0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) #define FA_NVRAM_FUNC0_ADDR 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) #define FA_NVRAM_FUNC1_ADDR 0x180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) #define FA_NVRAM_VPD_SIZE 0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) #define FA_NVRAM_VPD0_ADDR 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) #define FA_NVRAM_VPD1_ADDR 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) #define FA_BOOT_CODE_ADDR 0x00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) * RISC code begins at offset 512KB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) * within flash. Consisting of two
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) * contiguous RISC code segments.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) #define FA_RISC_CODE_ADDR 0x20000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) #define FA_RISC_CODE_SEGMENTS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) #define FA_FLASH_DESCR_ADDR_24 0x11000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) #define FA_FLASH_LAYOUT_ADDR_24 0x11400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) #define FA_NPIV_CONF0_ADDR_24 0x16000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) #define FA_NPIV_CONF1_ADDR_24 0x17000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) #define FA_FW_AREA_ADDR 0x40000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) #define FA_VPD_NVRAM_ADDR 0x48000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) #define FA_FEATURE_ADDR 0x4C000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) #define FA_FLASH_DESCR_ADDR 0x50000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) #define FA_FLASH_LAYOUT_ADDR 0x50400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) #define FA_HW_EVENT0_ADDR 0x54000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) #define FA_HW_EVENT1_ADDR 0x54400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) #define FA_HW_EVENT_SIZE 0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) #define FA_HW_EVENT_ENTRY_SIZE 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) #define FA_NPIV_CONF0_ADDR 0x5C000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) #define FA_NPIV_CONF1_ADDR 0x5D000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) #define FA_FCP_PRIO0_ADDR 0x10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) #define FA_FCP_PRIO1_ADDR 0x12000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) * Flash Error Log Event Codes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) #define HW_EVENT_RESET_ERR 0xF00B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) #define HW_EVENT_ISP_ERR 0xF020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) #define HW_EVENT_PARITY_ERR 0xF022
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) #define HW_EVENT_NVRAM_CHKSUM_ERR 0xF023
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) #define HW_EVENT_FLASH_FW_ERR 0xF024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) __le32 flash_data; /* Flash/NVRAM BIOS data. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) __le32 ctrl_status; /* Control/Status. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) #define CSRX_FLASH_ACCESS_ERROR BIT_18 /* Flash/NVRAM Access Error. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) #define CSRX_DMA_ACTIVE BIT_17 /* DMA Active status. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) #define CSRX_DMA_SHUTDOWN BIT_16 /* DMA Shutdown control status. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) #define CSRX_FUNCTION BIT_15 /* Function number. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) /* PCI-X Bus Mode. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) #define CSRX_PCIX_BUS_MODE_MASK (BIT_11|BIT_10|BIT_9|BIT_8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) #define PBM_PCI_33MHZ (0 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) #define PBM_PCIX_M1_66MHZ (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) #define PBM_PCIX_M1_100MHZ (2 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) #define PBM_PCIX_M1_133MHZ (3 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) #define PBM_PCIX_M2_66MHZ (5 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) #define PBM_PCIX_M2_100MHZ (6 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) #define PBM_PCIX_M2_133MHZ (7 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) #define PBM_PCI_66MHZ (8 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) /* Max Write Burst byte count. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) #define CSRX_MAX_WRT_BURST_MASK (BIT_5|BIT_4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) #define MWB_512_BYTES (0 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) #define MWB_1024_BYTES (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) #define MWB_2048_BYTES (2 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) #define MWB_4096_BYTES (3 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) #define CSRX_64BIT_SLOT BIT_2 /* PCI 64-Bit Bus Slot. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) #define CSRX_FLASH_ENABLE BIT_1 /* Flash BIOS Read/Write enable. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) #define CSRX_ISP_SOFT_RESET BIT_0 /* ISP soft reset. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) __le32 ictrl; /* Interrupt control. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) #define ICRX_EN_RISC_INT BIT_3 /* Enable RISC interrupts on PCI. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) __le32 istatus; /* Interrupt status. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) #define ISRX_RISC_INT BIT_3 /* RISC interrupt. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) __le32 unused_1[2]; /* Gap. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) /* Request Queue. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) __le32 req_q_in; /* In-Pointer. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) __le32 req_q_out; /* Out-Pointer. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) /* Response Queue. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) __le32 rsp_q_in; /* In-Pointer. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) __le32 rsp_q_out; /* Out-Pointer. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) /* Priority Request Queue. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) __le32 preq_q_in; /* In-Pointer. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) __le32 preq_q_out; /* Out-Pointer. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) __le32 unused_2[2]; /* Gap. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) /* ATIO Queue. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) __le32 atio_q_in; /* In-Pointer. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) __le32 atio_q_out; /* Out-Pointer. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) __le32 host_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) #define HSRX_RISC_INT BIT_15 /* RISC to Host interrupt. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) #define HSRX_RISC_PAUSED BIT_8 /* RISC Paused. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) __le32 hccr; /* Host command & control register. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) /* HCCR statuses. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) #define HCCRX_HOST_INT BIT_6 /* Host to RISC interrupt bit. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) #define HCCRX_RISC_RESET BIT_5 /* RISC Reset mode bit. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) /* HCCR commands. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) /* NOOP. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) #define HCCRX_NOOP 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) /* Set RISC Reset. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) #define HCCRX_SET_RISC_RESET 0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) /* Clear RISC Reset. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) #define HCCRX_CLR_RISC_RESET 0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) /* Set RISC Pause. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) #define HCCRX_SET_RISC_PAUSE 0x30000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) /* Releases RISC Pause. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) #define HCCRX_REL_RISC_PAUSE 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) /* Set HOST to RISC interrupt. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) #define HCCRX_SET_HOST_INT 0x50000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) /* Clear HOST to RISC interrupt. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) #define HCCRX_CLR_HOST_INT 0x60000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) /* Clear RISC to PCI interrupt. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) #define HCCRX_CLR_RISC_INT 0xA0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) __le32 gpiod; /* GPIO Data register. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) /* LED update mask. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) #define GPDX_LED_UPDATE_MASK (BIT_20|BIT_19|BIT_18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) /* Data update mask. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) #define GPDX_DATA_UPDATE_MASK (BIT_17|BIT_16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) /* Data update mask. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) #define GPDX_DATA_UPDATE_2_MASK (BIT_28|BIT_27|BIT_26|BIT_17|BIT_16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) /* LED control mask. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) #define GPDX_LED_COLOR_MASK (BIT_4|BIT_3|BIT_2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) /* LED bit values. Color names as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) * referenced in fw spec.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) #define GPDX_LED_YELLOW_ON BIT_2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) #define GPDX_LED_GREEN_ON BIT_3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) #define GPDX_LED_AMBER_ON BIT_4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) /* Data in/out. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) #define GPDX_DATA_INOUT (BIT_1|BIT_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) __le32 gpioe; /* GPIO Enable register. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) /* Enable update mask. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) #define GPEX_ENABLE_UPDATE_MASK (BIT_17|BIT_16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) /* Enable update mask. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) #define GPEX_ENABLE_UPDATE_2_MASK (BIT_28|BIT_27|BIT_26|BIT_17|BIT_16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) /* Enable. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) #define GPEX_ENABLE (BIT_1|BIT_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) __le32 iobase_addr; /* I/O Bus Base Address register. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) __le32 unused_3[10]; /* Gap. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) __le16 mailbox0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) __le16 mailbox1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) __le16 mailbox2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) __le16 mailbox3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) __le16 mailbox4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) __le16 mailbox5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) __le16 mailbox6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) __le16 mailbox7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) __le16 mailbox8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) __le16 mailbox9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) __le16 mailbox10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) __le16 mailbox11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) __le16 mailbox12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) __le16 mailbox13;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) __le16 mailbox14;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) __le16 mailbox15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) __le16 mailbox16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) __le16 mailbox17;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) __le16 mailbox18;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) __le16 mailbox19;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) __le16 mailbox20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) __le16 mailbox21;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) __le16 mailbox22;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) __le16 mailbox23;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) __le16 mailbox24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) __le16 mailbox25;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) __le16 mailbox26;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) __le16 mailbox27;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) __le16 mailbox28;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) __le16 mailbox29;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) __le16 mailbox30;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) __le16 mailbox31;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) __le32 iobase_window;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) __le32 iobase_c4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) __le32 iobase_c8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) __le32 unused_4_1[6]; /* Gap. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) __le32 iobase_q;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) __le32 unused_5[2]; /* Gap. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) __le32 iobase_select;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) __le32 unused_6[2]; /* Gap. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) __le32 iobase_sdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) /* RISC-RISC semaphore register PCI offet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) #define RISC_REGISTER_BASE_OFFSET 0x7010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) #define RISC_REGISTER_WINDOW_OFFSET 0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) /* RISC-RISC semaphore/flag register (risc address 0x7016) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) #define RISC_SEMAPHORE 0x1UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) #define RISC_SEMAPHORE_WE (RISC_SEMAPHORE << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) #define RISC_SEMAPHORE_CLR (RISC_SEMAPHORE_WE | 0x0UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) #define RISC_SEMAPHORE_SET (RISC_SEMAPHORE_WE | RISC_SEMAPHORE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) #define RISC_SEMAPHORE_FORCE 0x8000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) #define RISC_SEMAPHORE_FORCE_WE (RISC_SEMAPHORE_FORCE << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) #define RISC_SEMAPHORE_FORCE_CLR (RISC_SEMAPHORE_FORCE_WE | 0x0UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) #define RISC_SEMAPHORE_FORCE_SET \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) (RISC_SEMAPHORE_FORCE_WE | RISC_SEMAPHORE_FORCE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) /* RISC semaphore timeouts (ms) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) #define TIMEOUT_SEMAPHORE 2500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) #define TIMEOUT_SEMAPHORE_FORCE 2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) #define TIMEOUT_TOTAL_ELAPSED 4500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) /* Trace Control *************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) #define TC_AEN_DISABLE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) #define TC_EFT_ENABLE 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) #define TC_EFT_DISABLE 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) #define TC_FCE_ENABLE 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) #define TC_FCE_OPTIONS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) #define TC_FCE_DEFAULT_RX_SIZE 2112
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) #define TC_FCE_DEFAULT_TX_SIZE 2112
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) #define TC_FCE_DISABLE 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) #define TC_FCE_DISABLE_TRACE BIT_0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) /* MID Support ***************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) #define MIN_MULTI_ID_FABRIC 64 /* Must be power-of-2. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) #define MAX_MULTI_ID_FABRIC 256 /* ... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) struct mid_conf_entry_24xx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) uint16_t reserved_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) * BIT 0 = Enable Hard Loop Id
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) * BIT 1 = Acquire Loop ID in LIPA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) * BIT 2 = ID not Acquired
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) * BIT 3 = Enable VP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) * BIT 4 = Enable Initiator Mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) * BIT 5 = Disable Target Mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) * BIT 6-7 = Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) uint8_t options;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) uint8_t hard_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) uint8_t port_name[WWN_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) uint8_t node_name[WWN_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) struct mid_init_cb_24xx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) struct init_cb_24xx init_cb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) __le16 count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) __le16 options;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) struct mid_conf_entry_24xx entries[MAX_MULTI_ID_FABRIC];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) struct mid_db_entry_24xx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) uint16_t status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) #define MDBS_NON_PARTIC BIT_3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) #define MDBS_ID_ACQUIRED BIT_1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) #define MDBS_ENABLED BIT_0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) uint8_t options;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) uint8_t hard_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) uint8_t port_name[WWN_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) uint8_t node_name[WWN_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) uint8_t port_id[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) uint8_t reserved_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) * Virtual Port Control IOCB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) #define VP_CTRL_IOCB_TYPE 0x30 /* Virtual Port Control entry. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) struct vp_ctrl_entry_24xx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) uint8_t entry_type; /* Entry type. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) uint8_t entry_count; /* Entry count. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) uint8_t sys_define; /* System defined. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) uint8_t entry_status; /* Entry Status. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) uint32_t handle; /* System handle. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) __le16 vp_idx_failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) __le16 comp_status; /* Completion status. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) #define CS_VCE_IOCB_ERROR 0x01 /* Error processing IOCB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) #define CS_VCE_ACQ_ID_ERROR 0x02 /* Error while acquireing ID. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) #define CS_VCE_BUSY 0x05 /* Firmware not ready to accept cmd. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) __le16 command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) #define VCE_COMMAND_ENABLE_VPS 0x00 /* Enable VPs. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) #define VCE_COMMAND_DISABLE_VPS 0x08 /* Disable VPs. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) #define VCE_COMMAND_DISABLE_VPS_REINIT 0x09 /* Disable VPs and reinit link. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) #define VCE_COMMAND_DISABLE_VPS_LOGO 0x0a /* Disable VPs and LOGO ports. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) #define VCE_COMMAND_DISABLE_VPS_LOGO_ALL 0x0b /* Disable VPs and LOGO ports. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) __le16 vp_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) uint8_t vp_idx_map[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) __le16 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) __le16 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) uint16_t reserved_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) __le16 hopct;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) uint8_t reserved_5[24];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) * Modify Virtual Port Configuration IOCB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) #define VP_CONFIG_IOCB_TYPE 0x31 /* Virtual Port Config entry. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) struct vp_config_entry_24xx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) uint8_t entry_type; /* Entry type. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) uint8_t entry_count; /* Entry count. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) uint8_t handle_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) uint8_t entry_status; /* Entry Status. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) uint32_t handle; /* System handle. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) __le16 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) #define CS_VF_BIND_VPORTS_TO_VF BIT_0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) #define CS_VF_SET_QOS_OF_VPORTS BIT_1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) #define CS_VF_SET_HOPS_OF_VPORTS BIT_2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) __le16 comp_status; /* Completion status. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) #define CS_VCT_STS_ERROR 0x01 /* Specified VPs were not disabled. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) #define CS_VCT_CNT_ERROR 0x02 /* Invalid VP count. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) #define CS_VCT_ERROR 0x03 /* Unknown error. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) #define CS_VCT_IDX_ERROR 0x02 /* Invalid VP index. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) #define CS_VCT_BUSY 0x05 /* Firmware not ready to accept cmd. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) uint8_t command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) #define VCT_COMMAND_MOD_VPS 0x00 /* Modify VP configurations. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) #define VCT_COMMAND_MOD_ENABLE_VPS 0x01 /* Modify configuration & enable VPs. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) uint8_t vp_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) uint8_t vp_index1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) uint8_t vp_index2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) uint8_t options_idx1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) uint8_t hard_address_idx1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) uint16_t reserved_vp1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) uint8_t port_name_idx1[WWN_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) uint8_t node_name_idx1[WWN_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) uint8_t options_idx2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) uint8_t hard_address_idx2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) uint16_t reserved_vp2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) uint8_t port_name_idx2[WWN_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) uint8_t node_name_idx2[WWN_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) __le16 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) uint16_t reserved_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) __le16 hopct;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) uint8_t reserved_5[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) #define VP_RPT_ID_IOCB_TYPE 0x32 /* Report ID Acquisition entry. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) enum VP_STATUS {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) VP_STAT_COMPL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) VP_STAT_FAIL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) VP_STAT_ID_CHG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) VP_STAT_SNS_TO, /* timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) VP_STAT_SNS_RJT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) VP_STAT_SCR_TO, /* timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) VP_STAT_SCR_RJT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) enum VP_FLAGS {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) VP_FLAGS_CON_FLOOP = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) VP_FLAGS_CON_P2P = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) VP_FLAGS_CON_FABRIC = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) VP_FLAGS_NAME_VALID = BIT_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) struct vp_rpt_id_entry_24xx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) uint8_t entry_type; /* Entry type. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) uint8_t entry_count; /* Entry count. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) uint8_t sys_define; /* System defined. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) uint8_t entry_status; /* Entry Status. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) __le32 resv1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) uint8_t vp_acquired;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) uint8_t vp_setup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) uint8_t vp_idx; /* Format 0=reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) uint8_t vp_status; /* Format 0=reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) uint8_t port_id[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) uint8_t format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) struct _f0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) /* format 0 loop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) uint8_t vp_idx_map[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) uint8_t reserved_4[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) } f0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) struct _f1 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) /* format 1 fabric */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) uint8_t vpstat1_subcode; /* vp_status=1 subcode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) uint8_t flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) #define TOPO_MASK 0xE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) #define TOPO_FL 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) #define TOPO_N2N 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) #define TOPO_F 0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) uint16_t fip_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) uint8_t rsv2[12];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) uint8_t ls_rjt_vendor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) uint8_t ls_rjt_explanation;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) uint8_t ls_rjt_reason;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) uint8_t rsv3[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) uint8_t port_name[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) uint8_t node_name[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) uint16_t bbcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) uint8_t reserved_5[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) } f1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) struct _f2 { /* format 2: N2N direct connect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) uint8_t vpstat1_subcode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) uint8_t flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) uint16_t fip_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) uint8_t rsv2[12];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) uint8_t ls_rjt_vendor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) uint8_t ls_rjt_explanation;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) uint8_t ls_rjt_reason;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) uint8_t rsv3[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) uint8_t port_name[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) uint8_t node_name[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) uint16_t bbcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) uint8_t reserved_5[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) uint8_t remote_nport_id[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) } f2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) } u;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) #define VF_EVFP_IOCB_TYPE 0x26 /* Exchange Virtual Fabric Parameters entry. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) struct vf_evfp_entry_24xx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) uint8_t entry_type; /* Entry type. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) uint8_t entry_count; /* Entry count. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) uint8_t sys_define; /* System defined. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) uint8_t entry_status; /* Entry Status. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) uint32_t handle; /* System handle. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) __le16 comp_status; /* Completion status. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) __le16 timeout; /* timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) __le16 adim_tagging_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) __le16 vfport_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) uint32_t exch_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) __le16 nport_handle; /* N_PORT handle. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) __le16 control_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) uint32_t io_parameter_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) uint32_t io_parameter_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) __le64 tx_address __packed; /* Data segment 0 address. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) uint32_t tx_len; /* Data segment 0 length. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) __le64 rx_address __packed; /* Data segment 1 address. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) uint32_t rx_len; /* Data segment 1 length. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) /* END MID Support ***********************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) /* Flash Description Table ***************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) struct qla_fdt_layout {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) uint8_t sig[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) __le16 version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) __le16 len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) __le16 checksum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) uint8_t unused1[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) uint8_t model[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) __le16 man_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) __le16 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) uint8_t flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) uint8_t erase_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) uint8_t alt_erase_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) uint8_t wrt_enable_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) uint8_t wrt_enable_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) uint8_t wrt_sts_reg_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) uint8_t unprotect_sec_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) uint8_t read_man_id_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) __le32 block_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) __le32 alt_block_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) __le32 flash_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) __le32 wrt_enable_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) uint8_t read_id_addr_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) uint8_t wrt_disable_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) uint8_t read_dev_id_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) uint8_t chip_erase_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) __le16 read_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) uint8_t protect_sec_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) uint8_t unused2[65];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) /* Flash Layout Table ********************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) struct qla_flt_location {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) uint8_t sig[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) __le16 start_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) __le16 start_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) uint8_t version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) uint8_t unused[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) __le16 checksum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) #define FLT_REG_FW 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) #define FLT_REG_BOOT_CODE 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) #define FLT_REG_VPD_0 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) #define FLT_REG_NVRAM_0 0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) #define FLT_REG_VPD_1 0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) #define FLT_REG_NVRAM_1 0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) #define FLT_REG_VPD_2 0xD4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) #define FLT_REG_NVRAM_2 0xD5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) #define FLT_REG_VPD_3 0xD6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) #define FLT_REG_NVRAM_3 0xD7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) #define FLT_REG_FDT 0x1a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) #define FLT_REG_FLT 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) #define FLT_REG_HW_EVENT_0 0x1d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) #define FLT_REG_HW_EVENT_1 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) #define FLT_REG_NPIV_CONF_0 0x29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) #define FLT_REG_NPIV_CONF_1 0x2a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) #define FLT_REG_GOLD_FW 0x2f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) #define FLT_REG_FCP_PRIO_0 0x87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) #define FLT_REG_FCP_PRIO_1 0x88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) #define FLT_REG_CNA_FW 0x97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) #define FLT_REG_BOOT_CODE_8044 0xA2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) #define FLT_REG_FCOE_FW 0xA4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) #define FLT_REG_FCOE_NVRAM_0 0xAA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) #define FLT_REG_FCOE_NVRAM_1 0xAC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) /* 27xx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) #define FLT_REG_IMG_PRI_27XX 0x95
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) #define FLT_REG_IMG_SEC_27XX 0x96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) #define FLT_REG_FW_SEC_27XX 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) #define FLT_REG_BOOTLOAD_SEC_27XX 0x9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) #define FLT_REG_VPD_SEC_27XX_0 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) #define FLT_REG_VPD_SEC_27XX_1 0x52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) #define FLT_REG_VPD_SEC_27XX_2 0xD8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) #define FLT_REG_VPD_SEC_27XX_3 0xDA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) /* 28xx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) #define FLT_REG_AUX_IMG_PRI_28XX 0x125
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) #define FLT_REG_AUX_IMG_SEC_28XX 0x126
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) #define FLT_REG_VPD_SEC_28XX_0 0x10C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) #define FLT_REG_VPD_SEC_28XX_1 0x10E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) #define FLT_REG_VPD_SEC_28XX_2 0x110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) #define FLT_REG_VPD_SEC_28XX_3 0x112
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) #define FLT_REG_NVRAM_SEC_28XX_0 0x10D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) #define FLT_REG_NVRAM_SEC_28XX_1 0x10F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) #define FLT_REG_NVRAM_SEC_28XX_2 0x111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) #define FLT_REG_NVRAM_SEC_28XX_3 0x113
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) #define FLT_REG_MPI_PRI_28XX 0xD3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) #define FLT_REG_MPI_SEC_28XX 0xF0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) #define FLT_REG_PEP_PRI_28XX 0xD1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) #define FLT_REG_PEP_SEC_28XX 0xF1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) struct qla_flt_region {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) __le16 code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) uint8_t attribute;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) uint8_t reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) __le32 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) __le32 start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) __le32 end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) struct qla_flt_header {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) __le16 version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) __le16 length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) __le16 checksum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) __le16 unused;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) struct qla_flt_region region[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) #define FLT_REGION_SIZE 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) #define FLT_MAX_REGIONS 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) #define FLT_REGIONS_SIZE (FLT_REGION_SIZE * FLT_MAX_REGIONS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) /* Flash NPIV Configuration Table ********************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) struct qla_npiv_header {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) uint8_t sig[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) __le16 version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) __le16 entries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) __le16 unused[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) __le16 checksum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) struct qla_npiv_entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) __le16 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) __le16 vf_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) uint8_t q_qos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) uint8_t f_qos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) __le16 unused1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) uint8_t port_name[WWN_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) uint8_t node_name[WWN_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) /* 84XX Support **************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) #define MBA_ISP84XX_ALERT 0x800f /* Alert Notification. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) #define A84_PANIC_RECOVERY 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) #define A84_OP_LOGIN_COMPLETE 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) #define A84_DIAG_LOGIN_COMPLETE 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) #define A84_GOLD_LOGIN_COMPLETE 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) #define MBC_ISP84XX_RESET 0x3a /* Reset. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) #define FSTATE_REMOTE_FC_DOWN BIT_0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) #define FSTATE_NSL_LINK_DOWN BIT_1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) #define FSTATE_IS_DIAG_FW BIT_2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) #define FSTATE_LOGGED_IN BIT_3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) #define FSTATE_WAITING_FOR_VERIFY BIT_4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) #define VERIFY_CHIP_IOCB_TYPE 0x1B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) struct verify_chip_entry_84xx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) uint8_t entry_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) uint8_t entry_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) uint8_t sys_defined;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) uint8_t entry_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) uint32_t handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) __le16 options;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) #define VCO_DONT_UPDATE_FW BIT_0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) #define VCO_FORCE_UPDATE BIT_1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) #define VCO_DONT_RESET_UPDATE BIT_2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) #define VCO_DIAG_FW BIT_3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) #define VCO_END_OF_DATA BIT_14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) #define VCO_ENABLE_DSD BIT_15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) __le16 reserved_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) __le16 data_seg_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) __le16 reserved_2[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) __le32 fw_ver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) __le32 exchange_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) __le32 reserved_3[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) __le32 fw_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) __le32 fw_seq_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) __le32 relative_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) struct dsd64 dsd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) struct verify_chip_rsp_84xx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) uint8_t entry_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) uint8_t entry_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) uint8_t sys_defined;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) uint8_t entry_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) uint32_t handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) __le16 comp_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) #define CS_VCS_CHIP_FAILURE 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) #define CS_VCS_BAD_EXCHANGE 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) #define CS_VCS_SEQ_COMPLETEi 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) __le16 failure_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) #define VFC_CHECKSUM_ERROR 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) #define VFC_INVALID_LEN 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) #define VFC_ALREADY_IN_PROGRESS 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) __le16 reserved_1[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) __le32 fw_ver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) __le32 exchange_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) __le32 reserved_2[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) #define ACCESS_CHIP_IOCB_TYPE 0x2B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) struct access_chip_84xx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) uint8_t entry_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) uint8_t entry_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) uint8_t sys_defined;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) uint8_t entry_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) uint32_t handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) __le16 options;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) #define ACO_DUMP_MEMORY 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) #define ACO_LOAD_MEMORY 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) #define ACO_CHANGE_CONFIG_PARAM 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) #define ACO_REQUEST_INFO 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) __le16 reserved1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) __le16 dseg_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) __le16 reserved2[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) __le32 parameter1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) __le32 parameter2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) __le32 parameter3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) __le32 reserved3[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) __le32 total_byte_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) __le32 reserved4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) struct dsd64 dsd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) struct access_chip_rsp_84xx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) uint8_t entry_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) uint8_t entry_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) uint8_t sys_defined;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) uint8_t entry_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) uint32_t handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) __le16 comp_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) __le16 failure_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) __le32 residual_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) __le32 reserved[12];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) /* 81XX Support **************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) #define MBA_DCBX_START 0x8016
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) #define MBA_DCBX_COMPLETE 0x8030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) #define MBA_FCF_CONF_ERR 0x8031
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) #define MBA_DCBX_PARAM_UPDATE 0x8032
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) #define MBA_IDC_COMPLETE 0x8100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) #define MBA_IDC_NOTIFY 0x8101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) #define MBA_IDC_TIME_EXT 0x8102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) #define MBC_IDC_ACK 0x101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) #define MBC_RESTART_MPI_FW 0x3d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) #define MBC_FLASH_ACCESS_CTRL 0x3e /* Control flash access. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) #define MBC_GET_XGMAC_STATS 0x7a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) #define MBC_GET_DCBX_PARAMS 0x51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) * ISP83xx mailbox commands
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) #define MBC_WRITE_REMOTE_REG 0x0001 /* Write remote register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) #define MBC_READ_REMOTE_REG 0x0009 /* Read remote register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) #define MBC_RESTART_NIC_FIRMWARE 0x003d /* Restart NIC firmware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) #define MBC_SET_ACCESS_CONTROL 0x003e /* Access control command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) /* Flash access control option field bit definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) #define FAC_OPT_FORCE_SEMAPHORE BIT_15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) #define FAC_OPT_REQUESTOR_ID BIT_14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) #define FAC_OPT_CMD_SUBCODE 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) /* Flash access control command subcodes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) #define FAC_OPT_CMD_WRITE_PROTECT 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) #define FAC_OPT_CMD_WRITE_ENABLE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) #define FAC_OPT_CMD_ERASE_SECTOR 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) #define FAC_OPT_CMD_LOCK_SEMAPHORE 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) #define FAC_OPT_CMD_UNLOCK_SEMAPHORE 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) #define FAC_OPT_CMD_GET_SECTOR_SIZE 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) /* enhanced features bit definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) #define NEF_LR_DIST_ENABLE BIT_0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) /* LR Distance bit positions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) #define LR_DIST_NV_POS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) #define LR_DIST_NV_MASK 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) #define LR_DIST_FW_POS 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) /* FAC semaphore defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) #define FAC_SEMAPHORE_UNLOCK 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) #define FAC_SEMAPHORE_LOCK 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) struct nvram_81xx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) /* NVRAM header. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) uint8_t id[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) __le16 nvram_version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) __le16 reserved_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) /* Firmware Initialization Control Block. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) __le16 version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) __le16 reserved_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) __le16 frame_payload_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) __le16 execution_throttle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) __le16 exchange_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) __le16 reserved_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) uint8_t port_name[WWN_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) uint8_t node_name[WWN_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) __le16 login_retry_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) __le16 reserved_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) __le16 interrupt_delay_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) __le16 login_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) __le32 firmware_options_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) __le32 firmware_options_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) __le32 firmware_options_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) __le16 reserved_4[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) /* Offset 64. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) uint8_t enode_mac[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) __le16 reserved_5[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) /* Offset 80. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) __le16 reserved_6[24];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) /* Offset 128. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) __le16 ex_version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) uint8_t prio_fcf_matching_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) uint8_t reserved_6_1[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) __le16 pri_fcf_vlan_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) uint8_t pri_fcf_fabric_name[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) __le16 reserved_6_2[7];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) uint8_t spma_mac_addr[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) __le16 reserved_6_3[14];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) /* Offset 192. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) uint8_t min_supported_speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) uint8_t reserved_7_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) __le16 reserved_7[31];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) * BIT 0 = Enable spinup delay
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) * BIT 1 = Disable BIOS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) * BIT 2 = Enable Memory Map BIOS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) * BIT 3 = Enable Selectable Boot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) * BIT 4 = Disable RISC code load
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) * BIT 5 = Disable Serdes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) * BIT 6 = Opt boot mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) * BIT 7 = Interrupt enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) * BIT 8 = EV Control enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) * BIT 9 = Enable lip reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) * BIT 10 = Enable lip full login
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) * BIT 11 = Enable target reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) * BIT 12 = Stop firmware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) * BIT 13 = Enable nodename option
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) * BIT 14 = Default WWPN valid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) * BIT 15 = Enable alternate WWN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) * BIT 16 = CLP LUN string
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) * BIT 17 = CLP Target string
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) * BIT 18 = CLP BIOS enable string
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) * BIT 19 = CLP Serdes string
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) * BIT 20 = CLP WWPN string
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) * BIT 21 = CLP WWNN string
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) * BIT 22 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) * BIT 23 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) * BIT 24 = Keep WWPN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) * BIT 25 = Temp WWPN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) * BIT 26-31 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) __le32 host_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) uint8_t alternate_port_name[WWN_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) uint8_t alternate_node_name[WWN_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) uint8_t boot_port_name[WWN_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) __le16 boot_lun_number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) __le16 reserved_8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) uint8_t alt1_boot_port_name[WWN_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) __le16 alt1_boot_lun_number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) __le16 reserved_9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) uint8_t alt2_boot_port_name[WWN_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) __le16 alt2_boot_lun_number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) __le16 reserved_10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) uint8_t alt3_boot_port_name[WWN_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) __le16 alt3_boot_lun_number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) __le16 reserved_11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) * BIT 0 = Selective Login
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) * BIT 1 = Alt-Boot Enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) * BIT 2 = Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) * BIT 3 = Boot Order List
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) * BIT 4 = Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) * BIT 5 = Selective LUN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) * BIT 6 = Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) * BIT 7-31 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) __le32 efi_parameters;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) uint8_t reset_delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) uint8_t reserved_12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) __le16 reserved_13;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) __le16 boot_id_number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) __le16 reserved_14;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) __le16 max_luns_per_target;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) __le16 reserved_15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) __le16 port_down_retry_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) __le16 link_down_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) /* FCode parameters. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) __le16 fcode_parameter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) __le16 reserved_16[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) /* Offset 352. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) uint8_t reserved_17[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) __le16 reserved_18[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) uint8_t reserved_19[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) __le16 reserved_20[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) /* Offset 384. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) uint8_t reserved_21[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) __le16 reserved_22[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) /* Offset 406 (0x196) Enhanced Features
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) * BIT 0 = Extended BB credits for LR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) * BIT 1 = Virtual Fabric Enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) * BIT 2-5 = Distance Support if BIT 0 is on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) * BIT 6 = Prefer FCP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) * BIT 7 = SCM Disabled if BIT is set (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) * BIT 8-15 = Unused
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) uint16_t enhanced_features;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) uint16_t reserved_24[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) /* Offset 416. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) __le16 reserved_25[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) /* Offset 480. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) uint8_t model_name[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) /* Offset 496. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) __le16 feature_mask_l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) __le16 feature_mask_h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) __le16 reserved_26[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) __le16 subsystem_vendor_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) __le16 subsystem_device_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) __le32 checksum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) * ISP Initialization Control Block.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) * Little endian except where noted.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) #define ICB_VERSION 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) struct init_cb_81xx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) __le16 version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) __le16 reserved_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) __le16 frame_payload_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) __le16 execution_throttle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) __le16 exchange_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) __le16 reserved_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) uint8_t port_name[WWN_SIZE]; /* Big endian. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) uint8_t node_name[WWN_SIZE]; /* Big endian. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) __le16 response_q_inpointer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) __le16 request_q_outpointer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) __le16 login_retry_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) __le16 prio_request_q_outpointer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) __le16 response_q_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) __le16 request_q_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) __le16 reserved_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) __le16 prio_request_q_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) __le64 request_q_address __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) __le64 response_q_address __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) __le64 prio_request_q_address __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) uint8_t reserved_4[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) __le16 atio_q_inpointer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) __le16 atio_q_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) __le64 atio_q_address __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) __le16 interrupt_delay_timer; /* 100us increments. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) __le16 login_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) * BIT 0-3 = Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) * BIT 4 = Enable Target Mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) * BIT 5 = Disable Initiator Mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) * BIT 6 = Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) * BIT 7 = Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) * BIT 8-13 = Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) * BIT 14 = Node Name Option
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) * BIT 15-31 = Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) __le32 firmware_options_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) * BIT 0 = Operation Mode bit 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) * BIT 1 = Operation Mode bit 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) * BIT 2 = Operation Mode bit 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) * BIT 3 = Operation Mode bit 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) * BIT 4-7 = Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) * BIT 8 = Enable Class 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) * BIT 9 = Enable ACK0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) * BIT 10 = Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) * BIT 11 = Enable FC-SP Security
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) * BIT 12 = FC Tape Enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) * BIT 13 = Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) * BIT 14 = Enable Target PRLI Control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) * BIT 15-31 = Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) __le32 firmware_options_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) * BIT 0-3 = Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) * BIT 4 = FCP RSP Payload bit 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) * BIT 5 = FCP RSP Payload bit 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) * BIT 6 = Enable Receive Out-of-Order data frame handling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) * BIT 7 = Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) * BIT 8 = Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) * BIT 9 = Enable Out-of-Order FCP_XFER_RDY relative offset handling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) * BIT 10-16 = Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) * BIT 17 = Enable multiple FCFs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) * BIT 18-20 = MAC addressing mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) * BIT 21-25 = Ethernet data rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) * BIT 26 = Enable ethernet header rx IOCB for ATIO q
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) * BIT 27 = Enable ethernet header rx IOCB for response q
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) * BIT 28 = SPMA selection bit 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) * BIT 28 = SPMA selection bit 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) * BIT 30-31 = Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) __le32 firmware_options_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) uint8_t reserved_5[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) uint8_t enode_mac[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) uint8_t reserved_6[10];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) struct mid_init_cb_81xx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) struct init_cb_81xx init_cb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) uint16_t count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) uint16_t options;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) struct mid_conf_entry_24xx entries[MAX_MULTI_ID_FABRIC];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) struct ex_init_cb_81xx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) uint16_t ex_version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) uint8_t prio_fcf_matching_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) uint8_t reserved_1[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) uint16_t pri_fcf_vlan_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) uint8_t pri_fcf_fabric_name[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) uint16_t reserved_2[7];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) uint8_t spma_mac_addr[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) uint16_t reserved_3[14];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) #define FARX_ACCESS_FLASH_CONF_81XX 0x7FFD0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) #define FARX_ACCESS_FLASH_DATA_81XX 0x7F800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) #define FARX_ACCESS_FLASH_CONF_28XX 0x7FFD0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) #define FARX_ACCESS_FLASH_DATA_28XX 0x7F7D0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) /* FCP priority config defines *************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) /* operations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) #define QLFC_FCP_PRIO_DISABLE 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) #define QLFC_FCP_PRIO_ENABLE 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) #define QLFC_FCP_PRIO_GET_CONFIG 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) #define QLFC_FCP_PRIO_SET_CONFIG 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) struct qla_fcp_prio_entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) uint16_t flags; /* Describes parameter(s) in FCP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) /* priority entry that are valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) #define FCP_PRIO_ENTRY_VALID 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) #define FCP_PRIO_ENTRY_TAG_VALID 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) #define FCP_PRIO_ENTRY_SPID_VALID 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) #define FCP_PRIO_ENTRY_DPID_VALID 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) #define FCP_PRIO_ENTRY_LUNB_VALID 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) #define FCP_PRIO_ENTRY_LUNE_VALID 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) #define FCP_PRIO_ENTRY_SWWN_VALID 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) #define FCP_PRIO_ENTRY_DWWN_VALID 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) uint8_t tag; /* Priority value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) uint8_t reserved; /* Reserved for future use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) uint32_t src_pid; /* Src port id. high order byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) /* unused; -1 (wild card) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) uint32_t dst_pid; /* Src port id. high order byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) /* unused; -1 (wild card) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) uint16_t lun_beg; /* 1st lun num of lun range. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) /* -1 (wild card) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) uint16_t lun_end; /* 2nd lun num of lun range. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) /* -1 (wild card) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) uint8_t src_wwpn[8]; /* Source WWPN: -1 (wild card) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) uint8_t dst_wwpn[8]; /* Destination WWPN: -1 (wild card) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) struct qla_fcp_prio_cfg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) uint8_t signature[4]; /* "HQOS" signature of config data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) uint16_t version; /* 1: Initial version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) uint16_t length; /* config data size in num bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) uint16_t checksum; /* config data bytes checksum */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) uint16_t num_entries; /* Number of entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) uint16_t size_of_entry; /* Size of each entry in num bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) uint8_t attributes; /* enable/disable, persistence */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) #define FCP_PRIO_ATTR_DISABLE 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) #define FCP_PRIO_ATTR_ENABLE 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) #define FCP_PRIO_ATTR_PERSIST 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) uint8_t reserved; /* Reserved for future use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) #define FCP_PRIO_CFG_HDR_SIZE offsetof(struct qla_fcp_prio_cfg, entry)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) struct qla_fcp_prio_entry entry[1023]; /* fcp priority entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) uint8_t reserved2[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) #define FCP_PRIO_CFG_SIZE (32*1024) /* fcp prio data per port*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) /* 25XX Support ****************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) #define FA_FCP_PRIO0_ADDR_25 0x3C000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) #define FA_FCP_PRIO1_ADDR_25 0x3E000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) /* 81XX Flash locations -- occupies second 2MB region. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) #define FA_BOOT_CODE_ADDR_81 0x80000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) #define FA_RISC_CODE_ADDR_81 0xA0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) #define FA_FW_AREA_ADDR_81 0xC0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) #define FA_VPD_NVRAM_ADDR_81 0xD0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) #define FA_VPD0_ADDR_81 0xD0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) #define FA_VPD1_ADDR_81 0xD0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) #define FA_NVRAM0_ADDR_81 0xD0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) #define FA_NVRAM1_ADDR_81 0xD0180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) #define FA_FEATURE_ADDR_81 0xD4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) #define FA_FLASH_DESCR_ADDR_81 0xD8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) #define FA_FLASH_LAYOUT_ADDR_81 0xD8400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) #define FA_HW_EVENT0_ADDR_81 0xDC000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) #define FA_HW_EVENT1_ADDR_81 0xDC400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) #define FA_NPIV_CONF0_ADDR_81 0xD1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) #define FA_NPIV_CONF1_ADDR_81 0xD2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) /* 83XX Flash locations -- occupies second 8MB region. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) #define FA_FLASH_LAYOUT_ADDR_83 (0x3F1000/4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) #define FA_FLASH_LAYOUT_ADDR_28 (0x11000/4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) #define NVRAM_DUAL_FCP_NVME_FLAG_OFFSET 0x196
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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