^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * QLogic Fibre Channel HBA Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (c) 2003-2014 QLogic Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #ifndef __QLA_DEF_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define __QLA_DEF_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/list.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/dmapool.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/mempool.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/completion.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/workqueue.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/firmware.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/aer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/btree.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <scsi/scsi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <scsi/scsi_host.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <scsi/scsi_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <scsi/scsi_cmnd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <scsi/scsi_transport_fc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <scsi/scsi_bsg_fc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <uapi/scsi/fc/fc_els.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* Big endian Fibre Channel S_ID (source ID) or D_ID (destination ID). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) uint8_t domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) uint8_t area;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) uint8_t al_pa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) } be_id_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /* Little endian Fibre Channel S_ID (source ID) or D_ID (destination ID). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) uint8_t al_pa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) uint8_t area;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) uint8_t domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) } le_id_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #include "qla_bsg.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #include "qla_dsd.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #include "qla_nx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #include "qla_nx2.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #include "qla_nvme.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define QLA2XXX_DRIVER_NAME "qla2xxx"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define QLA2XXX_APIDEV "ql2xapidev"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define QLA2XXX_MANUFACTURER "QLogic Corporation"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * We have MAILBOX_REGISTER_COUNT sized arrays in a few places,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * but that's fine as we don't look at the last 24 ones for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * ISP2100 HBAs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define MAILBOX_REGISTER_COUNT_2100 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define MAILBOX_REGISTER_COUNT_2200 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define MAILBOX_REGISTER_COUNT 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define QLA2200A_RISC_ROM_VER 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define FPM_2300 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define FPM_2310 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #include "qla_settings.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define MODE_DUAL (MODE_TARGET | MODE_INITIATOR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * Data bit definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define BIT_0 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define BIT_1 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define BIT_2 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define BIT_3 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define BIT_4 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define BIT_5 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define BIT_6 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define BIT_7 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define BIT_8 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define BIT_9 0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define BIT_10 0x400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define BIT_11 0x800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define BIT_12 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define BIT_13 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define BIT_14 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define BIT_15 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define BIT_16 0x10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define BIT_17 0x20000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define BIT_18 0x40000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define BIT_19 0x80000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define BIT_20 0x100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define BIT_21 0x200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define BIT_22 0x400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define BIT_23 0x800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define BIT_24 0x1000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define BIT_25 0x2000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define BIT_26 0x4000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define BIT_27 0x8000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define BIT_28 0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define BIT_29 0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define BIT_30 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define BIT_31 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define LSB(x) ((uint8_t)(x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define MSB(x) ((uint8_t)((uint16_t)(x) >> 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define LSW(x) ((uint16_t)(x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define MSW(x) ((uint16_t)((uint32_t)(x) >> 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define LSD(x) ((uint32_t)((uint64_t)(x)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define MSD(x) ((uint32_t)((((uint64_t)(x)) >> 16) >> 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static inline uint32_t make_handle(uint16_t x, uint16_t y)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) return ((uint32_t)x << 16) | y;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * I/O register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static inline u8 rd_reg_byte(const volatile u8 __iomem *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) return readb(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static inline u16 rd_reg_word(const volatile __le16 __iomem *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) return readw(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static inline u32 rd_reg_dword(const volatile __le32 __iomem *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) return readl(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static inline u8 rd_reg_byte_relaxed(const volatile u8 __iomem *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) return readb_relaxed(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static inline u16 rd_reg_word_relaxed(const volatile __le16 __iomem *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) return readw_relaxed(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static inline u32 rd_reg_dword_relaxed(const volatile __le32 __iomem *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) return readl_relaxed(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static inline void wrt_reg_byte(volatile u8 __iomem *addr, u8 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) return writeb(data, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) static inline void wrt_reg_word(volatile __le16 __iomem *addr, u16 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) return writew(data, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static inline void wrt_reg_dword(volatile __le32 __iomem *addr, u32 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) return writel(data, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) * ISP83XX specific remote register addresses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define QLA83XX_LED_PORT0 0x00201320
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define QLA83XX_LED_PORT1 0x00201328
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define QLA83XX_IDC_DEV_STATE 0x22102384
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define QLA83XX_IDC_MAJOR_VERSION 0x22102380
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define QLA83XX_IDC_MINOR_VERSION 0x22102398
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define QLA83XX_IDC_DRV_PRESENCE 0x22102388
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define QLA83XX_IDC_DRIVER_ACK 0x2210238c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define QLA83XX_IDC_CONTROL 0x22102390
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define QLA83XX_IDC_AUDIT 0x22102394
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define QLA83XX_IDC_LOCK_RECOVERY 0x2210239c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define QLA83XX_DRIVER_LOCKID 0x22102104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define QLA83XX_DRIVER_LOCK 0x8111c028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define QLA83XX_DRIVER_UNLOCK 0x8111c02c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define QLA83XX_FLASH_LOCKID 0x22102100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define QLA83XX_FLASH_LOCK 0x8111c010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define QLA83XX_FLASH_UNLOCK 0x8111c014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define QLA83XX_DEV_PARTINFO1 0x221023e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define QLA83XX_DEV_PARTINFO2 0x221023e4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define QLA83XX_FW_HEARTBEAT 0x221020b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define QLA83XX_PEG_HALT_STATUS1 0x221020a8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define QLA83XX_PEG_HALT_STATUS2 0x221020ac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) /* 83XX: Macros defining 8200 AEN Reason codes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define IDC_DEVICE_STATE_CHANGE BIT_0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define IDC_PEG_HALT_STATUS_CHANGE BIT_1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define IDC_NIC_FW_REPORTED_FAILURE BIT_2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define IDC_HEARTBEAT_FAILURE BIT_3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) /* 83XX: Macros defining 8200 AEN Error-levels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define ERR_LEVEL_NON_FATAL 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define ERR_LEVEL_RECOVERABLE_FATAL 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define ERR_LEVEL_UNRECOVERABLE_FATAL 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /* 83XX: Macros for IDC Version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define QLA83XX_SUPP_IDC_MAJOR_VERSION 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define QLA83XX_SUPP_IDC_MINOR_VERSION 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /* 83XX: Macros for scheduling dpc tasks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define QLA83XX_NIC_CORE_RESET 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define QLA83XX_IDC_STATE_HANDLER 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define QLA83XX_NIC_CORE_UNRECOVERABLE 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) /* 83XX: Macros for defining IDC-Control bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define QLA83XX_IDC_RESET_DISABLED BIT_0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define QLA83XX_IDC_GRACEFUL_RESET BIT_1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) /* 83XX: Macros for different timeouts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define QLA83XX_IDC_INITIALIZATION_TIMEOUT 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define QLA83XX_IDC_RESET_ACK_TIMEOUT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define QLA83XX_MAX_LOCK_RECOVERY_WAIT (2 * HZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) /* 83XX: Macros for defining class in DEV-Partition Info register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define QLA83XX_CLASS_TYPE_NONE 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define QLA83XX_CLASS_TYPE_NIC 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define QLA83XX_CLASS_TYPE_FCOE 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define QLA83XX_CLASS_TYPE_ISCSI 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /* 83XX: Macros for IDC Lock-Recovery stages */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define IDC_LOCK_RECOVERY_STAGE1 0x1 /* Stage1: Intent for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) * lock-recovery
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define IDC_LOCK_RECOVERY_STAGE2 0x2 /* Stage2: Perform lock-recovery */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) /* 83XX: Macros for IDC Audit type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define IDC_AUDIT_TIMESTAMP 0x0 /* IDC-AUDIT: Record timestamp of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) * dev-state change to NEED-RESET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) * or NEED-QUIESCENT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define IDC_AUDIT_COMPLETION 0x1 /* IDC-AUDIT: Record duration of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) * reset-recovery completion is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) * second
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) /* ISP2031: Values for laser on/off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define PORT_0_2031 0x00201340
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define PORT_1_2031 0x00201350
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define LASER_ON_2031 0x01800100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define LASER_OFF_2031 0x01800180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) * The ISP2312 v2 chip cannot access the FLASH/GPIO registers via MMIO in an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) * 133Mhz slot.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define RD_REG_WORD_PIO(addr) (inw((unsigned long)addr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define WRT_REG_WORD_PIO(addr, data) (outw(data, (unsigned long)addr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) * Fibre Channel device definitions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define WWN_SIZE 8 /* Size of WWPN, WWN & WWNN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define MAX_FIBRE_DEVICES_2100 512
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define MAX_FIBRE_DEVICES_2400 2048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define MAX_FIBRE_DEVICES_LOOP 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define MAX_FIBRE_DEVICES_MAX MAX_FIBRE_DEVICES_2400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define LOOPID_MAP_SIZE (ha->max_fibre_devices)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define MAX_FIBRE_LUNS 0xFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define MAX_HOST_COUNT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) * Host adapter default definitions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define MAX_BUSES 1 /* We only have one bus today */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define MIN_LUNS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define MAX_LUNS MAX_FIBRE_LUNS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define MAX_CMDS_PER_LUN 255
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) * Fibre Channel device definitions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define SNS_LAST_LOOP_ID_2100 0xfe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define SNS_LAST_LOOP_ID_2300 0x7ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define LAST_LOCAL_LOOP_ID 0x7d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define SNS_FL_PORT 0x7e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define FABRIC_CONTROLLER 0x7f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define SIMPLE_NAME_SERVER 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define SNS_FIRST_LOOP_ID 0x81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define MANAGEMENT_SERVER 0xfe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define BROADCAST 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) * There is no correspondence between an N-PORT id and an AL_PA. Therefore the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) * valid range of an N-PORT id is 0 through 0x7ef.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define NPH_LAST_HANDLE 0x7ee
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define NPH_MGMT_SERVER 0x7ef /* FFFFEF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define NPH_SNS 0x7fc /* FFFFFC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define NPH_FABRIC_CONTROLLER 0x7fd /* FFFFFD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define NPH_F_PORT 0x7fe /* FFFFFE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define NPH_IP_BROADCAST 0x7ff /* FFFFFF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define NPH_SNS_LID(ha) (IS_FWI2_CAPABLE(ha) ? NPH_SNS : SIMPLE_NAME_SERVER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define MAX_CMDSZ 16 /* SCSI maximum CDB size. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #include "qla_fw.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) struct name_list_extended {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) struct get_name_list_extended *l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) dma_addr_t ldma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) struct list_head fcports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) u32 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) u8 sent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) * Timeout timer counts in seconds
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define PORT_RETRY_TIME 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define LOOP_DOWN_TIMEOUT 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define LOOP_DOWN_TIME 255 /* 240 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define LOOP_DOWN_RESET (LOOP_DOWN_TIME - 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define DEFAULT_OUTSTANDING_COMMANDS 4096
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define MIN_OUTSTANDING_COMMANDS 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) /* ISP request and response entry counts (37-65535) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define REQUEST_ENTRY_CNT_2100 128 /* Number of request entries. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define REQUEST_ENTRY_CNT_2200 2048 /* Number of request entries. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define REQUEST_ENTRY_CNT_24XX 2048 /* Number of request entries. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define REQUEST_ENTRY_CNT_83XX 8192 /* Number of request entries. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define RESPONSE_ENTRY_CNT_83XX 4096 /* Number of response entries.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define RESPONSE_ENTRY_CNT_2100 64 /* Number of response entries.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define RESPONSE_ENTRY_CNT_2300 512 /* Number of response entries.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define RESPONSE_ENTRY_CNT_MQ 128 /* Number of response entries.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define ATIO_ENTRY_CNT_24XX 4096 /* Number of ATIO entries. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define RESPONSE_ENTRY_CNT_FX00 256 /* Number of response entries.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define FW_DEF_EXCHANGES_CNT 2048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define FW_MAX_EXCHANGES_CNT (32 * 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define REDUCE_EXCHANGES_CNT (8 * 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) struct req_que;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) struct qla_tgt_sess;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) * SCSI Request Block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) struct srb_cmd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) struct scsi_cmnd *cmd; /* Linux SCSI command pkt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) uint32_t request_sense_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) uint32_t fw_sense_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) uint8_t *request_sense_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) struct ct6_dsd *ct6_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) struct crc_context *crc_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) * SRB flag definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define SRB_DMA_VALID BIT_0 /* Command sent to ISP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define SRB_FCP_CMND_DMA_VALID BIT_12 /* DIF: DSD List valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define SRB_CRC_CTX_DMA_VALID BIT_2 /* DIF: context DMA valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define SRB_CRC_PROT_DMA_VALID BIT_4 /* DIF: prot DMA valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define SRB_CRC_CTX_DSD_VALID BIT_5 /* DIF: dsd_list valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define SRB_WAKEUP_ON_COMP BIT_6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define SRB_DIF_BUNDL_DMA_VALID BIT_7 /* DIF: DMA list valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) /* To identify if a srb is of T10-CRC type. @sp => srb_t pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define IS_PROT_IO(sp) (sp->flags & SRB_CRC_CTX_DSD_VALID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) * 24 bit port ID type definition.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) typedef union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) uint32_t b24 : 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #ifdef __BIG_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) uint8_t domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) uint8_t area;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) uint8_t al_pa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #elif defined(__LITTLE_ENDIAN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) uint8_t al_pa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) uint8_t area;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) uint8_t domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #error "__BIG_ENDIAN or __LITTLE_ENDIAN must be defined!"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) uint8_t rsvd_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) } b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) } port_id_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define INVALID_PORT_ID 0xFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) static inline le_id_t be_id_to_le(be_id_t id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) le_id_t res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) res.domain = id.domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) res.area = id.area;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) res.al_pa = id.al_pa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) static inline be_id_t le_id_to_be(le_id_t id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) be_id_t res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) res.domain = id.domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) res.area = id.area;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) res.al_pa = id.al_pa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) static inline port_id_t be_to_port_id(be_id_t id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) port_id_t res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) res.b.domain = id.domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) res.b.area = id.area;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) res.b.al_pa = id.al_pa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) res.b.rsvd_1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) static inline be_id_t port_id_to_be_id(port_id_t port_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) be_id_t res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) res.domain = port_id.b.domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) res.area = port_id.b.area;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) res.al_pa = port_id.b.al_pa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) struct els_logo_payload {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) uint8_t opcode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) uint8_t rsvd[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) uint8_t s_id[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) uint8_t rsvd1[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) uint8_t wwpn[WWN_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) struct els_plogi_payload {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) uint8_t opcode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) uint8_t rsvd[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) __be32 data[112 / 4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) struct ct_arg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) void *iocb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) u16 nport_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) dma_addr_t req_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) dma_addr_t rsp_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) u32 req_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) u32 rsp_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) u32 req_allocated_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) u32 rsp_allocated_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) void *req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) void *rsp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) port_id_t id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) * SRB extensions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) struct srb_iocb {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) uint16_t flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) #define SRB_LOGIN_RETRIED BIT_0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) #define SRB_LOGIN_COND_PLOGI BIT_1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) #define SRB_LOGIN_SKIP_PRLI BIT_2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) #define SRB_LOGIN_NVME_PRLI BIT_3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) #define SRB_LOGIN_PRLI_ONLY BIT_4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) uint16_t data[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) u32 iop[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) } logio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) #define ELS_DCMD_TIMEOUT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) #define ELS_DCMD_LOGO 0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) uint32_t flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) uint32_t els_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) struct completion comp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) struct els_logo_payload *els_logo_pyld;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) dma_addr_t els_logo_pyld_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) } els_logo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) struct els_plogi {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) #define ELS_DCMD_PLOGI 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) uint32_t flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) uint32_t els_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) struct completion comp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) struct els_plogi_payload *els_plogi_pyld;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) struct els_plogi_payload *els_resp_pyld;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) u32 tx_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) u32 rx_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) dma_addr_t els_plogi_pyld_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) dma_addr_t els_resp_pyld_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) __le32 fw_status[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) __le16 comp_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) __le16 len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) } els_plogi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) * Values for flags field below are as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) * defined in tsk_mgmt_entry struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) * for control_flags field in qla_fw.h.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) uint64_t lun;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) uint32_t flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) uint32_t data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) struct completion comp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) __le16 comp_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) } tmf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) #define SRB_FXDISC_REQ_DMA_VALID BIT_0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) #define SRB_FXDISC_RESP_DMA_VALID BIT_1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) #define SRB_FXDISC_REQ_DWRD_VALID BIT_2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) #define SRB_FXDISC_RSP_DWRD_VALID BIT_3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) #define FXDISC_TIMEOUT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) uint8_t flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) uint32_t req_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) uint32_t rsp_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) void *req_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) void *rsp_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) dma_addr_t req_dma_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) dma_addr_t rsp_dma_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) __le32 adapter_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) __le32 adapter_id_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) __le16 req_func_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) __le32 req_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) __le32 req_data_extra;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) __le32 result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) __le32 seq_number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) __le16 fw_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) struct completion fxiocb_comp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) __le32 reserved_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) uint8_t reserved_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) } fxiocb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) uint32_t cmd_hndl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) __le16 comp_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) __le16 req_que_no;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) struct completion comp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) } abt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) struct ct_arg ctarg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) #define MAX_IOCB_MB_REG 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) #define SIZEOF_IOCB_MB_REG (MAX_IOCB_MB_REG * sizeof(uint16_t))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) u16 in_mb[MAX_IOCB_MB_REG]; /* from FW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) u16 out_mb[MAX_IOCB_MB_REG]; /* to FW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) void *out, *in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) dma_addr_t out_dma, in_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) struct completion comp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) } mbx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) struct imm_ntfy_from_isp *ntfy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) } nack;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) __le16 comp_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) __le16 rsp_pyld_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) uint8_t aen_op;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) void *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) /* These are only used with ls4 requests */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) int cmd_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) int rsp_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) dma_addr_t cmd_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) dma_addr_t rsp_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) enum nvmefc_fcp_datadir dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) uint32_t dl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) uint32_t timeout_sec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) struct list_head entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) } nvme;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) u16 cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) u16 vp_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) } ctrlvp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) } u;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) struct timer_list timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) void (*timeout)(void *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) /* Values for srb_ctx type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) #define SRB_LOGIN_CMD 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) #define SRB_LOGOUT_CMD 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) #define SRB_ELS_CMD_RPT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) #define SRB_ELS_CMD_HST 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) #define SRB_CT_CMD 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) #define SRB_ADISC_CMD 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) #define SRB_TM_CMD 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) #define SRB_SCSI_CMD 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) #define SRB_BIDI_CMD 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) #define SRB_FXIOCB_DCMD 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) #define SRB_FXIOCB_BCMD 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) #define SRB_ABT_CMD 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) #define SRB_ELS_DCMD 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) #define SRB_MB_IOCB 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) #define SRB_CT_PTHRU_CMD 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) #define SRB_NACK_PLOGI 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) #define SRB_NACK_PRLI 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) #define SRB_NACK_LOGO 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) #define SRB_NVME_CMD 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) #define SRB_NVME_LS 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) #define SRB_PRLI_CMD 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) #define SRB_CTRL_VP 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) #define SRB_PRLO_CMD 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) TYPE_SRB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) TYPE_TGT_CMD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) TYPE_TGT_TMCMD, /* task management */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) struct iocb_resource {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) u8 res_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) u8 pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) u16 iocb_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) typedef struct srb {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) * Do not move cmd_type field, it needs to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) * line up with qla_tgt_cmd->cmd_type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) uint8_t cmd_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) uint8_t pad[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) struct iocb_resource iores;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) struct kref cmd_kref; /* need to migrate ref_count over to this */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) void *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) wait_queue_head_t nvme_ls_waitq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) struct fc_port *fcport;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) struct scsi_qla_host *vha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) unsigned int start_timer:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) uint32_t handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) uint16_t flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) uint16_t type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) int iocbs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) struct qla_qpair *qpair;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) struct srb *cmd_sp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) struct list_head elem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) u32 gen1; /* scratch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) u32 gen2; /* scratch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) int retry_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) struct completion *comp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) struct srb_iocb iocb_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) struct bsg_job *bsg_job;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) struct srb_cmd scmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) } u;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) * Report completion status @res and call sp_put(@sp). @res is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) * an NVMe status code, a SCSI result (e.g. DID_OK << 16) or a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) * QLA_* status value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) void (*done)(struct srb *sp, int res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) /* Stop the timer and free @sp. Only used by the FCP code. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) void (*free)(struct srb *sp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) * Call nvme_private->fd->done() and free @sp. Only used by the NVMe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) * code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) void (*put_fn)(struct kref *kref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) } srb_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) #define GET_CMD_SP(sp) (sp->u.scmd.cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) #define GET_CMD_SENSE_LEN(sp) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) (sp->u.scmd.request_sense_length)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) #define SET_CMD_SENSE_LEN(sp, len) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) (sp->u.scmd.request_sense_length = len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) #define GET_CMD_SENSE_PTR(sp) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) (sp->u.scmd.request_sense_ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) #define SET_CMD_SENSE_PTR(sp, ptr) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) (sp->u.scmd.request_sense_ptr = ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) #define GET_FW_SENSE_LEN(sp) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) (sp->u.scmd.fw_sense_length)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) #define SET_FW_SENSE_LEN(sp, len) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) (sp->u.scmd.fw_sense_length = len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) struct msg_echo_lb {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) dma_addr_t send_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) dma_addr_t rcv_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) uint16_t req_sg_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) uint16_t rsp_sg_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) uint16_t options;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) uint32_t transfer_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) uint32_t iteration_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) * ISP I/O Register Set structure definitions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) struct device_reg_2xxx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) __le16 flash_address; /* Flash BIOS address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) __le16 flash_data; /* Flash BIOS data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) __le16 unused_1[1]; /* Gap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) __le16 ctrl_status; /* Control/Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) #define CSR_FLASH_64K_BANK BIT_3 /* Flash upper 64K bank select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) #define CSR_FLASH_ENABLE BIT_1 /* Flash BIOS Read/Write enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) #define CSR_ISP_SOFT_RESET BIT_0 /* ISP soft reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) __le16 ictrl; /* Interrupt control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) #define ICR_EN_INT BIT_15 /* ISP enable interrupts. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) #define ICR_EN_RISC BIT_3 /* ISP enable RISC interrupts. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) __le16 istatus; /* Interrupt status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) #define ISR_RISC_INT BIT_3 /* RISC interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) __le16 semaphore; /* Semaphore */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) __le16 nvram; /* NVRAM register. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) #define NVR_DESELECT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) #define NVR_BUSY BIT_15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) #define NVR_WRT_ENABLE BIT_14 /* Write enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) #define NVR_PR_ENABLE BIT_13 /* Protection register enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) #define NVR_DATA_IN BIT_3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) #define NVR_DATA_OUT BIT_2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) #define NVR_SELECT BIT_1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) #define NVR_CLOCK BIT_0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) #define NVR_WAIT_CNT 20000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) __le16 mailbox0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) __le16 mailbox1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) __le16 mailbox2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) __le16 mailbox3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) __le16 mailbox4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) __le16 mailbox5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) __le16 mailbox6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) __le16 mailbox7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) __le16 unused_2[59]; /* Gap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) } __attribute__((packed)) isp2100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) /* Request Queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) __le16 req_q_in; /* In-Pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) __le16 req_q_out; /* Out-Pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) /* Response Queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) __le16 rsp_q_in; /* In-Pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) __le16 rsp_q_out; /* Out-Pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) /* RISC to Host Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) __le32 host_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) #define HSR_RISC_INT BIT_15 /* RISC interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) #define HSR_RISC_PAUSED BIT_8 /* RISC Paused */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) /* Host to Host Semaphore */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) __le16 host_semaphore;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) __le16 unused_3[17]; /* Gap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) __le16 mailbox0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) __le16 mailbox1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) __le16 mailbox2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) __le16 mailbox3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) __le16 mailbox4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) __le16 mailbox5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) __le16 mailbox6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) __le16 mailbox7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) __le16 mailbox8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) __le16 mailbox9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) __le16 mailbox10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) __le16 mailbox11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) __le16 mailbox12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) __le16 mailbox13;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) __le16 mailbox14;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) __le16 mailbox15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) __le16 mailbox16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) __le16 mailbox17;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) __le16 mailbox18;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) __le16 mailbox19;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) __le16 mailbox20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) __le16 mailbox21;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) __le16 mailbox22;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) __le16 mailbox23;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) __le16 mailbox24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) __le16 mailbox25;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) __le16 mailbox26;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) __le16 mailbox27;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) __le16 mailbox28;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) __le16 mailbox29;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) __le16 mailbox30;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) __le16 mailbox31;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) __le16 fb_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) __le16 unused_4[10]; /* Gap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) } __attribute__((packed)) isp2300;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) } u;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) __le16 fpm_diag_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) __le16 unused_5[0x4]; /* Gap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) __le16 risc_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) __le16 unused_5_1; /* Gap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) __le16 pcr; /* Processor Control Register. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) __le16 unused_6[0x5]; /* Gap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) __le16 mctr; /* Memory Configuration and Timing. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) __le16 unused_7[0x3]; /* Gap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) __le16 fb_cmd_2100; /* Unused on 23XX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) __le16 unused_8[0x3]; /* Gap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) __le16 hccr; /* Host command & control register. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) #define HCCR_HOST_INT BIT_7 /* Host interrupt bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) #define HCCR_RISC_PAUSE BIT_5 /* Pause mode bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) /* HCCR commands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) #define HCCR_RESET_RISC 0x1000 /* Reset RISC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) #define HCCR_PAUSE_RISC 0x2000 /* Pause RISC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) #define HCCR_RELEASE_RISC 0x3000 /* Release RISC from reset. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) #define HCCR_SET_HOST_INT 0x5000 /* Set host interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) #define HCCR_CLR_HOST_INT 0x6000 /* Clear HOST interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) #define HCCR_CLR_RISC_INT 0x7000 /* Clear RISC interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) #define HCCR_DISABLE_PARITY_PAUSE 0x4001 /* Disable parity error RISC pause. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) #define HCCR_ENABLE_PARITY 0xA000 /* Enable PARITY interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) __le16 unused_9[5]; /* Gap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) __le16 gpiod; /* GPIO Data register. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) __le16 gpioe; /* GPIO Enable register. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) #define GPIO_LED_MASK 0x00C0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) #define GPIO_LED_GREEN_OFF_AMBER_OFF 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) #define GPIO_LED_GREEN_ON_AMBER_OFF 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) #define GPIO_LED_GREEN_OFF_AMBER_ON 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) #define GPIO_LED_GREEN_ON_AMBER_ON 0x00C0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) #define GPIO_LED_ALL_OFF 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) #define GPIO_LED_RED_ON_OTHER_OFF 0x0001 /* isp2322 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) #define GPIO_LED_RGA_ON 0x00C1 /* isp2322: red green amber */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) __le16 unused_10[8]; /* Gap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) __le16 mailbox8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) __le16 mailbox9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) __le16 mailbox10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) __le16 mailbox11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) __le16 mailbox12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) __le16 mailbox13;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) __le16 mailbox14;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) __le16 mailbox15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) __le16 mailbox16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) __le16 mailbox17;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) __le16 mailbox18;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) __le16 mailbox19;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) __le16 mailbox20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) __le16 mailbox21;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) __le16 mailbox22;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) __le16 mailbox23; /* Also probe reg. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) } __attribute__((packed)) isp2200;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) } u_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) struct device_reg_25xxmq {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) __le32 req_q_in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) __le32 req_q_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) __le32 rsp_q_in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) __le32 rsp_q_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) __le32 atio_q_in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) __le32 atio_q_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) struct device_reg_fx00 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) __le32 mailbox0; /* 00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) __le32 mailbox1; /* 04 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) __le32 mailbox2; /* 08 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) __le32 mailbox3; /* 0C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) __le32 mailbox4; /* 10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) __le32 mailbox5; /* 14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) __le32 mailbox6; /* 18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) __le32 mailbox7; /* 1C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) __le32 mailbox8; /* 20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) __le32 mailbox9; /* 24 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) __le32 mailbox10; /* 28 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) __le32 mailbox11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) __le32 mailbox12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) __le32 mailbox13;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) __le32 mailbox14;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) __le32 mailbox15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) __le32 mailbox16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) __le32 mailbox17;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) __le32 mailbox18;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) __le32 mailbox19;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) __le32 mailbox20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) __le32 mailbox21;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) __le32 mailbox22;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) __le32 mailbox23;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) __le32 mailbox24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) __le32 mailbox25;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) __le32 mailbox26;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) __le32 mailbox27;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) __le32 mailbox28;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) __le32 mailbox29;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) __le32 mailbox30;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) __le32 mailbox31;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) __le32 aenmailbox0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) __le32 aenmailbox1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) __le32 aenmailbox2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) __le32 aenmailbox3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) __le32 aenmailbox4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) __le32 aenmailbox5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) __le32 aenmailbox6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) __le32 aenmailbox7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) /* Request Queue. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) __le32 req_q_in; /* A0 - Request Queue In-Pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) __le32 req_q_out; /* A4 - Request Queue Out-Pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) /* Response Queue. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) __le32 rsp_q_in; /* A8 - Response Queue In-Pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) __le32 rsp_q_out; /* AC - Response Queue Out-Pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) /* Init values shadowed on FW Up Event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) __le32 initval0; /* B0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) __le32 initval1; /* B4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) __le32 initval2; /* B8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) __le32 initval3; /* BC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) __le32 initval4; /* C0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) __le32 initval5; /* C4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) __le32 initval6; /* C8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) __le32 initval7; /* CC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) __le32 fwheartbeat; /* D0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) __le32 pseudoaen; /* D4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) typedef union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) struct device_reg_2xxx isp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) struct device_reg_24xx isp24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) struct device_reg_25xxmq isp25mq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) struct device_reg_82xx isp82;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) struct device_reg_fx00 ispfx00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) } __iomem device_reg_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) #define ISP_REQ_Q_IN(ha, reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) &(reg)->u.isp2100.mailbox4 : \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) &(reg)->u.isp2300.req_q_in)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) #define ISP_REQ_Q_OUT(ha, reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) &(reg)->u.isp2100.mailbox4 : \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) &(reg)->u.isp2300.req_q_out)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) #define ISP_RSP_Q_IN(ha, reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) &(reg)->u.isp2100.mailbox5 : \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) &(reg)->u.isp2300.rsp_q_in)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) #define ISP_RSP_Q_OUT(ha, reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) &(reg)->u.isp2100.mailbox5 : \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) &(reg)->u.isp2300.rsp_q_out)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) #define ISP_ATIO_Q_IN(vha) (vha->hw->tgt.atio_q_in)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) #define ISP_ATIO_Q_OUT(vha) (vha->hw->tgt.atio_q_out)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) #define MAILBOX_REG(ha, reg, num) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) (num < 8 ? \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) &(reg)->u.isp2100.mailbox0 + (num) : \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) &(reg)->u_end.isp2200.mailbox8 + (num) - 8) : \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) &(reg)->u.isp2300.mailbox0 + (num))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) #define RD_MAILBOX_REG(ha, reg, num) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) rd_reg_word(MAILBOX_REG(ha, reg, num))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) #define WRT_MAILBOX_REG(ha, reg, num, data) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) wrt_reg_word(MAILBOX_REG(ha, reg, num), data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) #define FB_CMD_REG(ha, reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) &(reg)->fb_cmd_2100 : \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) &(reg)->u.isp2300.fb_cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) #define RD_FB_CMD_REG(ha, reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) rd_reg_word(FB_CMD_REG(ha, reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) #define WRT_FB_CMD_REG(ha, reg, data) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) wrt_reg_word(FB_CMD_REG(ha, reg), data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) uint32_t out_mb; /* outbound from driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) uint32_t in_mb; /* Incoming from RISC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) uint16_t mb[MAILBOX_REGISTER_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) long buf_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) void *bufp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) uint32_t tov;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) uint8_t flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) #define MBX_DMA_IN BIT_0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) #define MBX_DMA_OUT BIT_1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) #define IOCTL_CMD BIT_2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) } mbx_cmd_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) struct mbx_cmd_32 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) uint32_t out_mb; /* outbound from driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) uint32_t in_mb; /* Incoming from RISC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) uint32_t mb[MAILBOX_REGISTER_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) long buf_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) void *bufp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) uint32_t tov;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) uint8_t flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) #define MBX_DMA_IN BIT_0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) #define MBX_DMA_OUT BIT_1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) #define IOCTL_CMD BIT_2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) #define MBX_TOV_SECONDS 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) * ISP product identification definitions in mailboxes after reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) #define PROD_ID_1 0x4953
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) #define PROD_ID_2 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) #define PROD_ID_2a 0x5020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) #define PROD_ID_3 0x2020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) * ISP mailbox Self-Test status codes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) #define MBS_FRM_ALIVE 0 /* Firmware Alive. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) #define MBS_CHKSUM_ERR 1 /* Checksum Error. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) #define MBS_BUSY 4 /* Busy. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) * ISP mailbox command complete status codes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) #define MBS_COMMAND_COMPLETE 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) #define MBS_INVALID_COMMAND 0x4001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) #define MBS_HOST_INTERFACE_ERROR 0x4002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) #define MBS_TEST_FAILED 0x4003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) #define MBS_COMMAND_ERROR 0x4005
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) #define MBS_COMMAND_PARAMETER_ERROR 0x4006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) #define MBS_PORT_ID_USED 0x4007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) #define MBS_LOOP_ID_USED 0x4008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) #define MBS_ALL_IDS_IN_USE 0x4009
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) #define MBS_NOT_LOGGED_IN 0x400A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) #define MBS_LINK_DOWN_ERROR 0x400B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) #define MBS_DIAG_ECHO_TEST_ERROR 0x400C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) static inline bool qla2xxx_is_valid_mbs(unsigned int mbs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) return MBS_COMMAND_COMPLETE <= mbs && mbs <= MBS_DIAG_ECHO_TEST_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) * ISP mailbox asynchronous event status codes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) #define MBA_ASYNC_EVENT 0x8000 /* Asynchronous event. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) #define MBA_RESET 0x8001 /* Reset Detected. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) #define MBA_SYSTEM_ERR 0x8002 /* System Error. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) #define MBA_REQ_TRANSFER_ERR 0x8003 /* Request Transfer Error. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) #define MBA_RSP_TRANSFER_ERR 0x8004 /* Response Transfer Error. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) #define MBA_WAKEUP_THRES 0x8005 /* Request Queue Wake-up. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) #define MBA_LIP_OCCURRED 0x8010 /* Loop Initialization Procedure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) /* occurred. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) #define MBA_LOOP_UP 0x8011 /* FC Loop UP. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) #define MBA_LOOP_DOWN 0x8012 /* FC Loop Down. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) #define MBA_LIP_RESET 0x8013 /* LIP reset occurred. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) #define MBA_PORT_UPDATE 0x8014 /* Port Database update. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) #define MBA_RSCN_UPDATE 0x8015 /* Register State Chg Notification. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) #define MBA_LIP_F8 0x8016 /* Received a LIP F8. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) #define MBA_LOOP_INIT_ERR 0x8017 /* Loop Initialization Error. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) #define MBA_FABRIC_AUTH_REQ 0x801b /* Fabric Authentication Required. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) #define MBA_CONGN_NOTI_RECV 0x801e /* Congestion Notification Received */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) #define MBA_SCSI_COMPLETION 0x8020 /* SCSI Command Complete. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) #define MBA_CTIO_COMPLETION 0x8021 /* CTIO Complete. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) #define MBA_IP_COMPLETION 0x8022 /* IP Transmit Command Complete. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) #define MBA_IP_RECEIVE 0x8023 /* IP Received. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) #define MBA_IP_BROADCAST 0x8024 /* IP Broadcast Received. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) #define MBA_IP_LOW_WATER_MARK 0x8025 /* IP Low Water Mark reached. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) #define MBA_IP_RCV_BUFFER_EMPTY 0x8026 /* IP receive buffer queue empty. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) #define MBA_IP_HDR_DATA_SPLIT 0x8027 /* IP header/data splitting feature */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) /* used. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) #define MBA_TRACE_NOTIFICATION 0x8028 /* Trace/Diagnostic notification. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) #define MBA_POINT_TO_POINT 0x8030 /* Point to point mode. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) #define MBA_CMPLT_1_16BIT 0x8031 /* Completion 1 16bit IOSB. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) #define MBA_CMPLT_2_16BIT 0x8032 /* Completion 2 16bit IOSB. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) #define MBA_CMPLT_3_16BIT 0x8033 /* Completion 3 16bit IOSB. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) #define MBA_CMPLT_4_16BIT 0x8034 /* Completion 4 16bit IOSB. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) #define MBA_CMPLT_5_16BIT 0x8035 /* Completion 5 16bit IOSB. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) #define MBA_CHG_IN_CONNECTION 0x8036 /* Change in connection mode. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) #define MBA_RIO_RESPONSE 0x8040 /* RIO response queue update. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) #define MBA_ZIO_RESPONSE 0x8040 /* ZIO response queue update. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) #define MBA_CMPLT_2_32BIT 0x8042 /* Completion 2 32bit IOSB. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) #define MBA_BYPASS_NOTIFICATION 0x8043 /* Auto bypass notification. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) #define MBA_DISCARD_RND_FRAME 0x8048 /* discard RND frame due to error. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) #define MBA_REJECTED_FCP_CMD 0x8049 /* rejected FCP_CMD. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) #define MBA_FW_NOT_STARTED 0x8050 /* Firmware not started */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) #define MBA_FW_STARTING 0x8051 /* Firmware starting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) #define MBA_FW_RESTART_CMPLT 0x8060 /* Firmware restart complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) #define MBA_INIT_REQUIRED 0x8061 /* Initialization required */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) #define MBA_SHUTDOWN_REQUESTED 0x8062 /* Shutdown Requested */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) #define MBA_TEMPERATURE_ALERT 0x8070 /* Temperature Alert */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) #define MBA_DPORT_DIAGNOSTICS 0x8080 /* D-port Diagnostics */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) #define MBA_TRANS_INSERT 0x8130 /* Transceiver Insertion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) #define MBA_TRANS_REMOVE 0x8131 /* Transceiver Removal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) #define MBA_FW_INIT_FAILURE 0x8401 /* Firmware initialization failure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) #define MBA_MIRROR_LUN_CHANGE 0x8402 /* Mirror LUN State Change
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) Notification */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) #define MBA_FW_POLL_STATE 0x8600 /* Firmware in poll diagnostic state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) #define MBA_FW_RESET_FCT 0x8502 /* Firmware reset factory defaults */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) #define MBA_FW_INIT_INPROGRESS 0x8500 /* Firmware boot in progress */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) /* 83XX FCoE specific */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) #define MBA_IDC_AEN 0x8200 /* FCoE: NIC Core state change AEN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) /* Interrupt type codes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) #define INTR_ROM_MB_SUCCESS 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) #define INTR_ROM_MB_FAILED 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) #define INTR_MB_SUCCESS 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) #define INTR_MB_FAILED 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) #define INTR_ASYNC_EVENT 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) #define INTR_RSP_QUE_UPDATE 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) #define INTR_RSP_QUE_UPDATE_83XX 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) #define INTR_ATIO_QUE_UPDATE 0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) #define INTR_ATIO_RSP_QUE_UPDATE 0x1D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) #define INTR_ATIO_QUE_UPDATE_27XX 0x1E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) /* ISP mailbox loopback echo diagnostic error code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) #define MBS_LB_RESET 0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) * Firmware options 1, 2, 3.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) #define FO1_AE_ON_LIPF8 BIT_0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) #define FO1_AE_ALL_LIP_RESET BIT_1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) #define FO1_CTIO_RETRY BIT_3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) #define FO1_DISABLE_LIP_F7_SW BIT_4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) #define FO1_DISABLE_100MS_LOS_WAIT BIT_5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) #define FO1_DISABLE_GPIO6_7 BIT_6 /* LED bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) #define FO1_AE_ON_LOOP_INIT_ERR BIT_7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) #define FO1_SET_EMPHASIS_SWING BIT_8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) #define FO1_AE_AUTO_BYPASS BIT_9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) #define FO1_ENABLE_PURE_IOCB BIT_10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) #define FO1_AE_PLOGI_RJT BIT_11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) #define FO1_ENABLE_ABORT_SEQUENCE BIT_12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) #define FO1_AE_QUEUE_FULL BIT_13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) #define FO2_ENABLE_ATIO_TYPE_3 BIT_0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) #define FO2_REV_LOOPBACK BIT_1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) #define FO3_ENABLE_EMERG_IOCB BIT_0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) #define FO3_AE_RND_ERROR BIT_1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) /* 24XX additional firmware options */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) #define ADD_FO_COUNT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) #define ADD_FO1_DISABLE_GPIO_LED_CTRL BIT_6 /* LED bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) #define ADD_FO1_ENABLE_PUREX_IOCB BIT_10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) #define ADD_FO2_ENABLE_SEL_CLS2 BIT_5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) #define ADD_FO3_NO_ABT_ON_LINK_DOWN BIT_14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) * ISP mailbox commands
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) #define MBC_LOAD_RAM 1 /* Load RAM. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) #define MBC_EXECUTE_FIRMWARE 2 /* Execute firmware. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) #define MBC_READ_RAM_WORD 5 /* Read RAM word. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) #define MBC_MAILBOX_REGISTER_TEST 6 /* Wrap incoming mailboxes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) #define MBC_VERIFY_CHECKSUM 7 /* Verify checksum. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) #define MBC_GET_FIRMWARE_VERSION 8 /* Get firmware revision. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) #define MBC_LOAD_RISC_RAM 9 /* Load RAM command. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) #define MBC_DUMP_RISC_RAM 0xa /* Dump RAM command. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) #define MBC_SECURE_FLASH_UPDATE 0xa /* Secure Flash Update(28xx) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) #define MBC_LOAD_RISC_RAM_EXTENDED 0xb /* Load RAM extended. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) #define MBC_DUMP_RISC_RAM_EXTENDED 0xc /* Dump RAM extended. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) #define MBC_WRITE_RAM_WORD_EXTENDED 0xd /* Write RAM word extended */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) #define MBC_READ_RAM_EXTENDED 0xf /* Read RAM extended. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) #define MBC_IOCB_COMMAND 0x12 /* Execute IOCB command. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) #define MBC_STOP_FIRMWARE 0x14 /* Stop firmware. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) #define MBC_ABORT_COMMAND 0x15 /* Abort IOCB command. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) #define MBC_ABORT_DEVICE 0x16 /* Abort device (ID/LUN). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) #define MBC_ABORT_TARGET 0x17 /* Abort target (ID). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) #define MBC_RESET 0x18 /* Reset. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) #define MBC_GET_ADAPTER_LOOP_ID 0x20 /* Get loop id of ISP2200. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) #define MBC_GET_SET_ZIO_THRESHOLD 0x21 /* Get/SET ZIO THRESHOLD. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) #define MBC_GET_RETRY_COUNT 0x22 /* Get f/w retry cnt/delay. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) #define MBC_DISABLE_VI 0x24 /* Disable VI operation. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) #define MBC_ENABLE_VI 0x25 /* Enable VI operation. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) #define MBC_GET_FIRMWARE_OPTION 0x28 /* Get Firmware Options. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) #define MBC_GET_MEM_OFFLOAD_CNTRL_STAT 0x34 /* Memory Offload ctrl/Stat*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) #define MBC_SET_FIRMWARE_OPTION 0x38 /* Set Firmware Options. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) #define MBC_SET_GET_FC_LED_CONFIG 0x3b /* Set/Get FC LED config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) #define MBC_LOOP_PORT_BYPASS 0x40 /* Loop Port Bypass. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) #define MBC_LOOP_PORT_ENABLE 0x41 /* Loop Port Enable. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) #define MBC_GET_RESOURCE_COUNTS 0x42 /* Get Resource Counts. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) #define MBC_NON_PARTICIPATE 0x43 /* Non-Participating Mode. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) #define MBC_DIAGNOSTIC_ECHO 0x44 /* Diagnostic echo. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) #define MBC_DIAGNOSTIC_LOOP_BACK 0x45 /* Diagnostic loop back. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) #define MBC_ONLINE_SELF_TEST 0x46 /* Online self-test. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) #define MBC_ENHANCED_GET_PORT_DATABASE 0x47 /* Get port database + login */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) #define MBC_CONFIGURE_VF 0x4b /* Configure VFs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) #define MBC_RESET_LINK_STATUS 0x52 /* Reset Link Error Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) #define MBC_IOCB_COMMAND_A64 0x54 /* Execute IOCB command (64) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) #define MBC_PORT_LOGOUT 0x56 /* Port Logout request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) #define MBC_SEND_RNID_ELS 0x57 /* Send RNID ELS request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) #define MBC_SET_RNID_PARAMS 0x59 /* Set RNID parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) #define MBC_GET_RNID_PARAMS 0x5a /* Get RNID parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) #define MBC_DATA_RATE 0x5d /* Data Rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) #define MBC_INITIALIZE_FIRMWARE 0x60 /* Initialize firmware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) #define MBC_INITIATE_LIP 0x62 /* Initiate Loop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) /* Initialization Procedure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) #define MBC_GET_FC_AL_POSITION_MAP 0x63 /* Get FC_AL Position Map. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) #define MBC_GET_PORT_DATABASE 0x64 /* Get Port Database. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) #define MBC_CLEAR_ACA 0x65 /* Clear ACA. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) #define MBC_TARGET_RESET 0x66 /* Target Reset. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) #define MBC_CLEAR_TASK_SET 0x67 /* Clear Task Set. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) #define MBC_ABORT_TASK_SET 0x68 /* Abort Task Set. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) #define MBC_GET_FIRMWARE_STATE 0x69 /* Get firmware state. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) #define MBC_GET_PORT_NAME 0x6a /* Get port name. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) #define MBC_GET_LINK_STATUS 0x6b /* Get port link status. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) #define MBC_LIP_RESET 0x6c /* LIP reset. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) #define MBC_SEND_SNS_COMMAND 0x6e /* Send Simple Name Server */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) /* commandd. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) #define MBC_LOGIN_FABRIC_PORT 0x6f /* Login fabric port. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) #define MBC_SEND_CHANGE_REQUEST 0x70 /* Send Change Request. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) #define MBC_LOGOUT_FABRIC_PORT 0x71 /* Logout fabric port. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) #define MBC_LIP_FULL_LOGIN 0x72 /* Full login LIP. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) #define MBC_LOGIN_LOOP_PORT 0x74 /* Login Loop Port. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) #define MBC_PORT_NODE_NAME_LIST 0x75 /* Get port/node name list. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) #define MBC_INITIALIZE_RECEIVE_QUEUE 0x77 /* Initialize receive queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) #define MBC_UNLOAD_IP 0x79 /* Shutdown IP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) #define MBC_GET_ID_LIST 0x7C /* Get Port ID list. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) #define MBC_SEND_LFA_COMMAND 0x7D /* Send Loop Fabric Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) #define MBC_LUN_RESET 0x7E /* Send LUN reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) * all the Mt. Rainier mailbox command codes that clash with FC/FCoE ones
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) * should be defined with MBC_MR_*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) #define MBC_MR_DRV_SHUTDOWN 0x6A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) * ISP24xx mailbox commands
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) #define MBC_WRITE_SERDES 0x3 /* Write serdes word. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) #define MBC_READ_SERDES 0x4 /* Read serdes word. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) #define MBC_LOAD_DUMP_MPI_RAM 0x5 /* Load/Dump MPI RAM. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) #define MBC_SERDES_PARAMS 0x10 /* Serdes Tx Parameters. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) #define MBC_GET_IOCB_STATUS 0x12 /* Get IOCB status command. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) #define MBC_PORT_PARAMS 0x1A /* Port iDMA Parameters. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) #define MBC_GET_TIMEOUT_PARAMS 0x22 /* Get FW timeouts. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) #define MBC_TRACE_CONTROL 0x27 /* Trace control command. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) #define MBC_GEN_SYSTEM_ERROR 0x2a /* Generate System Error. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) #define MBC_WRITE_SFP 0x30 /* Write SFP Data. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) #define MBC_READ_SFP 0x31 /* Read SFP Data. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) #define MBC_SET_TIMEOUT_PARAMS 0x32 /* Set FW timeouts. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) #define MBC_DPORT_DIAGNOSTICS 0x47 /* D-Port Diagnostics */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) #define MBC_MID_INITIALIZE_FIRMWARE 0x48 /* MID Initialize firmware. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) #define MBC_MID_GET_VP_DATABASE 0x49 /* MID Get VP Database. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) #define MBC_MID_GET_VP_ENTRY 0x4a /* MID Get VP Entry. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) #define MBC_HOST_MEMORY_COPY 0x53 /* Host Memory Copy. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) #define MBC_SEND_RNFT_ELS 0x5e /* Send RNFT ELS request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) #define MBC_GET_LINK_PRIV_STATS 0x6d /* Get link & private data. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) #define MBC_LINK_INITIALIZATION 0x72 /* Do link initialization. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) #define MBC_SET_VENDOR_ID 0x76 /* Set Vendor ID. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) #define MBC_PORT_RESET 0x120 /* Port Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) #define MBC_SET_PORT_CONFIG 0x122 /* Set port configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) #define MBC_GET_PORT_CONFIG 0x123 /* Get port configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) * ISP81xx mailbox commands
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) #define MBC_WRITE_MPI_REGISTER 0x01 /* Write MPI Register. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) * ISP8044 mailbox commands
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) #define MBC_SET_GET_ETH_SERDES_REG 0x150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) #define HCS_WRITE_SERDES 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) #define HCS_READ_SERDES 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) /* Firmware return data sizes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) #define FCAL_MAP_SIZE 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) /* Mailbox bit definitions for out_mb and in_mb */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) #define MBX_31 BIT_31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) #define MBX_30 BIT_30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) #define MBX_29 BIT_29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) #define MBX_28 BIT_28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) #define MBX_27 BIT_27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) #define MBX_26 BIT_26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) #define MBX_25 BIT_25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) #define MBX_24 BIT_24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) #define MBX_23 BIT_23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) #define MBX_22 BIT_22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) #define MBX_21 BIT_21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) #define MBX_20 BIT_20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) #define MBX_19 BIT_19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) #define MBX_18 BIT_18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) #define MBX_17 BIT_17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) #define MBX_16 BIT_16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) #define MBX_15 BIT_15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) #define MBX_14 BIT_14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) #define MBX_13 BIT_13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) #define MBX_12 BIT_12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) #define MBX_11 BIT_11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) #define MBX_10 BIT_10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) #define MBX_9 BIT_9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) #define MBX_8 BIT_8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) #define MBX_7 BIT_7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) #define MBX_6 BIT_6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) #define MBX_5 BIT_5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) #define MBX_4 BIT_4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) #define MBX_3 BIT_3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) #define MBX_2 BIT_2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) #define MBX_1 BIT_1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) #define MBX_0 BIT_0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) #define RNID_TYPE_ELS_CMD 0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) #define RNID_TYPE_PORT_LOGIN 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) #define RNID_BUFFER_CREDITS 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) #define RNID_TYPE_SET_VERSION 0x9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) #define RNID_TYPE_ASIC_TEMP 0xC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) #define ELS_CMD_MAP_SIZE 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) * Firmware state codes from get firmware state mailbox command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) #define FSTATE_CONFIG_WAIT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) #define FSTATE_WAIT_AL_PA 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) #define FSTATE_WAIT_LOGIN 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) #define FSTATE_READY 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) #define FSTATE_LOSS_OF_SYNC 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) #define FSTATE_ERROR 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) #define FSTATE_REINIT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) #define FSTATE_NON_PART 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) #define FSTATE_CONFIG_CORRECT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) #define FSTATE_P2P_RCV_LIP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) #define FSTATE_P2P_CHOOSE_LOOP 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) #define FSTATE_P2P_RCV_UNIDEN_LIP 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) #define FSTATE_FATAL_ERROR 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) #define FSTATE_LOOP_BACK_CONN 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) #define QLA27XX_IMG_STATUS_VER_MAJOR 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) #define QLA27XX_IMG_STATUS_VER_MINOR 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) #define QLA27XX_IMG_STATUS_SIGN 0xFACEFADE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) #define QLA28XX_IMG_STATUS_SIGN 0xFACEFADF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) #define QLA28XX_IMG_STATUS_SIGN 0xFACEFADF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) #define QLA28XX_AUX_IMG_STATUS_SIGN 0xFACEFAED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) #define QLA27XX_DEFAULT_IMAGE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) #define QLA27XX_PRIMARY_IMAGE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) #define QLA27XX_SECONDARY_IMAGE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) * Port Database structure definition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) * Little endian except where noted.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) #define PORT_DATABASE_SIZE 128 /* bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) uint8_t options;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) uint8_t control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) uint8_t master_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) uint8_t slave_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) uint8_t reserved[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) uint8_t hard_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) uint8_t reserved_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) uint8_t port_id[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) uint8_t node_name[WWN_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) uint8_t port_name[WWN_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) __le16 execution_throttle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) uint16_t execution_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) uint8_t reset_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) uint8_t reserved_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) uint16_t resource_allocation;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) uint16_t current_allocation;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) uint16_t queue_head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) uint16_t queue_tail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) uint16_t transmit_execution_list_next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) uint16_t transmit_execution_list_previous;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) uint16_t common_features;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) uint16_t total_concurrent_sequences;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) uint16_t RO_by_information_category;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) uint8_t recipient;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) uint8_t initiator;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) uint16_t receive_data_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) uint16_t concurrent_sequences;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) uint16_t open_sequences_per_exchange;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) uint16_t lun_abort_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) uint16_t lun_stop_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) uint16_t stop_queue_head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) uint16_t stop_queue_tail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) uint16_t port_retry_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) uint16_t next_sequence_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) uint16_t frame_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) uint16_t PRLI_payload_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) uint8_t prli_svc_param_word_0[2]; /* Big endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) /* Bits 15-0 of word 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) uint8_t prli_svc_param_word_3[2]; /* Big endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) /* Bits 15-0 of word 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) uint16_t loop_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) uint16_t extended_lun_info_list_pointer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) uint16_t extended_lun_stop_list_pointer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) } port_database_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) * Port database slave/master states
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) #define PD_STATE_DISCOVERY 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) #define PD_STATE_WAIT_DISCOVERY_ACK 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) #define PD_STATE_PORT_LOGIN 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) #define PD_STATE_WAIT_PORT_LOGIN_ACK 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) #define PD_STATE_PROCESS_LOGIN 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) #define PD_STATE_WAIT_PROCESS_LOGIN_ACK 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) #define PD_STATE_PORT_LOGGED_IN 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) #define PD_STATE_PORT_UNAVAILABLE 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) #define PD_STATE_PROCESS_LOGOUT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) #define PD_STATE_WAIT_PROCESS_LOGOUT_ACK 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) #define PD_STATE_PORT_LOGOUT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) #define PD_STATE_WAIT_PORT_LOGOUT_ACK 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) #define QLA_ZIO_MODE_6 (BIT_2 | BIT_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) #define QLA_ZIO_DISABLED 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) #define QLA_ZIO_DEFAULT_TIMER 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) * ISP Initialization Control Block.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) * Little endian except where noted.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) #define ICB_VERSION 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) uint8_t version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) uint8_t reserved_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) * LSB BIT 0 = Enable Hard Loop Id
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) * LSB BIT 1 = Enable Fairness
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) * LSB BIT 2 = Enable Full-Duplex
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) * LSB BIT 3 = Enable Fast Posting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) * LSB BIT 4 = Enable Target Mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) * LSB BIT 5 = Disable Initiator Mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) * LSB BIT 6 = Enable ADISC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) * LSB BIT 7 = Enable Target Inquiry Data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) * MSB BIT 0 = Enable PDBC Notify
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) * MSB BIT 1 = Non Participating LIP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) * MSB BIT 2 = Descending Loop ID Search
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) * MSB BIT 3 = Acquire Loop ID in LIPA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) * MSB BIT 4 = Stop PortQ on Full Status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) * MSB BIT 5 = Full Login after LIP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) * MSB BIT 6 = Node Name Option
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) * MSB BIT 7 = Ext IFWCB enable bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) uint8_t firmware_options[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) __le16 frame_payload_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) __le16 max_iocb_allocation;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) __le16 execution_throttle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) uint8_t retry_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) uint8_t retry_delay; /* unused */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) uint8_t port_name[WWN_SIZE]; /* Big endian. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) uint16_t hard_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) uint8_t inquiry_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) uint8_t login_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) uint8_t node_name[WWN_SIZE]; /* Big endian. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) __le16 request_q_outpointer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) __le16 response_q_inpointer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) __le16 request_q_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) __le16 response_q_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) __le64 request_q_address __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) __le64 response_q_address __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) __le16 lun_enables;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) uint8_t command_resource_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) uint8_t immediate_notify_resource_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) __le16 timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) uint8_t reserved_2[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) * LSB BIT 0 = Timer Operation mode bit 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) * LSB BIT 1 = Timer Operation mode bit 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) * LSB BIT 2 = Timer Operation mode bit 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) * LSB BIT 3 = Timer Operation mode bit 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) * LSB BIT 4 = Init Config Mode bit 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) * LSB BIT 5 = Init Config Mode bit 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) * LSB BIT 6 = Init Config Mode bit 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) * LSB BIT 7 = Enable Non part on LIHA failure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) * MSB BIT 0 = Enable class 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) * MSB BIT 1 = Enable ACK0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) * MSB BIT 2 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) * MSB BIT 3 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) * MSB BIT 4 = FC Tape Enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) * MSB BIT 5 = Enable FC Confirm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) * MSB BIT 6 = Enable command queuing in target mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) * MSB BIT 7 = No Logo On Link Down
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) uint8_t add_firmware_options[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) uint8_t response_accumulation_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) uint8_t interrupt_delay_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) * LSB BIT 0 = Enable Read xfr_rdy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) * LSB BIT 1 = Soft ID only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) * LSB BIT 2 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) * LSB BIT 3 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) * LSB BIT 4 = FCP RSP Payload [0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) * LSB BIT 6 = Enable Out-of-Order frame handling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) * LSB BIT 7 = Disable Automatic PLOGI on Local Loop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) * MSB BIT 0 = Sbus enable - 2300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) * MSB BIT 1 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) * MSB BIT 2 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) * MSB BIT 3 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) * MSB BIT 4 = LED mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) * MSB BIT 5 = enable 50 ohm termination
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) * MSB BIT 6 = Data Rate (2300 only)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) * MSB BIT 7 = Data Rate (2300 only)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) uint8_t special_options[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) uint8_t reserved_3[26];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) } init_cb_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) /* Special Features Control Block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) struct init_sf_cb {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) uint8_t format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) uint8_t reserved0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) * BIT 15-14 = Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) * BIT_13 = SAN Congestion Management (1 - Enabled, 0 - Disabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) * BIT_12 = Remote Write Optimization (1 - Enabled, 0 - Disabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) * BIT 11-0 = Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) uint16_t flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) uint8_t reserved1[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) uint16_t discard_OHRB_timeout_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) uint16_t remote_write_opt_queue_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) uint8_t reserved2[40];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) uint8_t scm_related_parameter[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) uint8_t reserved3[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) * Get Link Status mailbox command return buffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) #define GLSO_SEND_RPS BIT_0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) #define GLSO_USE_DID BIT_3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) struct link_statistics {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) __le32 link_fail_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) __le32 loss_sync_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) __le32 loss_sig_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) __le32 prim_seq_err_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) __le32 inval_xmit_word_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) __le32 inval_crc_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) __le32 lip_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) __le32 link_up_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) __le32 link_down_loop_init_tmo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) __le32 link_down_los;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) __le32 link_down_loss_rcv_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) uint32_t reserved0[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) __le32 port_cfg_chg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) uint32_t reserved1[11];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) __le32 rsp_q_full;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) __le32 atio_q_full;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) __le32 drop_ae;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) __le32 els_proto_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) __le32 reserved2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) __le32 tx_frames;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) __le32 rx_frames;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) __le32 discarded_frames;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) __le32 dropped_frames;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) uint32_t reserved3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) __le32 nos_rcvd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) uint32_t reserved4[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) __le32 tx_prjt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) __le32 rcv_exfail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) __le32 rcv_abts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) __le32 seq_frm_miss;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) __le32 corr_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) __le32 mb_rqst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) __le32 nport_full;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) __le32 eofa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) uint32_t reserved5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) __le64 fpm_recv_word_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) __le64 fpm_disc_word_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) __le64 fpm_xmit_word_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) uint32_t reserved6[70];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) * NVRAM Command values.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) #define NV_START_BIT BIT_2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) #define NV_WRITE_OP (BIT_26+BIT_24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) #define NV_READ_OP (BIT_26+BIT_25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) #define NV_ERASE_OP (BIT_26+BIT_25+BIT_24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) #define NV_MASK_OP (BIT_26+BIT_25+BIT_24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) #define NV_DELAY_COUNT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) * QLogic ISP2100, ISP2200 and ISP2300 NVRAM structure definition.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) * NVRAM header
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) uint8_t id[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) uint8_t nvram_version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) uint8_t reserved_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) * NVRAM RISC parameter block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) uint8_t parameter_block_version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) uint8_t reserved_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) * LSB BIT 0 = Enable Hard Loop Id
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) * LSB BIT 1 = Enable Fairness
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) * LSB BIT 2 = Enable Full-Duplex
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) * LSB BIT 3 = Enable Fast Posting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) * LSB BIT 4 = Enable Target Mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) * LSB BIT 5 = Disable Initiator Mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) * LSB BIT 6 = Enable ADISC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) * LSB BIT 7 = Enable Target Inquiry Data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) * MSB BIT 0 = Enable PDBC Notify
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) * MSB BIT 1 = Non Participating LIP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) * MSB BIT 2 = Descending Loop ID Search
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) * MSB BIT 3 = Acquire Loop ID in LIPA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) * MSB BIT 4 = Stop PortQ on Full Status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) * MSB BIT 5 = Full Login after LIP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) * MSB BIT 6 = Node Name Option
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) * MSB BIT 7 = Ext IFWCB enable bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) uint8_t firmware_options[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) __le16 frame_payload_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) __le16 max_iocb_allocation;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) __le16 execution_throttle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) uint8_t retry_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) uint8_t retry_delay; /* unused */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) uint8_t port_name[WWN_SIZE]; /* Big endian. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) uint16_t hard_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) uint8_t inquiry_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) uint8_t login_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) uint8_t node_name[WWN_SIZE]; /* Big endian. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) * LSB BIT 0 = Timer Operation mode bit 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) * LSB BIT 1 = Timer Operation mode bit 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) * LSB BIT 2 = Timer Operation mode bit 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) * LSB BIT 3 = Timer Operation mode bit 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) * LSB BIT 4 = Init Config Mode bit 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) * LSB BIT 5 = Init Config Mode bit 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) * LSB BIT 6 = Init Config Mode bit 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) * LSB BIT 7 = Enable Non part on LIHA failure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) * MSB BIT 0 = Enable class 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) * MSB BIT 1 = Enable ACK0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) * MSB BIT 2 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) * MSB BIT 3 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) * MSB BIT 4 = FC Tape Enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) * MSB BIT 5 = Enable FC Confirm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) * MSB BIT 6 = Enable command queuing in target mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) * MSB BIT 7 = No Logo On Link Down
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) uint8_t add_firmware_options[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) uint8_t response_accumulation_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) uint8_t interrupt_delay_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) * LSB BIT 0 = Enable Read xfr_rdy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) * LSB BIT 1 = Soft ID only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) * LSB BIT 2 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) * LSB BIT 3 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) * LSB BIT 4 = FCP RSP Payload [0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) * LSB BIT 6 = Enable Out-of-Order frame handling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) * LSB BIT 7 = Disable Automatic PLOGI on Local Loop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) * MSB BIT 0 = Sbus enable - 2300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) * MSB BIT 1 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) * MSB BIT 2 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) * MSB BIT 3 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) * MSB BIT 4 = LED mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) * MSB BIT 5 = enable 50 ohm termination
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) * MSB BIT 6 = Data Rate (2300 only)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) * MSB BIT 7 = Data Rate (2300 only)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) uint8_t special_options[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) /* Reserved for expanded RISC parameter block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) uint8_t reserved_2[22];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) * LSB BIT 0 = Tx Sensitivity 1G bit 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) * LSB BIT 1 = Tx Sensitivity 1G bit 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) * LSB BIT 2 = Tx Sensitivity 1G bit 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) * LSB BIT 3 = Tx Sensitivity 1G bit 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) * LSB BIT 4 = Rx Sensitivity 1G bit 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) * LSB BIT 5 = Rx Sensitivity 1G bit 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) * LSB BIT 6 = Rx Sensitivity 1G bit 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) * LSB BIT 7 = Rx Sensitivity 1G bit 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) * MSB BIT 0 = Tx Sensitivity 2G bit 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) * MSB BIT 1 = Tx Sensitivity 2G bit 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) * MSB BIT 2 = Tx Sensitivity 2G bit 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) * MSB BIT 3 = Tx Sensitivity 2G bit 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) * MSB BIT 4 = Rx Sensitivity 2G bit 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) * MSB BIT 5 = Rx Sensitivity 2G bit 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) * MSB BIT 6 = Rx Sensitivity 2G bit 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) * MSB BIT 7 = Rx Sensitivity 2G bit 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) * LSB BIT 0 = Output Swing 1G bit 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) * LSB BIT 1 = Output Swing 1G bit 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) * LSB BIT 2 = Output Swing 1G bit 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) * LSB BIT 3 = Output Emphasis 1G bit 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) * LSB BIT 4 = Output Emphasis 1G bit 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) * LSB BIT 5 = Output Swing 2G bit 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) * LSB BIT 6 = Output Swing 2G bit 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) * LSB BIT 7 = Output Swing 2G bit 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) * MSB BIT 0 = Output Emphasis 2G bit 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) * MSB BIT 1 = Output Emphasis 2G bit 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) * MSB BIT 2 = Output Enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) * MSB BIT 3 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) * MSB BIT 4 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) * MSB BIT 5 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) * MSB BIT 6 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) * MSB BIT 7 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) uint8_t seriallink_options[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) * NVRAM host parameter block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) * LSB BIT 0 = Enable spinup delay
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) * LSB BIT 1 = Disable BIOS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) * LSB BIT 2 = Enable Memory Map BIOS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) * LSB BIT 3 = Enable Selectable Boot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) * LSB BIT 4 = Disable RISC code load
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) * LSB BIT 5 = Set cache line size 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) * LSB BIT 6 = PCI Parity Disable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) * LSB BIT 7 = Enable extended logging
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) * MSB BIT 0 = Enable 64bit addressing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) * MSB BIT 1 = Enable lip reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) * MSB BIT 2 = Enable lip full login
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) * MSB BIT 3 = Enable target reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) * MSB BIT 4 = Enable database storage
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) * MSB BIT 5 = Enable cache flush read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) * MSB BIT 6 = Enable database load
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) * MSB BIT 7 = Enable alternate WWN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) uint8_t host_p[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) uint8_t boot_node_name[WWN_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) uint8_t boot_lun_number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) uint8_t reset_delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) uint8_t port_down_retry_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) uint8_t boot_id_number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) __le16 max_luns_per_target;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) uint8_t fcode_boot_port_name[WWN_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) uint8_t alternate_port_name[WWN_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) uint8_t alternate_node_name[WWN_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) * BIT 0 = Selective Login
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) * BIT 1 = Alt-Boot Enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) * BIT 2 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) * BIT 3 = Boot Order List
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) * BIT 4 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) * BIT 5 = Selective LUN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) * BIT 6 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) * BIT 7 = unused
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) uint8_t efi_parameters;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) uint8_t link_down_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) uint8_t adapter_id[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) uint8_t alt1_boot_node_name[WWN_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) uint16_t alt1_boot_lun_number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) uint8_t alt2_boot_node_name[WWN_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) uint16_t alt2_boot_lun_number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) uint8_t alt3_boot_node_name[WWN_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) uint16_t alt3_boot_lun_number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) uint8_t alt4_boot_node_name[WWN_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) uint16_t alt4_boot_lun_number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) uint8_t alt5_boot_node_name[WWN_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) uint16_t alt5_boot_lun_number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) uint8_t alt6_boot_node_name[WWN_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) uint16_t alt6_boot_lun_number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) uint8_t alt7_boot_node_name[WWN_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) uint16_t alt7_boot_lun_number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) uint8_t reserved_3[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) /* Offset 200-215 : Model Number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) uint8_t model_number[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) /* OEM related items */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) uint8_t oem_specific[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) * NVRAM Adapter Features offset 232-239
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) * LSB BIT 0 = External GBIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) * LSB BIT 1 = Risc RAM parity
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) * LSB BIT 2 = Buffer Plus Module
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) * LSB BIT 3 = Multi Chip Adapter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) * LSB BIT 4 = Internal connector
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) * LSB BIT 5 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) * LSB BIT 6 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) * LSB BIT 7 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) * MSB BIT 0 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) * MSB BIT 1 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) * MSB BIT 2 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) * MSB BIT 3 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) * MSB BIT 4 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) * MSB BIT 5 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) * MSB BIT 6 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) * MSB BIT 7 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) uint8_t adapter_features[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) uint8_t reserved_4[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) /* Subsystem vendor ID for ISP2200 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) uint16_t subsystem_vendor_id_2200;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) /* Subsystem device ID for ISP2200 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) uint16_t subsystem_device_id_2200;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) uint8_t reserved_5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) uint8_t checksum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) } nvram_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) * ISP queue - response queue entry definition.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) uint8_t entry_type; /* Entry type. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) uint8_t entry_count; /* Entry count. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) uint8_t sys_define; /* System defined. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) uint8_t entry_status; /* Entry Status. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) uint32_t handle; /* System defined handle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) uint8_t data[52];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) uint32_t signature;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) #define RESPONSE_PROCESSED 0xDEADDEAD /* Signature */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) } response_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) * ISP queue - ATIO queue entry definition.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) struct atio {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) uint8_t entry_type; /* Entry type. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) uint8_t entry_count; /* Entry count. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) __le16 attr_n_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) uint8_t data[56];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) uint32_t signature;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) #define ATIO_PROCESSED 0xDEADDEAD /* Signature */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) typedef union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) __le16 extended;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) uint8_t reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) uint8_t standard;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) } id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) } target_id_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) #define SET_TARGET_ID(ha, to, from) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) if (HAS_EXTENDED_IDS(ha)) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) to.extended = cpu_to_le16(from); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) else \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) to.id.standard = (uint8_t)from; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) * ISP queue - command entry structure definition.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) #define COMMAND_TYPE 0x11 /* Command entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) uint8_t entry_type; /* Entry type. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) uint8_t entry_count; /* Entry count. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) uint8_t sys_define; /* System defined. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) uint8_t entry_status; /* Entry Status. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) uint32_t handle; /* System handle. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) target_id_t target; /* SCSI ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) __le16 lun; /* SCSI LUN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) __le16 control_flags; /* Control flags. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) #define CF_WRITE BIT_6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) #define CF_READ BIT_5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) #define CF_SIMPLE_TAG BIT_3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) #define CF_ORDERED_TAG BIT_2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) #define CF_HEAD_TAG BIT_1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) uint16_t reserved_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) __le16 timeout; /* Command timeout. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) __le16 dseg_count; /* Data segment count. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) __le32 byte_count; /* Total byte count. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) struct dsd32 dsd32[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) struct dsd64 dsd64[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) } cmd_entry_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) * ISP queue - 64-Bit addressing, command entry structure definition.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) #define COMMAND_A64_TYPE 0x19 /* Command A64 entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) uint8_t entry_type; /* Entry type. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) uint8_t entry_count; /* Entry count. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) uint8_t sys_define; /* System defined. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) uint8_t entry_status; /* Entry Status. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) uint32_t handle; /* System handle. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) target_id_t target; /* SCSI ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) __le16 lun; /* SCSI LUN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) __le16 control_flags; /* Control flags. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) uint16_t reserved_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) __le16 timeout; /* Command timeout. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) __le16 dseg_count; /* Data segment count. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) uint32_t byte_count; /* Total byte count. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) struct dsd64 dsd[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) } cmd_a64_entry_t, request_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) * ISP queue - continuation entry structure definition.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) #define CONTINUE_TYPE 0x02 /* Continuation entry. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) uint8_t entry_type; /* Entry type. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) uint8_t entry_count; /* Entry count. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) uint8_t sys_define; /* System defined. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) uint8_t entry_status; /* Entry Status. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) uint32_t reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) struct dsd32 dsd[7];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) } cont_entry_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) * ISP queue - 64-Bit addressing, continuation entry structure definition.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) #define CONTINUE_A64_TYPE 0x0A /* Continuation A64 entry. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) uint8_t entry_type; /* Entry type. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) uint8_t entry_count; /* Entry count. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) uint8_t sys_define; /* System defined. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) uint8_t entry_status; /* Entry Status. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) struct dsd64 dsd[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) } cont_a64_entry_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) #define PO_MODE_DIF_INSERT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) #define PO_MODE_DIF_REMOVE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) #define PO_MODE_DIF_PASS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) #define PO_MODE_DIF_REPLACE 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) #define PO_MODE_DIF_TCP_CKSUM 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) #define PO_ENABLE_INCR_GUARD_SEED BIT_3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) #define PO_DISABLE_GUARD_CHECK BIT_4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) #define PO_DISABLE_INCR_REF_TAG BIT_5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) #define PO_DIS_HEADER_MODE BIT_7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) #define PO_ENABLE_DIF_BUNDLING BIT_8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) #define PO_DIS_FRAME_MODE BIT_9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) #define PO_DIS_VALD_APP_ESC BIT_10 /* Dis validation for escape tag/ffffh */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) #define PO_DIS_VALD_APP_REF_ESC BIT_11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) #define PO_DIS_APP_TAG_REPL BIT_12 /* disable REG Tag replacement */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) #define PO_DIS_REF_TAG_REPL BIT_13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) #define PO_DIS_APP_TAG_VALD BIT_14 /* disable REF Tag validation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) #define PO_DIS_REF_TAG_VALD BIT_15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) * ISP queue - 64-Bit addressing, continuation crc entry structure definition.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) struct crc_context {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) uint32_t handle; /* System handle. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) __le32 ref_tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) __le16 app_tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) uint8_t ref_tag_mask[4]; /* Validation/Replacement Mask*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) uint8_t app_tag_mask[2]; /* Validation/Replacement Mask*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) __le16 guard_seed; /* Initial Guard Seed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) __le16 prot_opts; /* Requested Data Protection Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) __le16 blk_size; /* Data size in bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) __le16 runt_blk_guard; /* Guard value for runt block (tape
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) * only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) __le32 byte_count; /* Total byte count/ total data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) * transfer count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) uint32_t reserved_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) uint16_t reserved_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) uint16_t reserved_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) uint32_t reserved_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) struct dsd64 data_dsd[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) uint32_t reserved_5[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) uint32_t reserved_6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) } nobundling;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) __le32 dif_byte_count; /* Total DIF byte
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) * count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) uint16_t reserved_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) __le16 dseg_count; /* Data segment count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) uint32_t reserved_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) struct dsd64 data_dsd[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) struct dsd64 dif_dsd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) } bundling;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) } u;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) struct fcp_cmnd fcp_cmnd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) dma_addr_t crc_ctx_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) /* List of DMA context transfers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) struct list_head dsd_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) /* List of DIF Bundling context DMA address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) struct list_head ldif_dsd_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) u8 no_ldif_dsd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) struct list_head ldif_dma_hndl_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) u32 dif_bundl_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) u8 no_dif_bundl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) /* This structure should not exceed 512 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) #define CRC_CONTEXT_LEN_FW (offsetof(struct crc_context, fcp_cmnd.lun))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) #define CRC_CONTEXT_FCPCMND_OFF (offsetof(struct crc_context, fcp_cmnd.lun))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) * ISP queue - status entry structure definition.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) #define STATUS_TYPE 0x03 /* Status entry. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) uint8_t entry_type; /* Entry type. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) uint8_t entry_count; /* Entry count. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) uint8_t sys_define; /* System defined. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) uint8_t entry_status; /* Entry Status. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) uint32_t handle; /* System handle. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) __le16 scsi_status; /* SCSI status. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) __le16 comp_status; /* Completion status. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) __le16 state_flags; /* State flags. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) __le16 status_flags; /* Status flags. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) __le16 rsp_info_len; /* Response Info Length. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) __le16 req_sense_length; /* Request sense data length. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) __le32 residual_length; /* Residual transfer length. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) uint8_t rsp_info[8]; /* FCP response information. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) uint8_t req_sense_data[32]; /* Request sense data. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) } sts_entry_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) * Status entry entry status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) #define RF_RQ_DMA_ERROR BIT_6 /* Request Queue DMA error. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) #define RF_INV_E_ORDER BIT_5 /* Invalid entry order. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) #define RF_INV_E_COUNT BIT_4 /* Invalid entry count. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) #define RF_INV_E_PARAM BIT_3 /* Invalid entry parameter. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) #define RF_INV_E_TYPE BIT_2 /* Invalid entry type. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) #define RF_BUSY BIT_1 /* Busy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) #define RF_MASK (RF_RQ_DMA_ERROR | RF_INV_E_ORDER | RF_INV_E_COUNT | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) RF_INV_E_PARAM | RF_INV_E_TYPE | RF_BUSY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) #define RF_MASK_24XX (RF_INV_E_ORDER | RF_INV_E_COUNT | RF_INV_E_PARAM | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) RF_INV_E_TYPE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) * Status entry SCSI status bit definitions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) #define SS_MASK 0xfff /* Reserved bits BIT_12-BIT_15*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) #define SS_RESIDUAL_UNDER BIT_11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) #define SS_RESIDUAL_OVER BIT_10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) #define SS_SENSE_LEN_VALID BIT_9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) #define SS_RESPONSE_INFO_LEN_VALID BIT_8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) #define SS_SCSI_STATUS_BYTE 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) #define SS_RESERVE_CONFLICT (BIT_4 | BIT_3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) #define SS_BUSY_CONDITION BIT_3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) #define SS_CONDITION_MET BIT_2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) #define SS_CHECK_CONDITION BIT_1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) * Status entry completion status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) #define CS_COMPLETE 0x0 /* No errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) #define CS_INCOMPLETE 0x1 /* Incomplete transfer of cmd. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) #define CS_DMA 0x2 /* A DMA direction error. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) #define CS_TRANSPORT 0x3 /* Transport error. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) #define CS_RESET 0x4 /* SCSI bus reset occurred */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) #define CS_ABORTED 0x5 /* System aborted command. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) #define CS_TIMEOUT 0x6 /* Timeout error. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) #define CS_DATA_OVERRUN 0x7 /* Data overrun. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) #define CS_DIF_ERROR 0xC /* DIF error detected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) #define CS_DATA_UNDERRUN 0x15 /* Data Underrun. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) #define CS_QUEUE_FULL 0x1C /* Queue Full. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) #define CS_PORT_UNAVAILABLE 0x28 /* Port unavailable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) /* (selection timeout) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) #define CS_PORT_LOGGED_OUT 0x29 /* Port Logged Out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) #define CS_PORT_CONFIG_CHG 0x2A /* Port Configuration Changed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) #define CS_PORT_BUSY 0x2B /* Port Busy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) #define CS_COMPLETE_CHKCOND 0x30 /* Error? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) #define CS_IOCB_ERROR 0x31 /* Generic error for IOCB request
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) failure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) #define CS_BAD_PAYLOAD 0x80 /* Driver defined */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) #define CS_UNKNOWN 0x81 /* Driver defined */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) #define CS_RETRY 0x82 /* Driver defined */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) #define CS_LOOP_DOWN_ABORT 0x83 /* Driver defined */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) #define CS_BIDIR_RD_OVERRUN 0x700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) #define CS_BIDIR_RD_WR_OVERRUN 0x707
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) #define CS_BIDIR_RD_OVERRUN_WR_UNDERRUN 0x715
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) #define CS_BIDIR_RD_UNDERRUN 0x1500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) #define CS_BIDIR_RD_UNDERRUN_WR_OVERRUN 0x1507
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) #define CS_BIDIR_RD_WR_UNDERRUN 0x1515
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) #define CS_BIDIR_DMA 0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) * Status entry status flags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) #define SF_ABTS_TERMINATED BIT_10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) #define SF_LOGOUT_SENT BIT_13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) * ISP queue - status continuation entry structure definition.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) #define STATUS_CONT_TYPE 0x10 /* Status continuation entry. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) uint8_t entry_type; /* Entry type. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) uint8_t entry_count; /* Entry count. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) uint8_t sys_define; /* System defined. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) uint8_t entry_status; /* Entry Status. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) uint8_t data[60]; /* data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) } sts_cont_entry_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) * ISP queue - RIO Type 1 status entry (32 bit I/O entry handles)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) * structure definition.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) #define STATUS_TYPE_21 0x21 /* Status entry. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) uint8_t entry_type; /* Entry type. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) uint8_t entry_count; /* Entry count. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) uint8_t handle_count; /* Handle count. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) uint8_t entry_status; /* Entry Status. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) uint32_t handle[15]; /* System handles. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) } sts21_entry_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) * ISP queue - RIO Type 2 status entry (16 bit I/O entry handles)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) * structure definition.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) #define STATUS_TYPE_22 0x22 /* Status entry. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) uint8_t entry_type; /* Entry type. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) uint8_t entry_count; /* Entry count. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) uint8_t handle_count; /* Handle count. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) uint8_t entry_status; /* Entry Status. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) uint16_t handle[30]; /* System handles. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) } sts22_entry_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) * ISP queue - marker entry structure definition.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) #define MARKER_TYPE 0x04 /* Marker entry. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) uint8_t entry_type; /* Entry type. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) uint8_t entry_count; /* Entry count. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) uint8_t handle_count; /* Handle count. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) uint8_t entry_status; /* Entry Status. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) uint32_t sys_define_2; /* System defined. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) target_id_t target; /* SCSI ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) uint8_t modifier; /* Modifier (7-0). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) #define MK_SYNC_ID_LUN 0 /* Synchronize ID/LUN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) #define MK_SYNC_ID 1 /* Synchronize ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) #define MK_SYNC_ALL 2 /* Synchronize all ID/LUN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) #define MK_SYNC_LIP 3 /* Synchronize all ID/LUN, */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) /* clear port changed, */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) /* use sequence number. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) uint8_t reserved_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) __le16 sequence_number; /* Sequence number of event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) __le16 lun; /* SCSI LUN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) uint8_t reserved_2[48];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) } mrk_entry_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) * ISP queue - Management Server entry structure definition.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) #define MS_IOCB_TYPE 0x29 /* Management Server IOCB entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) uint8_t entry_type; /* Entry type. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) uint8_t entry_count; /* Entry count. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) uint8_t handle_count; /* Handle count. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) uint8_t entry_status; /* Entry Status. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) uint32_t handle1; /* System handle. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) target_id_t loop_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) __le16 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) __le16 control_flags; /* Control flags. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) uint16_t reserved2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) __le16 timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) __le16 cmd_dsd_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) __le16 total_dsd_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) uint8_t type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) uint8_t r_ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) __le16 rx_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) uint16_t reserved3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) uint32_t handle2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) __le32 rsp_bytecount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) __le32 req_bytecount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) struct dsd64 req_dsd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) struct dsd64 rsp_dsd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) } ms_iocb_entry_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) #define SCM_EDC_ACC_RECEIVED BIT_6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) #define SCM_RDF_ACC_RECEIVED BIT_7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) * ISP queue - Mailbox Command entry structure definition.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) #define MBX_IOCB_TYPE 0x39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) struct mbx_entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) uint8_t entry_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) uint8_t entry_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) uint8_t sys_define1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) /* Use sys_define1 for source type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) #define SOURCE_SCSI 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) #define SOURCE_IP 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) #define SOURCE_VI 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) #define SOURCE_SCTP 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) #define SOURCE_MP 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) #define SOURCE_MPIOCTL 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) #define SOURCE_ASYNC_IOCB 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) uint8_t entry_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) uint32_t handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) target_id_t loop_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) __le16 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) __le16 state_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) __le16 status_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) uint32_t sys_define2[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) __le16 mb0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) __le16 mb1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) __le16 mb2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) __le16 mb3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) __le16 mb6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) __le16 mb7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) __le16 mb9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) __le16 mb10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) uint32_t reserved_2[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) uint8_t node_name[WWN_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) uint8_t port_name[WWN_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) #ifndef IMMED_NOTIFY_TYPE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) #define IMMED_NOTIFY_TYPE 0x0D /* Immediate notify entry. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) * ISP queue - immediate notify entry structure definition.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) * This is sent by the ISP to the Target driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) * This IOCB would have report of events sent by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) * initiator, that needs to be handled by the target
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) * driver immediately.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) struct imm_ntfy_from_isp {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) uint8_t entry_type; /* Entry type. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) uint8_t entry_count; /* Entry count. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) uint8_t sys_define; /* System defined. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) uint8_t entry_status; /* Entry Status. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) __le32 sys_define_2; /* System defined. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) target_id_t target;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) __le16 lun;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) uint8_t target_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) uint8_t reserved_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) __le16 status_modifier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) __le16 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) __le16 task_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) __le16 seq_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) __le16 srr_rx_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) __le32 srr_rel_offs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) __le16 srr_ui;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) #define SRR_IU_DATA_IN 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) #define SRR_IU_DATA_OUT 0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) #define SRR_IU_STATUS 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) __le16 srr_ox_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) uint8_t reserved_2[28];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) } isp2x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) uint32_t reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) __le16 nport_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) uint16_t reserved_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) __le16 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) #define NOTIFY24XX_FLAGS_GLOBAL_TPRLO BIT_1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) #define NOTIFY24XX_FLAGS_PUREX_IOCB BIT_0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) __le16 srr_rx_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) __le16 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) uint8_t status_subcode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) uint8_t fw_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) __le32 exchange_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) __le32 srr_rel_offs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) __le16 srr_ui;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) __le16 srr_ox_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) uint8_t node_name[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) } plogi; /* PLOGI/ADISC/PDISC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) /* PRLI word 3 bit 0-15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) __le16 wd3_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) uint8_t resv0[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) } prli;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) uint8_t port_id[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) uint8_t resv1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) __le16 nport_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) uint16_t resv2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) } req_els;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) } u;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) uint8_t port_name[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) uint8_t resv3[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) uint8_t vp_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) uint32_t reserved_5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) uint8_t port_id[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) uint8_t reserved_6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) } isp24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) } u;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) uint16_t reserved_7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) __le16 ox_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) * ISP request and response queue entry sizes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) #define RESPONSE_ENTRY_SIZE (sizeof(response_t))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) #define REQUEST_ENTRY_SIZE (sizeof(request_t))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) * Switch info gathering structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) port_id_t d_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) uint8_t node_name[WWN_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) uint8_t port_name[WWN_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) uint8_t fabric_port_name[WWN_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) uint16_t fp_speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) uint8_t fc4_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) uint8_t fc4_features;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) } sw_info_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) /* FCP-4 types */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) #define FC4_TYPE_FCP_SCSI 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) #define FC4_TYPE_NVME 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) #define FC4_TYPE_OTHER 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) #define FC4_TYPE_UNKNOWN 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) /* mailbox command 4G & above */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) struct mbx_24xx_entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) uint8_t entry_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) uint8_t entry_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) uint8_t sys_define1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) uint8_t entry_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) uint32_t handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) uint16_t mb[28];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) #define IOCB_SIZE 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) * Fibre channel port type.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) typedef enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) FCT_UNKNOWN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) FCT_RSCN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) FCT_SWITCH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) FCT_BROADCAST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) FCT_INITIATOR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) FCT_TARGET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) FCT_NVME_INITIATOR = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) FCT_NVME_TARGET = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) FCT_NVME_DISCOVERY = 0x40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) FCT_NVME = 0xf0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) } fc_port_type_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) enum qla_sess_deletion {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) QLA_SESS_DELETION_NONE = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) QLA_SESS_DELETION_IN_PROGRESS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) QLA_SESS_DELETED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) enum qlt_plogi_link_t {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) QLT_PLOGI_LINK_SAME_WWN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) QLT_PLOGI_LINK_CONFLICT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) QLT_PLOGI_LINK_MAX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) struct qlt_plogi_ack_t {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) struct list_head list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) struct imm_ntfy_from_isp iocb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) port_id_t id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) int ref_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) void *fcport;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) struct ct_sns_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) struct ct_sns_pkt *ct_sns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) dma_addr_t ct_sns_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) enum discovery_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) DSC_DELETED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) DSC_GNN_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) DSC_GNL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) DSC_LOGIN_PEND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) DSC_LOGIN_FAILED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) DSC_GPDB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) DSC_UPD_FCPORT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) DSC_LOGIN_COMPLETE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) DSC_ADISC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) DSC_DELETE_PEND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) enum login_state { /* FW control Target side */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) DSC_LS_LLIOCB_SENT = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) DSC_LS_PLOGI_PEND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) DSC_LS_PLOGI_COMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) DSC_LS_PRLI_PEND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) DSC_LS_PRLI_COMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) DSC_LS_PORT_UNAVAIL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) DSC_LS_PRLO_PEND = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) DSC_LS_LOGO_PEND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) enum rscn_addr_format {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) RSCN_PORT_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) RSCN_AREA_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) RSCN_DOM_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) RSCN_FAB_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) * Fibre channel port structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) typedef struct fc_port {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) struct list_head list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) struct scsi_qla_host *vha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) unsigned int conf_compl_supported:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) unsigned int deleted:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) unsigned int free_pending:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) unsigned int local:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) unsigned int logout_on_delete:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) unsigned int logo_ack_needed:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) unsigned int keep_nport_handle:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) unsigned int send_els_logo:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) unsigned int login_pause:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) unsigned int login_succ:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) unsigned int query:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) unsigned int id_changed:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) unsigned int scan_needed:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) unsigned int n2n_flag:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) unsigned int explicit_logout:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) unsigned int prli_pend_timer:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) uint8_t nvme_flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) uint8_t node_name[WWN_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) uint8_t port_name[WWN_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) port_id_t d_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) uint16_t loop_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) uint16_t old_loop_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) struct completion nvme_del_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) uint32_t nvme_prli_service_param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) #define NVME_PRLI_SP_PI_CTRL BIT_9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) #define NVME_PRLI_SP_SLER BIT_8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) #define NVME_PRLI_SP_CONF BIT_7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) #define NVME_PRLI_SP_INITIATOR BIT_5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) #define NVME_PRLI_SP_TARGET BIT_4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) #define NVME_PRLI_SP_DISCOVERY BIT_3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) #define NVME_PRLI_SP_FIRST_BURST BIT_0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) uint32_t nvme_first_burst_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) #define NVME_FLAG_REGISTERED 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) #define NVME_FLAG_DELETING 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) #define NVME_FLAG_RESETTING 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) struct fc_port *conflict;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) unsigned char logout_completed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) int generation;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) struct se_session *se_sess;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) struct kref sess_kref;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) struct qla_tgt *tgt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) unsigned long expires;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) struct list_head del_list_entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) struct work_struct free_work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) struct work_struct reg_work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) uint64_t jiffies_at_registration;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) unsigned long prli_expired;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) struct qlt_plogi_ack_t *plogi_link[QLT_PLOGI_LINK_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) uint16_t tgt_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) uint16_t old_tgt_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) uint16_t sec_since_registration;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) uint8_t fcp_prio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) uint8_t fabric_port_name[WWN_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) uint16_t fp_speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) fc_port_type_t port_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) atomic_t state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) uint32_t flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) int login_retry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) struct fc_rport *rport, *drport;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) u32 supported_classes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) uint8_t fc4_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) uint8_t fc4_features;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) uint8_t scan_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) unsigned long last_queue_full;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530) unsigned long last_ramp_up;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) uint16_t port_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) struct nvme_fc_remote_port *nvme_remote_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) unsigned long retry_delay_timestamp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) struct qla_tgt_sess *tgt_session;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) struct ct_sns_desc ct_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) enum discovery_state disc_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) atomic_t shadow_disc_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) enum discovery_state next_disc_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) enum login_state fw_login_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) unsigned long dm_login_expire;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) unsigned long plogi_nack_done_deadline;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) u32 login_gen, last_login_gen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) u32 rscn_gen, last_rscn_gen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) u32 chip_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) struct list_head gnl_entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) struct work_struct del_work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) u8 iocb[IOCB_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) u8 current_login_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) u8 last_login_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) u16 n2n_link_reset_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) u16 n2n_chip_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) struct dentry *dfs_rport_dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) } fc_port_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) FC4_PRIORITY_NVME = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562) FC4_PRIORITY_FCP = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) #define QLA_FCPORT_SCAN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) #define QLA_FCPORT_FOUND 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) struct event_arg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) fc_port_t *fcport;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) srb_t *sp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571) port_id_t id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) u16 data[2], rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) u8 port_name[WWN_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) u32 iop[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) #include "qla_mr.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580) * Fibre channel port/lun states.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) #define FCS_UNCONFIGURED 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583) #define FCS_DEVICE_DEAD 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584) #define FCS_DEVICE_LOST 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) #define FCS_ONLINE 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) extern const char *const port_state_str[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589) static const char * const port_dstate_str[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) "DELETED",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) "GNN_ID",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592) "GNL",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) "LOGIN_PEND",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) "LOGIN_FAILED",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595) "GPDB",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596) "UPD_FCPORT",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) "LOGIN_COMPLETE",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598) "ADISC",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) "DELETE_PEND"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603) * FC port flags.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605) #define FCF_FABRIC_DEVICE BIT_0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606) #define FCF_LOGIN_NEEDED BIT_1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607) #define FCF_FCP2_DEVICE BIT_2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608) #define FCF_ASYNC_SENT BIT_3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609) #define FCF_CONF_COMP_SUPPORTED BIT_4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) #define FCF_ASYNC_ACTIVE BIT_5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612) /* No loop ID flag. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) #define FC_NO_LOOP_ID 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616) * FC-CT interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618) * NOTE: All structures are big-endian in form.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621) #define CT_REJECT_RESPONSE 0x8001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622) #define CT_ACCEPT_RESPONSE 0x8002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623) #define CT_REASON_INVALID_COMMAND_CODE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624) #define CT_REASON_CANNOT_PERFORM 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625) #define CT_REASON_COMMAND_UNSUPPORTED 0x0b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626) #define CT_EXPL_ALREADY_REGISTERED 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) #define CT_EXPL_HBA_ATTR_NOT_REGISTERED 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628) #define CT_EXPL_MULTIPLE_HBA_ATTR 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629) #define CT_EXPL_INVALID_HBA_BLOCK_LENGTH 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630) #define CT_EXPL_MISSING_REQ_HBA_ATTR 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631) #define CT_EXPL_PORT_NOT_REGISTERED_ 0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632) #define CT_EXPL_MISSING_HBA_ID_PORT_LIST 0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) #define CT_EXPL_HBA_NOT_REGISTERED 0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634) #define CT_EXPL_PORT_ATTR_NOT_REGISTERED 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635) #define CT_EXPL_PORT_NOT_REGISTERED 0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636) #define CT_EXPL_MULTIPLE_PORT_ATTR 0x22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637) #define CT_EXPL_INVALID_PORT_BLOCK_LENGTH 0x23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639) #define NS_N_PORT_TYPE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640) #define NS_NL_PORT_TYPE 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641) #define NS_NX_PORT_TYPE 0x7F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643) #define GA_NXT_CMD 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644) #define GA_NXT_REQ_SIZE (16 + 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645) #define GA_NXT_RSP_SIZE (16 + 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647) #define GPN_FT_CMD 0x172
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648) #define GPN_FT_REQ_SIZE (16 + 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649) #define GNN_FT_CMD 0x173
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650) #define GNN_FT_REQ_SIZE (16 + 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652) #define GID_PT_CMD 0x1A1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653) #define GID_PT_REQ_SIZE (16 + 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655) #define GPN_ID_CMD 0x112
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656) #define GPN_ID_REQ_SIZE (16 + 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657) #define GPN_ID_RSP_SIZE (16 + 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659) #define GNN_ID_CMD 0x113
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660) #define GNN_ID_REQ_SIZE (16 + 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661) #define GNN_ID_RSP_SIZE (16 + 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663) #define GFT_ID_CMD 0x117
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664) #define GFT_ID_REQ_SIZE (16 + 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665) #define GFT_ID_RSP_SIZE (16 + 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667) #define GID_PN_CMD 0x121
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668) #define GID_PN_REQ_SIZE (16 + 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669) #define GID_PN_RSP_SIZE (16 + 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671) #define RFT_ID_CMD 0x217
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672) #define RFT_ID_REQ_SIZE (16 + 4 + 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673) #define RFT_ID_RSP_SIZE 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675) #define RFF_ID_CMD 0x21F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676) #define RFF_ID_REQ_SIZE (16 + 4 + 2 + 1 + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677) #define RFF_ID_RSP_SIZE 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679) #define RNN_ID_CMD 0x213
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680) #define RNN_ID_REQ_SIZE (16 + 4 + 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681) #define RNN_ID_RSP_SIZE 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683) #define RSNN_NN_CMD 0x239
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684) #define RSNN_NN_REQ_SIZE (16 + 8 + 1 + 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685) #define RSNN_NN_RSP_SIZE 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687) #define GFPN_ID_CMD 0x11C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688) #define GFPN_ID_REQ_SIZE (16 + 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689) #define GFPN_ID_RSP_SIZE (16 + 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691) #define GPSC_CMD 0x127
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692) #define GPSC_REQ_SIZE (16 + 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693) #define GPSC_RSP_SIZE (16 + 2 + 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695) #define GFF_ID_CMD 0x011F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696) #define GFF_ID_REQ_SIZE (16 + 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697) #define GFF_ID_RSP_SIZE (16 + 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700) * FDMI HBA attribute types.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702) #define FDMI1_HBA_ATTR_COUNT 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703) #define FDMI2_HBA_ATTR_COUNT 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705) #define FDMI_HBA_NODE_NAME 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706) #define FDMI_HBA_MANUFACTURER 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707) #define FDMI_HBA_SERIAL_NUMBER 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708) #define FDMI_HBA_MODEL 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709) #define FDMI_HBA_MODEL_DESCRIPTION 0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710) #define FDMI_HBA_HARDWARE_VERSION 0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711) #define FDMI_HBA_DRIVER_VERSION 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712) #define FDMI_HBA_OPTION_ROM_VERSION 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713) #define FDMI_HBA_FIRMWARE_VERSION 0x9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714) #define FDMI_HBA_OS_NAME_AND_VERSION 0xa
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715) #define FDMI_HBA_MAXIMUM_CT_PAYLOAD_LENGTH 0xb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717) #define FDMI_HBA_NODE_SYMBOLIC_NAME 0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718) #define FDMI_HBA_VENDOR_SPECIFIC_INFO 0xd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2719) #define FDMI_HBA_NUM_PORTS 0xe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2720) #define FDMI_HBA_FABRIC_NAME 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2721) #define FDMI_HBA_BOOT_BIOS_NAME 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2722) #define FDMI_HBA_VENDOR_IDENTIFIER 0xe0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2724) struct ct_fdmi_hba_attr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2725) __be16 type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2726) __be16 len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2727) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2728) uint8_t node_name[WWN_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2729) uint8_t manufacturer[64];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2730) uint8_t serial_num[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2731) uint8_t model[16+1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2732) uint8_t model_desc[80];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2733) uint8_t hw_version[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2734) uint8_t driver_version[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2735) uint8_t orom_version[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2736) uint8_t fw_version[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2737) uint8_t os_version[128];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2738) __be32 max_ct_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2740) uint8_t sym_name[256];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2741) __be32 vendor_specific_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2742) __be32 num_ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2743) uint8_t fabric_name[WWN_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2744) uint8_t bios_name[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2745) uint8_t vendor_identifier[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2746) } a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2747) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2749) struct ct_fdmi1_hba_attributes {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2750) __be32 count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2751) struct ct_fdmi_hba_attr entry[FDMI1_HBA_ATTR_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2752) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2754) struct ct_fdmi2_hba_attributes {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2755) __be32 count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2756) struct ct_fdmi_hba_attr entry[FDMI2_HBA_ATTR_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2757) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2759) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2760) * FDMI Port attribute types.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2761) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2762) #define FDMI1_PORT_ATTR_COUNT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2763) #define FDMI2_PORT_ATTR_COUNT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2764) #define FDMI2_SMARTSAN_PORT_ATTR_COUNT 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2766) #define FDMI_PORT_FC4_TYPES 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2767) #define FDMI_PORT_SUPPORT_SPEED 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2768) #define FDMI_PORT_CURRENT_SPEED 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2769) #define FDMI_PORT_MAX_FRAME_SIZE 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2770) #define FDMI_PORT_OS_DEVICE_NAME 0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2771) #define FDMI_PORT_HOST_NAME 0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2773) #define FDMI_PORT_NODE_NAME 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2774) #define FDMI_PORT_NAME 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2775) #define FDMI_PORT_SYM_NAME 0x9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2776) #define FDMI_PORT_TYPE 0xa
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2777) #define FDMI_PORT_SUPP_COS 0xb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2778) #define FDMI_PORT_FABRIC_NAME 0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2779) #define FDMI_PORT_FC4_TYPE 0xd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2780) #define FDMI_PORT_STATE 0x101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2781) #define FDMI_PORT_COUNT 0x102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2782) #define FDMI_PORT_IDENTIFIER 0x103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2784) #define FDMI_SMARTSAN_SERVICE 0xF100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2785) #define FDMI_SMARTSAN_GUID 0xF101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2786) #define FDMI_SMARTSAN_VERSION 0xF102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2787) #define FDMI_SMARTSAN_PROD_NAME 0xF103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2788) #define FDMI_SMARTSAN_PORT_INFO 0xF104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2789) #define FDMI_SMARTSAN_QOS_SUPPORT 0xF105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2790) #define FDMI_SMARTSAN_SECURITY_SUPPORT 0xF106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2792) #define FDMI_PORT_SPEED_1GB 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2793) #define FDMI_PORT_SPEED_2GB 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2794) #define FDMI_PORT_SPEED_10GB 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2795) #define FDMI_PORT_SPEED_4GB 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2796) #define FDMI_PORT_SPEED_8GB 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2797) #define FDMI_PORT_SPEED_16GB 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2798) #define FDMI_PORT_SPEED_32GB 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2799) #define FDMI_PORT_SPEED_20GB 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2800) #define FDMI_PORT_SPEED_40GB 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2801) #define FDMI_PORT_SPEED_128GB 0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2802) #define FDMI_PORT_SPEED_64GB 0x400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2803) #define FDMI_PORT_SPEED_256GB 0x800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2804) #define FDMI_PORT_SPEED_UNKNOWN 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2806) #define FC_CLASS_2 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2807) #define FC_CLASS_3 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2808) #define FC_CLASS_2_3 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2810) struct ct_fdmi_port_attr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2811) __be16 type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2812) __be16 len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2813) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2814) uint8_t fc4_types[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2815) __be32 sup_speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2816) __be32 cur_speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2817) __be32 max_frame_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2818) uint8_t os_dev_name[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2819) uint8_t host_name[256];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2821) uint8_t node_name[WWN_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2822) uint8_t port_name[WWN_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2823) uint8_t port_sym_name[128];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2824) __be32 port_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2825) __be32 port_supported_cos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2826) uint8_t fabric_name[WWN_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2827) uint8_t port_fc4_type[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2828) __be32 port_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2829) __be32 num_ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2830) __be32 port_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2832) uint8_t smartsan_service[24];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2833) uint8_t smartsan_guid[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2834) uint8_t smartsan_version[24];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2835) uint8_t smartsan_prod_name[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2836) __be32 smartsan_port_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2837) __be32 smartsan_qos_support;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2838) __be32 smartsan_security_support;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2839) } a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2840) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2842) struct ct_fdmi1_port_attributes {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2843) __be32 count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2844) struct ct_fdmi_port_attr entry[FDMI1_PORT_ATTR_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2845) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2847) struct ct_fdmi2_port_attributes {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2848) __be32 count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2849) struct ct_fdmi_port_attr entry[FDMI2_PORT_ATTR_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2850) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2852) #define FDMI_ATTR_TYPELEN(obj) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2853) (sizeof((obj)->type) + sizeof((obj)->len))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2855) #define FDMI_ATTR_ALIGNMENT(len) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2856) (4 - ((len) & 3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2858) /* FDMI register call options */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2859) #define CALLOPT_FDMI1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2860) #define CALLOPT_FDMI2 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2861) #define CALLOPT_FDMI2_SMARTSAN 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2863) /* FDMI definitions. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2864) #define GRHL_CMD 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2865) #define GHAT_CMD 0x101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2866) #define GRPL_CMD 0x102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2867) #define GPAT_CMD 0x110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2869) #define RHBA_CMD 0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2870) #define RHBA_RSP_SIZE 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2872) #define RHAT_CMD 0x201
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2874) #define RPRT_CMD 0x210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2875) #define RPRT_RSP_SIZE 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2877) #define RPA_CMD 0x211
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2878) #define RPA_RSP_SIZE 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2879) #define SMARTSAN_RPA_RSP_SIZE 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2881) #define DHBA_CMD 0x300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2882) #define DHBA_REQ_SIZE (16 + 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2883) #define DHBA_RSP_SIZE 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2885) #define DHAT_CMD 0x301
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2886) #define DPRT_CMD 0x310
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2887) #define DPA_CMD 0x311
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2889) /* CT command header -- request/response common fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2890) struct ct_cmd_hdr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2891) uint8_t revision;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2892) uint8_t in_id[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2893) uint8_t gs_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2894) uint8_t gs_subtype;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2895) uint8_t options;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2896) uint8_t reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2897) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2899) /* CT command request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2900) struct ct_sns_req {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2901) struct ct_cmd_hdr header;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2902) __be16 command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2903) __be16 max_rsp_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2904) uint8_t fragment_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2905) uint8_t reserved[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2907) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2908) /* GA_NXT, GPN_ID, GNN_ID, GFT_ID, GFPN_ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2909) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2910) uint8_t reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2911) be_id_t port_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2912) } port_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2914) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2915) uint8_t reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2916) uint8_t domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2917) uint8_t area;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2918) uint8_t port_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2919) } gpn_ft;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2921) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2922) uint8_t port_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2923) uint8_t domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2924) uint8_t area;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2925) uint8_t reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2926) } gid_pt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2928) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2929) uint8_t reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2930) be_id_t port_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2931) uint8_t fc4_types[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2932) } rft_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2934) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2935) uint8_t reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2936) be_id_t port_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2937) uint16_t reserved2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2938) uint8_t fc4_feature;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2939) uint8_t fc4_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2940) } rff_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2942) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2943) uint8_t reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2944) be_id_t port_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2945) uint8_t node_name[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2946) } rnn_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2948) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2949) uint8_t node_name[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2950) uint8_t name_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2951) uint8_t sym_node_name[255];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2952) } rsnn_nn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2954) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2955) uint8_t hba_identifier[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2956) } ghat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2958) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2959) uint8_t hba_identifier[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2960) __be32 entry_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2961) uint8_t port_name[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2962) struct ct_fdmi2_hba_attributes attrs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2963) } rhba;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2965) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2966) uint8_t hba_identifier[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2967) struct ct_fdmi1_hba_attributes attrs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2968) } rhat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2970) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2971) uint8_t port_name[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2972) struct ct_fdmi2_port_attributes attrs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2973) } rpa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2975) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2976) uint8_t hba_identifier[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2977) uint8_t port_name[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2978) struct ct_fdmi2_port_attributes attrs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2979) } rprt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2981) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2982) uint8_t port_name[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2983) } dhba;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2985) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2986) uint8_t port_name[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2987) } dhat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2989) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2990) uint8_t port_name[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2991) } dprt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2993) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2994) uint8_t port_name[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2995) } dpa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2997) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2998) uint8_t port_name[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2999) } gpsc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3001) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3002) uint8_t reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3003) uint8_t port_id[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3004) } gff_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3006) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3007) uint8_t port_name[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3008) } gid_pn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3009) } req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3010) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3012) /* CT command response header */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3013) struct ct_rsp_hdr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3014) struct ct_cmd_hdr header;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3015) __be16 response;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3016) uint16_t residual;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3017) uint8_t fragment_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3018) uint8_t reason_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3019) uint8_t explanation_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3020) uint8_t vendor_unique;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3021) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3023) struct ct_sns_gid_pt_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3024) uint8_t control_byte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3025) be_id_t port_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3026) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3028) /* It's the same for both GPN_FT and GNN_FT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3029) struct ct_sns_gpnft_rsp {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3030) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3031) struct ct_cmd_hdr header;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3032) uint16_t response;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3033) uint16_t residual;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3034) uint8_t fragment_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3035) uint8_t reason_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3036) uint8_t explanation_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3037) uint8_t vendor_unique;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3038) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3039) /* Assume the largest number of targets for the union */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3040) struct ct_sns_gpn_ft_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3041) u8 control_byte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3042) u8 port_id[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3043) u32 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3044) u8 port_name[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3045) } entries[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3046) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3048) /* CT command response */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3049) struct ct_sns_rsp {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3050) struct ct_rsp_hdr header;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3052) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3053) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3054) uint8_t port_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3055) be_id_t port_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3056) uint8_t port_name[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3057) uint8_t sym_port_name_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3058) uint8_t sym_port_name[255];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3059) uint8_t node_name[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3060) uint8_t sym_node_name_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3061) uint8_t sym_node_name[255];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3062) uint8_t init_proc_assoc[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3063) uint8_t node_ip_addr[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3064) uint8_t class_of_service[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3065) uint8_t fc4_types[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3066) uint8_t ip_address[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3067) uint8_t fabric_port_name[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3068) uint8_t reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3069) uint8_t hard_address[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3070) } ga_nxt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3072) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3073) /* Assume the largest number of targets for the union */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3074) struct ct_sns_gid_pt_data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3075) entries[MAX_FIBRE_DEVICES_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3076) } gid_pt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3078) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3079) uint8_t port_name[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3080) } gpn_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3082) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3083) uint8_t node_name[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3084) } gnn_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3086) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3087) uint8_t fc4_types[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3088) } gft_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3090) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3091) uint32_t entry_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3092) uint8_t port_name[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3093) struct ct_fdmi1_hba_attributes attrs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3094) } ghat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3096) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3097) uint8_t port_name[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3098) } gfpn_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3100) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3101) __be16 speeds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3102) __be16 speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3103) } gpsc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3105) #define GFF_FCP_SCSI_OFFSET 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3106) #define GFF_NVME_OFFSET 23 /* type = 28h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3107) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3108) uint8_t fc4_features[128];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3109) } gff_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3110) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3111) uint8_t reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3112) uint8_t port_id[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3113) } gid_pn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3114) } rsp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3115) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3117) struct ct_sns_pkt {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3118) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3119) struct ct_sns_req req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3120) struct ct_sns_rsp rsp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3121) } p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3122) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3124) struct ct_sns_gpnft_pkt {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3125) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3126) struct ct_sns_req req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3127) struct ct_sns_gpnft_rsp rsp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3128) } p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3129) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3131) enum scan_flags_t {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3132) SF_SCANNING = BIT_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3133) SF_QUEUED = BIT_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3134) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3136) enum fc4type_t {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3137) FS_FC4TYPE_FCP = BIT_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3138) FS_FC4TYPE_NVME = BIT_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3139) FS_FCP_IS_N2N = BIT_7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3140) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3142) struct fab_scan_rp {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3143) port_id_t id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3144) enum fc4type_t fc4type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3145) u8 port_name[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3146) u8 node_name[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3147) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3149) struct fab_scan {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3150) struct fab_scan_rp *l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3151) u32 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3152) u16 scan_retry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3153) #define MAX_SCAN_RETRIES 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3154) enum scan_flags_t scan_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3155) struct delayed_work scan_work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3156) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3158) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3159) * SNS command structures -- for 2200 compatibility.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3160) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3161) #define RFT_ID_SNS_SCMD_LEN 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3162) #define RFT_ID_SNS_CMD_SIZE 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3163) #define RFT_ID_SNS_DATA_SIZE 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3165) #define RNN_ID_SNS_SCMD_LEN 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3166) #define RNN_ID_SNS_CMD_SIZE 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3167) #define RNN_ID_SNS_DATA_SIZE 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3169) #define GA_NXT_SNS_SCMD_LEN 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3170) #define GA_NXT_SNS_CMD_SIZE 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3171) #define GA_NXT_SNS_DATA_SIZE (620 + 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3173) #define GID_PT_SNS_SCMD_LEN 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3174) #define GID_PT_SNS_CMD_SIZE 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3175) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3176) * Assume MAX_FIBRE_DEVICES_2100 as these defines are only used with older
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3177) * adapters.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3178) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3179) #define GID_PT_SNS_DATA_SIZE (MAX_FIBRE_DEVICES_2100 * 4 + 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3181) #define GPN_ID_SNS_SCMD_LEN 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3182) #define GPN_ID_SNS_CMD_SIZE 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3183) #define GPN_ID_SNS_DATA_SIZE (8 + 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3185) #define GNN_ID_SNS_SCMD_LEN 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3186) #define GNN_ID_SNS_CMD_SIZE 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3187) #define GNN_ID_SNS_DATA_SIZE (8 + 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3189) struct sns_cmd_pkt {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3190) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3191) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3192) __le16 buffer_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3193) __le16 reserved_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3194) __le64 buffer_address __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3195) __le16 subcommand_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3196) __le16 reserved_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3197) __le16 subcommand;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3198) __le16 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3199) uint32_t reserved_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3200) uint8_t param[36];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3201) } cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3203) uint8_t rft_data[RFT_ID_SNS_DATA_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3204) uint8_t rnn_data[RNN_ID_SNS_DATA_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3205) uint8_t gan_data[GA_NXT_SNS_DATA_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3206) uint8_t gid_data[GID_PT_SNS_DATA_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3207) uint8_t gpn_data[GPN_ID_SNS_DATA_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3208) uint8_t gnn_data[GNN_ID_SNS_DATA_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3209) } p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3210) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3212) struct fw_blob {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3213) char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3214) uint32_t segs[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3215) const struct firmware *fw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3216) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3218) /* Return data from MBC_GET_ID_LIST call. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3219) struct gid_list_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3220) uint8_t al_pa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3221) uint8_t area;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3222) uint8_t domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3223) uint8_t loop_id_2100; /* ISP2100/ISP2200 -- 4 bytes. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3224) __le16 loop_id; /* ISP23XX -- 6 bytes. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3225) uint16_t reserved_1; /* ISP24XX -- 8 bytes. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3226) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3228) /* NPIV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3229) typedef struct vport_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3230) uint8_t port_name[WWN_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3231) uint8_t node_name[WWN_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3232) int vp_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3233) uint16_t loop_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3234) unsigned long host_no;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3235) uint8_t port_id[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3236) int loop_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3237) } vport_info_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3239) typedef struct vport_params {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3240) uint8_t port_name[WWN_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3241) uint8_t node_name[WWN_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3242) uint32_t options;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3243) #define VP_OPTS_RETRY_ENABLE BIT_0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3244) #define VP_OPTS_VP_DISABLE BIT_1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3245) } vport_params_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3247) /* NPIV - return codes of VP create and modify */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3248) #define VP_RET_CODE_OK 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3249) #define VP_RET_CODE_FATAL 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3250) #define VP_RET_CODE_WRONG_ID 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3251) #define VP_RET_CODE_WWPN 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3252) #define VP_RET_CODE_RESOURCES 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3253) #define VP_RET_CODE_NO_MEM 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3254) #define VP_RET_CODE_NOT_FOUND 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3256) struct qla_hw_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3257) struct rsp_que;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3258) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3259) * ISP operations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3260) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3261) struct isp_operations {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3263) int (*pci_config) (struct scsi_qla_host *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3264) int (*reset_chip)(struct scsi_qla_host *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3265) int (*chip_diag) (struct scsi_qla_host *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3266) void (*config_rings) (struct scsi_qla_host *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3267) int (*reset_adapter)(struct scsi_qla_host *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3268) int (*nvram_config) (struct scsi_qla_host *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3269) void (*update_fw_options) (struct scsi_qla_host *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3270) int (*load_risc) (struct scsi_qla_host *, uint32_t *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3272) char * (*pci_info_str)(struct scsi_qla_host *, char *, size_t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3273) char * (*fw_version_str)(struct scsi_qla_host *, char *, size_t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3275) irq_handler_t intr_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3276) void (*enable_intrs) (struct qla_hw_data *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3277) void (*disable_intrs) (struct qla_hw_data *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3279) int (*abort_command) (srb_t *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3280) int (*target_reset) (struct fc_port *, uint64_t, int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3281) int (*lun_reset) (struct fc_port *, uint64_t, int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3282) int (*fabric_login) (struct scsi_qla_host *, uint16_t, uint8_t,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3283) uint8_t, uint8_t, uint16_t *, uint8_t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3284) int (*fabric_logout) (struct scsi_qla_host *, uint16_t, uint8_t,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3285) uint8_t, uint8_t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3287) uint16_t (*calc_req_entries) (uint16_t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3288) void (*build_iocbs) (srb_t *, cmd_entry_t *, uint16_t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3289) void *(*prep_ms_iocb) (struct scsi_qla_host *, struct ct_arg *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3290) void *(*prep_ms_fdmi_iocb) (struct scsi_qla_host *, uint32_t,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3291) uint32_t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3293) uint8_t *(*read_nvram)(struct scsi_qla_host *, void *,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3294) uint32_t, uint32_t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3295) int (*write_nvram)(struct scsi_qla_host *, void *, uint32_t,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3296) uint32_t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3298) void (*fw_dump)(struct scsi_qla_host *vha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3299) void (*mpi_fw_dump)(struct scsi_qla_host *, int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3301) int (*beacon_on) (struct scsi_qla_host *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3302) int (*beacon_off) (struct scsi_qla_host *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3303) void (*beacon_blink) (struct scsi_qla_host *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3305) void *(*read_optrom)(struct scsi_qla_host *, void *,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3306) uint32_t, uint32_t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3307) int (*write_optrom)(struct scsi_qla_host *, void *, uint32_t,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3308) uint32_t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3310) int (*get_flash_version) (struct scsi_qla_host *, void *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3311) int (*start_scsi) (srb_t *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3312) int (*start_scsi_mq) (srb_t *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3313) int (*abort_isp) (struct scsi_qla_host *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3314) int (*iospace_config)(struct qla_hw_data *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3315) int (*initialize_adapter)(struct scsi_qla_host *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3316) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3318) /* MSI-X Support *************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3320) #define QLA_MSIX_CHIP_REV_24XX 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3321) #define QLA_MSIX_FW_MODE(m) (((m) & (BIT_7|BIT_8|BIT_9)) >> 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3322) #define QLA_MSIX_FW_MODE_1(m) (QLA_MSIX_FW_MODE(m) == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3324) #define QLA_BASE_VECTORS 2 /* default + RSP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3325) #define QLA_MSIX_RSP_Q 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3326) #define QLA_ATIO_VECTOR 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3327) #define QLA_MSIX_QPAIR_MULTIQ_RSP_Q 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3328) #define QLA_MSIX_QPAIR_MULTIQ_RSP_Q_HS 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3330) #define QLA_MIDX_DEFAULT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3331) #define QLA_MIDX_RSP_Q 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3332) #define QLA_PCI_MSIX_CONTROL 0xa2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3333) #define QLA_83XX_PCI_MSIX_CONTROL 0x92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3335) struct scsi_qla_host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3338) #define QLA83XX_RSPQ_MSIX_ENTRY_NUMBER 1 /* refer to qla83xx_msix_entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3340) struct qla_msix_entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3341) int have_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3342) int in_use;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3343) uint32_t vector;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3344) uint16_t entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3345) char name[30];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3346) void *handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3347) int cpuid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3348) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3350) #define WATCH_INTERVAL 1 /* number of seconds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3352) /* Work events. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3353) enum qla_work_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3354) QLA_EVT_AEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3355) QLA_EVT_IDC_ACK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3356) QLA_EVT_ASYNC_LOGIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3357) QLA_EVT_ASYNC_LOGOUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3358) QLA_EVT_ASYNC_ADISC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3359) QLA_EVT_UEVENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3360) QLA_EVT_AENFX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3361) QLA_EVT_GPNID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3362) QLA_EVT_UNMAP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3363) QLA_EVT_NEW_SESS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3364) QLA_EVT_GPDB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3365) QLA_EVT_PRLI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3366) QLA_EVT_GPSC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3367) QLA_EVT_GNL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3368) QLA_EVT_NACK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3369) QLA_EVT_RELOGIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3370) QLA_EVT_ASYNC_PRLO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3371) QLA_EVT_ASYNC_PRLO_DONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3372) QLA_EVT_GPNFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3373) QLA_EVT_GPNFT_DONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3374) QLA_EVT_GNNFT_DONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3375) QLA_EVT_GNNID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3376) QLA_EVT_GFPNID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3377) QLA_EVT_SP_RETRY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3378) QLA_EVT_IIDMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3379) QLA_EVT_ELS_PLOGI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3380) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3383) struct qla_work_evt {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3384) struct list_head list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3385) enum qla_work_type type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3386) u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3387) #define QLA_EVT_FLAG_FREE 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3389) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3390) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3391) enum fc_host_event_code code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3392) u32 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3393) } aen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3394) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3395) #define QLA_IDC_ACK_REGS 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3396) uint16_t mb[QLA_IDC_ACK_REGS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3397) } idc_ack;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3398) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3399) struct fc_port *fcport;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3400) #define QLA_LOGIO_LOGIN_RETRIED BIT_0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3401) u16 data[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3402) } logio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3403) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3404) u32 code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3405) #define QLA_UEVENT_CODE_FW_DUMP 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3406) } uevent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3407) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3408) uint32_t evtcode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3409) uint32_t mbx[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3410) uint32_t count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3411) } aenfx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3412) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3413) srb_t *sp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3414) } iosb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3415) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3416) port_id_t id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3417) } gpnid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3418) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3419) port_id_t id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3420) u8 port_name[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3421) u8 node_name[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3422) void *pla;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3423) u8 fc4_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3424) } new_sess;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3425) struct { /*Get PDB, Get Speed, update fcport, gnl, gidpn */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3426) fc_port_t *fcport;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3427) u8 opt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3428) } fcport;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3429) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3430) fc_port_t *fcport;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3431) u8 iocb[IOCB_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3432) int type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3433) } nack;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3434) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3435) u8 fc4_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3436) srb_t *sp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3437) } gpnft;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3438) } u;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3439) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3441) struct qla_chip_state_84xx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3442) struct list_head list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3443) struct kref kref;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3445) void *bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3446) spinlock_t access_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3447) struct mutex fw_update_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3448) uint32_t fw_update;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3449) uint32_t op_fw_version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3450) uint32_t op_fw_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3451) uint32_t op_fw_seq_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3452) uint32_t diag_fw_version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3453) uint32_t gold_fw_version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3454) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3456) struct qla_dif_statistics {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3457) uint64_t dif_input_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3458) uint64_t dif_output_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3459) uint64_t dif_input_requests;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3460) uint64_t dif_output_requests;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3461) uint32_t dif_guard_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3462) uint32_t dif_ref_tag_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3463) uint32_t dif_app_tag_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3464) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3466) struct qla_statistics {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3467) uint32_t total_isp_aborts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3468) uint64_t input_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3469) uint64_t output_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3470) uint64_t input_requests;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3471) uint64_t output_requests;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3472) uint32_t control_requests;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3474) uint64_t jiffies_at_last_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3475) uint32_t stat_max_pend_cmds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3476) uint32_t stat_max_qfull_cmds_alloc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3477) uint32_t stat_max_qfull_cmds_dropped;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3479) struct qla_dif_statistics qla_dif_stats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3480) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3482) struct bidi_statistics {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3483) unsigned long long io_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3484) unsigned long long transfer_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3485) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3487) struct qla_tc_param {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3488) struct scsi_qla_host *vha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3489) uint32_t blk_sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3490) uint32_t bufflen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3491) struct scatterlist *sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3492) struct scatterlist *prot_sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3493) struct crc_context *ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3494) uint8_t *ctx_dsd_alloced;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3495) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3497) /* Multi queue support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3498) #define MBC_INITIALIZE_MULTIQ 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3499) #define QLA_QUE_PAGE 0X1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3500) #define QLA_MQ_SIZE 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3501) #define QLA_MAX_QUEUES 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3502) #define ISP_QUE_REG(ha, id) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3503) ((ha->mqenable || IS_QLA83XX(ha) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3504) IS_QLA27XX(ha) || IS_QLA28XX(ha)) ? \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3505) ((void __iomem *)ha->mqiobase + (QLA_QUE_PAGE * id)) :\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3506) ((void __iomem *)ha->iobase))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3507) #define QLA_REQ_QUE_ID(tag) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3508) ((tag < QLA_MAX_QUEUES && tag > 0) ? tag : 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3509) #define QLA_DEFAULT_QUE_QOS 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3510) #define QLA_PRECONFIG_VPORTS 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3511) #define QLA_MAX_VPORTS_QLA24XX 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3512) #define QLA_MAX_VPORTS_QLA25XX 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3514) struct qla_tgt_counters {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3515) uint64_t qla_core_sbt_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3516) uint64_t core_qla_que_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3517) uint64_t qla_core_ret_ctio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3518) uint64_t core_qla_snd_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3519) uint64_t qla_core_ret_sta_ctio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3520) uint64_t core_qla_free_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3521) uint64_t num_q_full_sent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3522) uint64_t num_alloc_iocb_failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3523) uint64_t num_term_xchg_sent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3524) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3526) struct qla_counters {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3527) uint64_t input_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3528) uint64_t input_requests;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3529) uint64_t output_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3530) uint64_t output_requests;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3532) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3534) struct qla_qpair;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3536) /* Response queue data structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3537) struct rsp_que {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3538) dma_addr_t dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3539) response_t *ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3540) response_t *ring_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3541) __le32 __iomem *rsp_q_in; /* FWI2-capable only. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3542) __le32 __iomem *rsp_q_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3543) uint16_t ring_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3544) uint16_t out_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3545) uint16_t *in_ptr; /* queue shadow in index */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3546) uint16_t length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3547) uint16_t options;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3548) uint16_t rid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3549) uint16_t id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3550) uint16_t vp_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3551) struct qla_hw_data *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3552) struct qla_msix_entry *msix;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3553) struct req_que *req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3554) srb_t *status_srb; /* status continuation entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3555) struct qla_qpair *qpair;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3557) dma_addr_t dma_fx00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3558) response_t *ring_fx00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3559) uint16_t length_fx00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3560) uint8_t rsp_pkt[REQUEST_ENTRY_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3561) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3563) /* Request queue data structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3564) struct req_que {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3565) dma_addr_t dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3566) request_t *ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3567) request_t *ring_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3568) __le32 __iomem *req_q_in; /* FWI2-capable only. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3569) __le32 __iomem *req_q_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3570) uint16_t ring_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3571) uint16_t in_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3572) uint16_t *out_ptr; /* queue shadow out index */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3573) uint16_t cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3574) uint16_t length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3575) uint16_t options;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3576) uint16_t rid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3577) uint16_t id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3578) uint16_t qos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3579) uint16_t vp_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3580) struct rsp_que *rsp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3581) srb_t **outstanding_cmds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3582) uint32_t current_outstanding_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3583) uint16_t num_outstanding_cmds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3584) int max_q_depth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3586) dma_addr_t dma_fx00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3587) request_t *ring_fx00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3588) uint16_t length_fx00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3589) uint8_t req_pkt[REQUEST_ENTRY_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3590) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3592) struct qla_fw_resources {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3593) u16 iocbs_total;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3594) u16 iocbs_limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3595) u16 iocbs_qp_limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3596) u16 iocbs_used;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3597) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3599) #define QLA_IOCB_PCT_LIMIT 95
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3601) /*Queue pair data structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3602) struct qla_qpair {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3603) spinlock_t qp_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3604) atomic_t ref_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3605) uint32_t lun_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3606) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3607) * For qpair 0, qp_lock_ptr will point at hardware_lock due to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3608) * legacy code. For other Qpair(s), it will point at qp_lock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3609) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3610) spinlock_t *qp_lock_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3611) struct scsi_qla_host *vha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3612) u32 chip_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3614) /* distill these fields down to 'online=0/1'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3615) * ha->flags.eeh_busy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3616) * ha->flags.pci_channel_io_perm_failure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3617) * base_vha->loop_state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3618) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3619) uint32_t online:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3620) /* move vha->flags.difdix_supported here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3621) uint32_t difdix_supported:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3622) uint32_t delete_in_progress:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3623) uint32_t fw_started:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3624) uint32_t enable_class_2:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3625) uint32_t enable_explicit_conf:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3626) uint32_t use_shadow_reg:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3627) uint32_t rcv_intr:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3629) uint16_t id; /* qp number used with FW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3630) uint16_t vp_idx; /* vport ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3631) mempool_t *srb_mempool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3633) struct pci_dev *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3634) void (*reqq_start_iocbs)(struct qla_qpair *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3636) /* to do: New driver: move queues to here instead of pointers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3637) struct req_que *req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3638) struct rsp_que *rsp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3639) struct atio_que *atio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3640) struct qla_msix_entry *msix; /* point to &ha->msix_entries[x] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3641) struct qla_hw_data *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3642) struct work_struct q_work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3643) struct qla_counters counters;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3645) struct list_head qp_list_elem; /* vha->qp_list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3646) struct list_head hints_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3648) uint16_t retry_term_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3649) __le32 retry_term_exchg_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3650) uint64_t retry_term_jiff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3651) struct qla_tgt_counters tgt_counters;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3652) uint16_t cpuid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3653) struct qla_fw_resources fwres ____cacheline_aligned;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3654) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3656) /* Place holder for FW buffer parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3657) struct qlfc_fw {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3658) void *fw_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3659) dma_addr_t fw_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3660) uint32_t len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3661) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3663) struct rdp_req_payload {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3664) uint32_t els_request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3665) uint32_t desc_list_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3667) /* NPIV descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3668) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3669) uint32_t desc_tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3670) uint32_t desc_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3671) uint8_t reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3672) uint8_t nport_id[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3673) } npiv_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3674) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3676) struct rdp_rsp_payload {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3677) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3678) __be32 cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3679) __be32 len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3680) } hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3682) /* LS Request Info descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3683) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3684) __be32 desc_tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3685) __be32 desc_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3686) __be32 req_payload_word_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3687) } ls_req_info_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3689) /* LS Request Info descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3690) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3691) __be32 desc_tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3692) __be32 desc_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3693) __be32 req_payload_word_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3694) } ls_req_info_desc2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3696) /* SFP diagnostic param descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3697) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3698) __be32 desc_tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3699) __be32 desc_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3700) __be16 temperature;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3701) __be16 vcc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3702) __be16 tx_bias;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3703) __be16 tx_power;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3704) __be16 rx_power;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3705) __be16 sfp_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3706) } sfp_diag_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3708) /* Port Speed Descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3709) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3710) __be32 desc_tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3711) __be32 desc_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3712) __be16 speed_capab;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3713) __be16 operating_speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3714) } port_speed_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3716) /* Link Error Status Descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3717) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3718) __be32 desc_tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3719) __be32 desc_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3720) __be32 link_fail_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3721) __be32 loss_sync_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3722) __be32 loss_sig_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3723) __be32 prim_seq_err_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3724) __be32 inval_xmit_word_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3725) __be32 inval_crc_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3726) uint8_t pn_port_phy_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3727) uint8_t reserved[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3728) } ls_err_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3730) /* Port name description with diag param */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3731) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3732) __be32 desc_tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3733) __be32 desc_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3734) uint8_t WWNN[WWN_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3735) uint8_t WWPN[WWN_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3736) } port_name_diag_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3738) /* Port Name desc for Direct attached Fx_Port or Nx_Port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3739) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3740) __be32 desc_tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3741) __be32 desc_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3742) uint8_t WWNN[WWN_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3743) uint8_t WWPN[WWN_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3744) } port_name_direct_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3746) /* Buffer Credit descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3747) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3748) __be32 desc_tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3749) __be32 desc_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3750) __be32 fcport_b2b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3751) __be32 attached_fcport_b2b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3752) __be32 fcport_rtt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3753) } buffer_credit_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3755) /* Optical Element Data Descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3756) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3757) __be32 desc_tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3758) __be32 desc_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3759) __be16 high_alarm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3760) __be16 low_alarm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3761) __be16 high_warn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3762) __be16 low_warn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3763) __be32 element_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3764) } optical_elmt_desc[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3766) /* Optical Product Data Descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3767) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3768) __be32 desc_tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3769) __be32 desc_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3770) uint8_t vendor_name[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3771) uint8_t part_number[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3772) uint8_t serial_number[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3773) uint8_t revision[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3774) uint8_t date[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3775) } optical_prod_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3776) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3778) #define RDP_DESC_LEN(obj) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3779) (sizeof(obj) - sizeof((obj).desc_tag) - sizeof((obj).desc_len))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3781) #define RDP_PORT_SPEED_1GB BIT_15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3782) #define RDP_PORT_SPEED_2GB BIT_14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3783) #define RDP_PORT_SPEED_4GB BIT_13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3784) #define RDP_PORT_SPEED_10GB BIT_12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3785) #define RDP_PORT_SPEED_8GB BIT_11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3786) #define RDP_PORT_SPEED_16GB BIT_10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3787) #define RDP_PORT_SPEED_32GB BIT_9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3788) #define RDP_PORT_SPEED_64GB BIT_8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3789) #define RDP_PORT_SPEED_UNKNOWN BIT_0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3791) struct scsi_qlt_host {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3792) void *target_lport_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3793) struct mutex tgt_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3794) struct mutex tgt_host_action_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3795) struct qla_tgt *qla_tgt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3796) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3798) struct qlt_hw_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3799) /* Protected by hw lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3800) uint32_t node_name_set:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3802) dma_addr_t atio_dma; /* Physical address. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3803) struct atio *atio_ring; /* Base virtual address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3804) struct atio *atio_ring_ptr; /* Current address. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3805) uint16_t atio_ring_index; /* Current index. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3806) uint16_t atio_q_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3807) __le32 __iomem *atio_q_in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3808) __le32 __iomem *atio_q_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3810) struct qla_tgt_func_tmpl *tgt_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3811) struct qla_tgt_vp_map *tgt_vp_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3813) int saved_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3814) __le16 saved_exchange_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3815) __le32 saved_firmware_options_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3816) __le32 saved_firmware_options_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3817) __le32 saved_firmware_options_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3818) uint8_t saved_firmware_options[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3819) uint8_t saved_add_firmware_options[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3821) uint8_t tgt_node_name[WWN_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3823) struct dentry *dfs_tgt_sess;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3824) struct dentry *dfs_tgt_port_database;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3825) struct dentry *dfs_naqp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3827) struct list_head q_full_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3828) uint32_t num_pend_cmds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3829) uint32_t num_qfull_cmds_alloc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3830) uint32_t num_qfull_cmds_dropped;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3831) spinlock_t q_full_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3832) uint32_t leak_exchg_thresh_hold;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3833) spinlock_t sess_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3834) int num_act_qpairs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3835) #define DEFAULT_NAQP 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3836) spinlock_t atio_lock ____cacheline_aligned;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3837) struct btree_head32 host_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3838) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3840) #define MAX_QFULL_CMDS_ALLOC 8192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3841) #define Q_FULL_THRESH_HOLD_PERCENT 90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3842) #define Q_FULL_THRESH_HOLD(ha) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3843) ((ha->cur_fw_xcb_count/100) * Q_FULL_THRESH_HOLD_PERCENT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3845) #define LEAK_EXCHG_THRESH_HOLD_PERCENT 75 /* 75 percent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3847) struct qla_hw_data_stat {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3848) u32 num_fw_dump;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3849) u32 num_mpi_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3850) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3852) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3853) * Qlogic host adapter specific data structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3854) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3855) struct qla_hw_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3856) struct pci_dev *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3857) /* SRB cache. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3858) #define SRB_MIN_REQ 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3859) mempool_t *srb_mempool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3861) volatile struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3862) uint32_t mbox_int :1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3863) uint32_t mbox_busy :1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3864) uint32_t disable_risc_code_load :1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3865) uint32_t enable_64bit_addressing :1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3866) uint32_t enable_lip_reset :1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3867) uint32_t enable_target_reset :1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3868) uint32_t enable_lip_full_login :1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3869) uint32_t enable_led_scheme :1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3871) uint32_t msi_enabled :1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3872) uint32_t msix_enabled :1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3873) uint32_t disable_serdes :1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3874) uint32_t gpsc_supported :1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3875) uint32_t npiv_supported :1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3876) uint32_t pci_channel_io_perm_failure :1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3877) uint32_t fce_enabled :1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3878) uint32_t fac_supported :1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3880) uint32_t chip_reset_done :1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3881) uint32_t running_gold_fw :1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3882) uint32_t eeh_busy :1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3883) uint32_t disable_msix_handshake :1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3884) uint32_t fcp_prio_enabled :1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3885) uint32_t isp82xx_fw_hung:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3886) uint32_t nic_core_hung:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3888) uint32_t quiesce_owner:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3889) uint32_t nic_core_reset_hdlr_active:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3890) uint32_t nic_core_reset_owner:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3891) uint32_t isp82xx_no_md_cap:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3892) uint32_t host_shutting_down:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3893) uint32_t idc_compl_status:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3894) uint32_t mr_reset_hdlr_active:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3895) uint32_t mr_intr_valid:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3897) uint32_t dport_enabled:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3898) uint32_t fawwpn_enabled:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3899) uint32_t exlogins_enabled:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3900) uint32_t exchoffld_enabled:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3902) uint32_t lip_ae:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3903) uint32_t n2n_ae:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3904) uint32_t fw_started:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3905) uint32_t fw_init_done:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3907) uint32_t lr_detected:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3909) uint32_t rida_fmt2:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3910) uint32_t purge_mbox:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3911) uint32_t n2n_bigger:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3912) uint32_t secure_adapter:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3913) uint32_t secure_fw:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3914) /* Supported by Adapter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3915) uint32_t scm_supported_a:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3916) /* Supported by Firmware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3917) uint32_t scm_supported_f:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3918) /* Enabled in Driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3919) uint32_t scm_enabled:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3920) uint32_t plogi_template_valid:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3921) } flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3923) uint16_t max_exchg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3924) uint16_t lr_distance; /* 32G & above */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3925) #define LR_DISTANCE_5K 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3926) #define LR_DISTANCE_10K 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3928) /* This spinlock is used to protect "io transactions", you must
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3929) * acquire it before doing any IO to the card, eg with RD_REG*() and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3930) * WRT_REG*() for the duration of your entire commandtransaction.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3931) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3932) * This spinlock is of lower priority than the io request lock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3933) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3935) spinlock_t hardware_lock ____cacheline_aligned;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3936) int bars;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3937) int mem_only;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3938) device_reg_t *iobase; /* Base I/O address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3939) resource_size_t pio_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3941) #define MIN_IOBASE_LEN 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3942) dma_addr_t bar0_hdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3944) void __iomem *cregbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3945) dma_addr_t bar2_hdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3946) #define BAR0_LEN_FX00 (1024 * 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3947) #define BAR2_LEN_FX00 (128 * 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3949) uint32_t rqstq_intr_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3950) uint32_t mbx_intr_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3951) uint32_t req_que_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3952) uint32_t rsp_que_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3953) uint32_t req_que_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3954) uint32_t rsp_que_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3956) /* Multi queue data structs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3957) device_reg_t *mqiobase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3958) device_reg_t *msixbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3959) uint16_t msix_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3960) uint8_t mqenable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3961) struct req_que **req_q_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3962) struct rsp_que **rsp_q_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3963) struct qla_qpair **queue_pair_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3964) unsigned long req_qid_map[(QLA_MAX_QUEUES / 8) / sizeof(unsigned long)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3965) unsigned long rsp_qid_map[(QLA_MAX_QUEUES / 8) / sizeof(unsigned long)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3966) unsigned long qpair_qid_map[(QLA_MAX_QUEUES / 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3967) / sizeof(unsigned long)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3968) uint8_t max_req_queues;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3969) uint8_t max_rsp_queues;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3970) uint8_t max_qpairs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3971) uint8_t num_qpairs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3972) struct qla_qpair *base_qpair;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3973) struct qla_npiv_entry *npiv_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3974) uint16_t nvram_npiv_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3976) uint16_t switch_cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3977) #define FLOGI_SEQ_DEL BIT_8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3978) #define FLOGI_MID_SUPPORT BIT_10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3979) #define FLOGI_VSAN_SUPPORT BIT_12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3980) #define FLOGI_SP_SUPPORT BIT_13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3982) uint8_t port_no; /* Physical port of adapter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3983) uint8_t exch_starvation;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3985) /* Timeout timers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3986) uint8_t loop_down_abort_time; /* port down timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3987) atomic_t loop_down_timer; /* loop down timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3988) uint8_t link_down_timeout; /* link down timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3989) uint16_t max_loop_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3990) uint16_t max_fibre_devices; /* Maximum number of targets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3992) uint16_t fb_rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3993) uint16_t min_external_loopid; /* First external loop Id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3995) #define PORT_SPEED_UNKNOWN 0xFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3996) #define PORT_SPEED_1GB 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3997) #define PORT_SPEED_2GB 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3998) #define PORT_SPEED_AUTO 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3999) #define PORT_SPEED_4GB 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4000) #define PORT_SPEED_8GB 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4001) #define PORT_SPEED_16GB 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4002) #define PORT_SPEED_32GB 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4003) #define PORT_SPEED_64GB 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4004) #define PORT_SPEED_10GB 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4005) uint16_t link_data_rate; /* F/W operating speed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4006) uint16_t set_data_rate; /* Set by user */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4008) uint8_t current_topology;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4009) uint8_t prev_topology;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4010) #define ISP_CFG_NL 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4011) #define ISP_CFG_N 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4012) #define ISP_CFG_FL 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4013) #define ISP_CFG_F 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4015) uint8_t operating_mode; /* F/W operating mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4016) #define LOOP 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4017) #define P2P 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4018) #define LOOP_P2P 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4019) #define P2P_LOOP 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4020) uint8_t interrupts_on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4021) uint32_t isp_abort_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4022) #define PCI_DEVICE_ID_QLOGIC_ISP2532 0x2532
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4023) #define PCI_DEVICE_ID_QLOGIC_ISP8432 0x8432
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4024) #define PCI_DEVICE_ID_QLOGIC_ISP8001 0x8001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4025) #define PCI_DEVICE_ID_QLOGIC_ISP8031 0x8031
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4026) #define PCI_DEVICE_ID_QLOGIC_ISP2031 0x2031
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4027) #define PCI_DEVICE_ID_QLOGIC_ISP2071 0x2071
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4028) #define PCI_DEVICE_ID_QLOGIC_ISP2271 0x2271
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4029) #define PCI_DEVICE_ID_QLOGIC_ISP2261 0x2261
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4030) #define PCI_DEVICE_ID_QLOGIC_ISP2061 0x2061
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4031) #define PCI_DEVICE_ID_QLOGIC_ISP2081 0x2081
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4032) #define PCI_DEVICE_ID_QLOGIC_ISP2089 0x2089
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4033) #define PCI_DEVICE_ID_QLOGIC_ISP2281 0x2281
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4034) #define PCI_DEVICE_ID_QLOGIC_ISP2289 0x2289
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4036) uint32_t isp_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4037) #define DT_ISP2100 BIT_0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4038) #define DT_ISP2200 BIT_1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4039) #define DT_ISP2300 BIT_2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4040) #define DT_ISP2312 BIT_3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4041) #define DT_ISP2322 BIT_4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4042) #define DT_ISP6312 BIT_5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4043) #define DT_ISP6322 BIT_6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4044) #define DT_ISP2422 BIT_7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4045) #define DT_ISP2432 BIT_8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4046) #define DT_ISP5422 BIT_9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4047) #define DT_ISP5432 BIT_10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4048) #define DT_ISP2532 BIT_11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4049) #define DT_ISP8432 BIT_12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4050) #define DT_ISP8001 BIT_13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4051) #define DT_ISP8021 BIT_14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4052) #define DT_ISP2031 BIT_15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4053) #define DT_ISP8031 BIT_16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4054) #define DT_ISPFX00 BIT_17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4055) #define DT_ISP8044 BIT_18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4056) #define DT_ISP2071 BIT_19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4057) #define DT_ISP2271 BIT_20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4058) #define DT_ISP2261 BIT_21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4059) #define DT_ISP2061 BIT_22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4060) #define DT_ISP2081 BIT_23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4061) #define DT_ISP2089 BIT_24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4062) #define DT_ISP2281 BIT_25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4063) #define DT_ISP2289 BIT_26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4064) #define DT_ISP_LAST (DT_ISP2289 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4066) uint32_t device_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4067) #define DT_T10_PI BIT_25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4068) #define DT_IIDMA BIT_26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4069) #define DT_FWI2 BIT_27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4070) #define DT_ZIO_SUPPORTED BIT_28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4071) #define DT_OEM_001 BIT_29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4072) #define DT_ISP2200A BIT_30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4073) #define DT_EXTENDED_IDS BIT_31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4075) #define DT_MASK(ha) ((ha)->isp_type & (DT_ISP_LAST - 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4076) #define IS_QLA2100(ha) (DT_MASK(ha) & DT_ISP2100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4077) #define IS_QLA2200(ha) (DT_MASK(ha) & DT_ISP2200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4078) #define IS_QLA2300(ha) (DT_MASK(ha) & DT_ISP2300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4079) #define IS_QLA2312(ha) (DT_MASK(ha) & DT_ISP2312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4080) #define IS_QLA2322(ha) (DT_MASK(ha) & DT_ISP2322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4081) #define IS_QLA6312(ha) (DT_MASK(ha) & DT_ISP6312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4082) #define IS_QLA6322(ha) (DT_MASK(ha) & DT_ISP6322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4083) #define IS_QLA2422(ha) (DT_MASK(ha) & DT_ISP2422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4084) #define IS_QLA2432(ha) (DT_MASK(ha) & DT_ISP2432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4085) #define IS_QLA5422(ha) (DT_MASK(ha) & DT_ISP5422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4086) #define IS_QLA5432(ha) (DT_MASK(ha) & DT_ISP5432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4087) #define IS_QLA2532(ha) (DT_MASK(ha) & DT_ISP2532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4088) #define IS_QLA8432(ha) (DT_MASK(ha) & DT_ISP8432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4089) #define IS_QLA8001(ha) (DT_MASK(ha) & DT_ISP8001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4090) #define IS_QLA81XX(ha) (IS_QLA8001(ha))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4091) #define IS_QLA82XX(ha) (DT_MASK(ha) & DT_ISP8021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4092) #define IS_QLA8044(ha) (DT_MASK(ha) & DT_ISP8044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4093) #define IS_QLA2031(ha) (DT_MASK(ha) & DT_ISP2031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4094) #define IS_QLA8031(ha) (DT_MASK(ha) & DT_ISP8031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4095) #define IS_QLAFX00(ha) (DT_MASK(ha) & DT_ISPFX00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4096) #define IS_QLA2071(ha) (DT_MASK(ha) & DT_ISP2071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4097) #define IS_QLA2271(ha) (DT_MASK(ha) & DT_ISP2271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4098) #define IS_QLA2261(ha) (DT_MASK(ha) & DT_ISP2261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4099) #define IS_QLA2081(ha) (DT_MASK(ha) & DT_ISP2081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4100) #define IS_QLA2281(ha) (DT_MASK(ha) & DT_ISP2281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4102) #define IS_QLA23XX(ha) (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA2322(ha) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4103) IS_QLA6312(ha) || IS_QLA6322(ha))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4104) #define IS_QLA24XX(ha) (IS_QLA2422(ha) || IS_QLA2432(ha))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4105) #define IS_QLA54XX(ha) (IS_QLA5422(ha) || IS_QLA5432(ha))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4106) #define IS_QLA25XX(ha) (IS_QLA2532(ha))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4107) #define IS_QLA83XX(ha) (IS_QLA2031(ha) || IS_QLA8031(ha))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4108) #define IS_QLA84XX(ha) (IS_QLA8432(ha))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4109) #define IS_QLA27XX(ha) (IS_QLA2071(ha) || IS_QLA2271(ha) || IS_QLA2261(ha))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4110) #define IS_QLA28XX(ha) (IS_QLA2081(ha) || IS_QLA2281(ha))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4111) #define IS_QLA24XX_TYPE(ha) (IS_QLA24XX(ha) || IS_QLA54XX(ha) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4112) IS_QLA84XX(ha))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4113) #define IS_CNA_CAPABLE(ha) (IS_QLA81XX(ha) || IS_QLA82XX(ha) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4114) IS_QLA8031(ha) || IS_QLA8044(ha))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4115) #define IS_P3P_TYPE(ha) (IS_QLA82XX(ha) || IS_QLA8044(ha))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4116) #define IS_QLA2XXX_MIDTYPE(ha) (IS_QLA24XX(ha) || IS_QLA84XX(ha) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4117) IS_QLA25XX(ha) || IS_QLA81XX(ha) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4118) IS_QLA82XX(ha) || IS_QLA83XX(ha) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4119) IS_QLA8044(ha) || IS_QLA27XX(ha) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4120) IS_QLA28XX(ha))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4121) #define IS_MSIX_NACK_CAPABLE(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4122) IS_QLA27XX(ha) || IS_QLA28XX(ha))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4123) #define IS_NOPOLLING_TYPE(ha) (IS_QLA81XX(ha) && (ha)->flags.msix_enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4124) #define IS_FAC_REQUIRED(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4125) IS_QLA27XX(ha) || IS_QLA28XX(ha))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4126) #define IS_NOCACHE_VPD_TYPE(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4127) IS_QLA27XX(ha) || IS_QLA28XX(ha))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4128) #define IS_ALOGIO_CAPABLE(ha) (IS_QLA23XX(ha) || IS_FWI2_CAPABLE(ha))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4130) #define IS_T10_PI_CAPABLE(ha) ((ha)->device_type & DT_T10_PI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4131) #define IS_IIDMA_CAPABLE(ha) ((ha)->device_type & DT_IIDMA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4132) #define IS_FWI2_CAPABLE(ha) ((ha)->device_type & DT_FWI2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4133) #define IS_ZIO_SUPPORTED(ha) ((ha)->device_type & DT_ZIO_SUPPORTED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4134) #define IS_OEM_001(ha) ((ha)->device_type & DT_OEM_001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4135) #define HAS_EXTENDED_IDS(ha) ((ha)->device_type & DT_EXTENDED_IDS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4136) #define IS_CT6_SUPPORTED(ha) ((ha)->device_type & DT_CT6_SUPPORTED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4137) #define IS_MQUE_CAPABLE(ha) ((ha)->mqenable || IS_QLA83XX(ha) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4138) IS_QLA27XX(ha) || IS_QLA28XX(ha))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4139) #define IS_BIDI_CAPABLE(ha) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4140) (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4141) /* Bit 21 of fw_attributes decides the MCTP capabilities */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4142) #define IS_MCTP_CAPABLE(ha) (IS_QLA2031(ha) && \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4143) ((ha)->fw_attributes_ext[0] & BIT_0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4144) #define IS_PI_UNINIT_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4145) #define IS_PI_IPGUARD_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4146) #define IS_PI_DIFB_DIX0_CAPABLE(ha) (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4147) #define IS_PI_SPLIT_DET_CAPABLE_HBA(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4148) IS_QLA28XX(ha))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4149) #define IS_PI_SPLIT_DET_CAPABLE(ha) (IS_PI_SPLIT_DET_CAPABLE_HBA(ha) && \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4150) (((ha)->fw_attributes_h << 16 | (ha)->fw_attributes) & BIT_22))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4151) #define IS_ATIO_MSIX_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4152) IS_QLA28XX(ha))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4153) #define IS_TGT_MODE_CAPABLE(ha) (ha->tgt.atio_q_length)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4154) #define IS_SHADOW_REG_CAPABLE(ha) (IS_QLA27XX(ha) || IS_QLA28XX(ha))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4155) #define IS_DPORT_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4156) IS_QLA28XX(ha))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4157) #define IS_FAWWN_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4158) IS_QLA28XX(ha))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4159) #define IS_EXCHG_OFFLD_CAPABLE(ha) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4160) (IS_QLA81XX(ha) || IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4161) #define IS_EXLOGIN_OFFLD_CAPABLE(ha) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4162) (IS_QLA25XX(ha) || IS_QLA81XX(ha) || IS_QLA83XX(ha) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4163) IS_QLA27XX(ha) || IS_QLA28XX(ha))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4164) #define USE_ASYNC_SCAN(ha) (IS_QLA25XX(ha) || IS_QLA81XX(ha) ||\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4165) IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4167) #define IS_ZIO_THRESHOLD_CAPABLE(ha) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4168) ((IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) &&\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4169) (ha->zio_mode == QLA_ZIO_MODE_6))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4171) /* HBA serial number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4172) uint8_t serial0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4173) uint8_t serial1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4174) uint8_t serial2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4176) /* NVRAM configuration data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4177) #define MAX_NVRAM_SIZE 4096
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4178) #define VPD_OFFSET (MAX_NVRAM_SIZE / 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4179) uint16_t nvram_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4180) uint16_t nvram_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4181) void *nvram;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4182) uint16_t vpd_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4183) uint16_t vpd_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4184) void *vpd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4186) uint16_t loop_reset_delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4187) uint8_t retry_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4188) uint8_t login_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4189) uint16_t r_a_tov;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4190) int port_down_retry_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4191) uint8_t mbx_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4192) uint8_t aen_mbx_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4193) atomic_t num_pend_mbx_stage1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4194) atomic_t num_pend_mbx_stage2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4195) atomic_t num_pend_mbx_stage3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4196) uint16_t frame_payload_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4198) uint32_t login_retry_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4199) /* SNS command interfaces. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4200) ms_iocb_entry_t *ms_iocb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4201) dma_addr_t ms_iocb_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4202) struct ct_sns_pkt *ct_sns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4203) dma_addr_t ct_sns_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4204) /* SNS command interfaces for 2200. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4205) struct sns_cmd_pkt *sns_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4206) dma_addr_t sns_cmd_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4208) #define SFP_DEV_SIZE 512
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4209) #define SFP_BLOCK_SIZE 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4210) #define SFP_RTDI_LEN SFP_BLOCK_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4212) void *sfp_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4213) dma_addr_t sfp_data_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4215) struct qla_flt_header *flt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4216) dma_addr_t flt_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4218) #define XGMAC_DATA_SIZE 4096
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4219) void *xgmac_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4220) dma_addr_t xgmac_data_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4222) #define DCBX_TLV_DATA_SIZE 4096
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4223) void *dcbx_tlv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4224) dma_addr_t dcbx_tlv_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4226) struct task_struct *dpc_thread;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4227) uint8_t dpc_active; /* DPC routine is active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4229) dma_addr_t gid_list_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4230) struct gid_list_info *gid_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4231) int gid_list_info_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4233) /* Small DMA pool allocations -- maximum 256 bytes in length. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4234) #define DMA_POOL_SIZE 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4235) struct dma_pool *s_dma_pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4237) dma_addr_t init_cb_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4238) init_cb_t *init_cb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4239) int init_cb_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4240) dma_addr_t ex_init_cb_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4241) struct ex_init_cb_81xx *ex_init_cb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4242) dma_addr_t sf_init_cb_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4243) struct init_sf_cb *sf_init_cb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4245) void *scm_fpin_els_buff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4246) uint64_t scm_fpin_els_buff_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4247) bool scm_fpin_valid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4248) bool scm_fpin_payload_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4250) void *async_pd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4251) dma_addr_t async_pd_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4253) #define ENABLE_EXTENDED_LOGIN BIT_7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4255) /* Extended Logins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4256) void *exlogin_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4257) dma_addr_t exlogin_buf_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4258) uint32_t exlogin_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4260) #define ENABLE_EXCHANGE_OFFLD BIT_2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4262) /* Exchange Offload */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4263) void *exchoffld_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4264) dma_addr_t exchoffld_buf_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4265) int exchoffld_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4266) int exchoffld_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4268) /* n2n */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4269) struct fc_els_flogi plogi_els_payld;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4270) #define LOGIN_TEMPLATE_SIZE (sizeof(struct fc_els_flogi) - 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4272) void *swl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4274) /* These are used by mailbox operations. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4275) uint16_t mailbox_out[MAILBOX_REGISTER_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4276) uint32_t mailbox_out32[MAILBOX_REGISTER_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4277) uint32_t aenmb[AEN_MAILBOX_REGISTER_COUNT_FX00];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4279) mbx_cmd_t *mcp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4280) struct mbx_cmd_32 *mcp32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4282) unsigned long mbx_cmd_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4283) #define MBX_INTERRUPT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4284) #define MBX_INTR_WAIT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4285) #define MBX_UPDATE_FLASH_ACTIVE 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4287) struct mutex vport_lock; /* Virtual port synchronization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4288) spinlock_t vport_slock; /* order is hardware_lock, then vport_slock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4289) struct mutex mq_lock; /* multi-queue synchronization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4290) struct completion mbx_cmd_comp; /* Serialize mbx access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4291) struct completion mbx_intr_comp; /* Used for completion notification */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4292) struct completion dcbx_comp; /* For set port config notification */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4293) struct completion lb_portup_comp; /* Used to wait for link up during
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4294) * loopback */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4295) #define DCBX_COMP_TIMEOUT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4296) #define LB_PORTUP_COMP_TIMEOUT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4298) int notify_dcbx_comp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4299) int notify_lb_portup_comp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4300) struct mutex selflogin_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4302) /* Basic firmware related information. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4303) uint16_t fw_major_version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4304) uint16_t fw_minor_version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4305) uint16_t fw_subminor_version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4306) uint16_t fw_attributes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4307) uint16_t fw_attributes_h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4308) #define FW_ATTR_H_NVME_FBURST BIT_1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4309) #define FW_ATTR_H_NVME BIT_10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4310) #define FW_ATTR_H_NVME_UPDATED BIT_14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4312) /* About firmware SCM support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4313) #define FW_ATTR_EXT0_SCM_SUPPORTED BIT_12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4314) /* Brocade fabric attached */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4315) #define FW_ATTR_EXT0_SCM_BROCADE 0x00001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4316) /* Cisco fabric attached */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4317) #define FW_ATTR_EXT0_SCM_CISCO 0x00002000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4318) #define FW_ATTR_EXT0_NVME2 BIT_13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4319) uint16_t fw_attributes_ext[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4320) uint32_t fw_memory_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4321) uint32_t fw_transfer_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4322) uint32_t fw_srisc_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4323) #define RISC_START_ADDRESS_2100 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4324) #define RISC_START_ADDRESS_2300 0x800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4325) #define RISC_START_ADDRESS_2400 0x100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4327) uint16_t orig_fw_tgt_xcb_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4328) uint16_t cur_fw_tgt_xcb_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4329) uint16_t orig_fw_xcb_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4330) uint16_t cur_fw_xcb_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4331) uint16_t orig_fw_iocb_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4332) uint16_t cur_fw_iocb_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4333) uint16_t fw_max_fcf_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4335) uint32_t fw_shared_ram_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4336) uint32_t fw_shared_ram_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4337) uint32_t fw_ddr_ram_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4338) uint32_t fw_ddr_ram_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4340) uint16_t fw_options[16]; /* slots: 1,2,3,10,11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4341) uint8_t fw_seriallink_options[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4342) __le16 fw_seriallink_options24[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4344) uint8_t serdes_version[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4345) uint8_t mpi_version[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4346) uint32_t mpi_capabilities;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4347) uint8_t phy_version[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4348) uint8_t pep_version[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4350) /* Firmware dump template */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4351) struct fwdt {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4352) void *template;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4353) ulong length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4354) ulong dump_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4355) } fwdt[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4356) struct qla2xxx_fw_dump *fw_dump;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4357) uint32_t fw_dump_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4358) u32 fw_dump_alloc_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4359) bool fw_dumped;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4360) unsigned long fw_dump_cap_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4361) #define RISC_PAUSE_CMPL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4362) #define DMA_SHUTDOWN_CMPL 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4363) #define ISP_RESET_CMPL 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4364) #define RISC_RDY_AFT_RESET 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4365) #define RISC_SRAM_DUMP_CMPL 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4366) #define RISC_EXT_MEM_DUMP_CMPL 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4367) #define ISP_MBX_RDY 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4368) #define ISP_SOFT_RESET_CMPL 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4369) int fw_dump_reading;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4370) void *mpi_fw_dump;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4371) u32 mpi_fw_dump_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4372) unsigned int mpi_fw_dump_reading:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4373) unsigned int mpi_fw_dumped:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4374) int prev_minidump_failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4375) dma_addr_t eft_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4376) void *eft;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4377) /* Current size of mctp dump is 0x086064 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4378) #define MCTP_DUMP_SIZE 0x086064
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4379) dma_addr_t mctp_dump_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4380) void *mctp_dump;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4381) int mctp_dumped;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4382) int mctp_dump_reading;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4383) uint32_t chain_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4384) struct dentry *dfs_dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4385) struct dentry *dfs_fce;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4386) struct dentry *dfs_tgt_counters;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4387) struct dentry *dfs_fw_resource_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4389) dma_addr_t fce_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4390) void *fce;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4391) uint32_t fce_bufs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4392) uint16_t fce_mb[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4393) uint64_t fce_wr, fce_rd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4394) struct mutex fce_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4396) uint32_t pci_attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4397) uint16_t chip_revision;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4399) uint16_t product_id[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4401) uint8_t model_number[16+1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4402) char model_desc[80];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4403) uint8_t adapter_id[16+1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4405) /* Option ROM information. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4406) char *optrom_buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4407) uint32_t optrom_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4408) int optrom_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4409) #define QLA_SWAITING 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4410) #define QLA_SREADING 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4411) #define QLA_SWRITING 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4412) uint32_t optrom_region_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4413) uint32_t optrom_region_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4414) struct mutex optrom_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4416) /* PCI expansion ROM image information. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4417) #define ROM_CODE_TYPE_BIOS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4418) #define ROM_CODE_TYPE_FCODE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4419) #define ROM_CODE_TYPE_EFI 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4420) uint8_t bios_revision[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4421) uint8_t efi_revision[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4422) uint8_t fcode_revision[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4423) uint32_t fw_revision[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4425) uint32_t gold_fw_version[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4427) /* Offsets for flash/nvram access (set to ~0 if not used). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4428) uint32_t flash_conf_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4429) uint32_t flash_data_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4430) uint32_t nvram_conf_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4431) uint32_t nvram_data_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4433) uint32_t fdt_wrt_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4434) uint32_t fdt_wrt_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4435) uint32_t fdt_erase_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4436) uint32_t fdt_block_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4437) uint32_t fdt_unprotect_sec_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4438) uint32_t fdt_protect_sec_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4439) uint32_t fdt_wrt_sts_reg_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4441) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4442) uint32_t flt_region_flt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4443) uint32_t flt_region_fdt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4444) uint32_t flt_region_boot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4445) uint32_t flt_region_boot_sec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4446) uint32_t flt_region_fw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4447) uint32_t flt_region_fw_sec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4448) uint32_t flt_region_vpd_nvram;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4449) uint32_t flt_region_vpd_nvram_sec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4450) uint32_t flt_region_vpd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4451) uint32_t flt_region_vpd_sec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4452) uint32_t flt_region_nvram;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4453) uint32_t flt_region_nvram_sec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4454) uint32_t flt_region_npiv_conf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4455) uint32_t flt_region_gold_fw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4456) uint32_t flt_region_fcp_prio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4457) uint32_t flt_region_bootload;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4458) uint32_t flt_region_img_status_pri;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4459) uint32_t flt_region_img_status_sec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4460) uint32_t flt_region_aux_img_status_pri;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4461) uint32_t flt_region_aux_img_status_sec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4462) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4463) uint8_t active_image;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4465) /* Needed for BEACON */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4466) uint16_t beacon_blink_led;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4467) uint8_t beacon_color_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4468) #define QLA_LED_GRN_ON 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4469) #define QLA_LED_YLW_ON 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4470) #define QLA_LED_ABR_ON 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4471) #define QLA_LED_ALL_ON 0x07 /* yellow, green, amber. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4472) /* ISP2322: red, green, amber. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4473) uint16_t zio_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4474) uint16_t zio_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4476) struct qla_msix_entry *msix_entries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4478) struct list_head vp_list; /* list of VP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4479) unsigned long vp_idx_map[(MAX_MULTI_ID_FABRIC / 8) /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4480) sizeof(unsigned long)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4481) uint16_t num_vhosts; /* number of vports created */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4482) uint16_t num_vsans; /* number of vsan created */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4483) uint16_t max_npiv_vports; /* 63 or 125 per topoloty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4484) int cur_vport_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4486) struct qla_chip_state_84xx *cs84xx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4487) struct isp_operations *isp_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4488) struct workqueue_struct *wq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4489) struct qlfc_fw fw_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4491) /* FCP_CMND priority support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4492) struct qla_fcp_prio_cfg *fcp_prio_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4494) struct dma_pool *dl_dma_pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4495) #define DSD_LIST_DMA_POOL_SIZE 512
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4497) struct dma_pool *fcp_cmnd_dma_pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4498) mempool_t *ctx_mempool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4499) #define FCP_CMND_DMA_POOL_SIZE 512
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4501) void __iomem *nx_pcibase; /* Base I/O address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4502) void __iomem *nxdb_rd_ptr; /* Doorbell read pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4503) void __iomem *nxdb_wr_ptr; /* Door bell write pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4505) uint32_t crb_win;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4506) uint32_t curr_window;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4507) uint32_t ddr_mn_window;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4508) unsigned long mn_win_crb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4509) unsigned long ms_win_crb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4510) int qdr_sn_window;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4511) uint32_t fcoe_dev_init_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4512) uint32_t fcoe_reset_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4513) rwlock_t hw_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4514) uint16_t portnum; /* port number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4515) int link_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4516) struct fw_blob *hablob;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4517) struct qla82xx_legacy_intr_set nx_legacy_intr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4519) uint16_t gbl_dsd_inuse;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4520) uint16_t gbl_dsd_avail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4521) struct list_head gbl_dsd_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4522) #define NUM_DSD_CHAIN 4096
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4524) uint8_t fw_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4525) uint32_t file_prd_off; /* File firmware product offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4527) uint32_t md_template_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4528) void *md_tmplt_hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4529) dma_addr_t md_tmplt_hdr_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4530) void *md_dump;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4531) uint32_t md_dump_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4533) void *loop_id_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4535) /* QLA83XX IDC specific fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4536) uint32_t idc_audit_ts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4537) uint32_t idc_extend_tmo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4539) /* DPC low-priority workqueue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4540) struct workqueue_struct *dpc_lp_wq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4541) struct work_struct idc_aen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4542) /* DPC high-priority workqueue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4543) struct workqueue_struct *dpc_hp_wq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4544) struct work_struct nic_core_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4545) struct work_struct idc_state_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4546) struct work_struct nic_core_unrecoverable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4547) struct work_struct board_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4549) struct mr_data_fx00 mr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4550) uint32_t chip_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4552) struct qlt_hw_data tgt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4553) int allow_cna_fw_dump;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4554) uint32_t fw_ability_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4555) uint16_t min_supported_speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4556) uint16_t max_supported_speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4558) /* DMA pool for the DIF bundling buffers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4559) struct dma_pool *dif_bundl_pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4560) #define DIF_BUNDLING_DMA_POOL_SIZE 1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4561) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4562) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4563) struct list_head head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4564) uint count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4565) } good;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4566) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4567) struct list_head head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4568) uint count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4569) } unusable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4570) } pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4572) unsigned long long dif_bundle_crossed_pages;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4573) unsigned long long dif_bundle_reads;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4574) unsigned long long dif_bundle_writes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4575) unsigned long long dif_bundle_kallocs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4576) unsigned long long dif_bundle_dma_allocs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4578) atomic_t nvme_active_aen_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4579) uint16_t nvme_last_rptd_aen; /* Last recorded aen count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4581) uint8_t fc4_type_priority;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4583) atomic_t zio_threshold;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4584) uint16_t last_zio_threshold;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4586) #define DEFAULT_ZIO_THRESHOLD 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4588) struct qla_hw_data_stat stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4589) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4591) struct active_regions {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4592) uint8_t global;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4593) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4594) uint8_t board_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4595) uint8_t vpd_nvram;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4596) uint8_t npiv_config_0_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4597) uint8_t npiv_config_2_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4598) } aux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4599) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4601) #define FW_ABILITY_MAX_SPEED_MASK 0xFUL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4602) #define FW_ABILITY_MAX_SPEED_16G 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4603) #define FW_ABILITY_MAX_SPEED_32G 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4604) #define FW_ABILITY_MAX_SPEED(ha) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4605) (ha->fw_ability_mask & FW_ABILITY_MAX_SPEED_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4607) #define QLA_GET_DATA_RATE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4608) #define QLA_SET_DATA_RATE_NOLR 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4609) #define QLA_SET_DATA_RATE_LR 2 /* Set speed and initiate LR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4611) #define QLA_DEFAULT_PAYLOAD_SIZE 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4612) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4613) * This item might be allocated with a size > sizeof(struct purex_item).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4614) * The "size" variable gives the size of the payload (which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4615) * is variable) starting at "iocb".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4616) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4617) struct purex_item {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4618) struct list_head list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4619) struct scsi_qla_host *vha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4620) void (*process_item)(struct scsi_qla_host *vha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4621) struct purex_item *pkt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4622) atomic_t in_use;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4623) uint16_t size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4624) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4625) uint8_t iocb[64];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4626) } iocb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4627) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4629) #define SCM_FLAG_RDF_REJECT 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4630) #define SCM_FLAG_RDF_COMPLETED 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4632) #define QLA_CON_PRIMITIVE_RECEIVED 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4633) #define QLA_CONGESTION_ARB_WARNING 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4634) #define QLA_CONGESTION_ARB_ALARM 0X2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4636) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4637) * Qlogic scsi host structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4638) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4639) typedef struct scsi_qla_host {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4640) struct list_head list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4641) struct list_head vp_fcports; /* list of fcports */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4642) struct list_head work_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4643) spinlock_t work_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4644) struct work_struct iocb_work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4646) /* Commonly used flags and state information. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4647) struct Scsi_Host *host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4648) unsigned long host_no;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4649) uint8_t host_str[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4651) volatile struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4652) uint32_t init_done :1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4653) uint32_t online :1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4654) uint32_t reset_active :1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4656) uint32_t management_server_logged_in :1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4657) uint32_t process_response_queue :1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4658) uint32_t difdix_supported:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4659) uint32_t delete_progress:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4661) uint32_t fw_tgt_reported:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4662) uint32_t bbcr_enable:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4663) uint32_t qpairs_available:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4664) uint32_t qpairs_req_created:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4665) uint32_t qpairs_rsp_created:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4666) uint32_t nvme_enabled:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4667) uint32_t nvme_first_burst:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4668) uint32_t nvme2_enabled:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4669) } flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4671) atomic_t loop_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4672) #define LOOP_TIMEOUT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4673) #define LOOP_DOWN 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4674) #define LOOP_UP 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4675) #define LOOP_UPDATE 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4676) #define LOOP_READY 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4677) #define LOOP_DEAD 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4679) unsigned long relogin_jif;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4680) unsigned long dpc_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4681) #define RESET_MARKER_NEEDED 0 /* Send marker to ISP. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4682) #define RESET_ACTIVE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4683) #define ISP_ABORT_NEEDED 2 /* Initiate ISP abort. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4684) #define ABORT_ISP_ACTIVE 3 /* ISP abort in progress. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4685) #define LOOP_RESYNC_NEEDED 4 /* Device Resync needed. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4686) #define LOOP_RESYNC_ACTIVE 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4687) #define LOCAL_LOOP_UPDATE 6 /* Perform a local loop update. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4688) #define RSCN_UPDATE 7 /* Perform an RSCN update. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4689) #define RELOGIN_NEEDED 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4690) #define REGISTER_FC4_NEEDED 9 /* SNS FC4 registration required. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4691) #define ISP_ABORT_RETRY 10 /* ISP aborted. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4692) #define BEACON_BLINK_NEEDED 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4693) #define REGISTER_FDMI_NEEDED 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4694) #define FCPORT_UPDATE_NEEDED 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4695) #define VP_DPC_NEEDED 14 /* wake up for VP dpc handling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4696) #define UNLOADING 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4697) #define NPIV_CONFIG_NEEDED 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4698) #define ISP_UNRECOVERABLE 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4699) #define FCOE_CTX_RESET_NEEDED 18 /* Initiate FCoE context reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4700) #define MPI_RESET_NEEDED 19 /* Initiate MPI FW reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4701) #define ISP_QUIESCE_NEEDED 20 /* Driver need some quiescence */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4702) #define N2N_LINK_RESET 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4703) #define PORT_UPDATE_NEEDED 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4704) #define FX00_RESET_RECOVERY 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4705) #define FX00_TARGET_SCAN 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4706) #define FX00_CRITEMP_RECOVERY 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4707) #define FX00_HOST_INFO_RESEND 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4708) #define QPAIR_ONLINE_CHECK_NEEDED 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4709) #define SET_NVME_ZIO_THRESHOLD_NEEDED 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4710) #define DETECT_SFP_CHANGE 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4711) #define N2N_LOGIN_NEEDED 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4712) #define IOCB_WORK_ACTIVE 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4713) #define SET_ZIO_THRESHOLD_NEEDED 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4714) #define ISP_ABORT_TO_ROM 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4715) #define VPORT_DELETE 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4717) #define PROCESS_PUREX_IOCB 63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4719) unsigned long pci_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4720) #define PFLG_DISCONNECTED 0 /* PCI device removed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4721) #define PFLG_DRIVER_REMOVING 1 /* PCI driver .remove */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4722) #define PFLG_DRIVER_PROBING 2 /* PCI driver .probe */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4724) uint32_t device_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4725) #define SWITCH_FOUND BIT_0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4726) #define DFLG_NO_CABLE BIT_1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4727) #define DFLG_DEV_FAILED BIT_5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4729) /* ISP configuration data. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4730) uint16_t loop_id; /* Host adapter loop id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4731) uint16_t self_login_loop_id; /* host adapter loop id
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4732) * get it on self login
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4733) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4734) fc_port_t bidir_fcport; /* fcport used for bidir cmnds
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4735) * no need of allocating it for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4736) * each command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4737) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4739) port_id_t d_id; /* Host adapter port id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4740) uint8_t marker_needed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4741) uint16_t mgmt_svr_loop_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4745) /* Timeout timers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4746) uint8_t loop_down_abort_time; /* port down timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4747) atomic_t loop_down_timer; /* loop down timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4748) uint8_t link_down_timeout; /* link down timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4750) uint32_t timer_active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4751) struct timer_list timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4753) uint8_t node_name[WWN_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4754) uint8_t port_name[WWN_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4755) uint8_t fabric_node_name[WWN_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4756) uint8_t fabric_port_name[WWN_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4758) struct nvme_fc_local_port *nvme_local_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4759) struct completion nvme_del_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4761) uint16_t fcoe_vlan_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4762) uint16_t fcoe_fcf_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4763) uint8_t fcoe_vn_port_mac[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4765) /* list of commands waiting on workqueue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4766) struct list_head qla_cmd_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4767) struct list_head qla_sess_op_cmd_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4768) struct list_head unknown_atio_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4769) spinlock_t cmd_list_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4770) struct delayed_work unknown_atio_work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4772) /* Counter to detect races between ELS and RSCN events */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4773) atomic_t generation_tick;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4774) /* Time when global fcport update has been scheduled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4775) int total_fcport_update_gen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4776) /* List of pending LOGOs, protected by tgt_mutex */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4777) struct list_head logo_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4778) /* List of pending PLOGI acks, protected by hw lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4779) struct list_head plogi_ack_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4781) struct list_head qp_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4783) uint32_t vp_abort_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4785) struct fc_vport *fc_vport; /* holds fc_vport * for each vport */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4786) uint16_t vp_idx; /* vport ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4787) struct qla_qpair *qpair; /* base qpair */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4789) unsigned long vp_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4790) #define VP_IDX_ACQUIRED 0 /* bit no 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4791) #define VP_CREATE_NEEDED 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4792) #define VP_BIND_NEEDED 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4793) #define VP_DELETE_NEEDED 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4794) #define VP_SCR_NEEDED 4 /* State Change Request registration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4795) #define VP_CONFIG_OK 5 /* Flag to cfg VP, if FW is ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4796) atomic_t vp_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4797) #define VP_OFFLINE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4798) #define VP_ACTIVE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4799) #define VP_FAILED 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4800) // #define VP_DISABLE 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4801) uint16_t vp_err_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4802) uint16_t vp_prev_err_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4803) #define VP_ERR_UNKWN 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4804) #define VP_ERR_PORTDWN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4805) #define VP_ERR_FAB_UNSUPPORTED 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4806) #define VP_ERR_FAB_NORESOURCES 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4807) #define VP_ERR_FAB_LOGOUT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4808) #define VP_ERR_ADAP_NORESOURCES 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4809) struct qla_hw_data *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4810) struct scsi_qlt_host vha_tgt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4811) struct req_que *req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4812) int fw_heartbeat_counter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4813) int seconds_since_last_heartbeat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4814) struct fc_host_statistics fc_host_stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4815) struct qla_statistics qla_stats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4816) struct bidi_statistics bidi_stats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4817) atomic_t vref_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4818) struct qla8044_reset_template reset_tmplt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4819) uint16_t bbcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4821) uint16_t u_ql2xexchoffld;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4822) uint16_t u_ql2xiniexchg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4823) uint16_t qlini_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4824) uint16_t ql2xexchoffld;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4825) uint16_t ql2xiniexchg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4827) struct dentry *dfs_rport_root;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4829) struct purex_list {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4830) struct list_head head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4831) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4832) } purex_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4833) struct purex_item default_item;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4835) struct name_list_extended gnl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4836) /* Count of active session/fcport */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4837) int fcport_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4838) wait_queue_head_t fcport_waitQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4839) wait_queue_head_t vref_waitq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4840) uint8_t min_supported_speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4841) uint8_t n2n_node_name[WWN_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4842) uint8_t n2n_port_name[WWN_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4843) uint16_t n2n_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4844) __le16 dport_data[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4845) struct list_head gpnid_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4846) struct fab_scan scan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4847) uint8_t scm_fabric_connection_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4849) unsigned int irq_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4850) } scsi_qla_host_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4852) struct qla27xx_image_status {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4853) uint8_t image_status_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4854) __le16 generation;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4855) uint8_t ver_major;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4856) uint8_t ver_minor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4857) uint8_t bitmap; /* 28xx only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4858) uint8_t reserved[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4859) __le32 checksum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4860) __le32 signature;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4861) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4863) /* 28xx aux image status bimap values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4864) #define QLA28XX_AUX_IMG_BOARD_CONFIG BIT_0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4865) #define QLA28XX_AUX_IMG_VPD_NVRAM BIT_1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4866) #define QLA28XX_AUX_IMG_NPIV_CONFIG_0_1 BIT_2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4867) #define QLA28XX_AUX_IMG_NPIV_CONFIG_2_3 BIT_3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4869) #define SET_VP_IDX 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4870) #define SET_AL_PA 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4871) #define RESET_VP_IDX 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4872) #define RESET_AL_PA 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4873) struct qla_tgt_vp_map {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4874) uint8_t idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4875) scsi_qla_host_t *vha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4876) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4878) struct qla2_sgx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4879) dma_addr_t dma_addr; /* OUT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4880) uint32_t dma_len; /* OUT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4882) uint32_t tot_bytes; /* IN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4883) struct scatterlist *cur_sg; /* IN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4885) /* for book keeping, bzero on initial invocation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4886) uint32_t bytes_consumed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4887) uint32_t num_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4888) uint32_t tot_partial;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4890) /* for debugging */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4891) uint32_t num_sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4892) srb_t *sp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4893) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4895) #define QLA_FW_STARTED(_ha) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4896) int i; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4897) _ha->flags.fw_started = 1; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4898) _ha->base_qpair->fw_started = 1; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4899) for (i = 0; i < _ha->max_qpairs; i++) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4900) if (_ha->queue_pair_map[i]) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4901) _ha->queue_pair_map[i]->fw_started = 1; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4902) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4903) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4905) #define QLA_FW_STOPPED(_ha) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4906) int i; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4907) _ha->flags.fw_started = 0; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4908) _ha->base_qpair->fw_started = 0; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4909) for (i = 0; i < _ha->max_qpairs; i++) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4910) if (_ha->queue_pair_map[i]) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4911) _ha->queue_pair_map[i]->fw_started = 0; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4912) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4913) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4916) #define SFUB_CHECKSUM_SIZE 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4918) struct secure_flash_update_block {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4919) uint32_t block_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4920) uint32_t signature_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4921) uint32_t signature_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4922) uint32_t signature_upper[0x3e];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4923) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4925) struct secure_flash_update_block_pk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4926) uint32_t block_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4927) uint32_t signature_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4928) uint32_t signature_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4929) uint32_t signature_upper[0x3e];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4930) uint32_t public_key[0x41];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4931) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4933) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4934) * Macros to help code, maintain, etc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4935) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4936) #define LOOP_TRANSITION(ha) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4937) (test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4938) test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4939) atomic_read(&ha->loop_state) == LOOP_DOWN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4941) #define STATE_TRANSITION(ha) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4942) (test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4943) test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4945) #define QLA_VHA_MARK_BUSY(__vha, __bail) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4946) atomic_inc(&__vha->vref_count); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4947) mb(); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4948) if (__vha->flags.delete_progress) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4949) atomic_dec(&__vha->vref_count); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4950) wake_up(&__vha->vref_waitq); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4951) __bail = 1; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4952) } else { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4953) __bail = 0; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4954) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4955) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4957) #define QLA_VHA_MARK_NOT_BUSY(__vha) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4958) atomic_dec(&__vha->vref_count); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4959) wake_up(&__vha->vref_waitq); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4960) } while (0) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4962) #define QLA_QPAIR_MARK_BUSY(__qpair, __bail) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4963) atomic_inc(&__qpair->ref_count); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4964) mb(); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4965) if (__qpair->delete_in_progress) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4966) atomic_dec(&__qpair->ref_count); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4967) __bail = 1; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4968) } else { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4969) __bail = 0; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4970) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4971) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4973) #define QLA_QPAIR_MARK_NOT_BUSY(__qpair) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4974) atomic_dec(&__qpair->ref_count); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4977) #define QLA_ENA_CONF(_ha) {\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4978) int i;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4979) _ha->base_qpair->enable_explicit_conf = 1; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4980) for (i = 0; i < _ha->max_qpairs; i++) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4981) if (_ha->queue_pair_map[i]) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4982) _ha->queue_pair_map[i]->enable_explicit_conf = 1; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4983) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4984) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4986) #define QLA_DIS_CONF(_ha) {\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4987) int i;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4988) _ha->base_qpair->enable_explicit_conf = 0; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4989) for (i = 0; i < _ha->max_qpairs; i++) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4990) if (_ha->queue_pair_map[i]) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4991) _ha->queue_pair_map[i]->enable_explicit_conf = 0; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4992) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4993) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4995) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4996) * qla2x00 local function return status codes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4997) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4998) #define MBS_MASK 0x3fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5000) #define QLA_SUCCESS (MBS_COMMAND_COMPLETE & MBS_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5001) #define QLA_INVALID_COMMAND (MBS_INVALID_COMMAND & MBS_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5002) #define QLA_INTERFACE_ERROR (MBS_HOST_INTERFACE_ERROR & MBS_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5003) #define QLA_TEST_FAILED (MBS_TEST_FAILED & MBS_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5004) #define QLA_COMMAND_ERROR (MBS_COMMAND_ERROR & MBS_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5005) #define QLA_PARAMETER_ERROR (MBS_COMMAND_PARAMETER_ERROR & MBS_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5006) #define QLA_PORT_ID_USED (MBS_PORT_ID_USED & MBS_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5007) #define QLA_LOOP_ID_USED (MBS_LOOP_ID_USED & MBS_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5008) #define QLA_ALL_IDS_IN_USE (MBS_ALL_IDS_IN_USE & MBS_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5009) #define QLA_NOT_LOGGED_IN (MBS_NOT_LOGGED_IN & MBS_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5011) #define QLA_FUNCTION_TIMEOUT 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5012) #define QLA_FUNCTION_PARAMETER_ERROR 0x101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5013) #define QLA_FUNCTION_FAILED 0x102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5014) #define QLA_MEMORY_ALLOC_FAILED 0x103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5015) #define QLA_LOCK_TIMEOUT 0x104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5016) #define QLA_ABORTED 0x105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5017) #define QLA_SUSPENDED 0x106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5018) #define QLA_BUSY 0x107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5019) #define QLA_ALREADY_REGISTERED 0x109
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5020) #define QLA_OS_TIMER_EXPIRED 0x10a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5022) #define NVRAM_DELAY() udelay(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5024) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5025) * Flash support definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5026) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5027) #define OPTROM_SIZE_2300 0x20000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5028) #define OPTROM_SIZE_2322 0x100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5029) #define OPTROM_SIZE_24XX 0x100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5030) #define OPTROM_SIZE_25XX 0x200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5031) #define OPTROM_SIZE_81XX 0x400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5032) #define OPTROM_SIZE_82XX 0x800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5033) #define OPTROM_SIZE_83XX 0x1000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5034) #define OPTROM_SIZE_28XX 0x2000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5036) #define OPTROM_BURST_SIZE 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5037) #define OPTROM_BURST_DWORDS (OPTROM_BURST_SIZE / 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5039) #define QLA_DSDS_PER_IOCB 37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5041) #define CMD_SP(Cmnd) ((Cmnd)->SCp.ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5043) #define QLA_SG_ALL 1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5045) enum nexus_wait_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5046) WAIT_HOST = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5047) WAIT_TARGET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5048) WAIT_LUN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5049) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5051) /* Refer to SNIA SFF 8247 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5052) struct sff_8247_a0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5053) u8 txid; /* transceiver id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5054) u8 ext_txid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5055) u8 connector;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5056) /* compliance code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5057) u8 eth_infi_cc3; /* ethernet, inifiband */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5058) u8 sonet_cc4[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5059) u8 eth_cc6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5060) /* link length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5061) #define FC_LL_VL BIT_7 /* very long */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5062) #define FC_LL_S BIT_6 /* Short */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5063) #define FC_LL_I BIT_5 /* Intermidiate*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5064) #define FC_LL_L BIT_4 /* Long */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5065) #define FC_LL_M BIT_3 /* Medium */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5066) #define FC_LL_SA BIT_2 /* ShortWave laser */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5067) #define FC_LL_LC BIT_1 /* LongWave laser */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5068) #define FC_LL_EL BIT_0 /* Electrical inter enclosure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5069) u8 fc_ll_cc7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5070) /* FC technology */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5071) #define FC_TEC_EL BIT_7 /* Electrical inter enclosure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5072) #define FC_TEC_SN BIT_6 /* short wave w/o OFC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5073) #define FC_TEC_SL BIT_5 /* short wave with OFC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5074) #define FC_TEC_LL BIT_4 /* Longwave Laser */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5075) #define FC_TEC_ACT BIT_3 /* Active cable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5076) #define FC_TEC_PAS BIT_2 /* Passive cable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5077) u8 fc_tec_cc8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5078) /* Transmission Media */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5079) #define FC_MED_TW BIT_7 /* Twin Ax */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5080) #define FC_MED_TP BIT_6 /* Twited Pair */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5081) #define FC_MED_MI BIT_5 /* Min Coax */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5082) #define FC_MED_TV BIT_4 /* Video Coax */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5083) #define FC_MED_M6 BIT_3 /* Multimode, 62.5um */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5084) #define FC_MED_M5 BIT_2 /* Multimode, 50um */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5085) #define FC_MED_SM BIT_0 /* Single Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5086) u8 fc_med_cc9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5087) /* speed FC_SP_12: 12*100M = 1200 MB/s */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5088) #define FC_SP_12 BIT_7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5089) #define FC_SP_8 BIT_6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5090) #define FC_SP_16 BIT_5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5091) #define FC_SP_4 BIT_4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5092) #define FC_SP_32 BIT_3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5093) #define FC_SP_2 BIT_2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5094) #define FC_SP_1 BIT_0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5095) u8 fc_sp_cc10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5096) u8 encode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5097) u8 bitrate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5098) u8 rate_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5099) u8 length_km; /* offset 14/eh */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5100) u8 length_100m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5101) u8 length_50um_10m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5102) u8 length_62um_10m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5103) u8 length_om4_10m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5104) u8 length_om3_10m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5105) #define SFF_VEN_NAME_LEN 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5106) u8 vendor_name[SFF_VEN_NAME_LEN]; /* offset 20/14h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5107) u8 tx_compat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5108) u8 vendor_oui[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5109) #define SFF_PART_NAME_LEN 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5110) u8 vendor_pn[SFF_PART_NAME_LEN]; /* part number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5111) u8 vendor_rev[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5112) u8 wavelength[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5113) u8 resv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5114) u8 cc_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5115) u8 options[2]; /* offset 64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5116) u8 br_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5117) u8 br_min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5118) u8 vendor_sn[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5119) u8 date_code[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5120) u8 diag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5121) u8 enh_options;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5122) u8 sff_revision;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5123) u8 cc_ext;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5124) u8 vendor_specific[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5125) u8 resv2[128];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5126) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5128) /* BPM -- Buffer Plus Management support. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5129) #define IS_BPM_CAPABLE(ha) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5130) (IS_QLA25XX(ha) || IS_QLA81XX(ha) || IS_QLA83XX(ha) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5131) IS_QLA27XX(ha) || IS_QLA28XX(ha))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5132) #define IS_BPM_RANGE_CAPABLE(ha) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5133) (IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5134) #define IS_BPM_ENABLED(vha) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5135) (ql2xautodetectsfp && !vha->vp_idx && IS_BPM_CAPABLE(vha->hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5137) #define FLASH_SEMAPHORE_REGISTER_ADDR 0x00101016
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5139) #define USER_CTRL_IRQ(_ha) (ql2xuctrlirq && QLA_TGT_MODE_ENABLED() && \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5140) (IS_QLA27XX(_ha) || IS_QLA28XX(_ha) || IS_QLA83XX(_ha)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5142) #define SAVE_TOPO(_ha) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5143) if (_ha->current_topology) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5144) _ha->prev_topology = _ha->current_topology; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5147) #define N2N_TOPO(ha) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5148) ((ha->prev_topology == ISP_CFG_N && !ha->current_topology) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5149) ha->current_topology == ISP_CFG_N || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5150) !ha->current_topology)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5152) #define QLA_N2N_WAIT_TIME 5 /* 2 * ra_tov(n2n) + 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5154) #define NVME_TYPE(fcport) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5155) (fcport->fc4_type & FS_FC4TYPE_NVME) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5157) #define FCP_TYPE(fcport) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5158) (fcport->fc4_type & FS_FC4TYPE_FCP) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5160) #define NVME_ONLY_TARGET(fcport) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5161) (NVME_TYPE(fcport) && !FCP_TYPE(fcport)) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5163) #define NVME_FCP_TARGET(fcport) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5164) (FCP_TYPE(fcport) && NVME_TYPE(fcport)) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5166) #define NVME_TARGET(ha, fcport) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5167) ((NVME_FCP_TARGET(fcport) && \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5168) (ha->fc4_type_priority == FC4_PRIORITY_NVME)) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5169) NVME_ONLY_TARGET(fcport)) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5171) #define PRLI_PHASE(_cls) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5172) ((_cls == DSC_LS_PRLI_PEND) || (_cls == DSC_LS_PRLI_COMP))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5174) #include "qla_target.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5175) #include "qla_gbl.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5176) #include "qla_dbg.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5177) #include "qla_inline.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5179) #define IS_SESSION_DELETED(_fcport) (_fcport->disc_state == DSC_DELETE_PEND || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5180) _fcport->disc_state == DSC_DELETED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5182) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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