^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * QLogic Fibre Channel HBA Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (c) 2003-2014 QLogic Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include "qla_def.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Firmware Dump structure definition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) struct qla2300_fw_dump {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) __be16 hccr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) __be16 pbiu_reg[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) __be16 risc_host_reg[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) __be16 mailbox_reg[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) __be16 resp_dma_reg[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) __be16 dma_reg[48];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) __be16 risc_hdw_reg[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) __be16 risc_gp0_reg[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) __be16 risc_gp1_reg[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) __be16 risc_gp2_reg[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) __be16 risc_gp3_reg[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) __be16 risc_gp4_reg[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) __be16 risc_gp5_reg[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) __be16 risc_gp6_reg[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) __be16 risc_gp7_reg[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) __be16 frame_buf_hdw_reg[64];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) __be16 fpm_b0_reg[64];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) __be16 fpm_b1_reg[64];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) __be16 risc_ram[0xf800];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) __be16 stack_ram[0x1000];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) __be16 data_ram[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) struct qla2100_fw_dump {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) __be16 hccr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) __be16 pbiu_reg[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) __be16 mailbox_reg[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) __be16 dma_reg[48];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) __be16 risc_hdw_reg[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) __be16 risc_gp0_reg[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) __be16 risc_gp1_reg[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) __be16 risc_gp2_reg[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) __be16 risc_gp3_reg[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) __be16 risc_gp4_reg[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) __be16 risc_gp5_reg[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) __be16 risc_gp6_reg[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) __be16 risc_gp7_reg[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) __be16 frame_buf_hdw_reg[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) __be16 fpm_b0_reg[64];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) __be16 fpm_b1_reg[64];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) __be16 risc_ram[0xf000];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) u8 queue_dump[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) struct qla24xx_fw_dump {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) __be32 host_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) __be32 host_reg[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) __be32 shadow_reg[7];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) __be16 mailbox_reg[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) __be32 xseq_gp_reg[128];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) __be32 xseq_0_reg[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) __be32 xseq_1_reg[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) __be32 rseq_gp_reg[128];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) __be32 rseq_0_reg[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) __be32 rseq_1_reg[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) __be32 rseq_2_reg[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) __be32 cmd_dma_reg[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) __be32 req0_dma_reg[15];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) __be32 resp0_dma_reg[15];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) __be32 req1_dma_reg[15];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) __be32 xmt0_dma_reg[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) __be32 xmt1_dma_reg[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) __be32 xmt2_dma_reg[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) __be32 xmt3_dma_reg[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) __be32 xmt4_dma_reg[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) __be32 xmt_data_dma_reg[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) __be32 rcvt0_data_dma_reg[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) __be32 rcvt1_data_dma_reg[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) __be32 risc_gp_reg[128];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) __be32 lmc_reg[112];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) __be32 fpm_hdw_reg[192];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) __be32 fb_hdw_reg[176];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) __be32 code_ram[0x2000];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) __be32 ext_mem[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) struct qla25xx_fw_dump {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) __be32 host_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) __be32 host_risc_reg[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) __be32 pcie_regs[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) __be32 host_reg[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) __be32 shadow_reg[11];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) __be32 risc_io_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) __be16 mailbox_reg[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) __be32 xseq_gp_reg[128];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) __be32 xseq_0_reg[48];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) __be32 xseq_1_reg[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) __be32 rseq_gp_reg[128];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) __be32 rseq_0_reg[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) __be32 rseq_1_reg[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) __be32 rseq_2_reg[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) __be32 aseq_gp_reg[128];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) __be32 aseq_0_reg[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) __be32 aseq_1_reg[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) __be32 aseq_2_reg[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) __be32 cmd_dma_reg[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) __be32 req0_dma_reg[15];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) __be32 resp0_dma_reg[15];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) __be32 req1_dma_reg[15];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) __be32 xmt0_dma_reg[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) __be32 xmt1_dma_reg[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) __be32 xmt2_dma_reg[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) __be32 xmt3_dma_reg[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) __be32 xmt4_dma_reg[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) __be32 xmt_data_dma_reg[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) __be32 rcvt0_data_dma_reg[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) __be32 rcvt1_data_dma_reg[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) __be32 risc_gp_reg[128];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) __be32 lmc_reg[128];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) __be32 fpm_hdw_reg[192];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) __be32 fb_hdw_reg[192];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) __be32 code_ram[0x2000];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) __be32 ext_mem[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) struct qla81xx_fw_dump {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) __be32 host_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) __be32 host_risc_reg[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) __be32 pcie_regs[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) __be32 host_reg[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) __be32 shadow_reg[11];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) __be32 risc_io_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) __be16 mailbox_reg[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) __be32 xseq_gp_reg[128];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) __be32 xseq_0_reg[48];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) __be32 xseq_1_reg[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) __be32 rseq_gp_reg[128];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) __be32 rseq_0_reg[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) __be32 rseq_1_reg[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) __be32 rseq_2_reg[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) __be32 aseq_gp_reg[128];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) __be32 aseq_0_reg[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) __be32 aseq_1_reg[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) __be32 aseq_2_reg[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) __be32 cmd_dma_reg[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) __be32 req0_dma_reg[15];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) __be32 resp0_dma_reg[15];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) __be32 req1_dma_reg[15];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) __be32 xmt0_dma_reg[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) __be32 xmt1_dma_reg[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) __be32 xmt2_dma_reg[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) __be32 xmt3_dma_reg[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) __be32 xmt4_dma_reg[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) __be32 xmt_data_dma_reg[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) __be32 rcvt0_data_dma_reg[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) __be32 rcvt1_data_dma_reg[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) __be32 risc_gp_reg[128];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) __be32 lmc_reg[128];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) __be32 fpm_hdw_reg[224];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) __be32 fb_hdw_reg[208];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) __be32 code_ram[0x2000];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) __be32 ext_mem[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) struct qla83xx_fw_dump {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) __be32 host_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) __be32 host_risc_reg[48];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) __be32 pcie_regs[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) __be32 host_reg[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) __be32 shadow_reg[11];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) __be32 risc_io_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) __be16 mailbox_reg[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) __be32 xseq_gp_reg[256];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) __be32 xseq_0_reg[48];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) __be32 xseq_1_reg[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) __be32 xseq_2_reg[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) __be32 rseq_gp_reg[256];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) __be32 rseq_0_reg[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) __be32 rseq_1_reg[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) __be32 rseq_2_reg[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) __be32 rseq_3_reg[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) __be32 aseq_gp_reg[256];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) __be32 aseq_0_reg[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) __be32 aseq_1_reg[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) __be32 aseq_2_reg[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) __be32 aseq_3_reg[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) __be32 cmd_dma_reg[64];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) __be32 req0_dma_reg[15];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) __be32 resp0_dma_reg[15];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) __be32 req1_dma_reg[15];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) __be32 xmt0_dma_reg[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) __be32 xmt1_dma_reg[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) __be32 xmt2_dma_reg[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) __be32 xmt3_dma_reg[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) __be32 xmt4_dma_reg[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) __be32 xmt_data_dma_reg[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) __be32 rcvt0_data_dma_reg[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) __be32 rcvt1_data_dma_reg[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) __be32 risc_gp_reg[128];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) __be32 lmc_reg[128];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) __be32 fpm_hdw_reg[256];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) __be32 rq0_array_reg[256];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) __be32 rq1_array_reg[256];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) __be32 rp0_array_reg[256];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) __be32 rp1_array_reg[256];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) __be32 queue_control_reg[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) __be32 fb_hdw_reg[432];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) __be32 at0_array_reg[128];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) __be32 code_ram[0x2400];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) __be32 ext_mem[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define EFT_NUM_BUFFERS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define EFT_BYTES_PER_BUFFER 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define EFT_SIZE ((EFT_BYTES_PER_BUFFER) * (EFT_NUM_BUFFERS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define FCE_NUM_BUFFERS 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define FCE_BYTES_PER_BUFFER 0x400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define FCE_SIZE ((FCE_BYTES_PER_BUFFER) * (FCE_NUM_BUFFERS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define fce_calc_size(b) ((FCE_BYTES_PER_BUFFER) * (b))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) struct qla2xxx_fce_chain {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) __be32 type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) __be32 chain_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) __be32 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) __be32 addr_l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) __be32 addr_h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) __be32 eregs[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) /* used by exchange off load and extended login offload */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) struct qla2xxx_offld_chain {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) __be32 type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) __be32 chain_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) __be32 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) __be32 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) __be64 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) struct qla2xxx_mq_chain {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) __be32 type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) __be32 chain_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) __be32 count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) __be32 qregs[4 * QLA_MQ_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) struct qla2xxx_mqueue_header {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) __be32 queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define TYPE_REQUEST_QUEUE 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define TYPE_RESPONSE_QUEUE 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define TYPE_ATIO_QUEUE 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) __be32 number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) __be32 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) struct qla2xxx_mqueue_chain {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) __be32 type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) __be32 chain_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define DUMP_CHAIN_VARIANT 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define DUMP_CHAIN_FCE 0x7FFFFAF0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define DUMP_CHAIN_MQ 0x7FFFFAF1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define DUMP_CHAIN_QUEUE 0x7FFFFAF2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define DUMP_CHAIN_EXLOGIN 0x7FFFFAF3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define DUMP_CHAIN_EXCHG 0x7FFFFAF4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define DUMP_CHAIN_LAST 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) struct qla2xxx_fw_dump {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) uint8_t signature[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) __be32 version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) __be32 fw_major_version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) __be32 fw_minor_version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) __be32 fw_subminor_version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) __be32 fw_attributes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) __be32 vendor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) __be32 device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) __be32 subsystem_vendor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) __be32 subsystem_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) __be32 fixed_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) __be32 mem_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) __be32 req_q_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) __be32 rsp_q_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) __be32 eft_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) __be32 eft_addr_l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) __be32 eft_addr_h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) __be32 header_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) struct qla2100_fw_dump isp21;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) struct qla2300_fw_dump isp23;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) struct qla24xx_fw_dump isp24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) struct qla25xx_fw_dump isp25;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) struct qla81xx_fw_dump isp81;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) struct qla83xx_fw_dump isp83;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) } isp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define QL_MSGHDR "qla2xxx"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define QL_DBG_DEFAULT1_MASK 0x1e400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define ql_log_fatal 0 /* display fatal errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define ql_log_warn 1 /* display critical errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define ql_log_info 2 /* display all recovered errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define ql_log_all 3 /* This value is only used by ql_errlev.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) * No messages will use this value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) * This should be always highest value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) * as compared to other log levels.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) extern uint ql_errlev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) void __attribute__((format (printf, 4, 5)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) ql_dbg(uint, scsi_qla_host_t *vha, uint, const char *fmt, ...);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) void __attribute__((format (printf, 4, 5)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) ql_dbg_pci(uint, struct pci_dev *pdev, uint, const char *fmt, ...);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) void __attribute__((format (printf, 4, 5)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) ql_dbg_qp(uint32_t, struct qla_qpair *, int32_t, const char *fmt, ...);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) void __attribute__((format (printf, 4, 5)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) ql_log(uint, scsi_qla_host_t *vha, uint, const char *fmt, ...);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) void __attribute__((format (printf, 4, 5)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) ql_log_pci(uint, struct pci_dev *pdev, uint, const char *fmt, ...);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) void __attribute__((format (printf, 4, 5)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) ql_log_qp(uint32_t, struct qla_qpair *, int32_t, const char *fmt, ...);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) /* Debug Levels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) /* The 0x40000000 is the max value any debug level can have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) * as ql2xextended_error_logging is of type signed int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define ql_dbg_init 0x40000000 /* Init Debug */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define ql_dbg_mbx 0x20000000 /* MBX Debug */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define ql_dbg_disc 0x10000000 /* Device Discovery Debug */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define ql_dbg_io 0x08000000 /* IO Tracing Debug */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define ql_dbg_dpc 0x04000000 /* DPC Thead Debug */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define ql_dbg_async 0x02000000 /* Async events Debug */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define ql_dbg_timer 0x01000000 /* Timer Debug */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define ql_dbg_user 0x00800000 /* User Space Interations Debug */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define ql_dbg_taskm 0x00400000 /* Task Management Debug */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define ql_dbg_aer 0x00200000 /* AER/EEH Debug */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define ql_dbg_multiq 0x00100000 /* MultiQ Debug */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define ql_dbg_p3p 0x00080000 /* P3P specific Debug */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define ql_dbg_vport 0x00040000 /* Virtual Port Debug */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define ql_dbg_buffer 0x00020000 /* For dumping the buffer/regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define ql_dbg_misc 0x00010000 /* For dumping everything that is not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) * not covered by upper categories
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define ql_dbg_verbose 0x00008000 /* More verbosity for each level
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) * This is to be used with other levels where
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) * more verbosity is required. It might not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) * be applicable to all the levels.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define ql_dbg_tgt 0x00004000 /* Target mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define ql_dbg_tgt_mgt 0x00002000 /* Target mode management */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define ql_dbg_tgt_tmr 0x00001000 /* Target mode task management */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define ql_dbg_tgt_dif 0x00000800 /* Target mode dif */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) extern int qla27xx_dump_mpi_ram(struct qla_hw_data *, uint32_t, uint32_t *,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) uint32_t, void **);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) extern int qla24xx_dump_ram(struct qla_hw_data *, uint32_t, __be32 *,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) uint32_t, void **);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) extern void qla24xx_pause_risc(struct device_reg_24xx __iomem *,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) struct qla_hw_data *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) extern int qla24xx_soft_reset(struct qla_hw_data *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) static inline int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) ql_mask_match(uint level)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) if (ql2xextended_error_logging == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) return (level & ql2xextended_error_logging) == level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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