^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * QLogic Fibre Channel HBA Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (c) 2003-2014 QLogic Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Table for showing the current message id in use for particular level
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Change this table for addition of log/debug messages.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * ----------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * | Level | Last Value Used | Holes |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * ----------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * | Module Init and Probe | 0x0199 | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * | Mailbox commands | 0x1206 | 0x11a5-0x11ff |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * | Device Discovery | 0x2134 | 0x210e-0x2115 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * | | | 0x211c-0x2128 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * | | | 0x212c-0x2134 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * | Queue Command and IO tracing | 0x3074 | 0x300b |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * | | | 0x3027-0x3028 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * | | | 0x303d-0x3041 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * | | | 0x302d,0x3033 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * | | | 0x3036,0x3038 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * | | | 0x303a |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * | DPC Thread | 0x4023 | 0x4002,0x4013 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * | Async Events | 0x509c | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * | Timer Routines | 0x6012 | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * | User Space Interactions | 0x70e3 | 0x7018,0x702e |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * | | | 0x7020,0x7024 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * | | | 0x7039,0x7045 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * | | | 0x7073-0x7075 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * | | | 0x70a5-0x70a6 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * | | | 0x70a8,0x70ab |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * | | | 0x70ad-0x70ae |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * | | | 0x70d0-0x70d6 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * | | | 0x70d7-0x70db |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * | Task Management | 0x8042 | 0x8000 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * | | | 0x8019 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * | | | 0x8025,0x8026 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * | | | 0x8031,0x8032 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * | | | 0x8039,0x803c |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * | AER/EEH | 0x9011 | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * | Virtual Port | 0xa007 | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * | ISP82XX Specific | 0xb157 | 0xb002,0xb024 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * | | | 0xb09e,0xb0ae |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * | | | 0xb0c3,0xb0c6 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * | | | 0xb0e0-0xb0ef |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * | | | 0xb085,0xb0dc |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * | | | 0xb107,0xb108 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * | | | 0xb111,0xb11e |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * | | | 0xb12c,0xb12d |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * | | | 0xb13a,0xb142 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * | | | 0xb13c-0xb140 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * | | | 0xb149 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * | MultiQ | 0xc010 | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * | Misc | 0xd303 | 0xd031-0xd0ff |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * | | | 0xd101-0xd1fe |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * | | | 0xd214-0xd2fe |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * | Target Mode | 0xe081 | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * | Target Mode Management | 0xf09b | 0xf002 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * | | | 0xf046-0xf049 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * | Target Mode Task Management | 0x1000d | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * ----------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #include "qla_def.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define CREATE_TRACE_POINTS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #include <trace/events/qla.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static uint32_t ql_dbg_offset = 0x800;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) qla2xxx_prep_dump(struct qla_hw_data *ha, struct qla2xxx_fw_dump *fw_dump)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) fw_dump->fw_major_version = htonl(ha->fw_major_version);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) fw_dump->fw_minor_version = htonl(ha->fw_minor_version);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) fw_dump->fw_subminor_version = htonl(ha->fw_subminor_version);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) fw_dump->fw_attributes = htonl(ha->fw_attributes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) fw_dump->vendor = htonl(ha->pdev->vendor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) fw_dump->device = htonl(ha->pdev->device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) fw_dump->subsystem_vendor = htonl(ha->pdev->subsystem_vendor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) fw_dump->subsystem_device = htonl(ha->pdev->subsystem_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) static inline void *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) qla2xxx_copy_queues(struct qla_hw_data *ha, void *ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) struct req_que *req = ha->req_q_map[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) struct rsp_que *rsp = ha->rsp_q_map[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /* Request queue. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) memcpy(ptr, req->ring, req->length *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) sizeof(request_t));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /* Response queue. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) ptr += req->length * sizeof(request_t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) memcpy(ptr, rsp->ring, rsp->length *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) sizeof(response_t));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) return ptr + (rsp->length * sizeof(response_t));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) qla27xx_dump_mpi_ram(struct qla_hw_data *ha, uint32_t addr, uint32_t *ram,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) uint32_t ram_dwords, void **nxt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) dma_addr_t dump_dma = ha->gid_list_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) uint32_t *chunk = (uint32_t *)ha->gid_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) uint32_t dwords = qla2x00_gid_list_size(ha) / 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) uint32_t stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) ulong i, j, timer = 6000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) int rval = QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) for (i = 0; i < ram_dwords; i += dwords, addr += dwords) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) if (i + dwords > ram_dwords)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) dwords = ram_dwords - i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) wrt_reg_word(®->mailbox0, MBC_LOAD_DUMP_MPI_RAM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) wrt_reg_word(®->mailbox1, LSW(addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) wrt_reg_word(®->mailbox8, MSW(addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) wrt_reg_word(®->mailbox2, MSW(LSD(dump_dma)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) wrt_reg_word(®->mailbox3, LSW(LSD(dump_dma)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) wrt_reg_word(®->mailbox6, MSW(MSD(dump_dma)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) wrt_reg_word(®->mailbox7, LSW(MSD(dump_dma)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) wrt_reg_word(®->mailbox4, MSW(dwords));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) wrt_reg_word(®->mailbox5, LSW(dwords));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) wrt_reg_word(®->mailbox9, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) wrt_reg_dword(®->hccr, HCCRX_SET_HOST_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) ha->flags.mbox_int = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) while (timer--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) udelay(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) stat = rd_reg_dword(®->host_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /* Check for pending interrupts. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) if (!(stat & HSRX_RISC_INT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) stat &= 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) if (stat != 0x1 && stat != 0x2 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) stat != 0x10 && stat != 0x11) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /* Clear this intr; it wasn't a mailbox intr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) wrt_reg_dword(®->hccr, HCCRX_CLR_RISC_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) rd_reg_dword(®->hccr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) set_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) rval = rd_reg_word(®->mailbox0) & MBS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) wrt_reg_dword(®->hccr, HCCRX_CLR_RISC_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) rd_reg_dword(®->hccr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) ha->flags.mbox_int = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) *nxt = ram + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) if (!test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /* no interrupt, timed out*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) if (rval) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /* error completion status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) for (j = 0; j < dwords; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) ram[i + j] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) (IS_QLA27XX(ha) || IS_QLA28XX(ha)) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) chunk[j] : swab32(chunk[j]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) *nxt = ram + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) return QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) qla24xx_dump_ram(struct qla_hw_data *ha, uint32_t addr, __be32 *ram,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) uint32_t ram_dwords, void **nxt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) int rval = QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) dma_addr_t dump_dma = ha->gid_list_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) uint32_t *chunk = (uint32_t *)ha->gid_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) uint32_t dwords = qla2x00_gid_list_size(ha) / 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) uint32_t stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) ulong i, j, timer = 6000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) for (i = 0; i < ram_dwords; i += dwords, addr += dwords) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) if (i + dwords > ram_dwords)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) dwords = ram_dwords - i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) wrt_reg_word(®->mailbox0, MBC_DUMP_RISC_RAM_EXTENDED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) wrt_reg_word(®->mailbox1, LSW(addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) wrt_reg_word(®->mailbox8, MSW(addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) wrt_reg_word(®->mailbox10, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) wrt_reg_word(®->mailbox2, MSW(LSD(dump_dma)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) wrt_reg_word(®->mailbox3, LSW(LSD(dump_dma)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) wrt_reg_word(®->mailbox6, MSW(MSD(dump_dma)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) wrt_reg_word(®->mailbox7, LSW(MSD(dump_dma)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) wrt_reg_word(®->mailbox4, MSW(dwords));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) wrt_reg_word(®->mailbox5, LSW(dwords));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) wrt_reg_dword(®->hccr, HCCRX_SET_HOST_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) ha->flags.mbox_int = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) while (timer--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) udelay(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) stat = rd_reg_dword(®->host_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) /* Check for pending interrupts. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) if (!(stat & HSRX_RISC_INT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) stat &= 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) if (stat != 0x1 && stat != 0x2 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) stat != 0x10 && stat != 0x11) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) wrt_reg_dword(®->hccr, HCCRX_CLR_RISC_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) rd_reg_dword(®->hccr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) set_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) rval = rd_reg_word(®->mailbox0) & MBS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) wrt_reg_dword(®->hccr, HCCRX_CLR_RISC_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) rd_reg_dword(®->hccr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) ha->flags.mbox_int = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) *nxt = ram + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) if (!test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) /* no interrupt, timed out*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) if (rval) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /* error completion status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) for (j = 0; j < dwords; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) ram[i + j] = (__force __be32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) ((IS_QLA27XX(ha) || IS_QLA28XX(ha)) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) chunk[j] : swab32(chunk[j]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) *nxt = ram + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) return QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) qla24xx_dump_memory(struct qla_hw_data *ha, __be32 *code_ram,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) uint32_t cram_size, void **nxt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) int rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) /* Code RAM. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) rval = qla24xx_dump_ram(ha, 0x20000, code_ram, cram_size / 4, nxt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) if (rval != QLA_SUCCESS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) set_bit(RISC_SRAM_DUMP_CMPL, &ha->fw_dump_cap_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) /* External Memory. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) rval = qla24xx_dump_ram(ha, 0x100000, *nxt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) ha->fw_memory_size - 0x100000 + 1, nxt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) if (rval == QLA_SUCCESS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) set_bit(RISC_EXT_MEM_DUMP_CMPL, &ha->fw_dump_cap_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) static __be32 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) qla24xx_read_window(struct device_reg_24xx __iomem *reg, uint32_t iobase,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) uint32_t count, __be32 *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) __le32 __iomem *dmp_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) wrt_reg_dword(®->iobase_addr, iobase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) dmp_reg = ®->iobase_window;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) for ( ; count--; dmp_reg++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) *buf++ = htonl(rd_reg_dword(dmp_reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) return buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) qla24xx_pause_risc(struct device_reg_24xx __iomem *reg, struct qla_hw_data *ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) wrt_reg_dword(®->hccr, HCCRX_SET_RISC_PAUSE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) /* 100 usec delay is sufficient enough for hardware to pause RISC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) if (rd_reg_dword(®->host_status) & HSRX_RISC_PAUSED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) set_bit(RISC_PAUSE_CMPL, &ha->fw_dump_cap_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) qla24xx_soft_reset(struct qla_hw_data *ha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) int rval = QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) uint32_t cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) uint16_t wd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) * Reset RISC. The delay is dependent on system architecture.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) * Driver can proceed with the reset sequence after waiting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) * for a timeout period.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) wrt_reg_dword(®->ctrl_status, CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) for (cnt = 0; cnt < 30000; cnt++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) if ((rd_reg_dword(®->ctrl_status) & CSRX_DMA_ACTIVE) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) if (!(rd_reg_dword(®->ctrl_status) & CSRX_DMA_ACTIVE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) set_bit(DMA_SHUTDOWN_CMPL, &ha->fw_dump_cap_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) wrt_reg_dword(®->ctrl_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) /* Wait for soft-reset to complete. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) for (cnt = 0; cnt < 30000; cnt++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) if ((rd_reg_dword(®->ctrl_status) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) CSRX_ISP_SOFT_RESET) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) if (!(rd_reg_dword(®->ctrl_status) & CSRX_ISP_SOFT_RESET))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) set_bit(ISP_RESET_CMPL, &ha->fw_dump_cap_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) wrt_reg_dword(®->hccr, HCCRX_CLR_RISC_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) rd_reg_dword(®->hccr); /* PCI Posting. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) for (cnt = 10000; rd_reg_word(®->mailbox0) != 0 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) rval == QLA_SUCCESS; cnt--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) if (cnt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) rval = QLA_FUNCTION_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) if (rval == QLA_SUCCESS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) set_bit(RISC_RDY_AFT_RESET, &ha->fw_dump_cap_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) qla2xxx_dump_ram(struct qla_hw_data *ha, uint32_t addr, __be16 *ram,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) uint32_t ram_words, void **nxt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) int rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) uint32_t cnt, stat, timer, words, idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) uint16_t mb0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) dma_addr_t dump_dma = ha->gid_list_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) __le16 *dump = (__force __le16 *)ha->gid_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) rval = QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) mb0 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) WRT_MAILBOX_REG(ha, reg, 0, MBC_DUMP_RISC_RAM_EXTENDED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) words = qla2x00_gid_list_size(ha) / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) for (cnt = 0; cnt < ram_words && rval == QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) cnt += words, addr += words) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) if (cnt + words > ram_words)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) words = ram_words - cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) WRT_MAILBOX_REG(ha, reg, 1, LSW(addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) WRT_MAILBOX_REG(ha, reg, 8, MSW(addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) WRT_MAILBOX_REG(ha, reg, 2, MSW(dump_dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) WRT_MAILBOX_REG(ha, reg, 3, LSW(dump_dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) WRT_MAILBOX_REG(ha, reg, 6, MSW(MSD(dump_dma)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) WRT_MAILBOX_REG(ha, reg, 7, LSW(MSD(dump_dma)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) WRT_MAILBOX_REG(ha, reg, 4, words);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) wrt_reg_word(®->hccr, HCCR_SET_HOST_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) for (timer = 6000000; timer; timer--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) /* Check for pending interrupts. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) stat = rd_reg_dword(®->u.isp2300.host_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) if (stat & HSR_RISC_INT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) stat &= 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) if (stat == 0x1 || stat == 0x2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) set_bit(MBX_INTERRUPT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) &ha->mbx_cmd_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) mb0 = RD_MAILBOX_REG(ha, reg, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) /* Release mailbox registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) wrt_reg_word(®->semaphore, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) wrt_reg_word(®->hccr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) HCCR_CLR_RISC_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) rd_reg_word(®->hccr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) } else if (stat == 0x10 || stat == 0x11) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) set_bit(MBX_INTERRUPT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) &ha->mbx_cmd_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) mb0 = RD_MAILBOX_REG(ha, reg, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) wrt_reg_word(®->hccr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) HCCR_CLR_RISC_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) rd_reg_word(®->hccr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) /* clear this intr; it wasn't a mailbox intr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) wrt_reg_word(®->hccr, HCCR_CLR_RISC_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) rd_reg_word(®->hccr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) udelay(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) rval = mb0 & MBS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) for (idx = 0; idx < words; idx++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) ram[cnt + idx] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) cpu_to_be16(le16_to_cpu(dump[idx]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) rval = QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) *nxt = rval == QLA_SUCCESS ? &ram[cnt] : NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) qla2xxx_read_window(struct device_reg_2xxx __iomem *reg, uint32_t count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) __be16 *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) __le16 __iomem *dmp_reg = ®->u.isp2300.fb_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) for ( ; count--; dmp_reg++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) *buf++ = htons(rd_reg_word(dmp_reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) static inline void *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) qla24xx_copy_eft(struct qla_hw_data *ha, void *ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) if (!ha->eft)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) return ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) memcpy(ptr, ha->eft, ntohl(ha->fw_dump->eft_size));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) return ptr + ntohl(ha->fw_dump->eft_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) static inline void *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) qla25xx_copy_fce(struct qla_hw_data *ha, void *ptr, __be32 **last_chain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) uint32_t cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) __be32 *iter_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) struct qla2xxx_fce_chain *fcec = ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) if (!ha->fce)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) return ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) *last_chain = &fcec->type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) fcec->type = htonl(DUMP_CHAIN_FCE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) fcec->chain_size = htonl(sizeof(struct qla2xxx_fce_chain) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) fce_calc_size(ha->fce_bufs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) fcec->size = htonl(fce_calc_size(ha->fce_bufs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) fcec->addr_l = htonl(LSD(ha->fce_dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) fcec->addr_h = htonl(MSD(ha->fce_dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) iter_reg = fcec->eregs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) for (cnt = 0; cnt < 8; cnt++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) *iter_reg++ = htonl(ha->fce_mb[cnt]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) memcpy(iter_reg, ha->fce, ntohl(fcec->size));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) return (char *)iter_reg + ntohl(fcec->size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) static inline void *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) qla25xx_copy_exlogin(struct qla_hw_data *ha, void *ptr, __be32 **last_chain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) struct qla2xxx_offld_chain *c = ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) if (!ha->exlogin_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) return ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) *last_chain = &c->type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) c->type = cpu_to_be32(DUMP_CHAIN_EXLOGIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) c->chain_size = cpu_to_be32(sizeof(struct qla2xxx_offld_chain) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) ha->exlogin_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) c->size = cpu_to_be32(ha->exlogin_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) c->addr = cpu_to_be64(ha->exlogin_buf_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) ptr += sizeof(struct qla2xxx_offld_chain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) memcpy(ptr, ha->exlogin_buf, ha->exlogin_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) return (char *)ptr + be32_to_cpu(c->size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) static inline void *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) qla81xx_copy_exchoffld(struct qla_hw_data *ha, void *ptr, __be32 **last_chain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) struct qla2xxx_offld_chain *c = ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) if (!ha->exchoffld_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) return ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) *last_chain = &c->type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) c->type = cpu_to_be32(DUMP_CHAIN_EXCHG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) c->chain_size = cpu_to_be32(sizeof(struct qla2xxx_offld_chain) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) ha->exchoffld_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) c->size = cpu_to_be32(ha->exchoffld_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) c->addr = cpu_to_be64(ha->exchoffld_buf_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) ptr += sizeof(struct qla2xxx_offld_chain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) memcpy(ptr, ha->exchoffld_buf, ha->exchoffld_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) return (char *)ptr + be32_to_cpu(c->size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) static inline void *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) qla2xxx_copy_atioqueues(struct qla_hw_data *ha, void *ptr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) __be32 **last_chain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) struct qla2xxx_mqueue_chain *q;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) struct qla2xxx_mqueue_header *qh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) uint32_t num_queues;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) int que;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) int length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) void *ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) } aq, *aqp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) if (!ha->tgt.atio_ring)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) return ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) num_queues = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) aqp = &aq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) aqp->length = ha->tgt.atio_q_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) aqp->ring = ha->tgt.atio_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) for (que = 0; que < num_queues; que++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) /* aqp = ha->atio_q_map[que]; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) q = ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) *last_chain = &q->type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) q->type = htonl(DUMP_CHAIN_QUEUE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) q->chain_size = htonl(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) sizeof(struct qla2xxx_mqueue_chain) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) sizeof(struct qla2xxx_mqueue_header) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) (aqp->length * sizeof(request_t)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) ptr += sizeof(struct qla2xxx_mqueue_chain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) /* Add header. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) qh = ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) qh->queue = htonl(TYPE_ATIO_QUEUE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) qh->number = htonl(que);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) qh->size = htonl(aqp->length * sizeof(request_t));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) ptr += sizeof(struct qla2xxx_mqueue_header);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) /* Add data. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) memcpy(ptr, aqp->ring, aqp->length * sizeof(request_t));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) ptr += aqp->length * sizeof(request_t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) return ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) static inline void *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) qla25xx_copy_mqueues(struct qla_hw_data *ha, void *ptr, __be32 **last_chain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) struct qla2xxx_mqueue_chain *q;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) struct qla2xxx_mqueue_header *qh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) struct req_que *req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) struct rsp_que *rsp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) int que;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) if (!ha->mqenable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) return ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) /* Request queues */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) for (que = 1; que < ha->max_req_queues; que++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) req = ha->req_q_map[que];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) if (!req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) /* Add chain. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) q = ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) *last_chain = &q->type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) q->type = htonl(DUMP_CHAIN_QUEUE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) q->chain_size = htonl(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) sizeof(struct qla2xxx_mqueue_chain) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) sizeof(struct qla2xxx_mqueue_header) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) (req->length * sizeof(request_t)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) ptr += sizeof(struct qla2xxx_mqueue_chain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) /* Add header. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) qh = ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) qh->queue = htonl(TYPE_REQUEST_QUEUE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) qh->number = htonl(que);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) qh->size = htonl(req->length * sizeof(request_t));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) ptr += sizeof(struct qla2xxx_mqueue_header);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) /* Add data. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) memcpy(ptr, req->ring, req->length * sizeof(request_t));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) ptr += req->length * sizeof(request_t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) /* Response queues */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) for (que = 1; que < ha->max_rsp_queues; que++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) rsp = ha->rsp_q_map[que];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) if (!rsp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) /* Add chain. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) q = ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) *last_chain = &q->type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) q->type = htonl(DUMP_CHAIN_QUEUE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) q->chain_size = htonl(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) sizeof(struct qla2xxx_mqueue_chain) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) sizeof(struct qla2xxx_mqueue_header) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) (rsp->length * sizeof(response_t)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) ptr += sizeof(struct qla2xxx_mqueue_chain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) /* Add header. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) qh = ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) qh->queue = htonl(TYPE_RESPONSE_QUEUE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) qh->number = htonl(que);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) qh->size = htonl(rsp->length * sizeof(response_t));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) ptr += sizeof(struct qla2xxx_mqueue_header);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) /* Add data. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) memcpy(ptr, rsp->ring, rsp->length * sizeof(response_t));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) ptr += rsp->length * sizeof(response_t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) return ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) static inline void *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) qla25xx_copy_mq(struct qla_hw_data *ha, void *ptr, __be32 **last_chain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) uint32_t cnt, que_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) uint8_t que_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) struct qla2xxx_mq_chain *mq = ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) device_reg_t *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) if (!ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) IS_QLA28XX(ha))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) return ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) mq = ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) *last_chain = &mq->type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) mq->type = htonl(DUMP_CHAIN_MQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) mq->chain_size = htonl(sizeof(struct qla2xxx_mq_chain));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) que_cnt = ha->max_req_queues > ha->max_rsp_queues ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) ha->max_req_queues : ha->max_rsp_queues;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) mq->count = htonl(que_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) for (cnt = 0; cnt < que_cnt; cnt++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) reg = ISP_QUE_REG(ha, cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) que_idx = cnt * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) mq->qregs[que_idx] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) htonl(rd_reg_dword(®->isp25mq.req_q_in));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) mq->qregs[que_idx+1] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) htonl(rd_reg_dword(®->isp25mq.req_q_out));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) mq->qregs[que_idx+2] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) htonl(rd_reg_dword(®->isp25mq.rsp_q_in));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) mq->qregs[que_idx+3] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) htonl(rd_reg_dword(®->isp25mq.rsp_q_out));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) return ptr + sizeof(struct qla2xxx_mq_chain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) qla2xxx_dump_post_process(scsi_qla_host_t *vha, int rval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) if (rval != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) ql_log(ql_log_warn, vha, 0xd000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) "Failed to dump firmware (%x), dump status flags (0x%lx).\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) rval, ha->fw_dump_cap_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) ha->fw_dumped = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) ql_log(ql_log_info, vha, 0xd001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) "Firmware dump saved to temp buffer (%ld/%p), dump status flags (0x%lx).\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) vha->host_no, ha->fw_dump, ha->fw_dump_cap_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) ha->fw_dumped = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) qla2x00_post_uevent_work(vha, QLA_UEVENT_CODE_FW_DUMP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) void qla2xxx_dump_fw(scsi_qla_host_t *vha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) spin_lock_irqsave(&vha->hw->hardware_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) vha->hw->isp_ops->fw_dump(vha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) spin_unlock_irqrestore(&vha->hw->hardware_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) * qla2300_fw_dump() - Dumps binary data from the 2300 firmware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) * @vha: HA context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) qla2300_fw_dump(scsi_qla_host_t *vha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) int rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) uint32_t cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) __le16 __iomem *dmp_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) struct qla2300_fw_dump *fw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) void *nxt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) lockdep_assert_held(&ha->hardware_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) if (!ha->fw_dump) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) ql_log(ql_log_warn, vha, 0xd002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) "No buffer available for dump.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) if (ha->fw_dumped) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) ql_log(ql_log_warn, vha, 0xd003,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) "Firmware has been previously dumped (%p) "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) "-- ignoring request.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) ha->fw_dump);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) fw = &ha->fw_dump->isp.isp23;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) qla2xxx_prep_dump(ha, ha->fw_dump);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) rval = QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) fw->hccr = htons(rd_reg_word(®->hccr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) /* Pause RISC. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) wrt_reg_word(®->hccr, HCCR_PAUSE_RISC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) if (IS_QLA2300(ha)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) for (cnt = 30000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) (rd_reg_word(®->hccr) & HCCR_RISC_PAUSE) == 0 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) rval == QLA_SUCCESS; cnt--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) if (cnt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) rval = QLA_FUNCTION_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) rd_reg_word(®->hccr); /* PCI Posting. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) if (rval == QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) dmp_reg = ®->flash_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) for (cnt = 0; cnt < ARRAY_SIZE(fw->pbiu_reg); cnt++, dmp_reg++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) fw->pbiu_reg[cnt] = htons(rd_reg_word(dmp_reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) dmp_reg = ®->u.isp2300.req_q_in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) for (cnt = 0; cnt < ARRAY_SIZE(fw->risc_host_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) cnt++, dmp_reg++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) fw->risc_host_reg[cnt] = htons(rd_reg_word(dmp_reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) dmp_reg = ®->u.isp2300.mailbox0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) for (cnt = 0; cnt < ARRAY_SIZE(fw->mailbox_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) cnt++, dmp_reg++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) fw->mailbox_reg[cnt] = htons(rd_reg_word(dmp_reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) wrt_reg_word(®->ctrl_status, 0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) qla2xxx_read_window(reg, 32, fw->resp_dma_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) wrt_reg_word(®->ctrl_status, 0x50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) qla2xxx_read_window(reg, 48, fw->dma_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) wrt_reg_word(®->ctrl_status, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) dmp_reg = ®->risc_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) for (cnt = 0; cnt < ARRAY_SIZE(fw->risc_hdw_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) cnt++, dmp_reg++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) fw->risc_hdw_reg[cnt] = htons(rd_reg_word(dmp_reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) wrt_reg_word(®->pcr, 0x2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) qla2xxx_read_window(reg, 16, fw->risc_gp0_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) wrt_reg_word(®->pcr, 0x2200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) qla2xxx_read_window(reg, 16, fw->risc_gp1_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) wrt_reg_word(®->pcr, 0x2400);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) qla2xxx_read_window(reg, 16, fw->risc_gp2_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) wrt_reg_word(®->pcr, 0x2600);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) qla2xxx_read_window(reg, 16, fw->risc_gp3_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) wrt_reg_word(®->pcr, 0x2800);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) qla2xxx_read_window(reg, 16, fw->risc_gp4_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) wrt_reg_word(®->pcr, 0x2A00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) qla2xxx_read_window(reg, 16, fw->risc_gp5_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) wrt_reg_word(®->pcr, 0x2C00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) qla2xxx_read_window(reg, 16, fw->risc_gp6_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) wrt_reg_word(®->pcr, 0x2E00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) qla2xxx_read_window(reg, 16, fw->risc_gp7_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) wrt_reg_word(®->ctrl_status, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) qla2xxx_read_window(reg, 64, fw->frame_buf_hdw_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) wrt_reg_word(®->ctrl_status, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) qla2xxx_read_window(reg, 64, fw->fpm_b0_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) wrt_reg_word(®->ctrl_status, 0x30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) qla2xxx_read_window(reg, 64, fw->fpm_b1_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) /* Reset RISC. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) wrt_reg_word(®->ctrl_status, CSR_ISP_SOFT_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) for (cnt = 0; cnt < 30000; cnt++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) if ((rd_reg_word(®->ctrl_status) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) CSR_ISP_SOFT_RESET) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) if (!IS_QLA2300(ha)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) for (cnt = 30000; RD_MAILBOX_REG(ha, reg, 0) != 0 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) rval == QLA_SUCCESS; cnt--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) if (cnt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) rval = QLA_FUNCTION_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) /* Get RISC SRAM. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) if (rval == QLA_SUCCESS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) rval = qla2xxx_dump_ram(ha, 0x800, fw->risc_ram,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) ARRAY_SIZE(fw->risc_ram), &nxt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) /* Get stack SRAM. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) if (rval == QLA_SUCCESS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) rval = qla2xxx_dump_ram(ha, 0x10000, fw->stack_ram,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) ARRAY_SIZE(fw->stack_ram), &nxt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) /* Get data SRAM. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) if (rval == QLA_SUCCESS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) rval = qla2xxx_dump_ram(ha, 0x11000, fw->data_ram,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) ha->fw_memory_size - 0x11000 + 1, &nxt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) if (rval == QLA_SUCCESS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) qla2xxx_copy_queues(ha, nxt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) qla2xxx_dump_post_process(base_vha, rval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) * qla2100_fw_dump() - Dumps binary data from the 2100/2200 firmware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) * @vha: HA context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) qla2100_fw_dump(scsi_qla_host_t *vha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) int rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) uint32_t cnt, timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) uint16_t risc_address = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) uint16_t mb0 = 0, mb2 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) __le16 __iomem *dmp_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) struct qla2100_fw_dump *fw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) lockdep_assert_held(&ha->hardware_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) if (!ha->fw_dump) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) ql_log(ql_log_warn, vha, 0xd004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) "No buffer available for dump.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) if (ha->fw_dumped) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) ql_log(ql_log_warn, vha, 0xd005,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) "Firmware has been previously dumped (%p) "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) "-- ignoring request.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) ha->fw_dump);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) fw = &ha->fw_dump->isp.isp21;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) qla2xxx_prep_dump(ha, ha->fw_dump);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) rval = QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) fw->hccr = htons(rd_reg_word(®->hccr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) /* Pause RISC. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) wrt_reg_word(®->hccr, HCCR_PAUSE_RISC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) for (cnt = 30000; (rd_reg_word(®->hccr) & HCCR_RISC_PAUSE) == 0 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) rval == QLA_SUCCESS; cnt--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) if (cnt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) rval = QLA_FUNCTION_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) if (rval == QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) dmp_reg = ®->flash_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) for (cnt = 0; cnt < ARRAY_SIZE(fw->pbiu_reg); cnt++, dmp_reg++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) fw->pbiu_reg[cnt] = htons(rd_reg_word(dmp_reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) dmp_reg = ®->u.isp2100.mailbox0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) for (cnt = 0; cnt < ha->mbx_count; cnt++, dmp_reg++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) if (cnt == 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) dmp_reg = ®->u_end.isp2200.mailbox8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) fw->mailbox_reg[cnt] = htons(rd_reg_word(dmp_reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) dmp_reg = ®->u.isp2100.unused_2[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) for (cnt = 0; cnt < ARRAY_SIZE(fw->dma_reg); cnt++, dmp_reg++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) fw->dma_reg[cnt] = htons(rd_reg_word(dmp_reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) wrt_reg_word(®->ctrl_status, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) dmp_reg = ®->risc_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) for (cnt = 0; cnt < ARRAY_SIZE(fw->risc_hdw_reg); cnt++, dmp_reg++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) fw->risc_hdw_reg[cnt] = htons(rd_reg_word(dmp_reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) wrt_reg_word(®->pcr, 0x2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) qla2xxx_read_window(reg, 16, fw->risc_gp0_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) wrt_reg_word(®->pcr, 0x2100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) qla2xxx_read_window(reg, 16, fw->risc_gp1_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) wrt_reg_word(®->pcr, 0x2200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) qla2xxx_read_window(reg, 16, fw->risc_gp2_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) wrt_reg_word(®->pcr, 0x2300);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) qla2xxx_read_window(reg, 16, fw->risc_gp3_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) wrt_reg_word(®->pcr, 0x2400);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) qla2xxx_read_window(reg, 16, fw->risc_gp4_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) wrt_reg_word(®->pcr, 0x2500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) qla2xxx_read_window(reg, 16, fw->risc_gp5_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) wrt_reg_word(®->pcr, 0x2600);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) qla2xxx_read_window(reg, 16, fw->risc_gp6_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) wrt_reg_word(®->pcr, 0x2700);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) qla2xxx_read_window(reg, 16, fw->risc_gp7_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) wrt_reg_word(®->ctrl_status, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) qla2xxx_read_window(reg, 16, fw->frame_buf_hdw_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) wrt_reg_word(®->ctrl_status, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) qla2xxx_read_window(reg, 64, fw->fpm_b0_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) wrt_reg_word(®->ctrl_status, 0x30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) qla2xxx_read_window(reg, 64, fw->fpm_b1_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) /* Reset the ISP. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) wrt_reg_word(®->ctrl_status, CSR_ISP_SOFT_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) for (cnt = 30000; RD_MAILBOX_REG(ha, reg, 0) != 0 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) rval == QLA_SUCCESS; cnt--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) if (cnt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) rval = QLA_FUNCTION_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) /* Pause RISC. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) if (rval == QLA_SUCCESS && (IS_QLA2200(ha) || (IS_QLA2100(ha) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) (rd_reg_word(®->mctr) & (BIT_1 | BIT_0)) != 0))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) wrt_reg_word(®->hccr, HCCR_PAUSE_RISC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) for (cnt = 30000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) (rd_reg_word(®->hccr) & HCCR_RISC_PAUSE) == 0 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) rval == QLA_SUCCESS; cnt--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) if (cnt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) rval = QLA_FUNCTION_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) if (rval == QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) /* Set memory configuration and timing. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) if (IS_QLA2100(ha))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) wrt_reg_word(®->mctr, 0xf1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) wrt_reg_word(®->mctr, 0xf2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) rd_reg_word(®->mctr); /* PCI Posting. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) /* Release RISC. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) wrt_reg_word(®->hccr, HCCR_RELEASE_RISC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) if (rval == QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) /* Get RISC SRAM. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) risc_address = 0x1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) WRT_MAILBOX_REG(ha, reg, 0, MBC_READ_RAM_WORD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) for (cnt = 0; cnt < ARRAY_SIZE(fw->risc_ram) && rval == QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) cnt++, risc_address++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) WRT_MAILBOX_REG(ha, reg, 1, risc_address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) wrt_reg_word(®->hccr, HCCR_SET_HOST_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) for (timer = 6000000; timer != 0; timer--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) /* Check for pending interrupts. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) if (rd_reg_word(®->istatus) & ISR_RISC_INT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) if (rd_reg_word(®->semaphore) & BIT_0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) set_bit(MBX_INTERRUPT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) &ha->mbx_cmd_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) mb0 = RD_MAILBOX_REG(ha, reg, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) mb2 = RD_MAILBOX_REG(ha, reg, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) wrt_reg_word(®->semaphore, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) wrt_reg_word(®->hccr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) HCCR_CLR_RISC_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) rd_reg_word(®->hccr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) wrt_reg_word(®->hccr, HCCR_CLR_RISC_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) rd_reg_word(®->hccr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) udelay(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) rval = mb0 & MBS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) fw->risc_ram[cnt] = htons(mb2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) rval = QLA_FUNCTION_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) if (rval == QLA_SUCCESS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) qla2xxx_copy_queues(ha, &fw->queue_dump[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) qla2xxx_dump_post_process(base_vha, rval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) qla24xx_fw_dump(scsi_qla_host_t *vha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) int rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) uint32_t cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) __le32 __iomem *dmp_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) __be32 *iter_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) __le16 __iomem *mbx_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) struct qla24xx_fw_dump *fw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) void *nxt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) void *nxt_chain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) __be32 *last_chain = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) lockdep_assert_held(&ha->hardware_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) if (IS_P3P_TYPE(ha))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) ha->fw_dump_cap_flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) if (!ha->fw_dump) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) ql_log(ql_log_warn, vha, 0xd006,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) "No buffer available for dump.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) if (ha->fw_dumped) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) ql_log(ql_log_warn, vha, 0xd007,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) "Firmware has been previously dumped (%p) "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) "-- ignoring request.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) ha->fw_dump);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) QLA_FW_STOPPED(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) fw = &ha->fw_dump->isp.isp24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) qla2xxx_prep_dump(ha, ha->fw_dump);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) fw->host_status = htonl(rd_reg_dword(®->host_status));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) * Pause RISC. No need to track timeout, as resetting the chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) * is the right approach incase of pause timeout
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) qla24xx_pause_risc(reg, ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) /* Host interface registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) dmp_reg = ®->flash_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) for (cnt = 0; cnt < ARRAY_SIZE(fw->host_reg); cnt++, dmp_reg++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) fw->host_reg[cnt] = htonl(rd_reg_dword(dmp_reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) /* Disable interrupts. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) wrt_reg_dword(®->ictrl, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) rd_reg_dword(®->ictrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) /* Shadow registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) wrt_reg_dword(®->iobase_addr, 0x0F70);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) rd_reg_dword(®->iobase_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) wrt_reg_dword(®->iobase_select, 0xB0000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) fw->shadow_reg[0] = htonl(rd_reg_dword(®->iobase_sdata));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) wrt_reg_dword(®->iobase_select, 0xB0100000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) fw->shadow_reg[1] = htonl(rd_reg_dword(®->iobase_sdata));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) wrt_reg_dword(®->iobase_select, 0xB0200000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) fw->shadow_reg[2] = htonl(rd_reg_dword(®->iobase_sdata));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) wrt_reg_dword(®->iobase_select, 0xB0300000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) fw->shadow_reg[3] = htonl(rd_reg_dword(®->iobase_sdata));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) wrt_reg_dword(®->iobase_select, 0xB0400000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) fw->shadow_reg[4] = htonl(rd_reg_dword(®->iobase_sdata));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) wrt_reg_dword(®->iobase_select, 0xB0500000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) fw->shadow_reg[5] = htonl(rd_reg_dword(®->iobase_sdata));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) wrt_reg_dword(®->iobase_select, 0xB0600000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) fw->shadow_reg[6] = htonl(rd_reg_dword(®->iobase_sdata));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) /* Mailbox registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) mbx_reg = ®->mailbox0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) for (cnt = 0; cnt < ARRAY_SIZE(fw->mailbox_reg); cnt++, mbx_reg++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) fw->mailbox_reg[cnt] = htons(rd_reg_word(mbx_reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) /* Transfer sequence registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) iter_reg = fw->xseq_gp_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) qla24xx_read_window(reg, 0xBF70, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) qla24xx_read_window(reg, 0xBFE0, 16, fw->xseq_0_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) /* Receive sequence registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) iter_reg = fw->rseq_gp_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) qla24xx_read_window(reg, 0xFF70, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) qla24xx_read_window(reg, 0xFFD0, 16, fw->rseq_0_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) /* Command DMA registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) /* Queues. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) iter_reg = fw->req0_dma_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) dmp_reg = ®->iobase_q;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) for (cnt = 0; cnt < 7; cnt++, dmp_reg++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) *iter_reg++ = htonl(rd_reg_dword(dmp_reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) iter_reg = fw->resp0_dma_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) dmp_reg = ®->iobase_q;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) for (cnt = 0; cnt < 7; cnt++, dmp_reg++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) *iter_reg++ = htonl(rd_reg_dword(dmp_reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) iter_reg = fw->req1_dma_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) dmp_reg = ®->iobase_q;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) for (cnt = 0; cnt < 7; cnt++, dmp_reg++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) *iter_reg++ = htonl(rd_reg_dword(dmp_reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) /* Transmit DMA registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) iter_reg = fw->xmt0_dma_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) qla24xx_read_window(reg, 0x7610, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) iter_reg = fw->xmt1_dma_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) qla24xx_read_window(reg, 0x7630, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) iter_reg = fw->xmt2_dma_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) qla24xx_read_window(reg, 0x7650, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) iter_reg = fw->xmt3_dma_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) qla24xx_read_window(reg, 0x7670, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) iter_reg = fw->xmt4_dma_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) qla24xx_read_window(reg, 0x7690, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) /* Receive DMA registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) iter_reg = fw->rcvt0_data_dma_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) qla24xx_read_window(reg, 0x7710, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) iter_reg = fw->rcvt1_data_dma_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) qla24xx_read_window(reg, 0x7730, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) /* RISC registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) iter_reg = fw->risc_gp_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) qla24xx_read_window(reg, 0x0F70, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) /* Local memory controller registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) iter_reg = fw->lmc_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) qla24xx_read_window(reg, 0x3060, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) /* Fibre Protocol Module registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) iter_reg = fw->fpm_hdw_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) qla24xx_read_window(reg, 0x40B0, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) /* Frame Buffer registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) iter_reg = fw->fb_hdw_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) qla24xx_read_window(reg, 0x61B0, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) rval = qla24xx_soft_reset(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) if (rval != QLA_SUCCESS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) goto qla24xx_fw_dump_failed_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) &nxt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) if (rval != QLA_SUCCESS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) goto qla24xx_fw_dump_failed_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) nxt = qla2xxx_copy_queues(ha, nxt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) qla24xx_copy_eft(ha, nxt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) nxt_chain = (void *)ha->fw_dump + ha->chain_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) nxt_chain = qla2xxx_copy_atioqueues(ha, nxt_chain, &last_chain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) if (last_chain) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) ha->fw_dump->version |= htonl(DUMP_CHAIN_VARIANT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) *last_chain |= htonl(DUMP_CHAIN_LAST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) /* Adjust valid length. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) ha->fw_dump_len = (nxt_chain - (void *)ha->fw_dump);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) qla24xx_fw_dump_failed_0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) qla2xxx_dump_post_process(base_vha, rval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) qla25xx_fw_dump(scsi_qla_host_t *vha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) int rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) uint32_t cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) __le32 __iomem *dmp_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) __be32 *iter_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) __le16 __iomem *mbx_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) struct qla25xx_fw_dump *fw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) void *nxt, *nxt_chain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) __be32 *last_chain = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) lockdep_assert_held(&ha->hardware_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) ha->fw_dump_cap_flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) if (!ha->fw_dump) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) ql_log(ql_log_warn, vha, 0xd008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) "No buffer available for dump.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) if (ha->fw_dumped) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) ql_log(ql_log_warn, vha, 0xd009,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) "Firmware has been previously dumped (%p) "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) "-- ignoring request.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) ha->fw_dump);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) QLA_FW_STOPPED(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) fw = &ha->fw_dump->isp.isp25;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) qla2xxx_prep_dump(ha, ha->fw_dump);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) ha->fw_dump->version = htonl(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) fw->host_status = htonl(rd_reg_dword(®->host_status));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) * Pause RISC. No need to track timeout, as resetting the chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) * is the right approach incase of pause timeout
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) qla24xx_pause_risc(reg, ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) /* Host/Risc registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) iter_reg = fw->host_risc_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) iter_reg = qla24xx_read_window(reg, 0x7000, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) qla24xx_read_window(reg, 0x7010, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) /* PCIe registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) wrt_reg_dword(®->iobase_addr, 0x7C00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) rd_reg_dword(®->iobase_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) wrt_reg_dword(®->iobase_window, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) dmp_reg = ®->iobase_c4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) fw->pcie_regs[0] = htonl(rd_reg_dword(dmp_reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) dmp_reg++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) fw->pcie_regs[1] = htonl(rd_reg_dword(dmp_reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) dmp_reg++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) fw->pcie_regs[2] = htonl(rd_reg_dword(dmp_reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) fw->pcie_regs[3] = htonl(rd_reg_dword(®->iobase_window));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) wrt_reg_dword(®->iobase_window, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) rd_reg_dword(®->iobase_window);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) /* Host interface registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) dmp_reg = ®->flash_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) for (cnt = 0; cnt < ARRAY_SIZE(fw->host_reg); cnt++, dmp_reg++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) fw->host_reg[cnt] = htonl(rd_reg_dword(dmp_reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) /* Disable interrupts. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) wrt_reg_dword(®->ictrl, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) rd_reg_dword(®->ictrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) /* Shadow registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) wrt_reg_dword(®->iobase_addr, 0x0F70);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) rd_reg_dword(®->iobase_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) wrt_reg_dword(®->iobase_select, 0xB0000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) fw->shadow_reg[0] = htonl(rd_reg_dword(®->iobase_sdata));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) wrt_reg_dword(®->iobase_select, 0xB0100000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) fw->shadow_reg[1] = htonl(rd_reg_dword(®->iobase_sdata));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) wrt_reg_dword(®->iobase_select, 0xB0200000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) fw->shadow_reg[2] = htonl(rd_reg_dword(®->iobase_sdata));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) wrt_reg_dword(®->iobase_select, 0xB0300000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) fw->shadow_reg[3] = htonl(rd_reg_dword(®->iobase_sdata));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) wrt_reg_dword(®->iobase_select, 0xB0400000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) fw->shadow_reg[4] = htonl(rd_reg_dword(®->iobase_sdata));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) wrt_reg_dword(®->iobase_select, 0xB0500000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) fw->shadow_reg[5] = htonl(rd_reg_dword(®->iobase_sdata));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) wrt_reg_dword(®->iobase_select, 0xB0600000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) fw->shadow_reg[6] = htonl(rd_reg_dword(®->iobase_sdata));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) wrt_reg_dword(®->iobase_select, 0xB0700000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) fw->shadow_reg[7] = htonl(rd_reg_dword(®->iobase_sdata));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) wrt_reg_dword(®->iobase_select, 0xB0800000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) fw->shadow_reg[8] = htonl(rd_reg_dword(®->iobase_sdata));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) wrt_reg_dword(®->iobase_select, 0xB0900000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) fw->shadow_reg[9] = htonl(rd_reg_dword(®->iobase_sdata));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) wrt_reg_dword(®->iobase_select, 0xB0A00000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) fw->shadow_reg[10] = htonl(rd_reg_dword(®->iobase_sdata));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) /* RISC I/O register. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) wrt_reg_dword(®->iobase_addr, 0x0010);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) fw->risc_io_reg = htonl(rd_reg_dword(®->iobase_window));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) /* Mailbox registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) mbx_reg = ®->mailbox0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) for (cnt = 0; cnt < ARRAY_SIZE(fw->mailbox_reg); cnt++, mbx_reg++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) fw->mailbox_reg[cnt] = htons(rd_reg_word(mbx_reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) /* Transfer sequence registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) iter_reg = fw->xseq_gp_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) qla24xx_read_window(reg, 0xBF70, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) iter_reg = fw->xseq_0_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) iter_reg = qla24xx_read_window(reg, 0xBFC0, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) iter_reg = qla24xx_read_window(reg, 0xBFD0, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) qla24xx_read_window(reg, 0xBFE0, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) /* Receive sequence registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) iter_reg = fw->rseq_gp_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) qla24xx_read_window(reg, 0xFF70, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) iter_reg = fw->rseq_0_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) iter_reg = qla24xx_read_window(reg, 0xFFC0, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) qla24xx_read_window(reg, 0xFFD0, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) /* Auxiliary sequence registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) iter_reg = fw->aseq_gp_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) iter_reg = qla24xx_read_window(reg, 0xB000, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) iter_reg = qla24xx_read_window(reg, 0xB010, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) iter_reg = qla24xx_read_window(reg, 0xB020, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) iter_reg = qla24xx_read_window(reg, 0xB030, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) iter_reg = qla24xx_read_window(reg, 0xB040, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) iter_reg = qla24xx_read_window(reg, 0xB050, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) iter_reg = qla24xx_read_window(reg, 0xB060, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) qla24xx_read_window(reg, 0xB070, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) iter_reg = fw->aseq_0_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) iter_reg = qla24xx_read_window(reg, 0xB0C0, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) qla24xx_read_window(reg, 0xB0D0, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) qla24xx_read_window(reg, 0xB0E0, 16, fw->aseq_1_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) qla24xx_read_window(reg, 0xB0F0, 16, fw->aseq_2_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) /* Command DMA registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) /* Queues. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) iter_reg = fw->req0_dma_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) dmp_reg = ®->iobase_q;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) for (cnt = 0; cnt < 7; cnt++, dmp_reg++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) *iter_reg++ = htonl(rd_reg_dword(dmp_reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) iter_reg = fw->resp0_dma_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) dmp_reg = ®->iobase_q;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) for (cnt = 0; cnt < 7; cnt++, dmp_reg++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) *iter_reg++ = htonl(rd_reg_dword(dmp_reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) iter_reg = fw->req1_dma_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) dmp_reg = ®->iobase_q;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) for (cnt = 0; cnt < 7; cnt++, dmp_reg++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) *iter_reg++ = htonl(rd_reg_dword(dmp_reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) /* Transmit DMA registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) iter_reg = fw->xmt0_dma_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) qla24xx_read_window(reg, 0x7610, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) iter_reg = fw->xmt1_dma_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) qla24xx_read_window(reg, 0x7630, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) iter_reg = fw->xmt2_dma_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) qla24xx_read_window(reg, 0x7650, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) iter_reg = fw->xmt3_dma_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) qla24xx_read_window(reg, 0x7670, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) iter_reg = fw->xmt4_dma_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) qla24xx_read_window(reg, 0x7690, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) /* Receive DMA registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) iter_reg = fw->rcvt0_data_dma_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) qla24xx_read_window(reg, 0x7710, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) iter_reg = fw->rcvt1_data_dma_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) qla24xx_read_window(reg, 0x7730, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) /* RISC registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) iter_reg = fw->risc_gp_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) qla24xx_read_window(reg, 0x0F70, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) /* Local memory controller registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) iter_reg = fw->lmc_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) iter_reg = qla24xx_read_window(reg, 0x3060, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) qla24xx_read_window(reg, 0x3070, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) /* Fibre Protocol Module registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) iter_reg = fw->fpm_hdw_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) qla24xx_read_window(reg, 0x40B0, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) /* Frame Buffer registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) iter_reg = fw->fb_hdw_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) iter_reg = qla24xx_read_window(reg, 0x61B0, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) qla24xx_read_window(reg, 0x6F00, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) /* Multi queue registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) nxt_chain = qla25xx_copy_mq(ha, (void *)ha->fw_dump + ha->chain_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) &last_chain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) rval = qla24xx_soft_reset(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) if (rval != QLA_SUCCESS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) goto qla25xx_fw_dump_failed_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) &nxt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) if (rval != QLA_SUCCESS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) goto qla25xx_fw_dump_failed_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) nxt = qla2xxx_copy_queues(ha, nxt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) qla24xx_copy_eft(ha, nxt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) /* Chain entries -- started with MQ. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) nxt_chain = qla25xx_copy_fce(ha, nxt_chain, &last_chain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) nxt_chain = qla25xx_copy_mqueues(ha, nxt_chain, &last_chain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) nxt_chain = qla2xxx_copy_atioqueues(ha, nxt_chain, &last_chain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) nxt_chain = qla25xx_copy_exlogin(ha, nxt_chain, &last_chain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) if (last_chain) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) ha->fw_dump->version |= htonl(DUMP_CHAIN_VARIANT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) *last_chain |= htonl(DUMP_CHAIN_LAST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) /* Adjust valid length. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) ha->fw_dump_len = (nxt_chain - (void *)ha->fw_dump);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) qla25xx_fw_dump_failed_0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) qla2xxx_dump_post_process(base_vha, rval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) qla81xx_fw_dump(scsi_qla_host_t *vha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) int rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) uint32_t cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) __le32 __iomem *dmp_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) __be32 *iter_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) __le16 __iomem *mbx_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) struct qla81xx_fw_dump *fw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) void *nxt, *nxt_chain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) __be32 *last_chain = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) lockdep_assert_held(&ha->hardware_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) ha->fw_dump_cap_flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) if (!ha->fw_dump) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) ql_log(ql_log_warn, vha, 0xd00a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) "No buffer available for dump.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) if (ha->fw_dumped) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) ql_log(ql_log_warn, vha, 0xd00b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) "Firmware has been previously dumped (%p) "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) "-- ignoring request.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) ha->fw_dump);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) fw = &ha->fw_dump->isp.isp81;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) qla2xxx_prep_dump(ha, ha->fw_dump);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) fw->host_status = htonl(rd_reg_dword(®->host_status));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) * Pause RISC. No need to track timeout, as resetting the chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) * is the right approach incase of pause timeout
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) qla24xx_pause_risc(reg, ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) /* Host/Risc registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) iter_reg = fw->host_risc_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) iter_reg = qla24xx_read_window(reg, 0x7000, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) qla24xx_read_window(reg, 0x7010, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) /* PCIe registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) wrt_reg_dword(®->iobase_addr, 0x7C00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) rd_reg_dword(®->iobase_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) wrt_reg_dword(®->iobase_window, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) dmp_reg = ®->iobase_c4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) fw->pcie_regs[0] = htonl(rd_reg_dword(dmp_reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) dmp_reg++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) fw->pcie_regs[1] = htonl(rd_reg_dword(dmp_reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) dmp_reg++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) fw->pcie_regs[2] = htonl(rd_reg_dword(dmp_reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) fw->pcie_regs[3] = htonl(rd_reg_dword(®->iobase_window));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) wrt_reg_dword(®->iobase_window, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) rd_reg_dword(®->iobase_window);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) /* Host interface registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) dmp_reg = ®->flash_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) for (cnt = 0; cnt < ARRAY_SIZE(fw->host_reg); cnt++, dmp_reg++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) fw->host_reg[cnt] = htonl(rd_reg_dword(dmp_reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) /* Disable interrupts. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) wrt_reg_dword(®->ictrl, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) rd_reg_dword(®->ictrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) /* Shadow registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) wrt_reg_dword(®->iobase_addr, 0x0F70);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) rd_reg_dword(®->iobase_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) wrt_reg_dword(®->iobase_select, 0xB0000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) fw->shadow_reg[0] = htonl(rd_reg_dword(®->iobase_sdata));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) wrt_reg_dword(®->iobase_select, 0xB0100000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) fw->shadow_reg[1] = htonl(rd_reg_dword(®->iobase_sdata));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) wrt_reg_dword(®->iobase_select, 0xB0200000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) fw->shadow_reg[2] = htonl(rd_reg_dword(®->iobase_sdata));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) wrt_reg_dword(®->iobase_select, 0xB0300000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) fw->shadow_reg[3] = htonl(rd_reg_dword(®->iobase_sdata));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) wrt_reg_dword(®->iobase_select, 0xB0400000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) fw->shadow_reg[4] = htonl(rd_reg_dword(®->iobase_sdata));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) wrt_reg_dword(®->iobase_select, 0xB0500000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) fw->shadow_reg[5] = htonl(rd_reg_dword(®->iobase_sdata));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) wrt_reg_dword(®->iobase_select, 0xB0600000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) fw->shadow_reg[6] = htonl(rd_reg_dword(®->iobase_sdata));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) wrt_reg_dword(®->iobase_select, 0xB0700000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) fw->shadow_reg[7] = htonl(rd_reg_dword(®->iobase_sdata));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) wrt_reg_dword(®->iobase_select, 0xB0800000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) fw->shadow_reg[8] = htonl(rd_reg_dword(®->iobase_sdata));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) wrt_reg_dword(®->iobase_select, 0xB0900000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) fw->shadow_reg[9] = htonl(rd_reg_dword(®->iobase_sdata));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) wrt_reg_dword(®->iobase_select, 0xB0A00000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) fw->shadow_reg[10] = htonl(rd_reg_dword(®->iobase_sdata));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) /* RISC I/O register. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) wrt_reg_dword(®->iobase_addr, 0x0010);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) fw->risc_io_reg = htonl(rd_reg_dword(®->iobase_window));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) /* Mailbox registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) mbx_reg = ®->mailbox0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) for (cnt = 0; cnt < ARRAY_SIZE(fw->mailbox_reg); cnt++, mbx_reg++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) fw->mailbox_reg[cnt] = htons(rd_reg_word(mbx_reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) /* Transfer sequence registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) iter_reg = fw->xseq_gp_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) qla24xx_read_window(reg, 0xBF70, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) iter_reg = fw->xseq_0_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) iter_reg = qla24xx_read_window(reg, 0xBFC0, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) iter_reg = qla24xx_read_window(reg, 0xBFD0, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) qla24xx_read_window(reg, 0xBFE0, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) /* Receive sequence registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) iter_reg = fw->rseq_gp_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) qla24xx_read_window(reg, 0xFF70, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) iter_reg = fw->rseq_0_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) iter_reg = qla24xx_read_window(reg, 0xFFC0, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) qla24xx_read_window(reg, 0xFFD0, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) /* Auxiliary sequence registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) iter_reg = fw->aseq_gp_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) iter_reg = qla24xx_read_window(reg, 0xB000, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) iter_reg = qla24xx_read_window(reg, 0xB010, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) iter_reg = qla24xx_read_window(reg, 0xB020, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) iter_reg = qla24xx_read_window(reg, 0xB030, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) iter_reg = qla24xx_read_window(reg, 0xB040, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) iter_reg = qla24xx_read_window(reg, 0xB050, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) iter_reg = qla24xx_read_window(reg, 0xB060, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) qla24xx_read_window(reg, 0xB070, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) iter_reg = fw->aseq_0_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) iter_reg = qla24xx_read_window(reg, 0xB0C0, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) qla24xx_read_window(reg, 0xB0D0, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) qla24xx_read_window(reg, 0xB0E0, 16, fw->aseq_1_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) qla24xx_read_window(reg, 0xB0F0, 16, fw->aseq_2_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) /* Command DMA registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) /* Queues. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) iter_reg = fw->req0_dma_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) dmp_reg = ®->iobase_q;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) for (cnt = 0; cnt < 7; cnt++, dmp_reg++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) *iter_reg++ = htonl(rd_reg_dword(dmp_reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) iter_reg = fw->resp0_dma_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) dmp_reg = ®->iobase_q;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) for (cnt = 0; cnt < 7; cnt++, dmp_reg++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) *iter_reg++ = htonl(rd_reg_dword(dmp_reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) iter_reg = fw->req1_dma_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) dmp_reg = ®->iobase_q;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) for (cnt = 0; cnt < 7; cnt++, dmp_reg++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) *iter_reg++ = htonl(rd_reg_dword(dmp_reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) /* Transmit DMA registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) iter_reg = fw->xmt0_dma_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) qla24xx_read_window(reg, 0x7610, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) iter_reg = fw->xmt1_dma_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) qla24xx_read_window(reg, 0x7630, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) iter_reg = fw->xmt2_dma_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) qla24xx_read_window(reg, 0x7650, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) iter_reg = fw->xmt3_dma_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) qla24xx_read_window(reg, 0x7670, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) iter_reg = fw->xmt4_dma_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) qla24xx_read_window(reg, 0x7690, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) /* Receive DMA registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) iter_reg = fw->rcvt0_data_dma_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) qla24xx_read_window(reg, 0x7710, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) iter_reg = fw->rcvt1_data_dma_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) qla24xx_read_window(reg, 0x7730, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) /* RISC registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) iter_reg = fw->risc_gp_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) qla24xx_read_window(reg, 0x0F70, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) /* Local memory controller registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) iter_reg = fw->lmc_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) iter_reg = qla24xx_read_window(reg, 0x3060, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) qla24xx_read_window(reg, 0x3070, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) /* Fibre Protocol Module registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) iter_reg = fw->fpm_hdw_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) iter_reg = qla24xx_read_window(reg, 0x40B0, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) iter_reg = qla24xx_read_window(reg, 0x40C0, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) qla24xx_read_window(reg, 0x40D0, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) /* Frame Buffer registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) iter_reg = fw->fb_hdw_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) iter_reg = qla24xx_read_window(reg, 0x61B0, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) iter_reg = qla24xx_read_window(reg, 0x61C0, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) qla24xx_read_window(reg, 0x6F00, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) /* Multi queue registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) nxt_chain = qla25xx_copy_mq(ha, (void *)ha->fw_dump + ha->chain_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) &last_chain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) rval = qla24xx_soft_reset(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) if (rval != QLA_SUCCESS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) goto qla81xx_fw_dump_failed_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) &nxt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) if (rval != QLA_SUCCESS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) goto qla81xx_fw_dump_failed_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) nxt = qla2xxx_copy_queues(ha, nxt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) qla24xx_copy_eft(ha, nxt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) /* Chain entries -- started with MQ. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) nxt_chain = qla25xx_copy_fce(ha, nxt_chain, &last_chain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) nxt_chain = qla25xx_copy_mqueues(ha, nxt_chain, &last_chain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) nxt_chain = qla2xxx_copy_atioqueues(ha, nxt_chain, &last_chain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) nxt_chain = qla25xx_copy_exlogin(ha, nxt_chain, &last_chain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) nxt_chain = qla81xx_copy_exchoffld(ha, nxt_chain, &last_chain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) if (last_chain) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) ha->fw_dump->version |= htonl(DUMP_CHAIN_VARIANT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) *last_chain |= htonl(DUMP_CHAIN_LAST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) /* Adjust valid length. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) ha->fw_dump_len = (nxt_chain - (void *)ha->fw_dump);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) qla81xx_fw_dump_failed_0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) qla2xxx_dump_post_process(base_vha, rval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) qla83xx_fw_dump(scsi_qla_host_t *vha)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) int rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) uint32_t cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) __le32 __iomem *dmp_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) __be32 *iter_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) __le16 __iomem *mbx_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) struct qla83xx_fw_dump *fw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) void *nxt, *nxt_chain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) __be32 *last_chain = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) lockdep_assert_held(&ha->hardware_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) ha->fw_dump_cap_flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) if (!ha->fw_dump) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) ql_log(ql_log_warn, vha, 0xd00c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) "No buffer available for dump!!!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) if (ha->fw_dumped) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) ql_log(ql_log_warn, vha, 0xd00d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) "Firmware has been previously dumped (%p) -- ignoring "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) "request...\n", ha->fw_dump);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) QLA_FW_STOPPED(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) fw = &ha->fw_dump->isp.isp83;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) qla2xxx_prep_dump(ha, ha->fw_dump);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) fw->host_status = htonl(rd_reg_dword(®->host_status));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) * Pause RISC. No need to track timeout, as resetting the chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) * is the right approach incase of pause timeout
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) qla24xx_pause_risc(reg, ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) wrt_reg_dword(®->iobase_addr, 0x6000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) dmp_reg = ®->iobase_window;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) rd_reg_dword(dmp_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) wrt_reg_dword(dmp_reg, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) dmp_reg = ®->unused_4_1[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) rd_reg_dword(dmp_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) wrt_reg_dword(dmp_reg, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) wrt_reg_dword(®->iobase_addr, 0x6010);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) dmp_reg = ®->unused_4_1[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) rd_reg_dword(dmp_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) wrt_reg_dword(dmp_reg, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) /* select PCR and disable ecc checking and correction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) wrt_reg_dword(®->iobase_addr, 0x0F70);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) rd_reg_dword(®->iobase_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) wrt_reg_dword(®->iobase_select, 0x60000000); /* write to F0h = PCR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) /* Host/Risc registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) iter_reg = fw->host_risc_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) iter_reg = qla24xx_read_window(reg, 0x7000, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) iter_reg = qla24xx_read_window(reg, 0x7010, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) qla24xx_read_window(reg, 0x7040, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) /* PCIe registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) wrt_reg_dword(®->iobase_addr, 0x7C00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) rd_reg_dword(®->iobase_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) wrt_reg_dword(®->iobase_window, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) dmp_reg = ®->iobase_c4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) fw->pcie_regs[0] = htonl(rd_reg_dword(dmp_reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) dmp_reg++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) fw->pcie_regs[1] = htonl(rd_reg_dword(dmp_reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) dmp_reg++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) fw->pcie_regs[2] = htonl(rd_reg_dword(dmp_reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) fw->pcie_regs[3] = htonl(rd_reg_dword(®->iobase_window));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) wrt_reg_dword(®->iobase_window, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) rd_reg_dword(®->iobase_window);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) /* Host interface registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) dmp_reg = ®->flash_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) for (cnt = 0; cnt < ARRAY_SIZE(fw->host_reg); cnt++, dmp_reg++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) fw->host_reg[cnt] = htonl(rd_reg_dword(dmp_reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) /* Disable interrupts. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) wrt_reg_dword(®->ictrl, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) rd_reg_dword(®->ictrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) /* Shadow registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) wrt_reg_dword(®->iobase_addr, 0x0F70);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) rd_reg_dword(®->iobase_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) wrt_reg_dword(®->iobase_select, 0xB0000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) fw->shadow_reg[0] = htonl(rd_reg_dword(®->iobase_sdata));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) wrt_reg_dword(®->iobase_select, 0xB0100000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) fw->shadow_reg[1] = htonl(rd_reg_dword(®->iobase_sdata));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) wrt_reg_dword(®->iobase_select, 0xB0200000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) fw->shadow_reg[2] = htonl(rd_reg_dword(®->iobase_sdata));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) wrt_reg_dword(®->iobase_select, 0xB0300000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) fw->shadow_reg[3] = htonl(rd_reg_dword(®->iobase_sdata));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) wrt_reg_dword(®->iobase_select, 0xB0400000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) fw->shadow_reg[4] = htonl(rd_reg_dword(®->iobase_sdata));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) wrt_reg_dword(®->iobase_select, 0xB0500000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) fw->shadow_reg[5] = htonl(rd_reg_dword(®->iobase_sdata));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) wrt_reg_dword(®->iobase_select, 0xB0600000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) fw->shadow_reg[6] = htonl(rd_reg_dword(®->iobase_sdata));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) wrt_reg_dword(®->iobase_select, 0xB0700000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) fw->shadow_reg[7] = htonl(rd_reg_dword(®->iobase_sdata));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) wrt_reg_dword(®->iobase_select, 0xB0800000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) fw->shadow_reg[8] = htonl(rd_reg_dword(®->iobase_sdata));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) wrt_reg_dword(®->iobase_select, 0xB0900000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) fw->shadow_reg[9] = htonl(rd_reg_dword(®->iobase_sdata));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) wrt_reg_dword(®->iobase_select, 0xB0A00000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) fw->shadow_reg[10] = htonl(rd_reg_dword(®->iobase_sdata));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) /* RISC I/O register. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) wrt_reg_dword(®->iobase_addr, 0x0010);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) fw->risc_io_reg = htonl(rd_reg_dword(®->iobase_window));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) /* Mailbox registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) mbx_reg = ®->mailbox0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) for (cnt = 0; cnt < ARRAY_SIZE(fw->mailbox_reg); cnt++, mbx_reg++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) fw->mailbox_reg[cnt] = htons(rd_reg_word(mbx_reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) /* Transfer sequence registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) iter_reg = fw->xseq_gp_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) iter_reg = qla24xx_read_window(reg, 0xBE00, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) iter_reg = qla24xx_read_window(reg, 0xBE10, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) iter_reg = qla24xx_read_window(reg, 0xBE20, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) iter_reg = qla24xx_read_window(reg, 0xBE30, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) iter_reg = qla24xx_read_window(reg, 0xBE40, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) iter_reg = qla24xx_read_window(reg, 0xBE50, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) iter_reg = qla24xx_read_window(reg, 0xBE60, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) iter_reg = qla24xx_read_window(reg, 0xBE70, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) qla24xx_read_window(reg, 0xBF70, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) iter_reg = fw->xseq_0_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) iter_reg = qla24xx_read_window(reg, 0xBFC0, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) iter_reg = qla24xx_read_window(reg, 0xBFD0, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) qla24xx_read_window(reg, 0xBFE0, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) qla24xx_read_window(reg, 0xBEF0, 16, fw->xseq_2_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) /* Receive sequence registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) iter_reg = fw->rseq_gp_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) iter_reg = qla24xx_read_window(reg, 0xFE00, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) iter_reg = qla24xx_read_window(reg, 0xFE10, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) iter_reg = qla24xx_read_window(reg, 0xFE20, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) iter_reg = qla24xx_read_window(reg, 0xFE30, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) iter_reg = qla24xx_read_window(reg, 0xFE40, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) iter_reg = qla24xx_read_window(reg, 0xFE50, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) iter_reg = qla24xx_read_window(reg, 0xFE60, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) iter_reg = qla24xx_read_window(reg, 0xFE70, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) qla24xx_read_window(reg, 0xFF70, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) iter_reg = fw->rseq_0_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) iter_reg = qla24xx_read_window(reg, 0xFFC0, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) qla24xx_read_window(reg, 0xFFD0, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) qla24xx_read_window(reg, 0xFEF0, 16, fw->rseq_3_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) /* Auxiliary sequence registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) iter_reg = fw->aseq_gp_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) iter_reg = qla24xx_read_window(reg, 0xB000, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) iter_reg = qla24xx_read_window(reg, 0xB010, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) iter_reg = qla24xx_read_window(reg, 0xB020, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) iter_reg = qla24xx_read_window(reg, 0xB030, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) iter_reg = qla24xx_read_window(reg, 0xB040, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) iter_reg = qla24xx_read_window(reg, 0xB050, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) iter_reg = qla24xx_read_window(reg, 0xB060, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) iter_reg = qla24xx_read_window(reg, 0xB070, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) iter_reg = qla24xx_read_window(reg, 0xB100, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) iter_reg = qla24xx_read_window(reg, 0xB110, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) iter_reg = qla24xx_read_window(reg, 0xB120, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) iter_reg = qla24xx_read_window(reg, 0xB130, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) iter_reg = qla24xx_read_window(reg, 0xB140, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) iter_reg = qla24xx_read_window(reg, 0xB150, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) iter_reg = qla24xx_read_window(reg, 0xB160, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) qla24xx_read_window(reg, 0xB170, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) iter_reg = fw->aseq_0_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) iter_reg = qla24xx_read_window(reg, 0xB0C0, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) qla24xx_read_window(reg, 0xB0D0, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) qla24xx_read_window(reg, 0xB0E0, 16, fw->aseq_1_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) qla24xx_read_window(reg, 0xB0F0, 16, fw->aseq_2_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) qla24xx_read_window(reg, 0xB1F0, 16, fw->aseq_3_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) /* Command DMA registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) iter_reg = fw->cmd_dma_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) iter_reg = qla24xx_read_window(reg, 0x7100, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) iter_reg = qla24xx_read_window(reg, 0x7120, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) iter_reg = qla24xx_read_window(reg, 0x7130, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) qla24xx_read_window(reg, 0x71F0, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) /* Queues. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) iter_reg = fw->req0_dma_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) dmp_reg = ®->iobase_q;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) for (cnt = 0; cnt < 7; cnt++, dmp_reg++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) *iter_reg++ = htonl(rd_reg_dword(dmp_reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) iter_reg = fw->resp0_dma_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) dmp_reg = ®->iobase_q;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) for (cnt = 0; cnt < 7; cnt++, dmp_reg++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) *iter_reg++ = htonl(rd_reg_dword(dmp_reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) iter_reg = fw->req1_dma_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) dmp_reg = ®->iobase_q;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) for (cnt = 0; cnt < 7; cnt++, dmp_reg++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) *iter_reg++ = htonl(rd_reg_dword(dmp_reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) /* Transmit DMA registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) iter_reg = fw->xmt0_dma_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) qla24xx_read_window(reg, 0x7610, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) iter_reg = fw->xmt1_dma_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) qla24xx_read_window(reg, 0x7630, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) iter_reg = fw->xmt2_dma_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) qla24xx_read_window(reg, 0x7650, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) iter_reg = fw->xmt3_dma_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) qla24xx_read_window(reg, 0x7670, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) iter_reg = fw->xmt4_dma_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) qla24xx_read_window(reg, 0x7690, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) /* Receive DMA registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) iter_reg = fw->rcvt0_data_dma_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) qla24xx_read_window(reg, 0x7710, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) iter_reg = fw->rcvt1_data_dma_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) qla24xx_read_window(reg, 0x7730, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) /* RISC registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) iter_reg = fw->risc_gp_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) qla24xx_read_window(reg, 0x0F70, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) /* Local memory controller registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) iter_reg = fw->lmc_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) iter_reg = qla24xx_read_window(reg, 0x3060, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) qla24xx_read_window(reg, 0x3070, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) /* Fibre Protocol Module registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) iter_reg = fw->fpm_hdw_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) iter_reg = qla24xx_read_window(reg, 0x40B0, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) iter_reg = qla24xx_read_window(reg, 0x40C0, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) iter_reg = qla24xx_read_window(reg, 0x40D0, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) iter_reg = qla24xx_read_window(reg, 0x40E0, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) qla24xx_read_window(reg, 0x40F0, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) /* RQ0 Array registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) iter_reg = fw->rq0_array_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) iter_reg = qla24xx_read_window(reg, 0x5C00, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) iter_reg = qla24xx_read_window(reg, 0x5C10, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) iter_reg = qla24xx_read_window(reg, 0x5C20, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) iter_reg = qla24xx_read_window(reg, 0x5C30, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) iter_reg = qla24xx_read_window(reg, 0x5C40, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) iter_reg = qla24xx_read_window(reg, 0x5C50, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) iter_reg = qla24xx_read_window(reg, 0x5C60, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) iter_reg = qla24xx_read_window(reg, 0x5C70, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) iter_reg = qla24xx_read_window(reg, 0x5C80, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) iter_reg = qla24xx_read_window(reg, 0x5C90, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) iter_reg = qla24xx_read_window(reg, 0x5CA0, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) iter_reg = qla24xx_read_window(reg, 0x5CB0, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) iter_reg = qla24xx_read_window(reg, 0x5CC0, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) iter_reg = qla24xx_read_window(reg, 0x5CD0, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) iter_reg = qla24xx_read_window(reg, 0x5CE0, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) qla24xx_read_window(reg, 0x5CF0, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) /* RQ1 Array registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) iter_reg = fw->rq1_array_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) iter_reg = qla24xx_read_window(reg, 0x5D00, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) iter_reg = qla24xx_read_window(reg, 0x5D10, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) iter_reg = qla24xx_read_window(reg, 0x5D20, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) iter_reg = qla24xx_read_window(reg, 0x5D30, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) iter_reg = qla24xx_read_window(reg, 0x5D40, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) iter_reg = qla24xx_read_window(reg, 0x5D50, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) iter_reg = qla24xx_read_window(reg, 0x5D60, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) iter_reg = qla24xx_read_window(reg, 0x5D70, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) iter_reg = qla24xx_read_window(reg, 0x5D80, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) iter_reg = qla24xx_read_window(reg, 0x5D90, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) iter_reg = qla24xx_read_window(reg, 0x5DA0, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) iter_reg = qla24xx_read_window(reg, 0x5DB0, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) iter_reg = qla24xx_read_window(reg, 0x5DC0, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) iter_reg = qla24xx_read_window(reg, 0x5DD0, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) iter_reg = qla24xx_read_window(reg, 0x5DE0, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) qla24xx_read_window(reg, 0x5DF0, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) /* RP0 Array registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) iter_reg = fw->rp0_array_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) iter_reg = qla24xx_read_window(reg, 0x5E00, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) iter_reg = qla24xx_read_window(reg, 0x5E10, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) iter_reg = qla24xx_read_window(reg, 0x5E20, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) iter_reg = qla24xx_read_window(reg, 0x5E30, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) iter_reg = qla24xx_read_window(reg, 0x5E40, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) iter_reg = qla24xx_read_window(reg, 0x5E50, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) iter_reg = qla24xx_read_window(reg, 0x5E60, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) iter_reg = qla24xx_read_window(reg, 0x5E70, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) iter_reg = qla24xx_read_window(reg, 0x5E80, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) iter_reg = qla24xx_read_window(reg, 0x5E90, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) iter_reg = qla24xx_read_window(reg, 0x5EA0, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) iter_reg = qla24xx_read_window(reg, 0x5EB0, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) iter_reg = qla24xx_read_window(reg, 0x5EC0, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) iter_reg = qla24xx_read_window(reg, 0x5ED0, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) iter_reg = qla24xx_read_window(reg, 0x5EE0, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) qla24xx_read_window(reg, 0x5EF0, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) /* RP1 Array registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) iter_reg = fw->rp1_array_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) iter_reg = qla24xx_read_window(reg, 0x5F00, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) iter_reg = qla24xx_read_window(reg, 0x5F10, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) iter_reg = qla24xx_read_window(reg, 0x5F20, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) iter_reg = qla24xx_read_window(reg, 0x5F30, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) iter_reg = qla24xx_read_window(reg, 0x5F40, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) iter_reg = qla24xx_read_window(reg, 0x5F50, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) iter_reg = qla24xx_read_window(reg, 0x5F60, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) iter_reg = qla24xx_read_window(reg, 0x5F70, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) iter_reg = qla24xx_read_window(reg, 0x5F80, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) iter_reg = qla24xx_read_window(reg, 0x5F90, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) iter_reg = qla24xx_read_window(reg, 0x5FA0, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) iter_reg = qla24xx_read_window(reg, 0x5FB0, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) iter_reg = qla24xx_read_window(reg, 0x5FC0, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) iter_reg = qla24xx_read_window(reg, 0x5FD0, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) iter_reg = qla24xx_read_window(reg, 0x5FE0, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) qla24xx_read_window(reg, 0x5FF0, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) iter_reg = fw->at0_array_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) iter_reg = qla24xx_read_window(reg, 0x7080, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) iter_reg = qla24xx_read_window(reg, 0x7090, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) iter_reg = qla24xx_read_window(reg, 0x70A0, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) iter_reg = qla24xx_read_window(reg, 0x70B0, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) iter_reg = qla24xx_read_window(reg, 0x70C0, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) iter_reg = qla24xx_read_window(reg, 0x70D0, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) iter_reg = qla24xx_read_window(reg, 0x70E0, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) qla24xx_read_window(reg, 0x70F0, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) /* I/O Queue Control registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) qla24xx_read_window(reg, 0x7800, 16, fw->queue_control_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) /* Frame Buffer registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) iter_reg = fw->fb_hdw_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) iter_reg = qla24xx_read_window(reg, 0x6060, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) iter_reg = qla24xx_read_window(reg, 0x6070, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) iter_reg = qla24xx_read_window(reg, 0x61B0, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) iter_reg = qla24xx_read_window(reg, 0x61C0, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) iter_reg = qla24xx_read_window(reg, 0x6530, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) iter_reg = qla24xx_read_window(reg, 0x6540, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) iter_reg = qla24xx_read_window(reg, 0x6550, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) iter_reg = qla24xx_read_window(reg, 0x6560, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) iter_reg = qla24xx_read_window(reg, 0x6570, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) iter_reg = qla24xx_read_window(reg, 0x6580, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) iter_reg = qla24xx_read_window(reg, 0x6590, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) iter_reg = qla24xx_read_window(reg, 0x65A0, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) iter_reg = qla24xx_read_window(reg, 0x65B0, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) iter_reg = qla24xx_read_window(reg, 0x65C0, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) iter_reg = qla24xx_read_window(reg, 0x65D0, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) iter_reg = qla24xx_read_window(reg, 0x65E0, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) qla24xx_read_window(reg, 0x6F00, 16, iter_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) /* Multi queue registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) nxt_chain = qla25xx_copy_mq(ha, (void *)ha->fw_dump + ha->chain_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) &last_chain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) rval = qla24xx_soft_reset(ha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) if (rval != QLA_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) ql_log(ql_log_warn, vha, 0xd00e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) "SOFT RESET FAILED, forcing continuation of dump!!!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) rval = QLA_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) ql_log(ql_log_warn, vha, 0xd00f, "try a bigger hammer!!!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) wrt_reg_dword(®->hccr, HCCRX_SET_RISC_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) rd_reg_dword(®->hccr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) wrt_reg_dword(®->hccr, HCCRX_REL_RISC_PAUSE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) rd_reg_dword(®->hccr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) wrt_reg_dword(®->hccr, HCCRX_CLR_RISC_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) rd_reg_dword(®->hccr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) for (cnt = 30000; cnt && (rd_reg_word(®->mailbox0)); cnt--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) udelay(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) if (!cnt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) nxt = fw->code_ram;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) nxt += sizeof(fw->code_ram);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) nxt += (ha->fw_memory_size - 0x100000 + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) goto copy_queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) set_bit(RISC_RDY_AFT_RESET, &ha->fw_dump_cap_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) ql_log(ql_log_warn, vha, 0xd010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) "bigger hammer success?\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) &nxt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) if (rval != QLA_SUCCESS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) goto qla83xx_fw_dump_failed_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) copy_queue:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) nxt = qla2xxx_copy_queues(ha, nxt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) qla24xx_copy_eft(ha, nxt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) /* Chain entries -- started with MQ. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) nxt_chain = qla25xx_copy_fce(ha, nxt_chain, &last_chain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) nxt_chain = qla25xx_copy_mqueues(ha, nxt_chain, &last_chain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) nxt_chain = qla2xxx_copy_atioqueues(ha, nxt_chain, &last_chain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) nxt_chain = qla25xx_copy_exlogin(ha, nxt_chain, &last_chain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) nxt_chain = qla81xx_copy_exchoffld(ha, nxt_chain, &last_chain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) if (last_chain) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) ha->fw_dump->version |= htonl(DUMP_CHAIN_VARIANT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) *last_chain |= htonl(DUMP_CHAIN_LAST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) /* Adjust valid length. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) ha->fw_dump_len = (nxt_chain - (void *)ha->fw_dump);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) qla83xx_fw_dump_failed_0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) qla2xxx_dump_post_process(base_vha, rval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) /* Driver Debug Functions. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) /* Write the debug message prefix into @pbuf. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) static void ql_dbg_prefix(char *pbuf, int pbuf_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) const scsi_qla_host_t *vha, uint msg_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) if (vha) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) const struct pci_dev *pdev = vha->hw->pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) /* <module-name> [<dev-name>]-<msg-id>:<host>: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) snprintf(pbuf, pbuf_size, "%s [%s]-%04x:%lu: ", QL_MSGHDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) dev_name(&(pdev->dev)), msg_id, vha->host_no);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) /* <module-name> [<dev-name>]-<msg-id>: : */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) snprintf(pbuf, pbuf_size, "%s [%s]-%04x: : ", QL_MSGHDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) "0000:00:00.0", msg_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) * This function is for formatting and logging debug information.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) * It is to be used when vha is available. It formats the message
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) * and logs it to the messages file.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) * parameters:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) * level: The level of the debug messages to be printed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) * If ql2xextended_error_logging value is correctly set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) * this message will appear in the messages file.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) * vha: Pointer to the scsi_qla_host_t.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) * id: This is a unique identifier for the level. It identifies the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) * part of the code from where the message originated.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) * msg: The message to be displayed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) ql_dbg(uint level, scsi_qla_host_t *vha, uint id, const char *fmt, ...)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) va_list va;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) struct va_format vaf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) char pbuf[64];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) if (!ql_mask_match(level) && !trace_ql_dbg_log_enabled())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) va_start(va, fmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) vaf.fmt = fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) vaf.va = &va;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) ql_dbg_prefix(pbuf, ARRAY_SIZE(pbuf), vha, id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) if (!ql_mask_match(level))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) trace_ql_dbg_log(pbuf, &vaf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) pr_warn("%s%pV", pbuf, &vaf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) va_end(va);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) * This function is for formatting and logging debug information.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) * It is to be used when vha is not available and pci is available,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) * i.e., before host allocation. It formats the message and logs it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) * to the messages file.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) * parameters:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) * level: The level of the debug messages to be printed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) * If ql2xextended_error_logging value is correctly set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) * this message will appear in the messages file.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) * pdev: Pointer to the struct pci_dev.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) * id: This is a unique id for the level. It identifies the part
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) * of the code from where the message originated.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) * msg: The message to be displayed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) ql_dbg_pci(uint level, struct pci_dev *pdev, uint id, const char *fmt, ...)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) va_list va;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) struct va_format vaf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) char pbuf[128];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) if (pdev == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) if (!ql_mask_match(level))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) va_start(va, fmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) vaf.fmt = fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528) vaf.va = &va;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530) ql_dbg_prefix(pbuf, ARRAY_SIZE(pbuf), NULL, id + ql_dbg_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) pr_warn("%s%pV", pbuf, &vaf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) va_end(va);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) * This function is for formatting and logging log messages.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) * It is to be used when vha is available. It formats the message
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) * and logs it to the messages file. All the messages will be logged
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) * irrespective of value of ql2xextended_error_logging.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) * parameters:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) * level: The level of the log messages to be printed in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) * messages file.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) * vha: Pointer to the scsi_qla_host_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) * id: This is a unique id for the level. It identifies the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) * part of the code from where the message originated.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) * msg: The message to be displayed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) ql_log(uint level, scsi_qla_host_t *vha, uint id, const char *fmt, ...)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) va_list va;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) struct va_format vaf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) char pbuf[128];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) if (level > ql_errlev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559) ql_dbg_prefix(pbuf, ARRAY_SIZE(pbuf), vha, id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) va_start(va, fmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) vaf.fmt = fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) vaf.va = &va;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) switch (level) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567) case ql_log_fatal: /* FATAL LOG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) pr_crit("%s%pV", pbuf, &vaf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) case ql_log_warn:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571) pr_err("%s%pV", pbuf, &vaf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) case ql_log_info:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) pr_warn("%s%pV", pbuf, &vaf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) pr_info("%s%pV", pbuf, &vaf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) va_end(va);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) * This function is for formatting and logging log messages.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) * It is to be used when vha is not available and pci is available,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) * i.e., before host allocation. It formats the message and logs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588) * it to the messages file. All the messages are logged irrespective
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589) * of the value of ql2xextended_error_logging.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) * parameters:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) * level: The level of the log messages to be printed in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592) * messages file.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) * pdev: Pointer to the struct pci_dev.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) * id: This is a unique id for the level. It identifies the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595) * part of the code from where the message originated.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596) * msg: The message to be displayed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598) void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) ql_log_pci(uint level, struct pci_dev *pdev, uint id, const char *fmt, ...)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601) va_list va;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) struct va_format vaf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603) char pbuf[128];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605) if (pdev == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607) if (level > ql_errlev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) ql_dbg_prefix(pbuf, ARRAY_SIZE(pbuf), NULL, id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612) va_start(va, fmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614) vaf.fmt = fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615) vaf.va = &va;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617) switch (level) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618) case ql_log_fatal: /* FATAL LOG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619) pr_crit("%s%pV", pbuf, &vaf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621) case ql_log_warn:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622) pr_err("%s%pV", pbuf, &vaf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624) case ql_log_info:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625) pr_warn("%s%pV", pbuf, &vaf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628) pr_info("%s%pV", pbuf, &vaf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632) va_end(va);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635) void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636) ql_dump_regs(uint level, scsi_qla_host_t *vha, uint id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639) struct qla_hw_data *ha = vha->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640) struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641) struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642) struct device_reg_82xx __iomem *reg82 = &ha->iobase->isp82;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643) __le16 __iomem *mbx_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645) if (!ql_mask_match(level))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648) if (IS_P3P_TYPE(ha))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649) mbx_reg = ®82->mailbox_in[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650) else if (IS_FWI2_CAPABLE(ha))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651) mbx_reg = ®24->mailbox0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653) mbx_reg = MAILBOX_REG(ha, reg, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655) ql_dbg(level, vha, id, "Mailbox registers:\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656) for (i = 0; i < 6; i++, mbx_reg++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657) ql_dbg(level, vha, id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658) "mbox[%d] %#04x\n", i, rd_reg_word(mbx_reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661) void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662) ql_dump_buffer(uint level, scsi_qla_host_t *vha, uint id, const void *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663) uint size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665) uint cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667) if (!ql_mask_match(level))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670) ql_dbg(level, vha, id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671) "%-+5d 0 1 2 3 4 5 6 7 8 9 A B C D E F\n", size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672) ql_dbg(level, vha, id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673) "----- -----------------------------------------------\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674) for (cnt = 0; cnt < size; cnt += 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675) ql_dbg(level, vha, id, "%04x: ", cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676) print_hex_dump(KERN_CONT, "", DUMP_PREFIX_NONE, 16, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677) buf + cnt, min(16U, size - cnt), false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682) * This function is for formatting and logging log messages.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683) * It is to be used when vha is available. It formats the message
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684) * and logs it to the messages file. All the messages will be logged
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685) * irrespective of value of ql2xextended_error_logging.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686) * parameters:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687) * level: The level of the log messages to be printed in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688) * messages file.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689) * vha: Pointer to the scsi_qla_host_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690) * id: This is a unique id for the level. It identifies the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691) * part of the code from where the message originated.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692) * msg: The message to be displayed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694) void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695) ql_log_qp(uint32_t level, struct qla_qpair *qpair, int32_t id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696) const char *fmt, ...)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698) va_list va;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699) struct va_format vaf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700) char pbuf[128];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702) if (level > ql_errlev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705) ql_dbg_prefix(pbuf, ARRAY_SIZE(pbuf), qpair ? qpair->vha : NULL, id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707) va_start(va, fmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709) vaf.fmt = fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710) vaf.va = &va;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712) switch (level) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713) case ql_log_fatal: /* FATAL LOG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714) pr_crit("%s%pV", pbuf, &vaf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716) case ql_log_warn:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717) pr_err("%s%pV", pbuf, &vaf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2719) case ql_log_info:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2720) pr_warn("%s%pV", pbuf, &vaf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2721) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2722) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2723) pr_info("%s%pV", pbuf, &vaf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2724) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2725) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2727) va_end(va);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2728) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2730) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2731) * This function is for formatting and logging debug information.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2732) * It is to be used when vha is available. It formats the message
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2733) * and logs it to the messages file.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2734) * parameters:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2735) * level: The level of the debug messages to be printed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2736) * If ql2xextended_error_logging value is correctly set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2737) * this message will appear in the messages file.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2738) * vha: Pointer to the scsi_qla_host_t.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2739) * id: This is a unique identifier for the level. It identifies the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2740) * part of the code from where the message originated.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2741) * msg: The message to be displayed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2742) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2743) void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2744) ql_dbg_qp(uint32_t level, struct qla_qpair *qpair, int32_t id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2745) const char *fmt, ...)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2746) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2747) va_list va;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2748) struct va_format vaf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2749) char pbuf[128];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2751) if (!ql_mask_match(level))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2752) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2754) va_start(va, fmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2756) vaf.fmt = fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2757) vaf.va = &va;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2759) ql_dbg_prefix(pbuf, ARRAY_SIZE(pbuf), qpair ? qpair->vha : NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2760) id + ql_dbg_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2761) pr_warn("%s%pV", pbuf, &vaf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2763) va_end(va);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2765) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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