^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * QLogic Fibre Channel HBA Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (c) 2003-2014 QLogic Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #ifndef __QLA_BSG_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define __QLA_BSG_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) /* BSG Vendor specific commands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define QL_VND_LOOPBACK 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define QL_VND_A84_RESET 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define QL_VND_A84_UPDATE_FW 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define QL_VND_A84_MGMT_CMD 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define QL_VND_IIDMA 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define QL_VND_FCP_PRIO_CFG_CMD 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define QL_VND_READ_FLASH 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define QL_VND_UPDATE_FLASH 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define QL_VND_SET_FRU_VERSION 0x0B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define QL_VND_READ_FRU_STATUS 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define QL_VND_WRITE_FRU_STATUS 0x0D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define QL_VND_DIAG_IO_CMD 0x0A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define QL_VND_WRITE_I2C 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define QL_VND_READ_I2C 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define QL_VND_FX00_MGMT_CMD 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define QL_VND_SERDES_OP 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define QL_VND_SERDES_OP_EX 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define QL_VND_GET_FLASH_UPDATE_CAPS 0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define QL_VND_SET_FLASH_UPDATE_CAPS 0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define QL_VND_GET_BBCR_DATA 0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define QL_VND_GET_PRIV_STATS 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define QL_VND_DPORT_DIAGNOSTICS 0x19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define QL_VND_GET_PRIV_STATS_EX 0x1A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define QL_VND_SS_GET_FLASH_IMAGE_STATUS 0x1E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /* BSG Vendor specific subcode returns */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define EXT_STATUS_OK 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define EXT_STATUS_ERR 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define EXT_STATUS_BUSY 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define EXT_STATUS_INVALID_PARAM 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define EXT_STATUS_DATA_OVERRUN 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define EXT_STATUS_DATA_UNDERRUN 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define EXT_STATUS_MAILBOX 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define EXT_STATUS_NO_MEMORY 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define EXT_STATUS_DEVICE_OFFLINE 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * To support bidirectional iocb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * BSG Vendor specific returns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define EXT_STATUS_NOT_SUPPORTED 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define EXT_STATUS_INVALID_CFG 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define EXT_STATUS_DMA_ERR 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define EXT_STATUS_TIMEOUT 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define EXT_STATUS_THREAD_FAILED 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define EXT_STATUS_DATA_CMP_FAILED 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* BSG definations for interpreting CommandSent field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define INT_DEF_LB_LOOPBACK_CMD 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define INT_DEF_LB_ECHO_CMD 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /* Loopback related definations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define INTERNAL_LOOPBACK 0xF1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define EXTERNAL_LOOPBACK 0xF2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define ENABLE_INTERNAL_LOOPBACK 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define ENABLE_EXTERNAL_LOOPBACK 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define INTERNAL_LOOPBACK_MASK 0x000E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define MAX_ELS_FRAME_PAYLOAD 252
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define ELS_OPCODE_BYTE 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /* BSG Vendor specific definations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define A84_ISSUE_WRITE_TYPE_CMD 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define A84_ISSUE_READ_TYPE_CMD 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define A84_CLEANUP_CMD 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define A84_ISSUE_RESET_OP_FW 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define A84_ISSUE_RESET_DIAG_FW 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define A84_ISSUE_UPDATE_OPFW_CMD 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define A84_ISSUE_UPDATE_DIAGFW_CMD 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) struct qla84_mgmt_param {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) uint32_t start_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) } mem; /* for QLA84_MGMT_READ/WRITE_MEM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) uint32_t id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define QLA84_MGMT_CONFIG_ID_UIF 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define QLA84_MGMT_CONFIG_ID_FCOE_COS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define QLA84_MGMT_CONFIG_ID_PAUSE 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define QLA84_MGMT_CONFIG_ID_TIMEOUTS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) uint32_t param0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) uint32_t param1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) } config; /* for QLA84_MGMT_CHNG_CONFIG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) uint32_t type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define QLA84_MGMT_INFO_CONFIG_LOG_DATA 1 /* Get Config Log Data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define QLA84_MGMT_INFO_LOG_DATA 2 /* Get Log Data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define QLA84_MGMT_INFO_PORT_STAT 3 /* Get Port Statistics */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define QLA84_MGMT_INFO_LIF_STAT 4 /* Get LIF Statistics */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define QLA84_MGMT_INFO_ASIC_STAT 5 /* Get ASIC Statistics */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define QLA84_MGMT_INFO_CONFIG_PARAMS 6 /* Get Config Parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define QLA84_MGMT_INFO_PANIC_LOG 7 /* Get Panic Log */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) uint32_t context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * context definitions for QLA84_MGMT_INFO_CONFIG_LOG_DATA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define IC_LOG_DATA_LOG_ID_DEBUG_LOG 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define IC_LOG_DATA_LOG_ID_LEARN_LOG 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define IC_LOG_DATA_LOG_ID_FC_ACL_INGRESS_LOG 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define IC_LOG_DATA_LOG_ID_FC_ACL_EGRESS_LOG 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define IC_LOG_DATA_LOG_ID_ETHERNET_ACL_INGRESS_LOG 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define IC_LOG_DATA_LOG_ID_ETHERNET_ACL_EGRESS_LOG 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define IC_LOG_DATA_LOG_ID_MESSAGE_TRANSMIT_LOG 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define IC_LOG_DATA_LOG_ID_MESSAGE_RECEIVE_LOG 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define IC_LOG_DATA_LOG_ID_LINK_EVENT_LOG 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define IC_LOG_DATA_LOG_ID_DCX_LOG 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * context definitions for QLA84_MGMT_INFO_PORT_STAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define IC_PORT_STATISTICS_PORT_NUMBER_ETHERNET_PORT0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define IC_PORT_STATISTICS_PORT_NUMBER_ETHERNET_PORT1 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define IC_PORT_STATISTICS_PORT_NUMBER_NSL_PORT0 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define IC_PORT_STATISTICS_PORT_NUMBER_NSL_PORT1 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define IC_PORT_STATISTICS_PORT_NUMBER_FC_PORT0 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define IC_PORT_STATISTICS_PORT_NUMBER_FC_PORT1 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * context definitions for QLA84_MGMT_INFO_LIF_STAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define IC_LIF_STATISTICS_LIF_NUMBER_ETHERNET_PORT0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define IC_LIF_STATISTICS_LIF_NUMBER_ETHERNET_PORT1 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define IC_LIF_STATISTICS_LIF_NUMBER_FC_PORT0 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define IC_LIF_STATISTICS_LIF_NUMBER_FC_PORT1 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define IC_LIF_STATISTICS_LIF_NUMBER_CPU 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) } info; /* for QLA84_MGMT_GET_INFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) } u;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct qla84_msg_mgmt {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) uint16_t cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define QLA84_MGMT_READ_MEM 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define QLA84_MGMT_WRITE_MEM 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define QLA84_MGMT_CHNG_CONFIG 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define QLA84_MGMT_GET_INFO 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) uint16_t rsrvd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) struct qla84_mgmt_param mgmtp;/* parameters for cmd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) uint32_t len; /* bytes in payload following this struct */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) uint8_t payload[0]; /* payload for cmd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) struct qla_bsg_a84_mgmt {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) struct qla84_msg_mgmt mgmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) } __attribute__ ((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) struct qla_scsi_addr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) uint16_t bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) uint16_t target;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) } __attribute__ ((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) struct qla_ext_dest_addr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) uint8_t wwnn[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) uint8_t wwpn[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) uint8_t id[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) struct qla_scsi_addr scsi_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) } dest_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) uint16_t dest_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define EXT_DEF_TYPE_WWPN 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) uint16_t lun;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) uint16_t padding[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) } __attribute__ ((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) struct qla_port_param {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) struct qla_ext_dest_addr fc_scsi_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) uint16_t mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) uint16_t speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) } __attribute__ ((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /* FRU VPD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define MAX_FRU_SIZE 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) struct qla_field_address {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) uint16_t offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) uint16_t device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) uint16_t option;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) struct qla_field_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) uint8_t version[MAX_FRU_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) struct qla_image_version {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) struct qla_field_address field_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) struct qla_field_info field_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) struct qla_image_version_list {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) uint32_t count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) struct qla_image_version version[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) struct qla_status_reg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) struct qla_field_address field_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) uint8_t status_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) uint8_t reserved[7];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) struct qla_i2c_access {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) uint16_t device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) uint16_t offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) uint16_t option;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) uint16_t length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) uint8_t buffer[0x40];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) /* 26xx serdes register interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) /* serdes reg commands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define INT_SC_SERDES_READ_REG 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define INT_SC_SERDES_WRITE_REG 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) struct qla_serdes_reg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) uint16_t cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) uint16_t addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) uint16_t val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) struct qla_serdes_reg_ex {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) uint16_t cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) uint32_t addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) uint32_t val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) struct qla_flash_update_caps {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) uint64_t capabilities;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) uint32_t outage_duration;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) uint8_t reserved[20];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) /* BB_CR Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define QLA_BBCR_STATUS_DISABLED 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define QLA_BBCR_STATUS_ENABLED 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define QLA_BBCR_STATUS_UNKNOWN 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) /* BB_CR State */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define QLA_BBCR_STATE_OFFLINE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define QLA_BBCR_STATE_ONLINE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) /* BB_CR Offline Reason Code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define QLA_BBCR_REASON_PORT_SPEED 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define QLA_BBCR_REASON_PEER_PORT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define QLA_BBCR_REASON_SWITCH 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define QLA_BBCR_REASON_LOGIN_REJECT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) struct qla_bbcr_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) uint8_t status; /* 1 - enabled, 0 - Disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) uint8_t state; /* 1 - online, 0 - offline */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) uint8_t configured_bbscn; /* 0-15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) uint8_t negotiated_bbscn; /* 0-15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) uint8_t offline_reason_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) uint16_t mbx1; /* Port state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) uint8_t reserved[9];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) struct qla_dport_diag {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) uint16_t options;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) uint32_t buf[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) uint8_t unused[62];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) /* D_Port options */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define QLA_DPORT_RESULT 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define QLA_DPORT_START 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) /* active images in flash */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) struct qla_active_regions {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) uint8_t global_image;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) uint8_t board_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) uint8_t vpd_nvram;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) uint8_t npiv_config_0_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) uint8_t npiv_config_2_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) uint8_t reserved[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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